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2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define TARGET_LONG_BITS 32
25 #define ELF_MACHINE EM_ARM
29 #include "softfloat.h"
31 #define TARGET_HAS_ICE 1
33 #define EXCP_UDEF 1 /* undefined instruction */
34 #define EXCP_SWI 2 /* software interrupt */
35 #define EXCP_PREFETCH_ABORT 3
36 #define EXCP_DATA_ABORT 4
41 typedef void ARMWriteCPFunc(void *opaque
, int cp_info
,
42 int srcreg
, int operand
, uint32_t value
);
43 typedef uint32_t ARMReadCPFunc(void *opaque
, int cp_info
,
44 int dstreg
, int operand
);
46 /* We currently assume float and double are IEEE single and double
47 precision respectively.
48 Doing runtime conversions is tricky because VFP registers may contain
49 integer values (eg. as the result of a FTOSI instruction).
50 s<2n> maps to the least significant half of d<n>
51 s<2n+1> maps to the most significant half of d<n>
54 typedef struct CPUARMState
{
55 /* Regs for current mode. */
57 /* Frequently accessed CPSR bits are stored separately for efficiently.
58 This contains all the other bits. Use cpsr_{read,write} to access
60 uint32_t uncached_cpsr
;
63 /* Banked registers. */
64 uint32_t banked_spsr
[6];
65 uint32_t banked_r13
[6];
66 uint32_t banked_r14
[6];
68 /* These hold r8-r12. */
72 /* cpsr flag cache for faster execution */
73 uint32_t CF
; /* 0 or 1 */
74 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
75 uint32_t NZF
; /* N is bit 31. Z is computed from NZF */
76 uint32_t QF
; /* 0 or 1 */
78 int thumb
; /* 0 = arm mode, 1 = thumb mode */
80 /* System control coprocessor (cp15) */
83 uint32_t c0_cachetype
;
84 uint32_t c1_sys
; /* System control register. */
85 uint32_t c1_coproc
; /* Coprocessor access register. */
86 uint32_t c2
; /* MMU translation table base. */
87 uint32_t c3
; /* MMU domain access control register. */
88 uint32_t c5_insn
; /* Fault status registers. */
90 uint32_t c6_insn
; /* Fault address registers. */
92 uint32_t c9_insn
; /* Cache lockdown registers. */
94 uint32_t c13_fcse
; /* FCSE PID. */
95 uint32_t c13_context
; /* Context ID. */
96 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
99 /* Coprocessor IO used by peripherals */
101 ARMReadCPFunc
*cp_read
;
102 ARMWriteCPFunc
*cp_write
;
106 /* Internal CPU feature flags. */
109 /* exception/interrupt handling */
112 int interrupt_request
;
116 /* VFP coprocessor state. */
121 /* We store these fpcsr fields separately for convenience. */
125 /* Temporary variables if we don't have spare fp regs. */
126 float32 tmp0s
, tmp1s
;
127 float64 tmp0d
, tmp1d
;
129 float_status fp_status
;
132 /* iwMMXt coprocessor state. */
140 #if defined(CONFIG_USER_ONLY)
141 /* For usermode syscall translation. */
147 /* These fields after the common ones so thes are preserved on reset. */
149 const char *kernel_filename
;
150 const char *kernel_cmdline
;
151 const char *initrd_filename
;
155 CPUARMState
*cpu_arm_init(void);
156 int cpu_arm_exec(CPUARMState
*s
);
157 void cpu_arm_close(CPUARMState
*s
);
158 void do_interrupt(CPUARMState
*);
159 void switch_mode(CPUARMState
*, int);
161 /* you can call this signal handler from your SIGBUS and SIGSEGV
162 signal handlers to inform the virtual CPU of exceptions. non zero
163 is returned if the signal was handled by the virtual CPU. */
164 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
167 #define CPSR_M (0x1f)
168 #define CPSR_T (1 << 5)
169 #define CPSR_F (1 << 6)
170 #define CPSR_I (1 << 7)
171 #define CPSR_A (1 << 8)
172 #define CPSR_E (1 << 9)
173 #define CPSR_IT_2_7 (0xfc00)
174 /* Bits 20-23 reserved. */
175 #define CPSR_J (1 << 24)
176 #define CPSR_IT_0_1 (3 << 25)
177 #define CPSR_Q (1 << 27)
178 #define CPSR_NZCV (0xf << 28)
180 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
181 /* Return the current CPSR value. */
182 static inline uint32_t cpsr_read(CPUARMState
*env
)
185 ZF
= (env
->NZF
== 0);
186 return env
->uncached_cpsr
| (env
->NZF
& 0x80000000) | (ZF
<< 30) |
187 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
191 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
192 static inline void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
194 /* NOTE: N = 1 and Z = 1 cannot be stored currently */
195 if (mask
& CPSR_NZCV
) {
196 env
->NZF
= (val
& 0xc0000000) ^ 0x40000000;
197 env
->CF
= (val
>> 29) & 1;
198 env
->VF
= (val
<< 3) & 0x80000000;
201 env
->QF
= ((val
& CPSR_Q
) != 0);
203 env
->thumb
= ((val
& CPSR_T
) != 0);
205 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
206 switch_mode(env
, val
& CPSR_M
);
208 mask
&= ~CACHED_CPSR_BITS
;
209 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
213 ARM_CPU_MODE_USR
= 0x10,
214 ARM_CPU_MODE_FIQ
= 0x11,
215 ARM_CPU_MODE_IRQ
= 0x12,
216 ARM_CPU_MODE_SVC
= 0x13,
217 ARM_CPU_MODE_ABT
= 0x17,
218 ARM_CPU_MODE_UND
= 0x1b,
219 ARM_CPU_MODE_SYS
= 0x1f
222 /* VFP system registers. */
223 #define ARM_VFP_FPSID 0
224 #define ARM_VFP_FPSCR 1
225 #define ARM_VFP_FPEXC 8
226 #define ARM_VFP_FPINST 9
227 #define ARM_VFP_FPINST2 10
229 /* iwMMXt coprocessor control registers. */
230 #define ARM_IWMMXT_wCID 0
231 #define ARM_IWMMXT_wCon 1
232 #define ARM_IWMMXT_wCSSF 2
233 #define ARM_IWMMXT_wCASF 3
234 #define ARM_IWMMXT_wCGR0 8
235 #define ARM_IWMMXT_wCGR1 9
236 #define ARM_IWMMXT_wCGR2 10
237 #define ARM_IWMMXT_wCGR3 11
241 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
242 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
243 ARM_FEATURE_IWMMXT
/* Intel iwMMXt extension. */
246 static inline int arm_feature(CPUARMState
*env
, int feature
)
248 return (env
->features
& (1u << feature
)) != 0;
251 void arm_cpu_list(void);
252 void cpu_arm_set_model(CPUARMState
*env
, const char *name
);
254 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
255 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
258 #define ARM_CPUID_ARM1026 0x4106a262
259 #define ARM_CPUID_ARM926 0x41069265
260 #define ARM_CPUID_PXA250 0x69052100
261 #define ARM_CPUID_PXA255 0x69052d00
262 #define ARM_CPUID_PXA260 0x69052903
263 #define ARM_CPUID_PXA261 0x69052d05
264 #define ARM_CPUID_PXA262 0x69052d06
265 #define ARM_CPUID_PXA270 0x69054110
266 #define ARM_CPUID_PXA270_A0 0x69054110
267 #define ARM_CPUID_PXA270_A1 0x69054111
268 #define ARM_CPUID_PXA270_B0 0x69054112
269 #define ARM_CPUID_PXA270_B1 0x69054113
270 #define ARM_CPUID_PXA270_C0 0x69054114
271 #define ARM_CPUID_PXA270_C5 0x69054117
273 #if defined(CONFIG_USER_ONLY)
274 #define TARGET_PAGE_BITS 12
276 /* The ARM MMU allows 1k pages. */
277 /* ??? Linux doesn't actually use these, and they're deprecated in recent
278 architecture revisions. Maybe an a configure option to disable them. */
279 #define TARGET_PAGE_BITS 10