target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "exec/cpu-defs.h"
  31
  32 #include "fpu/softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiency.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cssel; /* Cache size selection.  */
 111         uint32_t c1_sys; /* System control register.  */
 112         uint32_t c1_coproc; /* Coprocessor access register.  */
 113         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 114         uint32_t c1_scr; /* secure config register.  */
 115         uint32_t c2_base0; /* MMU translation table base 0.  */
 116         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 117         uint32_t c2_base1; /* MMU translation table base 0.  */
 118         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 119         uint32_t c2_control; /* MMU translation table base control.  */
 120         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 121         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 122         uint32_t c2_data; /* MPU data cachable bits.  */
 123         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 124         uint32_t c3; /* MMU domain access control register
 125                         MPU write buffer control.  */
 126         uint32_t c5_insn; /* Fault status registers.  */
 127         uint32_t c5_data;
 128         uint32_t c6_region[8]; /* MPU base/size registers.  */
 129         uint32_t c6_insn; /* Fault address registers.  */
 130         uint32_t c6_data;
 131         uint32_t c7_par;  /* Translation result. */
 132         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 133         uint32_t c9_insn; /* Cache lockdown registers.  */
 134         uint32_t c9_data;
 135         uint32_t c9_pmcr; /* performance monitor control register */
 136         uint32_t c9_pmcnten; /* perf monitor counter enables */
 137         uint32_t c9_pmovsr; /* perf monitor overflow status */
 138         uint32_t c9_pmxevtyper; /* perf monitor event type */
 139         uint32_t c9_pmuserenr; /* perf monitor user enable */
 140         uint32_t c9_pminten; /* perf monitor interrupt enables */
 141         uint32_t c13_fcse; /* FCSE PID.  */
 142         uint32_t c13_context; /* Context ID.  */
 143         uint32_t c13_tls1; /* User RW Thread register.  */
 144         uint32_t c13_tls2; /* User RO Thread register.  */
 145         uint32_t c13_tls3; /* Privileged Thread register.  */
 146         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 147         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 148         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 149         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 150         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 151         uint32_t c15_config_base_address; /* SCU base address.  */
 152         uint32_t c15_diagnostic; /* diagnostic register */
 153         uint32_t c15_power_diagnostic;
 154         uint32_t c15_power_control; /* power control */
 155     } cp15;
 156
 157     struct {
 158         uint32_t other_sp;
 159         uint32_t vecbase;
 160         uint32_t basepri;
 161         uint32_t control;
 162         int current_sp;
 163         int exception;
 164         int pending_exception;
 165     } v7m;
 166
 167     /* Thumb-2 EE state.  */
 168     uint32_t teecr;
 169     uint32_t teehbr;
 170
 171     /* VFP coprocessor state.  */
 172     struct {
 173         float64 regs[32];
 174
 175         uint32_t xregs[16];
 176         /* We store these fpcsr fields separately for convenience.  */
 177         int vec_len;
 178         int vec_stride;
 179
 180         /* scratch space when Tn are not sufficient.  */
 181         uint32_t scratch[8];
 182
 183         /* fp_status is the "normal" fp status. standard_fp_status retains
 184          * values corresponding to the ARM "Standard FPSCR Value", ie
 185          * default-NaN, flush-to-zero, round-to-nearest and is used by
 186          * any operations (generally Neon) which the architecture defines
 187          * as controlled by the standard FPSCR value rather than the FPSCR.
 188          *
 189          * To avoid having to transfer exception bits around, we simply
 190          * say that the FPSCR cumulative exception flags are the logical
 191          * OR of the flags in the two fp statuses. This relies on the
 192          * only thing which needs to read the exception flags being
 193          * an explicit FPSCR read.
 194          */
 195         float_status fp_status;
 196         float_status standard_fp_status;
 197     } vfp;
 198     uint32_t exclusive_addr;
 199     uint32_t exclusive_val;
 200     uint32_t exclusive_high;
 201 #if defined(CONFIG_USER_ONLY)
 202     uint32_t exclusive_test;
 203     uint32_t exclusive_info;
 204 #endif
 205
 206     /* iwMMXt coprocessor state.  */
 207     struct {
 208         uint64_t regs[16];
 209         uint64_t val;
 210
 211         uint32_t cregs[16];
 212     } iwmmxt;
 213
 214     /* For mixed endian mode.  */
 215     bool bswap_code;
 216
 217 #if defined(CONFIG_USER_ONLY)
 218     /* For usermode syscall translation.  */
 219     int eabi;
 220 #endif
 221
 222     CPU_COMMON
 223
 224     /* These fields after the common ones so they are preserved on reset.  */
 225
 226     /* Internal CPU feature flags.  */
 227     uint64_t features;
 228
 229     void *nvic;
 230     const struct arm_boot_info *boot_info;
 231 } CPUARMState;
 232
 233 #include "cpu-qom.h"
 234
 235 ARMCPU *cpu_arm_init(const char *cpu_model);
 236 void arm_translate_init(void);
 237 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 238 int cpu_arm_exec(CPUARMState *s);
 239 int bank_number(int mode);
 240 void switch_mode(CPUARMState *, int);
 241 uint32_t do_arm_semihosting(CPUARMState *env);
 242
 243 /* you can call this signal handler from your SIGBUS and SIGSEGV
 244    signal handlers to inform the virtual CPU of exceptions. non zero
 245    is returned if the signal was handled by the virtual CPU.  */
 246 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 247                            void *puc);
 248 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 249                               int mmu_idx);
 250 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 251
 252 #define CPSR_M (0x1f)
 253 #define CPSR_T (1 << 5)
 254 #define CPSR_F (1 << 6)
 255 #define CPSR_I (1 << 7)
 256 #define CPSR_A (1 << 8)
 257 #define CPSR_E (1 << 9)
 258 #define CPSR_IT_2_7 (0xfc00)
 259 #define CPSR_GE (0xf << 16)
 260 #define CPSR_RESERVED (0xf << 20)
 261 #define CPSR_J (1 << 24)
 262 #define CPSR_IT_0_1 (3 << 25)
 263 #define CPSR_Q (1 << 27)
 264 #define CPSR_V (1 << 28)
 265 #define CPSR_C (1 << 29)
 266 #define CPSR_Z (1 << 30)
 267 #define CPSR_N (1 << 31)
 268 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 269
 270 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 271 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 272 /* Bits writable in user mode.  */
 273 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 274 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 275 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 276
 277 /* Return the current CPSR value.  */
 278 uint32_t cpsr_read(CPUARMState *env);
 279 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 280 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 281
 282 /* Return the current xPSR value.  */
 283 static inline uint32_t xpsr_read(CPUARMState *env)
 284 {
 285     int ZF;
 286     ZF = (env->ZF == 0);
 287     return (env->NF & 0x80000000) | (ZF << 30)
 288         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 289         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 290         | ((env->condexec_bits & 0xfc) << 8)
 291         | env->v7m.exception;
 292 }
 293
 294 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 295 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 296 {
 297     if (mask & CPSR_NZCV) {
 298         env->ZF = (~val) & CPSR_Z;
 299         env->NF = val;
 300         env->CF = (val >> 29) & 1;
 301         env->VF = (val << 3) & 0x80000000;
 302     }
 303     if (mask & CPSR_Q)
 304         env->QF = ((val & CPSR_Q) != 0);
 305     if (mask & (1 << 24))
 306         env->thumb = ((val & (1 << 24)) != 0);
 307     if (mask & CPSR_IT_0_1) {
 308         env->condexec_bits &= ~3;
 309         env->condexec_bits |= (val >> 25) & 3;
 310     }
 311     if (mask & CPSR_IT_2_7) {
 312         env->condexec_bits &= 3;
 313         env->condexec_bits |= (val >> 8) & 0xfc;
 314     }
 315     if (mask & 0x1ff) {
 316         env->v7m.exception = val & 0x1ff;
 317     }
 318 }
 319
 320 /* Return the current FPSCR value.  */
 321 uint32_t vfp_get_fpscr(CPUARMState *env);
 322 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 323
 324 enum arm_cpu_mode {
 325   ARM_CPU_MODE_USR = 0x10,
 326   ARM_CPU_MODE_FIQ = 0x11,
 327   ARM_CPU_MODE_IRQ = 0x12,
 328   ARM_CPU_MODE_SVC = 0x13,
 329   ARM_CPU_MODE_ABT = 0x17,
 330   ARM_CPU_MODE_UND = 0x1b,
 331   ARM_CPU_MODE_SYS = 0x1f
 332 };
 333
 334 /* VFP system registers.  */
 335 #define ARM_VFP_FPSID   0
 336 #define ARM_VFP_FPSCR   1
 337 #define ARM_VFP_MVFR1   6
 338 #define ARM_VFP_MVFR0   7
 339 #define ARM_VFP_FPEXC   8
 340 #define ARM_VFP_FPINST  9
 341 #define ARM_VFP_FPINST2 10
 342
 343 /* iwMMXt coprocessor control registers.  */
 344 #define ARM_IWMMXT_wCID         0
 345 #define ARM_IWMMXT_wCon         1
 346 #define ARM_IWMMXT_wCSSF        2
 347 #define ARM_IWMMXT_wCASF        3
 348 #define ARM_IWMMXT_wCGR0        8
 349 #define ARM_IWMMXT_wCGR1        9
 350 #define ARM_IWMMXT_wCGR2        10
 351 #define ARM_IWMMXT_wCGR3        11
 352
 353 /* If adding a feature bit which corresponds to a Linux ELF
 354  * HWCAP bit, remember to update the feature-bit-to-hwcap
 355  * mapping in linux-user/elfload.c:get_elf_hwcap().
 356  */
 357 enum arm_features {
 358     ARM_FEATURE_VFP,
 359     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 360     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 361     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 362     ARM_FEATURE_V6,
 363     ARM_FEATURE_V6K,
 364     ARM_FEATURE_V7,
 365     ARM_FEATURE_THUMB2,
 366     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 367     ARM_FEATURE_VFP3,
 368     ARM_FEATURE_VFP_FP16,
 369     ARM_FEATURE_NEON,
 370     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 371     ARM_FEATURE_M, /* Microcontroller profile.  */
 372     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 373     ARM_FEATURE_THUMB2EE,
 374     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 375     ARM_FEATURE_V4T,
 376     ARM_FEATURE_V5,
 377     ARM_FEATURE_STRONGARM,
 378     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 379     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 380     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 381     ARM_FEATURE_GENERIC_TIMER,
 382     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 383     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 384     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 385     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 386     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 387     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 388     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 389     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 390     ARM_FEATURE_V8,
 391 };
 392
 393 static inline int arm_feature(CPUARMState *env, int feature)
 394 {
 395     return (env->features & (1ULL << feature)) != 0;
 396 }
 397
 398 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 399
 400 /* Interface between CPU and Interrupt controller.  */
 401 void armv7m_nvic_set_pending(void *opaque, int irq);
 402 int armv7m_nvic_acknowledge_irq(void *opaque);
 403 void armv7m_nvic_complete_irq(void *opaque, int irq);
 404
 405 /* Interface for defining coprocessor registers.
 406  * Registers are defined in tables of arm_cp_reginfo structs
 407  * which are passed to define_arm_cp_regs().
 408  */
 409
 410 /* When looking up a coprocessor register we look for it
 411  * via an integer which encodes all of:
 412  *  coprocessor number
 413  *  Crn, Crm, opc1, opc2 fields
 414  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 415  *    or via MRRC/MCRR?)
 416  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 417  * (In this case crn and opc2 should be zero.)
 418  */
 419 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 420     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 421      ((crm) << 7) | ((opc1) << 3) | (opc2))
 422
 423 /* Note that these must line up with the KVM/ARM register
 424  * ID field definitions (kvm.c will check this, but we
 425  * can't just use the KVM defines here as the kvm headers
 426  * are unavailable to non-KVM-specific files)
 427  */
 428 #define CP_REG_SIZE_SHIFT 52
 429 #define CP_REG_SIZE_MASK       0x00f0000000000000ULL
 430 #define CP_REG_SIZE_U32        0x0020000000000000ULL
 431 #define CP_REG_SIZE_U64        0x0030000000000000ULL
 432 #define CP_REG_ARM             0x4000000000000000ULL
 433
 434 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 435  * version used as a key for the coprocessor register hashtable
 436  */
 437 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 438 {
 439     uint32_t cpregid = kvmid;
 440     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 441         cpregid |= (1 << 15);
 442     }
 443     return cpregid;
 444 }
 445
 446 /* Convert a truncated 32 bit hashtable key into the full
 447  * 64 bit KVM register ID.
 448  */
 449 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 450 {
 451     uint64_t kvmid = cpregid & ~(1 << 15);
 452     if (cpregid & (1 << 15)) {
 453         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 454     } else {
 455         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 456     }
 457     return kvmid;
 458 }
 459
 460 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 461  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 462  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 463  * TCG can assume the value to be constant (ie load at translate time)
 464  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 465  * indicates that the TB should not be ended after a write to this register
 466  * (the default is that the TB ends after cp writes). OVERRIDE permits
 467  * a register definition to override a previous definition for the
 468  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 469  * old must have the OVERRIDE bit set.
 470  * NO_MIGRATE indicates that this register should be ignored for migration;
 471  * (eg because any state is accessed via some other coprocessor register).
 472  */
 473 #define ARM_CP_SPECIAL 1
 474 #define ARM_CP_CONST 2
 475 #define ARM_CP_64BIT 4
 476 #define ARM_CP_SUPPRESS_TB_END 8
 477 #define ARM_CP_OVERRIDE 16
 478 #define ARM_CP_NO_MIGRATE 32
 479 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 480 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 481 #define ARM_LAST_SPECIAL ARM_CP_WFI
 482 /* Used only as a terminator for ARMCPRegInfo lists */
 483 #define ARM_CP_SENTINEL 0xffff
 484 /* Mask of only the flag bits in a type field */
 485 #define ARM_CP_FLAG_MASK 0x3f
 486
 487 /* Return true if cptype is a valid type field. This is used to try to
 488  * catch errors where the sentinel has been accidentally left off the end
 489  * of a list of registers.
 490  */
 491 static inline bool cptype_valid(int cptype)
 492 {
 493     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 494         || ((cptype & ARM_CP_SPECIAL) &&
 495             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 496 }
 497
 498 /* Access rights:
 499  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 500  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 501  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 502  * (ie any of the privileged modes in Secure state, or Monitor mode).
 503  * If a register is accessible in one privilege level it's always accessible
 504  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 505  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 506  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 507  * terminology a little and call this PL3.
 508  *
 509  * If access permissions for a register are more complex than can be
 510  * described with these bits, then use a laxer set of restrictions, and
 511  * do the more restrictive/complex check inside a helper function.
 512  */
 513 #define PL3_R 0x80
 514 #define PL3_W 0x40
 515 #define PL2_R (0x20 | PL3_R)
 516 #define PL2_W (0x10 | PL3_W)
 517 #define PL1_R (0x08 | PL2_R)
 518 #define PL1_W (0x04 | PL2_W)
 519 #define PL0_R (0x02 | PL1_R)
 520 #define PL0_W (0x01 | PL1_W)
 521
 522 #define PL3_RW (PL3_R | PL3_W)
 523 #define PL2_RW (PL2_R | PL2_W)
 524 #define PL1_RW (PL1_R | PL1_W)
 525 #define PL0_RW (PL0_R | PL0_W)
 526
 527 static inline int arm_current_pl(CPUARMState *env)
 528 {
 529     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 530         return 0;
 531     }
 532     /* We don't currently implement the Virtualization or TrustZone
 533      * extensions, so PL2 and PL3 don't exist for us.
 534      */
 535     return 1;
 536 }
 537
 538 typedef struct ARMCPRegInfo ARMCPRegInfo;
 539
 540 /* Access functions for coprocessor registers. These should return
 541  * 0 on success, or one of the EXCP_* constants if access should cause
 542  * an exception (in which case *value is not written).
 543  */
 544 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 545                      uint64_t *value);
 546 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 547                       uint64_t value);
 548 /* Hook function for register reset */
 549 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 550
 551 #define CP_ANY 0xff
 552
 553 /* Definition of an ARM coprocessor register */
 554 struct ARMCPRegInfo {
 555     /* Name of register (useful mainly for debugging, need not be unique) */
 556     const char *name;
 557     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 558      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 559      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 560      * will be decoded to this register. The register read and write
 561      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 562      * used by the program, so it is possible to register a wildcard and
 563      * then behave differently on read/write if necessary.
 564      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 565      * must both be zero.
 566      */
 567     uint8_t cp;
 568     uint8_t crn;
 569     uint8_t crm;
 570     uint8_t opc1;
 571     uint8_t opc2;
 572     /* Register type: ARM_CP_* bits/values */
 573     int type;
 574     /* Access rights: PL*_[RW] */
 575     int access;
 576     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 577      * this register was defined: can be used to hand data through to the
 578      * register read/write functions, since they are passed the ARMCPRegInfo*.
 579      */
 580     void *opaque;
 581     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 582      * fieldoffset is non-zero, the reset value of the register.
 583      */
 584     uint64_t resetvalue;
 585     /* Offset of the field in CPUARMState for this register. This is not
 586      * needed if either:
 587      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 588      *  2. both readfn and writefn are specified
 589      */
 590     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 591     /* Function for handling reads of this register. If NULL, then reads
 592      * will be done by loading from the offset into CPUARMState specified
 593      * by fieldoffset.
 594      */
 595     CPReadFn *readfn;
 596     /* Function for handling writes of this register. If NULL, then writes
 597      * will be done by writing to the offset into CPUARMState specified
 598      * by fieldoffset.
 599      */
 600     CPWriteFn *writefn;
 601     /* Function for doing a "raw" read; used when we need to copy
 602      * coprocessor state to the kernel for KVM or out for
 603      * migration. This only needs to be provided if there is also a
 604      * readfn and it makes an access permission check.
 605      */
 606     CPReadFn *raw_readfn;
 607     /* Function for doing a "raw" write; used when we need to copy KVM
 608      * kernel coprocessor state into userspace, or for inbound
 609      * migration. This only needs to be provided if there is also a
 610      * writefn and it makes an access permission check or masks out
 611      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 612      */
 613     CPWriteFn *raw_writefn;
 614     /* Function for resetting the register. If NULL, then reset will be done
 615      * by writing resetvalue to the field specified in fieldoffset. If
 616      * fieldoffset is 0 then no reset will be done.
 617      */
 618     CPResetFn *resetfn;
 619 };
 620
 621 /* Macros which are lvalues for the field in CPUARMState for the
 622  * ARMCPRegInfo *ri.
 623  */
 624 #define CPREG_FIELD32(env, ri) \
 625     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 626 #define CPREG_FIELD64(env, ri) \
 627     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 628
 629 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 630
 631 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 632                                     const ARMCPRegInfo *regs, void *opaque);
 633 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 634                                        const ARMCPRegInfo *regs, void *opaque);
 635 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 636 {
 637     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 638 }
 639 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 640 {
 641     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 642 }
 643 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 644
 645 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 646 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 647                         uint64_t value);
 648 /* CPReadFn that can be used for read-as-zero behaviour */
 649 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 650
 651 static inline bool cp_access_ok(CPUARMState *env,
 652                                 const ARMCPRegInfo *ri, int isread)
 653 {
 654     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 655 }
 656
 657 /**
 658  * write_list_to_cpustate
 659  * @cpu: ARMCPU
 660  *
 661  * For each register listed in the ARMCPU cpreg_indexes list, write
 662  * its value from the cpreg_values list into the ARMCPUState structure.
 663  * This updates TCG's working data structures from KVM data or
 664  * from incoming migration state.
 665  *
 666  * Returns: true if all register values were updated correctly,
 667  * false if some register was unknown or could not be written.
 668  * Note that we do not stop early on failure -- we will attempt
 669  * writing all registers in the list.
 670  */
 671 bool write_list_to_cpustate(ARMCPU *cpu);
 672
 673 /**
 674  * write_cpustate_to_list:
 675  * @cpu: ARMCPU
 676  *
 677  * For each register listed in the ARMCPU cpreg_indexes list, write
 678  * its value from the ARMCPUState structure into the cpreg_values list.
 679  * This is used to copy info from TCG's working data structures into
 680  * KVM or for outbound migration.
 681  *
 682  * Returns: true if all register values were read correctly,
 683  * false if some register was unknown or could not be read.
 684  * Note that we do not stop early on failure -- we will attempt
 685  * reading all registers in the list.
 686  */
 687 bool write_cpustate_to_list(ARMCPU *cpu);
 688
 689 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 690    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 691    conventional cores (ie. Application or Realtime profile).  */
 692
 693 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 694
 695 #define ARM_CPUID_TI915T      0x54029152
 696 #define ARM_CPUID_TI925T      0x54029252
 697
 698 #if defined(CONFIG_USER_ONLY)
 699 #define TARGET_PAGE_BITS 12
 700 #else
 701 /* The ARM MMU allows 1k pages.  */
 702 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 703    architecture revisions.  Maybe a configure option to disable them.  */
 704 #define TARGET_PAGE_BITS 10
 705 #endif
 706
 707 #define TARGET_PHYS_ADDR_SPACE_BITS 40
 708 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 709
 710 static inline CPUARMState *cpu_init(const char *cpu_model)
 711 {
 712     ARMCPU *cpu = cpu_arm_init(cpu_model);
 713     if (cpu) {
 714         return &cpu->env;
 715     }
 716     return NULL;
 717 }
 718
 719 #define cpu_exec cpu_arm_exec
 720 #define cpu_gen_code cpu_arm_gen_code
 721 #define cpu_signal_handler cpu_arm_signal_handler
 722 #define cpu_list arm_cpu_list
 723
 724 /* MMU modes definitions */
 725 #define MMU_MODE0_SUFFIX _kernel
 726 #define MMU_MODE1_SUFFIX _user
 727 #define MMU_USER_IDX 1
 728 static inline int cpu_mmu_index (CPUARMState *env)
 729 {
 730     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 731 }
 732
 733 #include "exec/cpu-all.h"
 734
 735 /* Bit usage in the TB flags field: */
 736 #define ARM_TBFLAG_THUMB_SHIFT      0
 737 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 738 #define ARM_TBFLAG_VECLEN_SHIFT     1
 739 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 740 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 741 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 742 #define ARM_TBFLAG_PRIV_SHIFT       6
 743 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 744 #define ARM_TBFLAG_VFPEN_SHIFT      7
 745 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 746 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 747 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 748 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 749 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 750 /* Bits 31..17 are currently unused. */
 751
 752 /* some convenience accessor macros */
 753 #define ARM_TBFLAG_THUMB(F) \
 754     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 755 #define ARM_TBFLAG_VECLEN(F) \
 756     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 757 #define ARM_TBFLAG_VECSTRIDE(F) \
 758     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 759 #define ARM_TBFLAG_PRIV(F) \
 760     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 761 #define ARM_TBFLAG_VFPEN(F) \
 762     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 763 #define ARM_TBFLAG_CONDEXEC(F) \
 764     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 765 #define ARM_TBFLAG_BSWAP_CODE(F) \
 766     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 767
 768 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 769                                         target_ulong *cs_base, int *flags)
 770 {
 771     int privmode;
 772     *pc = env->regs[15];
 773     *cs_base = 0;
 774     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 775         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 776         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 777         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 778         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 779     if (arm_feature(env, ARM_FEATURE_M)) {
 780         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 781     } else {
 782         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 783     }
 784     if (privmode) {
 785         *flags |= ARM_TBFLAG_PRIV_MASK;
 786     }
 787     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 788         *flags |= ARM_TBFLAG_VFPEN_MASK;
 789     }
 790 }
 791
 792 static inline bool cpu_has_work(CPUState *cpu)
 793 {
 794     return cpu->interrupt_request &
 795         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 796 }
 797
 798 #include "exec/exec-all.h"
 799
 800 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 801 {
 802     env->regs[15] = tb->pc;
 803 }
 804
 805 /* Load an instruction and return it in the standard little-endian order */
 806 static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
 807                                     bool do_swap)
 808 {
 809     uint32_t insn = cpu_ldl_code(env, addr);
 810     if (do_swap) {
 811         return bswap32(insn);
 812     }
 813     return insn;
 814 }
 815
 816 /* Ditto, for a halfword (Thumb) instruction */
 817 static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
 818                                      bool do_swap)
 819 {
 820     uint16_t insn = cpu_lduw_code(env, addr);
 821     if (do_swap) {
 822         return bswap16(insn);
 823     }
 824     return insn;
 825 }
 826
 827 #endif