target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cssel; /* Cache size selection.  */
 111         uint32_t c1_sys; /* System control register.  */
 112         uint32_t c1_coproc; /* Coprocessor access register.  */
 113         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 114         uint32_t c1_scr; /* secure config register.  */
 115         uint32_t c2_base0; /* MMU translation table base 0.  */
 116         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 117         uint32_t c2_base1; /* MMU translation table base 0.  */
 118         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 119         uint32_t c2_control; /* MMU translation table base control.  */
 120         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 121         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 122         uint32_t c2_data; /* MPU data cachable bits.  */
 123         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 124         uint32_t c3; /* MMU domain access control register
 125                         MPU write buffer control.  */
 126         uint32_t c5_insn; /* Fault status registers.  */
 127         uint32_t c5_data;
 128         uint32_t c6_region[8]; /* MPU base/size registers.  */
 129         uint32_t c6_insn; /* Fault address registers.  */
 130         uint32_t c6_data;
 131         uint32_t c7_par;  /* Translation result. */
 132         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 133         uint32_t c9_insn; /* Cache lockdown registers.  */
 134         uint32_t c9_data;
 135         uint32_t c9_pmcr; /* performance monitor control register */
 136         uint32_t c9_pmcnten; /* perf monitor counter enables */
 137         uint32_t c9_pmovsr; /* perf monitor overflow status */
 138         uint32_t c9_pmxevtyper; /* perf monitor event type */
 139         uint32_t c9_pmuserenr; /* perf monitor user enable */
 140         uint32_t c9_pminten; /* perf monitor interrupt enables */
 141         uint32_t c13_fcse; /* FCSE PID.  */
 142         uint32_t c13_context; /* Context ID.  */
 143         uint32_t c13_tls1; /* User RW Thread register.  */
 144         uint32_t c13_tls2; /* User RO Thread register.  */
 145         uint32_t c13_tls3; /* Privileged Thread register.  */
 146         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 147         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 148         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 149         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 150         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 151         uint32_t c15_config_base_address; /* SCU base address.  */
 152         uint32_t c15_diagnostic; /* diagnostic register */
 153         uint32_t c15_power_diagnostic;
 154         uint32_t c15_power_control; /* power control */
 155     } cp15;
 156
 157     struct {
 158         uint32_t other_sp;
 159         uint32_t vecbase;
 160         uint32_t basepri;
 161         uint32_t control;
 162         int current_sp;
 163         int exception;
 164         int pending_exception;
 165     } v7m;
 166
 167     /* Thumb-2 EE state.  */
 168     uint32_t teecr;
 169     uint32_t teehbr;
 170
 171     /* VFP coprocessor state.  */
 172     struct {
 173         float64 regs[32];
 174
 175         uint32_t xregs[16];
 176         /* We store these fpcsr fields separately for convenience.  */
 177         int vec_len;
 178         int vec_stride;
 179
 180         /* scratch space when Tn are not sufficient.  */
 181         uint32_t scratch[8];
 182
 183         /* fp_status is the "normal" fp status. standard_fp_status retains
 184          * values corresponding to the ARM "Standard FPSCR Value", ie
 185          * default-NaN, flush-to-zero, round-to-nearest and is used by
 186          * any operations (generally Neon) which the architecture defines
 187          * as controlled by the standard FPSCR value rather than the FPSCR.
 188          *
 189          * To avoid having to transfer exception bits around, we simply
 190          * say that the FPSCR cumulative exception flags are the logical
 191          * OR of the flags in the two fp statuses. This relies on the
 192          * only thing which needs to read the exception flags being
 193          * an explicit FPSCR read.
 194          */
 195         float_status fp_status;
 196         float_status standard_fp_status;
 197     } vfp;
 198     uint32_t exclusive_addr;
 199     uint32_t exclusive_val;
 200     uint32_t exclusive_high;
 201 #if defined(CONFIG_USER_ONLY)
 202     uint32_t exclusive_test;
 203     uint32_t exclusive_info;
 204 #endif
 205
 206     /* iwMMXt coprocessor state.  */
 207     struct {
 208         uint64_t regs[16];
 209         uint64_t val;
 210
 211         uint32_t cregs[16];
 212     } iwmmxt;
 213
 214     /* For mixed endian mode.  */
 215     bool bswap_code;
 216
 217 #if defined(CONFIG_USER_ONLY)
 218     /* For usermode syscall translation.  */
 219     int eabi;
 220 #endif
 221
 222     CPU_COMMON
 223
 224     /* These fields after the common ones so they are preserved on reset.  */
 225
 226     /* Internal CPU feature flags.  */
 227     uint64_t features;
 228
 229     void *nvic;
 230     const struct arm_boot_info *boot_info;
 231 } CPUARMState;
 232
 233 #include "cpu-qom.h"
 234
 235 ARMCPU *cpu_arm_init(const char *cpu_model);
 236 void arm_translate_init(void);
 237 int cpu_arm_exec(CPUARMState *s);
 238 void do_interrupt(CPUARMState *);
 239 void switch_mode(CPUARMState *, int);
 240 uint32_t do_arm_semihosting(CPUARMState *env);
 241
 242 /* you can call this signal handler from your SIGBUS and SIGSEGV
 243    signal handlers to inform the virtual CPU of exceptions. non zero
 244    is returned if the signal was handled by the virtual CPU.  */
 245 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 246                            void *puc);
 247 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 248                               int mmu_idx);
 249 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 250
 251 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 252 {
 253   env->cp15.c13_tls2 = newtls;
 254 }
 255
 256 #define CPSR_M (0x1f)
 257 #define CPSR_T (1 << 5)
 258 #define CPSR_F (1 << 6)
 259 #define CPSR_I (1 << 7)
 260 #define CPSR_A (1 << 8)
 261 #define CPSR_E (1 << 9)
 262 #define CPSR_IT_2_7 (0xfc00)
 263 #define CPSR_GE (0xf << 16)
 264 #define CPSR_RESERVED (0xf << 20)
 265 #define CPSR_J (1 << 24)
 266 #define CPSR_IT_0_1 (3 << 25)
 267 #define CPSR_Q (1 << 27)
 268 #define CPSR_V (1 << 28)
 269 #define CPSR_C (1 << 29)
 270 #define CPSR_Z (1 << 30)
 271 #define CPSR_N (1 << 31)
 272 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 273
 274 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 275 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 276 /* Bits writable in user mode.  */
 277 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 278 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 279 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 280
 281 /* Return the current CPSR value.  */
 282 uint32_t cpsr_read(CPUARMState *env);
 283 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 284 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 285
 286 /* Return the current xPSR value.  */
 287 static inline uint32_t xpsr_read(CPUARMState *env)
 288 {
 289     int ZF;
 290     ZF = (env->ZF == 0);
 291     return (env->NF & 0x80000000) | (ZF << 30)
 292         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 293         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 294         | ((env->condexec_bits & 0xfc) << 8)
 295         | env->v7m.exception;
 296 }
 297
 298 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 299 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 300 {
 301     if (mask & CPSR_NZCV) {
 302         env->ZF = (~val) & CPSR_Z;
 303         env->NF = val;
 304         env->CF = (val >> 29) & 1;
 305         env->VF = (val << 3) & 0x80000000;
 306     }
 307     if (mask & CPSR_Q)
 308         env->QF = ((val & CPSR_Q) != 0);
 309     if (mask & (1 << 24))
 310         env->thumb = ((val & (1 << 24)) != 0);
 311     if (mask & CPSR_IT_0_1) {
 312         env->condexec_bits &= ~3;
 313         env->condexec_bits |= (val >> 25) & 3;
 314     }
 315     if (mask & CPSR_IT_2_7) {
 316         env->condexec_bits &= 3;
 317         env->condexec_bits |= (val >> 8) & 0xfc;
 318     }
 319     if (mask & 0x1ff) {
 320         env->v7m.exception = val & 0x1ff;
 321     }
 322 }
 323
 324 /* Return the current FPSCR value.  */
 325 uint32_t vfp_get_fpscr(CPUARMState *env);
 326 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 327
 328 enum arm_cpu_mode {
 329   ARM_CPU_MODE_USR = 0x10,
 330   ARM_CPU_MODE_FIQ = 0x11,
 331   ARM_CPU_MODE_IRQ = 0x12,
 332   ARM_CPU_MODE_SVC = 0x13,
 333   ARM_CPU_MODE_ABT = 0x17,
 334   ARM_CPU_MODE_UND = 0x1b,
 335   ARM_CPU_MODE_SYS = 0x1f
 336 };
 337
 338 /* VFP system registers.  */
 339 #define ARM_VFP_FPSID   0
 340 #define ARM_VFP_FPSCR   1
 341 #define ARM_VFP_MVFR1   6
 342 #define ARM_VFP_MVFR0   7
 343 #define ARM_VFP_FPEXC   8
 344 #define ARM_VFP_FPINST  9
 345 #define ARM_VFP_FPINST2 10
 346
 347 /* iwMMXt coprocessor control registers.  */
 348 #define ARM_IWMMXT_wCID         0
 349 #define ARM_IWMMXT_wCon         1
 350 #define ARM_IWMMXT_wCSSF        2
 351 #define ARM_IWMMXT_wCASF        3
 352 #define ARM_IWMMXT_wCGR0        8
 353 #define ARM_IWMMXT_wCGR1        9
 354 #define ARM_IWMMXT_wCGR2        10
 355 #define ARM_IWMMXT_wCGR3        11
 356
 357 /* If adding a feature bit which corresponds to a Linux ELF
 358  * HWCAP bit, remember to update the feature-bit-to-hwcap
 359  * mapping in linux-user/elfload.c:get_elf_hwcap().
 360  */
 361 enum arm_features {
 362     ARM_FEATURE_VFP,
 363     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 364     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 365     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 366     ARM_FEATURE_V6,
 367     ARM_FEATURE_V6K,
 368     ARM_FEATURE_V7,
 369     ARM_FEATURE_THUMB2,
 370     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 371     ARM_FEATURE_VFP3,
 372     ARM_FEATURE_VFP_FP16,
 373     ARM_FEATURE_NEON,
 374     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 375     ARM_FEATURE_M, /* Microcontroller profile.  */
 376     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 377     ARM_FEATURE_THUMB2EE,
 378     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 379     ARM_FEATURE_V4T,
 380     ARM_FEATURE_V5,
 381     ARM_FEATURE_STRONGARM,
 382     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 383     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 384     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 385     ARM_FEATURE_GENERIC_TIMER,
 386     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 387     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 388     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 389     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 390     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 391     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 392     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 393     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 394 };
 395
 396 static inline int arm_feature(CPUARMState *env, int feature)
 397 {
 398     return (env->features & (1ULL << feature)) != 0;
 399 }
 400
 401 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 402
 403 /* Interface between CPU and Interrupt controller.  */
 404 void armv7m_nvic_set_pending(void *opaque, int irq);
 405 int armv7m_nvic_acknowledge_irq(void *opaque);
 406 void armv7m_nvic_complete_irq(void *opaque, int irq);
 407
 408 /* Interface for defining coprocessor registers.
 409  * Registers are defined in tables of arm_cp_reginfo structs
 410  * which are passed to define_arm_cp_regs().
 411  */
 412
 413 /* When looking up a coprocessor register we look for it
 414  * via an integer which encodes all of:
 415  *  coprocessor number
 416  *  Crn, Crm, opc1, opc2 fields
 417  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 418  *    or via MRRC/MCRR?)
 419  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 420  * (In this case crn and opc2 should be zero.)
 421  */
 422 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 423     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 424      ((crm) << 7) | ((opc1) << 3) | (opc2))
 425
 426 #define DECODE_CPREG_CRN(enc) (((enc) >> 7) & 0xf)
 427
 428 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 429  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 430  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 431  * TCG can assume the value to be constant (ie load at translate time)
 432  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 433  * indicates that the TB should not be ended after a write to this register
 434  * (the default is that the TB ends after cp writes). OVERRIDE permits
 435  * a register definition to override a previous definition for the
 436  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 437  * old must have the OVERRIDE bit set.
 438  */
 439 #define ARM_CP_SPECIAL 1
 440 #define ARM_CP_CONST 2
 441 #define ARM_CP_64BIT 4
 442 #define ARM_CP_SUPPRESS_TB_END 8
 443 #define ARM_CP_OVERRIDE 16
 444 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 445 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 446 #define ARM_LAST_SPECIAL ARM_CP_WFI
 447 /* Used only as a terminator for ARMCPRegInfo lists */
 448 #define ARM_CP_SENTINEL 0xffff
 449 /* Mask of only the flag bits in a type field */
 450 #define ARM_CP_FLAG_MASK 0x1f
 451
 452 /* Return true if cptype is a valid type field. This is used to try to
 453  * catch errors where the sentinel has been accidentally left off the end
 454  * of a list of registers.
 455  */
 456 static inline bool cptype_valid(int cptype)
 457 {
 458     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 459         || ((cptype & ARM_CP_SPECIAL) &&
 460             (cptype <= ARM_LAST_SPECIAL));
 461 }
 462
 463 /* Access rights:
 464  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 465  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 466  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 467  * (ie any of the privileged modes in Secure state, or Monitor mode).
 468  * If a register is accessible in one privilege level it's always accessible
 469  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 470  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 471  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 472  * terminology a little and call this PL3.
 473  *
 474  * If access permissions for a register are more complex than can be
 475  * described with these bits, then use a laxer set of restrictions, and
 476  * do the more restrictive/complex check inside a helper function.
 477  */
 478 #define PL3_R 0x80
 479 #define PL3_W 0x40
 480 #define PL2_R (0x20 | PL3_R)
 481 #define PL2_W (0x10 | PL3_W)
 482 #define PL1_R (0x08 | PL2_R)
 483 #define PL1_W (0x04 | PL2_W)
 484 #define PL0_R (0x02 | PL1_R)
 485 #define PL0_W (0x01 | PL1_W)
 486
 487 #define PL3_RW (PL3_R | PL3_W)
 488 #define PL2_RW (PL2_R | PL2_W)
 489 #define PL1_RW (PL1_R | PL1_W)
 490 #define PL0_RW (PL0_R | PL0_W)
 491
 492 static inline int arm_current_pl(CPUARMState *env)
 493 {
 494     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 495         return 0;
 496     }
 497     /* We don't currently implement the Virtualization or TrustZone
 498      * extensions, so PL2 and PL3 don't exist for us.
 499      */
 500     return 1;
 501 }
 502
 503 typedef struct ARMCPRegInfo ARMCPRegInfo;
 504
 505 /* Access functions for coprocessor registers. These should return
 506  * 0 on success, or one of the EXCP_* constants if access should cause
 507  * an exception (in which case *value is not written).
 508  */
 509 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 510                      uint64_t *value);
 511 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 512                       uint64_t value);
 513 /* Hook function for register reset */
 514 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 515
 516 #define CP_ANY 0xff
 517
 518 /* Definition of an ARM coprocessor register */
 519 struct ARMCPRegInfo {
 520     /* Name of register (useful mainly for debugging, need not be unique) */
 521     const char *name;
 522     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 523      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 524      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 525      * will be decoded to this register. The register read and write
 526      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 527      * used by the program, so it is possible to register a wildcard and
 528      * then behave differently on read/write if necessary.
 529      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 530      * must both be zero.
 531      */
 532     uint8_t cp;
 533     uint8_t crn;
 534     uint8_t crm;
 535     uint8_t opc1;
 536     uint8_t opc2;
 537     /* Register type: ARM_CP_* bits/values */
 538     int type;
 539     /* Access rights: PL*_[RW] */
 540     int access;
 541     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 542      * this register was defined: can be used to hand data through to the
 543      * register read/write functions, since they are passed the ARMCPRegInfo*.
 544      */
 545     void *opaque;
 546     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 547      * fieldoffset is non-zero, the reset value of the register.
 548      */
 549     uint64_t resetvalue;
 550     /* Offset of the field in CPUARMState for this register. This is not
 551      * needed if either:
 552      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 553      *  2. both readfn and writefn are specified
 554      */
 555     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 556     /* Function for handling reads of this register. If NULL, then reads
 557      * will be done by loading from the offset into CPUARMState specified
 558      * by fieldoffset.
 559      */
 560     CPReadFn *readfn;
 561     /* Function for handling writes of this register. If NULL, then writes
 562      * will be done by writing to the offset into CPUARMState specified
 563      * by fieldoffset.
 564      */
 565     CPWriteFn *writefn;
 566     /* Function for resetting the register. If NULL, then reset will be done
 567      * by writing resetvalue to the field specified in fieldoffset. If
 568      * fieldoffset is 0 then no reset will be done.
 569      */
 570     CPResetFn *resetfn;
 571 };
 572
 573 /* Macros which are lvalues for the field in CPUARMState for the
 574  * ARMCPRegInfo *ri.
 575  */
 576 #define CPREG_FIELD32(env, ri) \
 577     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 578 #define CPREG_FIELD64(env, ri) \
 579     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 580
 581 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 582
 583 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 584                                     const ARMCPRegInfo *regs, void *opaque);
 585 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 586                                        const ARMCPRegInfo *regs, void *opaque);
 587 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 588 {
 589     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 590 }
 591 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 592 {
 593     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 594 }
 595 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 596
 597 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 598 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 599                         uint64_t value);
 600 /* CPReadFn that can be used for read-as-zero behaviour */
 601 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 602
 603 static inline bool cp_access_ok(CPUARMState *env,
 604                                 const ARMCPRegInfo *ri, int isread)
 605 {
 606     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 607 }
 608
 609 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 610    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 611    conventional cores (ie. Application or Realtime profile).  */
 612
 613 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 614
 615 #define ARM_CPUID_TI915T      0x54029152
 616 #define ARM_CPUID_TI925T      0x54029252
 617
 618 #if defined(CONFIG_USER_ONLY)
 619 #define TARGET_PAGE_BITS 12
 620 #else
 621 /* The ARM MMU allows 1k pages.  */
 622 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 623    architecture revisions.  Maybe a configure option to disable them.  */
 624 #define TARGET_PAGE_BITS 10
 625 #endif
 626
 627 #define TARGET_PHYS_ADDR_SPACE_BITS 40
 628 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 629
 630 static inline CPUARMState *cpu_init(const char *cpu_model)
 631 {
 632     ARMCPU *cpu = cpu_arm_init(cpu_model);
 633     if (cpu) {
 634         return &cpu->env;
 635     }
 636     return NULL;
 637 }
 638
 639 #define cpu_exec cpu_arm_exec
 640 #define cpu_gen_code cpu_arm_gen_code
 641 #define cpu_signal_handler cpu_arm_signal_handler
 642 #define cpu_list arm_cpu_list
 643
 644 #define CPU_SAVE_VERSION 9
 645
 646 /* MMU modes definitions */
 647 #define MMU_MODE0_SUFFIX _kernel
 648 #define MMU_MODE1_SUFFIX _user
 649 #define MMU_USER_IDX 1
 650 static inline int cpu_mmu_index (CPUARMState *env)
 651 {
 652     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 653 }
 654
 655 #if defined(CONFIG_USER_ONLY)
 656 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 657 {
 658     if (newsp)
 659         env->regs[13] = newsp;
 660     env->regs[0] = 0;
 661 }
 662 #endif
 663
 664 #include "cpu-all.h"
 665
 666 /* Bit usage in the TB flags field: */
 667 #define ARM_TBFLAG_THUMB_SHIFT      0
 668 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 669 #define ARM_TBFLAG_VECLEN_SHIFT     1
 670 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 671 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 672 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 673 #define ARM_TBFLAG_PRIV_SHIFT       6
 674 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 675 #define ARM_TBFLAG_VFPEN_SHIFT      7
 676 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 677 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 678 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 679 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 680 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 681 /* Bits 31..17 are currently unused. */
 682
 683 /* some convenience accessor macros */
 684 #define ARM_TBFLAG_THUMB(F) \
 685     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 686 #define ARM_TBFLAG_VECLEN(F) \
 687     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 688 #define ARM_TBFLAG_VECSTRIDE(F) \
 689     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 690 #define ARM_TBFLAG_PRIV(F) \
 691     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 692 #define ARM_TBFLAG_VFPEN(F) \
 693     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 694 #define ARM_TBFLAG_CONDEXEC(F) \
 695     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 696 #define ARM_TBFLAG_BSWAP_CODE(F) \
 697     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 698
 699 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 700                                         target_ulong *cs_base, int *flags)
 701 {
 702     int privmode;
 703     *pc = env->regs[15];
 704     *cs_base = 0;
 705     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 706         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 707         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 708         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 709         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 710     if (arm_feature(env, ARM_FEATURE_M)) {
 711         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 712     } else {
 713         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 714     }
 715     if (privmode) {
 716         *flags |= ARM_TBFLAG_PRIV_MASK;
 717     }
 718     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 719         *flags |= ARM_TBFLAG_VFPEN_MASK;
 720     }
 721 }
 722
 723 static inline bool cpu_has_work(CPUARMState *env)
 724 {
 725     return env->interrupt_request &
 726         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 727 }
 728
 729 #include "exec-all.h"
 730
 731 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 732 {
 733     env->regs[15] = tb->pc;
 734 }
 735
 736 /* Load an instruction and return it in the standard little-endian order */
 737 static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
 738 {
 739     uint32_t insn = ldl_code(addr);
 740     if (do_swap) {
 741         return bswap32(insn);
 742     }
 743     return insn;
 744 }
 745
 746 /* Ditto, for a halfword (Thumb) instruction */
 747 static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
 748 {
 749     uint16_t insn = lduw_code(addr);
 750     if (do_swap) {
 751         return bswap16(insn);
 752     }
 753     return insn;
 754 }
 755
 756 #endif