target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cssel; /* Cache size selection.  */
 111         uint32_t c1_sys; /* System control register.  */
 112         uint32_t c1_coproc; /* Coprocessor access register.  */
 113         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 114         uint32_t c1_scr; /* secure config register.  */
 115         uint32_t c2_base0; /* MMU translation table base 0.  */
 116         uint32_t c2_base1; /* MMU translation table base 1.  */
 117         uint32_t c2_control; /* MMU translation table base control.  */
 118         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 119         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 120         uint32_t c2_data; /* MPU data cachable bits.  */
 121         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 122         uint32_t c3; /* MMU domain access control register
 123                         MPU write buffer control.  */
 124         uint32_t c5_insn; /* Fault status registers.  */
 125         uint32_t c5_data;
 126         uint32_t c6_region[8]; /* MPU base/size registers.  */
 127         uint32_t c6_insn; /* Fault address registers.  */
 128         uint32_t c6_data;
 129         uint32_t c7_par;  /* Translation result. */
 130         uint32_t c9_insn; /* Cache lockdown registers.  */
 131         uint32_t c9_data;
 132         uint32_t c9_pmcr; /* performance monitor control register */
 133         uint32_t c9_pmcnten; /* perf monitor counter enables */
 134         uint32_t c9_pmovsr; /* perf monitor overflow status */
 135         uint32_t c9_pmxevtyper; /* perf monitor event type */
 136         uint32_t c9_pmuserenr; /* perf monitor user enable */
 137         uint32_t c9_pminten; /* perf monitor interrupt enables */
 138         uint32_t c13_fcse; /* FCSE PID.  */
 139         uint32_t c13_context; /* Context ID.  */
 140         uint32_t c13_tls1; /* User RW Thread register.  */
 141         uint32_t c13_tls2; /* User RO Thread register.  */
 142         uint32_t c13_tls3; /* Privileged Thread register.  */
 143         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 144         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 145         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 146         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 147         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 148         uint32_t c15_config_base_address; /* SCU base address.  */
 149         uint32_t c15_diagnostic; /* diagnostic register */
 150         uint32_t c15_power_diagnostic;
 151         uint32_t c15_power_control; /* power control */
 152     } cp15;
 153
 154     struct {
 155         uint32_t other_sp;
 156         uint32_t vecbase;
 157         uint32_t basepri;
 158         uint32_t control;
 159         int current_sp;
 160         int exception;
 161         int pending_exception;
 162     } v7m;
 163
 164     /* Thumb-2 EE state.  */
 165     uint32_t teecr;
 166     uint32_t teehbr;
 167
 168     /* VFP coprocessor state.  */
 169     struct {
 170         float64 regs[32];
 171
 172         uint32_t xregs[16];
 173         /* We store these fpcsr fields separately for convenience.  */
 174         int vec_len;
 175         int vec_stride;
 176
 177         /* scratch space when Tn are not sufficient.  */
 178         uint32_t scratch[8];
 179
 180         /* fp_status is the "normal" fp status. standard_fp_status retains
 181          * values corresponding to the ARM "Standard FPSCR Value", ie
 182          * default-NaN, flush-to-zero, round-to-nearest and is used by
 183          * any operations (generally Neon) which the architecture defines
 184          * as controlled by the standard FPSCR value rather than the FPSCR.
 185          *
 186          * To avoid having to transfer exception bits around, we simply
 187          * say that the FPSCR cumulative exception flags are the logical
 188          * OR of the flags in the two fp statuses. This relies on the
 189          * only thing which needs to read the exception flags being
 190          * an explicit FPSCR read.
 191          */
 192         float_status fp_status;
 193         float_status standard_fp_status;
 194     } vfp;
 195     uint32_t exclusive_addr;
 196     uint32_t exclusive_val;
 197     uint32_t exclusive_high;
 198 #if defined(CONFIG_USER_ONLY)
 199     uint32_t exclusive_test;
 200     uint32_t exclusive_info;
 201 #endif
 202
 203     /* iwMMXt coprocessor state.  */
 204     struct {
 205         uint64_t regs[16];
 206         uint64_t val;
 207
 208         uint32_t cregs[16];
 209     } iwmmxt;
 210
 211     /* For mixed endian mode.  */
 212     bool bswap_code;
 213
 214 #if defined(CONFIG_USER_ONLY)
 215     /* For usermode syscall translation.  */
 216     int eabi;
 217 #endif
 218
 219     CPU_COMMON
 220
 221     /* These fields after the common ones so they are preserved on reset.  */
 222
 223     /* Internal CPU feature flags.  */
 224     uint32_t features;
 225
 226     void *nvic;
 227     const struct arm_boot_info *boot_info;
 228 } CPUARMState;
 229
 230 #include "cpu-qom.h"
 231
 232 ARMCPU *cpu_arm_init(const char *cpu_model);
 233 void arm_translate_init(void);
 234 int cpu_arm_exec(CPUARMState *s);
 235 void do_interrupt(CPUARMState *);
 236 void switch_mode(CPUARMState *, int);
 237 uint32_t do_arm_semihosting(CPUARMState *env);
 238
 239 /* you can call this signal handler from your SIGBUS and SIGSEGV
 240    signal handlers to inform the virtual CPU of exceptions. non zero
 241    is returned if the signal was handled by the virtual CPU.  */
 242 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 243                            void *puc);
 244 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 245                               int mmu_idx);
 246 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 247
 248 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 249 {
 250   env->cp15.c13_tls2 = newtls;
 251 }
 252
 253 #define CPSR_M (0x1f)
 254 #define CPSR_T (1 << 5)
 255 #define CPSR_F (1 << 6)
 256 #define CPSR_I (1 << 7)
 257 #define CPSR_A (1 << 8)
 258 #define CPSR_E (1 << 9)
 259 #define CPSR_IT_2_7 (0xfc00)
 260 #define CPSR_GE (0xf << 16)
 261 #define CPSR_RESERVED (0xf << 20)
 262 #define CPSR_J (1 << 24)
 263 #define CPSR_IT_0_1 (3 << 25)
 264 #define CPSR_Q (1 << 27)
 265 #define CPSR_V (1 << 28)
 266 #define CPSR_C (1 << 29)
 267 #define CPSR_Z (1 << 30)
 268 #define CPSR_N (1 << 31)
 269 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 270
 271 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 272 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 273 /* Bits writable in user mode.  */
 274 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 275 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 276 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 277
 278 /* Return the current CPSR value.  */
 279 uint32_t cpsr_read(CPUARMState *env);
 280 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 281 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 282
 283 /* Return the current xPSR value.  */
 284 static inline uint32_t xpsr_read(CPUARMState *env)
 285 {
 286     int ZF;
 287     ZF = (env->ZF == 0);
 288     return (env->NF & 0x80000000) | (ZF << 30)
 289         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 290         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 291         | ((env->condexec_bits & 0xfc) << 8)
 292         | env->v7m.exception;
 293 }
 294
 295 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 296 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 297 {
 298     if (mask & CPSR_NZCV) {
 299         env->ZF = (~val) & CPSR_Z;
 300         env->NF = val;
 301         env->CF = (val >> 29) & 1;
 302         env->VF = (val << 3) & 0x80000000;
 303     }
 304     if (mask & CPSR_Q)
 305         env->QF = ((val & CPSR_Q) != 0);
 306     if (mask & (1 << 24))
 307         env->thumb = ((val & (1 << 24)) != 0);
 308     if (mask & CPSR_IT_0_1) {
 309         env->condexec_bits &= ~3;
 310         env->condexec_bits |= (val >> 25) & 3;
 311     }
 312     if (mask & CPSR_IT_2_7) {
 313         env->condexec_bits &= 3;
 314         env->condexec_bits |= (val >> 8) & 0xfc;
 315     }
 316     if (mask & 0x1ff) {
 317         env->v7m.exception = val & 0x1ff;
 318     }
 319 }
 320
 321 /* Return the current FPSCR value.  */
 322 uint32_t vfp_get_fpscr(CPUARMState *env);
 323 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 324
 325 enum arm_cpu_mode {
 326   ARM_CPU_MODE_USR = 0x10,
 327   ARM_CPU_MODE_FIQ = 0x11,
 328   ARM_CPU_MODE_IRQ = 0x12,
 329   ARM_CPU_MODE_SVC = 0x13,
 330   ARM_CPU_MODE_ABT = 0x17,
 331   ARM_CPU_MODE_UND = 0x1b,
 332   ARM_CPU_MODE_SYS = 0x1f
 333 };
 334
 335 /* VFP system registers.  */
 336 #define ARM_VFP_FPSID   0
 337 #define ARM_VFP_FPSCR   1
 338 #define ARM_VFP_MVFR1   6
 339 #define ARM_VFP_MVFR0   7
 340 #define ARM_VFP_FPEXC   8
 341 #define ARM_VFP_FPINST  9
 342 #define ARM_VFP_FPINST2 10
 343
 344 /* iwMMXt coprocessor control registers.  */
 345 #define ARM_IWMMXT_wCID         0
 346 #define ARM_IWMMXT_wCon         1
 347 #define ARM_IWMMXT_wCSSF        2
 348 #define ARM_IWMMXT_wCASF        3
 349 #define ARM_IWMMXT_wCGR0        8
 350 #define ARM_IWMMXT_wCGR1        9
 351 #define ARM_IWMMXT_wCGR2        10
 352 #define ARM_IWMMXT_wCGR3        11
 353
 354 /* If adding a feature bit which corresponds to a Linux ELF
 355  * HWCAP bit, remember to update the feature-bit-to-hwcap
 356  * mapping in linux-user/elfload.c:get_elf_hwcap().
 357  */
 358 enum arm_features {
 359     ARM_FEATURE_VFP,
 360     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 361     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 362     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 363     ARM_FEATURE_V6,
 364     ARM_FEATURE_V6K,
 365     ARM_FEATURE_V7,
 366     ARM_FEATURE_THUMB2,
 367     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 368     ARM_FEATURE_VFP3,
 369     ARM_FEATURE_VFP_FP16,
 370     ARM_FEATURE_NEON,
 371     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 372     ARM_FEATURE_M, /* Microcontroller profile.  */
 373     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 374     ARM_FEATURE_THUMB2EE,
 375     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 376     ARM_FEATURE_V4T,
 377     ARM_FEATURE_V5,
 378     ARM_FEATURE_STRONGARM,
 379     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 380     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 381     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 382     ARM_FEATURE_GENERIC_TIMER,
 383     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 384     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 385     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 386     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 387     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 388     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 389 };
 390
 391 static inline int arm_feature(CPUARMState *env, int feature)
 392 {
 393     return (env->features & (1u << feature)) != 0;
 394 }
 395
 396 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 397
 398 /* Interface between CPU and Interrupt controller.  */
 399 void armv7m_nvic_set_pending(void *opaque, int irq);
 400 int armv7m_nvic_acknowledge_irq(void *opaque);
 401 void armv7m_nvic_complete_irq(void *opaque, int irq);
 402
 403 /* Interface for defining coprocessor registers.
 404  * Registers are defined in tables of arm_cp_reginfo structs
 405  * which are passed to define_arm_cp_regs().
 406  */
 407
 408 /* When looking up a coprocessor register we look for it
 409  * via an integer which encodes all of:
 410  *  coprocessor number
 411  *  Crn, Crm, opc1, opc2 fields
 412  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 413  *    or via MRRC/MCRR?)
 414  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 415  * (In this case crn and opc2 should be zero.)
 416  */
 417 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 418     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 419      ((crm) << 7) | ((opc1) << 3) | (opc2))
 420
 421 #define DECODE_CPREG_CRN(enc) (((enc) >> 7) & 0xf)
 422
 423 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 424  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 425  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 426  * TCG can assume the value to be constant (ie load at translate time)
 427  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 428  * indicates that the TB should not be ended after a write to this register
 429  * (the default is that the TB ends after cp writes). OVERRIDE permits
 430  * a register definition to override a previous definition for the
 431  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 432  * old must have the OVERRIDE bit set.
 433  */
 434 #define ARM_CP_SPECIAL 1
 435 #define ARM_CP_CONST 2
 436 #define ARM_CP_64BIT 4
 437 #define ARM_CP_SUPPRESS_TB_END 8
 438 #define ARM_CP_OVERRIDE 16
 439 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 440 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 441 #define ARM_LAST_SPECIAL ARM_CP_WFI
 442 /* Used only as a terminator for ARMCPRegInfo lists */
 443 #define ARM_CP_SENTINEL 0xffff
 444 /* Mask of only the flag bits in a type field */
 445 #define ARM_CP_FLAG_MASK 0x1f
 446
 447 /* Return true if cptype is a valid type field. This is used to try to
 448  * catch errors where the sentinel has been accidentally left off the end
 449  * of a list of registers.
 450  */
 451 static inline bool cptype_valid(int cptype)
 452 {
 453     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 454         || ((cptype & ARM_CP_SPECIAL) &&
 455             (cptype <= ARM_LAST_SPECIAL));
 456 }
 457
 458 /* Access rights:
 459  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 460  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 461  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 462  * (ie any of the privileged modes in Secure state, or Monitor mode).
 463  * If a register is accessible in one privilege level it's always accessible
 464  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 465  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 466  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 467  * terminology a little and call this PL3.
 468  *
 469  * If access permissions for a register are more complex than can be
 470  * described with these bits, then use a laxer set of restrictions, and
 471  * do the more restrictive/complex check inside a helper function.
 472  */
 473 #define PL3_R 0x80
 474 #define PL3_W 0x40
 475 #define PL2_R (0x20 | PL3_R)
 476 #define PL2_W (0x10 | PL3_W)
 477 #define PL1_R (0x08 | PL2_R)
 478 #define PL1_W (0x04 | PL2_W)
 479 #define PL0_R (0x02 | PL1_R)
 480 #define PL0_W (0x01 | PL1_W)
 481
 482 #define PL3_RW (PL3_R | PL3_W)
 483 #define PL2_RW (PL2_R | PL2_W)
 484 #define PL1_RW (PL1_R | PL1_W)
 485 #define PL0_RW (PL0_R | PL0_W)
 486
 487 static inline int arm_current_pl(CPUARMState *env)
 488 {
 489     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 490         return 0;
 491     }
 492     /* We don't currently implement the Virtualization or TrustZone
 493      * extensions, so PL2 and PL3 don't exist for us.
 494      */
 495     return 1;
 496 }
 497
 498 typedef struct ARMCPRegInfo ARMCPRegInfo;
 499
 500 /* Access functions for coprocessor registers. These should return
 501  * 0 on success, or one of the EXCP_* constants if access should cause
 502  * an exception (in which case *value is not written).
 503  */
 504 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 505                      uint64_t *value);
 506 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 507                       uint64_t value);
 508 /* Hook function for register reset */
 509 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 510
 511 #define CP_ANY 0xff
 512
 513 /* Definition of an ARM coprocessor register */
 514 struct ARMCPRegInfo {
 515     /* Name of register (useful mainly for debugging, need not be unique) */
 516     const char *name;
 517     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 518      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 519      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 520      * will be decoded to this register. The register read and write
 521      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 522      * used by the program, so it is possible to register a wildcard and
 523      * then behave differently on read/write if necessary.
 524      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 525      * must both be zero.
 526      */
 527     uint8_t cp;
 528     uint8_t crn;
 529     uint8_t crm;
 530     uint8_t opc1;
 531     uint8_t opc2;
 532     /* Register type: ARM_CP_* bits/values */
 533     int type;
 534     /* Access rights: PL*_[RW] */
 535     int access;
 536     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 537      * this register was defined: can be used to hand data through to the
 538      * register read/write functions, since they are passed the ARMCPRegInfo*.
 539      */
 540     void *opaque;
 541     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 542      * fieldoffset is non-zero, the reset value of the register.
 543      */
 544     uint64_t resetvalue;
 545     /* Offset of the field in CPUARMState for this register. This is not
 546      * needed if either:
 547      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 548      *  2. both readfn and writefn are specified
 549      */
 550     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 551     /* Function for handling reads of this register. If NULL, then reads
 552      * will be done by loading from the offset into CPUARMState specified
 553      * by fieldoffset.
 554      */
 555     CPReadFn *readfn;
 556     /* Function for handling writes of this register. If NULL, then writes
 557      * will be done by writing to the offset into CPUARMState specified
 558      * by fieldoffset.
 559      */
 560     CPWriteFn *writefn;
 561     /* Function for resetting the register. If NULL, then reset will be done
 562      * by writing resetvalue to the field specified in fieldoffset. If
 563      * fieldoffset is 0 then no reset will be done.
 564      */
 565     CPResetFn *resetfn;
 566 };
 567
 568 /* Macros which are lvalues for the field in CPUARMState for the
 569  * ARMCPRegInfo *ri.
 570  */
 571 #define CPREG_FIELD32(env, ri) \
 572     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 573 #define CPREG_FIELD64(env, ri) \
 574     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 575
 576 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 577
 578 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 579                                     const ARMCPRegInfo *regs, void *opaque);
 580 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 581                                        const ARMCPRegInfo *regs, void *opaque);
 582 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 583 {
 584     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 585 }
 586 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 587 {
 588     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 589 }
 590 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 591
 592 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 593 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 594                         uint64_t value);
 595 /* CPReadFn that can be used for read-as-zero behaviour */
 596 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 597
 598 static inline bool cp_access_ok(CPUARMState *env,
 599                                 const ARMCPRegInfo *ri, int isread)
 600 {
 601     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 602 }
 603
 604 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 605    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 606    conventional cores (ie. Application or Realtime profile).  */
 607
 608 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 609
 610 #define ARM_CPUID_TI915T      0x54029152
 611 #define ARM_CPUID_TI925T      0x54029252
 612
 613 #if defined(CONFIG_USER_ONLY)
 614 #define TARGET_PAGE_BITS 12
 615 #else
 616 /* The ARM MMU allows 1k pages.  */
 617 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 618    architecture revisions.  Maybe a configure option to disable them.  */
 619 #define TARGET_PAGE_BITS 10
 620 #endif
 621
 622 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 623 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 624
 625 static inline CPUARMState *cpu_init(const char *cpu_model)
 626 {
 627     ARMCPU *cpu = cpu_arm_init(cpu_model);
 628     if (cpu) {
 629         return &cpu->env;
 630     }
 631     return NULL;
 632 }
 633
 634 #define cpu_exec cpu_arm_exec
 635 #define cpu_gen_code cpu_arm_gen_code
 636 #define cpu_signal_handler cpu_arm_signal_handler
 637 #define cpu_list arm_cpu_list
 638
 639 #define CPU_SAVE_VERSION 7
 640
 641 /* MMU modes definitions */
 642 #define MMU_MODE0_SUFFIX _kernel
 643 #define MMU_MODE1_SUFFIX _user
 644 #define MMU_USER_IDX 1
 645 static inline int cpu_mmu_index (CPUARMState *env)
 646 {
 647     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 648 }
 649
 650 #if defined(CONFIG_USER_ONLY)
 651 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 652 {
 653     if (newsp)
 654         env->regs[13] = newsp;
 655     env->regs[0] = 0;
 656 }
 657 #endif
 658
 659 #include "cpu-all.h"
 660
 661 /* Bit usage in the TB flags field: */
 662 #define ARM_TBFLAG_THUMB_SHIFT      0
 663 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 664 #define ARM_TBFLAG_VECLEN_SHIFT     1
 665 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 666 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 667 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 668 #define ARM_TBFLAG_PRIV_SHIFT       6
 669 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 670 #define ARM_TBFLAG_VFPEN_SHIFT      7
 671 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 672 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 673 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 674 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 675 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 676 /* Bits 31..17 are currently unused. */
 677
 678 /* some convenience accessor macros */
 679 #define ARM_TBFLAG_THUMB(F) \
 680     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 681 #define ARM_TBFLAG_VECLEN(F) \
 682     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 683 #define ARM_TBFLAG_VECSTRIDE(F) \
 684     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 685 #define ARM_TBFLAG_PRIV(F) \
 686     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 687 #define ARM_TBFLAG_VFPEN(F) \
 688     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 689 #define ARM_TBFLAG_CONDEXEC(F) \
 690     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 691 #define ARM_TBFLAG_BSWAP_CODE(F) \
 692     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 693
 694 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 695                                         target_ulong *cs_base, int *flags)
 696 {
 697     int privmode;
 698     *pc = env->regs[15];
 699     *cs_base = 0;
 700     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 701         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 702         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 703         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 704         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 705     if (arm_feature(env, ARM_FEATURE_M)) {
 706         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 707     } else {
 708         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 709     }
 710     if (privmode) {
 711         *flags |= ARM_TBFLAG_PRIV_MASK;
 712     }
 713     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 714         *flags |= ARM_TBFLAG_VFPEN_MASK;
 715     }
 716 }
 717
 718 static inline bool cpu_has_work(CPUARMState *env)
 719 {
 720     return env->interrupt_request &
 721         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 722 }
 723
 724 #include "exec-all.h"
 725
 726 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 727 {
 728     env->regs[15] = tb->pc;
 729 }
 730
 731 /* Load an instruction and return it in the standard little-endian order */
 732 static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
 733 {
 734     uint32_t insn = ldl_code(addr);
 735     if (do_swap) {
 736         return bswap32(insn);
 737     }
 738     return insn;
 739 }
 740
 741 /* Ditto, for a halfword (Thumb) instruction */
 742 static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
 743 {
 744     uint16_t insn = lduw_code(addr);
 745     if (do_swap) {
 746         return bswap16(insn);
 747     }
 748     return insn;
 749 }
 750
 751 #endif