target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cachetype;
 111         uint32_t c0_ccsid[16]; /* Cache size.  */
 112         uint32_t c0_clid; /* Cache level.  */
 113         uint32_t c0_cssel; /* Cache size selection.  */
 114         uint32_t c1_sys; /* System control register.  */
 115         uint32_t c1_coproc; /* Coprocessor access register.  */
 116         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 117         uint32_t c1_scr; /* secure config register.  */
 118         uint32_t c2_base0; /* MMU translation table base 0.  */
 119         uint32_t c2_base1; /* MMU translation table base 1.  */
 120         uint32_t c2_control; /* MMU translation table base control.  */
 121         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 122         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 123         uint32_t c2_data; /* MPU data cachable bits.  */
 124         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 125         uint32_t c3; /* MMU domain access control register
 126                         MPU write buffer control.  */
 127         uint32_t c5_insn; /* Fault status registers.  */
 128         uint32_t c5_data;
 129         uint32_t c6_region[8]; /* MPU base/size registers.  */
 130         uint32_t c6_insn; /* Fault address registers.  */
 131         uint32_t c6_data;
 132         uint32_t c7_par;  /* Translation result. */
 133         uint32_t c9_insn; /* Cache lockdown registers.  */
 134         uint32_t c9_data;
 135         uint32_t c9_pmcr; /* performance monitor control register */
 136         uint32_t c9_pmcnten; /* perf monitor counter enables */
 137         uint32_t c9_pmovsr; /* perf monitor overflow status */
 138         uint32_t c9_pmxevtyper; /* perf monitor event type */
 139         uint32_t c9_pmuserenr; /* perf monitor user enable */
 140         uint32_t c9_pminten; /* perf monitor interrupt enables */
 141         uint32_t c13_fcse; /* FCSE PID.  */
 142         uint32_t c13_context; /* Context ID.  */
 143         uint32_t c13_tls1; /* User RW Thread register.  */
 144         uint32_t c13_tls2; /* User RO Thread register.  */
 145         uint32_t c13_tls3; /* Privileged Thread register.  */
 146         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 147         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 148         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 149         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 150         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 151         uint32_t c15_config_base_address; /* SCU base address.  */
 152         uint32_t c15_diagnostic; /* diagnostic register */
 153         uint32_t c15_power_diagnostic;
 154         uint32_t c15_power_control; /* power control */
 155     } cp15;
 156
 157     struct {
 158         uint32_t other_sp;
 159         uint32_t vecbase;
 160         uint32_t basepri;
 161         uint32_t control;
 162         int current_sp;
 163         int exception;
 164         int pending_exception;
 165     } v7m;
 166
 167     /* Thumb-2 EE state.  */
 168     uint32_t teecr;
 169     uint32_t teehbr;
 170
 171     /* VFP coprocessor state.  */
 172     struct {
 173         float64 regs[32];
 174
 175         uint32_t xregs[16];
 176         /* We store these fpcsr fields separately for convenience.  */
 177         int vec_len;
 178         int vec_stride;
 179
 180         /* scratch space when Tn are not sufficient.  */
 181         uint32_t scratch[8];
 182
 183         /* fp_status is the "normal" fp status. standard_fp_status retains
 184          * values corresponding to the ARM "Standard FPSCR Value", ie
 185          * default-NaN, flush-to-zero, round-to-nearest and is used by
 186          * any operations (generally Neon) which the architecture defines
 187          * as controlled by the standard FPSCR value rather than the FPSCR.
 188          *
 189          * To avoid having to transfer exception bits around, we simply
 190          * say that the FPSCR cumulative exception flags are the logical
 191          * OR of the flags in the two fp statuses. This relies on the
 192          * only thing which needs to read the exception flags being
 193          * an explicit FPSCR read.
 194          */
 195         float_status fp_status;
 196         float_status standard_fp_status;
 197     } vfp;
 198     uint32_t exclusive_addr;
 199     uint32_t exclusive_val;
 200     uint32_t exclusive_high;
 201 #if defined(CONFIG_USER_ONLY)
 202     uint32_t exclusive_test;
 203     uint32_t exclusive_info;
 204 #endif
 205
 206     /* iwMMXt coprocessor state.  */
 207     struct {
 208         uint64_t regs[16];
 209         uint64_t val;
 210
 211         uint32_t cregs[16];
 212     } iwmmxt;
 213
 214     /* For mixed endian mode.  */
 215     bool bswap_code;
 216
 217 #if defined(CONFIG_USER_ONLY)
 218     /* For usermode syscall translation.  */
 219     int eabi;
 220 #endif
 221
 222     CPU_COMMON
 223
 224     /* These fields after the common ones so they are preserved on reset.  */
 225
 226     /* Internal CPU feature flags.  */
 227     uint32_t features;
 228
 229     void *nvic;
 230     const struct arm_boot_info *boot_info;
 231 } CPUARMState;
 232
 233 #include "cpu-qom.h"
 234
 235 ARMCPU *cpu_arm_init(const char *cpu_model);
 236 void arm_translate_init(void);
 237 int cpu_arm_exec(CPUARMState *s);
 238 void do_interrupt(CPUARMState *);
 239 void switch_mode(CPUARMState *, int);
 240 uint32_t do_arm_semihosting(CPUARMState *env);
 241
 242 /* you can call this signal handler from your SIGBUS and SIGSEGV
 243    signal handlers to inform the virtual CPU of exceptions. non zero
 244    is returned if the signal was handled by the virtual CPU.  */
 245 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 246                            void *puc);
 247 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 248                               int mmu_idx);
 249 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 250
 251 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 252 {
 253   env->cp15.c13_tls2 = newtls;
 254 }
 255
 256 #define CPSR_M (0x1f)
 257 #define CPSR_T (1 << 5)
 258 #define CPSR_F (1 << 6)
 259 #define CPSR_I (1 << 7)
 260 #define CPSR_A (1 << 8)
 261 #define CPSR_E (1 << 9)
 262 #define CPSR_IT_2_7 (0xfc00)
 263 #define CPSR_GE (0xf << 16)
 264 #define CPSR_RESERVED (0xf << 20)
 265 #define CPSR_J (1 << 24)
 266 #define CPSR_IT_0_1 (3 << 25)
 267 #define CPSR_Q (1 << 27)
 268 #define CPSR_V (1 << 28)
 269 #define CPSR_C (1 << 29)
 270 #define CPSR_Z (1 << 30)
 271 #define CPSR_N (1 << 31)
 272 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 273
 274 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 275 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 276 /* Bits writable in user mode.  */
 277 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 278 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 279 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 280
 281 /* Return the current CPSR value.  */
 282 uint32_t cpsr_read(CPUARMState *env);
 283 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 284 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 285
 286 /* Return the current xPSR value.  */
 287 static inline uint32_t xpsr_read(CPUARMState *env)
 288 {
 289     int ZF;
 290     ZF = (env->ZF == 0);
 291     return (env->NF & 0x80000000) | (ZF << 30)
 292         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 293         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 294         | ((env->condexec_bits & 0xfc) << 8)
 295         | env->v7m.exception;
 296 }
 297
 298 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 299 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 300 {
 301     if (mask & CPSR_NZCV) {
 302         env->ZF = (~val) & CPSR_Z;
 303         env->NF = val;
 304         env->CF = (val >> 29) & 1;
 305         env->VF = (val << 3) & 0x80000000;
 306     }
 307     if (mask & CPSR_Q)
 308         env->QF = ((val & CPSR_Q) != 0);
 309     if (mask & (1 << 24))
 310         env->thumb = ((val & (1 << 24)) != 0);
 311     if (mask & CPSR_IT_0_1) {
 312         env->condexec_bits &= ~3;
 313         env->condexec_bits |= (val >> 25) & 3;
 314     }
 315     if (mask & CPSR_IT_2_7) {
 316         env->condexec_bits &= 3;
 317         env->condexec_bits |= (val >> 8) & 0xfc;
 318     }
 319     if (mask & 0x1ff) {
 320         env->v7m.exception = val & 0x1ff;
 321     }
 322 }
 323
 324 /* Return the current FPSCR value.  */
 325 uint32_t vfp_get_fpscr(CPUARMState *env);
 326 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 327
 328 enum arm_cpu_mode {
 329   ARM_CPU_MODE_USR = 0x10,
 330   ARM_CPU_MODE_FIQ = 0x11,
 331   ARM_CPU_MODE_IRQ = 0x12,
 332   ARM_CPU_MODE_SVC = 0x13,
 333   ARM_CPU_MODE_ABT = 0x17,
 334   ARM_CPU_MODE_UND = 0x1b,
 335   ARM_CPU_MODE_SYS = 0x1f
 336 };
 337
 338 /* VFP system registers.  */
 339 #define ARM_VFP_FPSID   0
 340 #define ARM_VFP_FPSCR   1
 341 #define ARM_VFP_MVFR1   6
 342 #define ARM_VFP_MVFR0   7
 343 #define ARM_VFP_FPEXC   8
 344 #define ARM_VFP_FPINST  9
 345 #define ARM_VFP_FPINST2 10
 346
 347 /* iwMMXt coprocessor control registers.  */
 348 #define ARM_IWMMXT_wCID         0
 349 #define ARM_IWMMXT_wCon         1
 350 #define ARM_IWMMXT_wCSSF        2
 351 #define ARM_IWMMXT_wCASF        3
 352 #define ARM_IWMMXT_wCGR0        8
 353 #define ARM_IWMMXT_wCGR1        9
 354 #define ARM_IWMMXT_wCGR2        10
 355 #define ARM_IWMMXT_wCGR3        11
 356
 357 /* If adding a feature bit which corresponds to a Linux ELF
 358  * HWCAP bit, remember to update the feature-bit-to-hwcap
 359  * mapping in linux-user/elfload.c:get_elf_hwcap().
 360  */
 361 enum arm_features {
 362     ARM_FEATURE_VFP,
 363     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 364     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 365     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 366     ARM_FEATURE_V6,
 367     ARM_FEATURE_V6K,
 368     ARM_FEATURE_V7,
 369     ARM_FEATURE_THUMB2,
 370     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 371     ARM_FEATURE_VFP3,
 372     ARM_FEATURE_VFP_FP16,
 373     ARM_FEATURE_NEON,
 374     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 375     ARM_FEATURE_M, /* Microcontroller profile.  */
 376     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 377     ARM_FEATURE_THUMB2EE,
 378     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 379     ARM_FEATURE_V4T,
 380     ARM_FEATURE_V5,
 381     ARM_FEATURE_STRONGARM,
 382     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 383     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 384     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 385     ARM_FEATURE_GENERIC_TIMER,
 386     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 387     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 388     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 389     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 390     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 391 };
 392
 393 static inline int arm_feature(CPUARMState *env, int feature)
 394 {
 395     return (env->features & (1u << feature)) != 0;
 396 }
 397
 398 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 399
 400 /* Interface between CPU and Interrupt controller.  */
 401 void armv7m_nvic_set_pending(void *opaque, int irq);
 402 int armv7m_nvic_acknowledge_irq(void *opaque);
 403 void armv7m_nvic_complete_irq(void *opaque, int irq);
 404
 405 /* Interface for defining coprocessor registers.
 406  * Registers are defined in tables of arm_cp_reginfo structs
 407  * which are passed to define_arm_cp_regs().
 408  */
 409
 410 /* When looking up a coprocessor register we look for it
 411  * via an integer which encodes all of:
 412  *  coprocessor number
 413  *  Crn, Crm, opc1, opc2 fields
 414  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 415  *    or via MRRC/MCRR?)
 416  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 417  * (In this case crn and opc2 should be zero.)
 418  */
 419 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 420     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 421      ((crm) << 7) | ((opc1) << 3) | (opc2))
 422
 423 #define DECODE_CPREG_CRN(enc) (((enc) >> 7) & 0xf)
 424
 425 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 426  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 427  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 428  * TCG can assume the value to be constant (ie load at translate time)
 429  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 430  * indicates that the TB should not be ended after a write to this register
 431  * (the default is that the TB ends after cp writes). OVERRIDE permits
 432  * a register definition to override a previous definition for the
 433  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 434  * old must have the OVERRIDE bit set.
 435  */
 436 #define ARM_CP_SPECIAL 1
 437 #define ARM_CP_CONST 2
 438 #define ARM_CP_64BIT 4
 439 #define ARM_CP_SUPPRESS_TB_END 8
 440 #define ARM_CP_OVERRIDE 16
 441 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 442 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 443 #define ARM_LAST_SPECIAL ARM_CP_WFI
 444 /* Used only as a terminator for ARMCPRegInfo lists */
 445 #define ARM_CP_SENTINEL 0xffff
 446 /* Mask of only the flag bits in a type field */
 447 #define ARM_CP_FLAG_MASK 0x1f
 448
 449 /* Return true if cptype is a valid type field. This is used to try to
 450  * catch errors where the sentinel has been accidentally left off the end
 451  * of a list of registers.
 452  */
 453 static inline bool cptype_valid(int cptype)
 454 {
 455     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 456         || ((cptype & ARM_CP_SPECIAL) &&
 457             (cptype <= ARM_LAST_SPECIAL));
 458 }
 459
 460 /* Access rights:
 461  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 462  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 463  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 464  * (ie any of the privileged modes in Secure state, or Monitor mode).
 465  * If a register is accessible in one privilege level it's always accessible
 466  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 467  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 468  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 469  * terminology a little and call this PL3.
 470  *
 471  * If access permissions for a register are more complex than can be
 472  * described with these bits, then use a laxer set of restrictions, and
 473  * do the more restrictive/complex check inside a helper function.
 474  */
 475 #define PL3_R 0x80
 476 #define PL3_W 0x40
 477 #define PL2_R (0x20 | PL3_R)
 478 #define PL2_W (0x10 | PL3_W)
 479 #define PL1_R (0x08 | PL2_R)
 480 #define PL1_W (0x04 | PL2_W)
 481 #define PL0_R (0x02 | PL1_R)
 482 #define PL0_W (0x01 | PL1_W)
 483
 484 #define PL3_RW (PL3_R | PL3_W)
 485 #define PL2_RW (PL2_R | PL2_W)
 486 #define PL1_RW (PL1_R | PL1_W)
 487 #define PL0_RW (PL0_R | PL0_W)
 488
 489 static inline int arm_current_pl(CPUARMState *env)
 490 {
 491     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 492         return 0;
 493     }
 494     /* We don't currently implement the Virtualization or TrustZone
 495      * extensions, so PL2 and PL3 don't exist for us.
 496      */
 497     return 1;
 498 }
 499
 500 typedef struct ARMCPRegInfo ARMCPRegInfo;
 501
 502 /* Access functions for coprocessor registers. These should return
 503  * 0 on success, or one of the EXCP_* constants if access should cause
 504  * an exception (in which case *value is not written).
 505  */
 506 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 507                      uint64_t *value);
 508 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 509                       uint64_t value);
 510 /* Hook function for register reset */
 511 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 512
 513 #define CP_ANY 0xff
 514
 515 /* Definition of an ARM coprocessor register */
 516 struct ARMCPRegInfo {
 517     /* Name of register (useful mainly for debugging, need not be unique) */
 518     const char *name;
 519     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 520      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 521      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 522      * will be decoded to this register. The register read and write
 523      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 524      * used by the program, so it is possible to register a wildcard and
 525      * then behave differently on read/write if necessary.
 526      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 527      * must both be zero.
 528      */
 529     uint8_t cp;
 530     uint8_t crn;
 531     uint8_t crm;
 532     uint8_t opc1;
 533     uint8_t opc2;
 534     /* Register type: ARM_CP_* bits/values */
 535     int type;
 536     /* Access rights: PL*_[RW] */
 537     int access;
 538     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 539      * this register was defined: can be used to hand data through to the
 540      * register read/write functions, since they are passed the ARMCPRegInfo*.
 541      */
 542     void *opaque;
 543     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 544      * fieldoffset is non-zero, the reset value of the register.
 545      */
 546     uint64_t resetvalue;
 547     /* Offset of the field in CPUARMState for this register. This is not
 548      * needed if either:
 549      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 550      *  2. both readfn and writefn are specified
 551      */
 552     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 553     /* Function for handling reads of this register. If NULL, then reads
 554      * will be done by loading from the offset into CPUARMState specified
 555      * by fieldoffset.
 556      */
 557     CPReadFn *readfn;
 558     /* Function for handling writes of this register. If NULL, then writes
 559      * will be done by writing to the offset into CPUARMState specified
 560      * by fieldoffset.
 561      */
 562     CPWriteFn *writefn;
 563     /* Function for resetting the register. If NULL, then reset will be done
 564      * by writing resetvalue to the field specified in fieldoffset. If
 565      * fieldoffset is 0 then no reset will be done.
 566      */
 567     CPResetFn *resetfn;
 568 };
 569
 570 /* Macros which are lvalues for the field in CPUARMState for the
 571  * ARMCPRegInfo *ri.
 572  */
 573 #define CPREG_FIELD32(env, ri) \
 574     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 575 #define CPREG_FIELD64(env, ri) \
 576     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 577
 578 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 579
 580 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 581                                     const ARMCPRegInfo *regs, void *opaque);
 582 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 583                                        const ARMCPRegInfo *regs, void *opaque);
 584 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 585 {
 586     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 587 }
 588 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 589 {
 590     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 591 }
 592 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 593
 594 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 595 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 596                         uint64_t value);
 597 /* CPReadFn that can be used for read-as-zero behaviour */
 598 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 599
 600 static inline bool cp_access_ok(CPUARMState *env,
 601                                 const ARMCPRegInfo *ri, int isread)
 602 {
 603     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 604 }
 605
 606 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 607    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 608    conventional cores (ie. Application or Realtime profile).  */
 609
 610 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 611 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 612
 613 #define ARM_CPUID_ARM1026     0x4106a262
 614 #define ARM_CPUID_ARM926      0x41069265
 615 #define ARM_CPUID_ARM946      0x41059461
 616 #define ARM_CPUID_TI915T      0x54029152
 617 #define ARM_CPUID_TI925T      0x54029252
 618 #define ARM_CPUID_SA1100      0x4401A11B
 619 #define ARM_CPUID_SA1110      0x6901B119
 620 #define ARM_CPUID_PXA250      0x69052100
 621 #define ARM_CPUID_PXA255      0x69052d00
 622 #define ARM_CPUID_PXA260      0x69052903
 623 #define ARM_CPUID_PXA261      0x69052d05
 624 #define ARM_CPUID_PXA262      0x69052d06
 625 #define ARM_CPUID_PXA270      0x69054110
 626 #define ARM_CPUID_PXA270_A0   0x69054110
 627 #define ARM_CPUID_PXA270_A1   0x69054111
 628 #define ARM_CPUID_PXA270_B0   0x69054112
 629 #define ARM_CPUID_PXA270_B1   0x69054113
 630 #define ARM_CPUID_PXA270_C0   0x69054114
 631 #define ARM_CPUID_PXA270_C5   0x69054117
 632 #define ARM_CPUID_ARM1136     0x4117b363
 633 #define ARM_CPUID_ARM1136_R2  0x4107b362
 634 #define ARM_CPUID_ARM1176     0x410fb767
 635 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 636 #define ARM_CPUID_CORTEXA8    0x410fc080
 637 #define ARM_CPUID_CORTEXA9    0x410fc090
 638 #define ARM_CPUID_CORTEXA15   0x412fc0f1
 639 #define ARM_CPUID_CORTEXM3    0x410fc231
 640 #define ARM_CPUID_ANY         0xffffffff
 641
 642 #if defined(CONFIG_USER_ONLY)
 643 #define TARGET_PAGE_BITS 12
 644 #else
 645 /* The ARM MMU allows 1k pages.  */
 646 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 647    architecture revisions.  Maybe a configure option to disable them.  */
 648 #define TARGET_PAGE_BITS 10
 649 #endif
 650
 651 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 652 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 653
 654 static inline CPUARMState *cpu_init(const char *cpu_model)
 655 {
 656     ARMCPU *cpu = cpu_arm_init(cpu_model);
 657     if (cpu) {
 658         return &cpu->env;
 659     }
 660     return NULL;
 661 }
 662
 663 #define cpu_exec cpu_arm_exec
 664 #define cpu_gen_code cpu_arm_gen_code
 665 #define cpu_signal_handler cpu_arm_signal_handler
 666 #define cpu_list arm_cpu_list
 667
 668 #define CPU_SAVE_VERSION 6
 669
 670 /* MMU modes definitions */
 671 #define MMU_MODE0_SUFFIX _kernel
 672 #define MMU_MODE1_SUFFIX _user
 673 #define MMU_USER_IDX 1
 674 static inline int cpu_mmu_index (CPUARMState *env)
 675 {
 676     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 677 }
 678
 679 #if defined(CONFIG_USER_ONLY)
 680 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 681 {
 682     if (newsp)
 683         env->regs[13] = newsp;
 684     env->regs[0] = 0;
 685 }
 686 #endif
 687
 688 #include "cpu-all.h"
 689
 690 /* Bit usage in the TB flags field: */
 691 #define ARM_TBFLAG_THUMB_SHIFT      0
 692 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 693 #define ARM_TBFLAG_VECLEN_SHIFT     1
 694 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 695 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 696 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 697 #define ARM_TBFLAG_PRIV_SHIFT       6
 698 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 699 #define ARM_TBFLAG_VFPEN_SHIFT      7
 700 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 701 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 702 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 703 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 704 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 705 /* Bits 31..17 are currently unused. */
 706
 707 /* some convenience accessor macros */
 708 #define ARM_TBFLAG_THUMB(F) \
 709     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 710 #define ARM_TBFLAG_VECLEN(F) \
 711     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 712 #define ARM_TBFLAG_VECSTRIDE(F) \
 713     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 714 #define ARM_TBFLAG_PRIV(F) \
 715     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 716 #define ARM_TBFLAG_VFPEN(F) \
 717     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 718 #define ARM_TBFLAG_CONDEXEC(F) \
 719     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 720 #define ARM_TBFLAG_BSWAP_CODE(F) \
 721     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 722
 723 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 724                                         target_ulong *cs_base, int *flags)
 725 {
 726     int privmode;
 727     *pc = env->regs[15];
 728     *cs_base = 0;
 729     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 730         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 731         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 732         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 733         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 734     if (arm_feature(env, ARM_FEATURE_M)) {
 735         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 736     } else {
 737         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 738     }
 739     if (privmode) {
 740         *flags |= ARM_TBFLAG_PRIV_MASK;
 741     }
 742     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 743         *flags |= ARM_TBFLAG_VFPEN_MASK;
 744     }
 745 }
 746
 747 static inline bool cpu_has_work(CPUARMState *env)
 748 {
 749     return env->interrupt_request &
 750         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 751 }
 752
 753 #include "exec-all.h"
 754
 755 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 756 {
 757     env->regs[15] = tb->pc;
 758 }
 759
 760 /* Load an instruction and return it in the standard little-endian order */
 761 static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
 762 {
 763     uint32_t insn = ldl_code(addr);
 764     if (do_swap) {
 765         return bswap32(insn);
 766     }
 767     return insn;
 768 }
 769
 770 /* Ditto, for a halfword (Thumb) instruction */
 771 static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
 772 {
 773     uint16_t insn = lduw_code(addr);
 774     if (do_swap) {
 775         return bswap16(insn);
 776     }
 777     return insn;
 778 }
 779
 780 #endif