target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40
  41 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  42                             int srcreg, int operand, uint32_t value);
  43 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  44                                int dstreg, int operand);
  45
  46 /* We currently assume float and double are IEEE single and double
  47    precision respectively.
  48    Doing runtime conversions is tricky because VFP registers may contain
  49    integer values (eg. as the result of a FTOSI instruction).
  50    s<2n> maps to the least significant half of d<n>
  51    s<2n+1> maps to the most significant half of d<n>
  52  */
  53
  54 typedef struct CPUARMState {
  55     /* Regs for current mode.  */
  56     uint32_t regs[16];
  57     /* Frequently accessed CPSR bits are stored separately for efficiently.
  58        This contains all the other bits.  Use cpsr_{read,write} to access
  59        the whole CPSR.  */
  60     uint32_t uncached_cpsr;
  61     uint32_t spsr;
  62
  63     /* Banked registers.  */
  64     uint32_t banked_spsr[6];
  65     uint32_t banked_r13[6];
  66     uint32_t banked_r14[6];
  67
  68     /* These hold r8-r12.  */
  69     uint32_t usr_regs[5];
  70     uint32_t fiq_regs[5];
  71
  72     /* cpsr flag cache for faster execution */
  73     uint32_t CF; /* 0 or 1 */
  74     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  75     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  76     uint32_t QF; /* 0 or 1 */
  77
  78     int thumb; /* 0 = arm mode, 1 = thumb mode */
  79
  80     /* System control coprocessor (cp15) */
  81     struct {
  82         uint32_t c0_cpuid;
  83         uint32_t c0_cachetype;
  84         uint32_t c1_sys; /* System control register.  */
  85         uint32_t c1_coproc; /* Coprocessor access register.  */
  86         uint32_t c2; /* MMU translation table base.  */
  87         uint32_t c3; /* MMU domain access control register.  */
  88         uint32_t c5_insn; /* Fault status registers.  */
  89         uint32_t c5_data;
  90         uint32_t c6_insn; /* Fault address registers.  */
  91         uint32_t c6_data;
  92         uint32_t c9_insn; /* Cache lockdown registers.  */
  93         uint32_t c9_data;
  94         uint32_t c13_fcse; /* FCSE PID.  */
  95         uint32_t c13_context; /* Context ID.  */
  96         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
  97     } cp15;
  98
  99     /* Coprocessor IO used by peripherals */
 100     struct {
 101         ARMReadCPFunc *cp_read;
 102         ARMWriteCPFunc *cp_write;
 103         void *opaque;
 104     } cp[15];
 105
 106     /* Internal CPU feature flags.  */
 107     uint32_t features;
 108
 109     /* exception/interrupt handling */
 110     jmp_buf jmp_env;
 111     int exception_index;
 112     int interrupt_request;
 113     int user_mode_only;
 114     int halted;
 115
 116     /* VFP coprocessor state.  */
 117     struct {
 118         float64 regs[16];
 119
 120         uint32_t xregs[16];
 121         /* We store these fpcsr fields separately for convenience.  */
 122         int vec_len;
 123         int vec_stride;
 124
 125         /* Temporary variables if we don't have spare fp regs.  */
 126         float32 tmp0s, tmp1s;
 127         float64 tmp0d, tmp1d;
 128
 129         float_status fp_status;
 130     } vfp;
 131
 132     /* iwMMXt coprocessor state.  */
 133     struct {
 134         uint64_t regs[16];
 135         uint64_t val;
 136
 137         uint32_t cregs[16];
 138     } iwmmxt;
 139
 140 #if defined(CONFIG_USER_ONLY)
 141     /* For usermode syscall translation.  */
 142     int eabi;
 143 #endif
 144
 145     CPU_COMMON
 146
 147     /* These fields after the common ones so they are preserved on reset.  */
 148     int ram_size;
 149     const char *kernel_filename;
 150     const char *kernel_cmdline;
 151     const char *initrd_filename;
 152     int board_id;
 153     target_phys_addr_t loader_start;
 154 } CPUARMState;
 155
 156 CPUARMState *cpu_arm_init(void);
 157 int cpu_arm_exec(CPUARMState *s);
 158 void cpu_arm_close(CPUARMState *s);
 159 void do_interrupt(CPUARMState *);
 160 void switch_mode(CPUARMState *, int);
 161
 162 /* you can call this signal handler from your SIGBUS and SIGSEGV
 163    signal handlers to inform the virtual CPU of exceptions. non zero
 164    is returned if the signal was handled by the virtual CPU.  */
 165 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 166                            void *puc);
 167
 168 #define CPSR_M (0x1f)
 169 #define CPSR_T (1 << 5)
 170 #define CPSR_F (1 << 6)
 171 #define CPSR_I (1 << 7)
 172 #define CPSR_A (1 << 8)
 173 #define CPSR_E (1 << 9)
 174 #define CPSR_IT_2_7 (0xfc00)
 175 /* Bits 20-23 reserved.  */
 176 #define CPSR_J (1 << 24)
 177 #define CPSR_IT_0_1 (3 << 25)
 178 #define CPSR_Q (1 << 27)
 179 #define CPSR_NZCV (0xf << 28)
 180
 181 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
 182 /* Return the current CPSR value.  */
 183 static inline uint32_t cpsr_read(CPUARMState *env)
 184 {
 185     int ZF;
 186     ZF = (env->NZF == 0);
 187     return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 188         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 189         | (env->thumb << 5);
 190 }
 191
 192 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 193 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 194 {
 195     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 196     if (mask & CPSR_NZCV) {
 197         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 198         env->CF = (val >> 29) & 1;
 199         env->VF = (val << 3) & 0x80000000;
 200     }
 201     if (mask & CPSR_Q)
 202         env->QF = ((val & CPSR_Q) != 0);
 203     if (mask & CPSR_T)
 204         env->thumb = ((val & CPSR_T) != 0);
 205
 206     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 207         switch_mode(env, val & CPSR_M);
 208     }
 209     mask &= ~CACHED_CPSR_BITS;
 210     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 211 }
 212
 213 enum arm_cpu_mode {
 214   ARM_CPU_MODE_USR = 0x10,
 215   ARM_CPU_MODE_FIQ = 0x11,
 216   ARM_CPU_MODE_IRQ = 0x12,
 217   ARM_CPU_MODE_SVC = 0x13,
 218   ARM_CPU_MODE_ABT = 0x17,
 219   ARM_CPU_MODE_UND = 0x1b,
 220   ARM_CPU_MODE_SYS = 0x1f
 221 };
 222
 223 /* VFP system registers.  */
 224 #define ARM_VFP_FPSID   0
 225 #define ARM_VFP_FPSCR   1
 226 #define ARM_VFP_FPEXC   8
 227 #define ARM_VFP_FPINST  9
 228 #define ARM_VFP_FPINST2 10
 229
 230 /* iwMMXt coprocessor control registers.  */
 231 #define ARM_IWMMXT_wCID         0
 232 #define ARM_IWMMXT_wCon         1
 233 #define ARM_IWMMXT_wCSSF        2
 234 #define ARM_IWMMXT_wCASF        3
 235 #define ARM_IWMMXT_wCGR0        8
 236 #define ARM_IWMMXT_wCGR1        9
 237 #define ARM_IWMMXT_wCGR2        10
 238 #define ARM_IWMMXT_wCGR3        11
 239
 240 enum arm_features {
 241     ARM_FEATURE_VFP,
 242     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 243     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 244     ARM_FEATURE_IWMMXT  /* Intel iwMMXt extension.  */
 245 };
 246
 247 static inline int arm_feature(CPUARMState *env, int feature)
 248 {
 249     return (env->features & (1u << feature)) != 0;
 250 }
 251
 252 void arm_cpu_list(void);
 253 void cpu_arm_set_model(CPUARMState *env, const char *name);
 254
 255 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 256                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 257                        void *opaque);
 258
 259 #define ARM_CPUID_ARM1026   0x4106a262
 260 #define ARM_CPUID_ARM926    0x41069265
 261 #define ARM_CPUID_PXA250    0x69052100
 262 #define ARM_CPUID_PXA255    0x69052d00
 263 #define ARM_CPUID_PXA260    0x69052903
 264 #define ARM_CPUID_PXA261    0x69052d05
 265 #define ARM_CPUID_PXA262    0x69052d06
 266 #define ARM_CPUID_PXA270    0x69054110
 267 #define ARM_CPUID_PXA270_A0 0x69054110
 268 #define ARM_CPUID_PXA270_A1 0x69054111
 269 #define ARM_CPUID_PXA270_B0 0x69054112
 270 #define ARM_CPUID_PXA270_B1 0x69054113
 271 #define ARM_CPUID_PXA270_C0 0x69054114
 272 #define ARM_CPUID_PXA270_C5 0x69054117
 273
 274 #if defined(CONFIG_USER_ONLY)
 275 #define TARGET_PAGE_BITS 12
 276 #else
 277 /* The ARM MMU allows 1k pages.  */
 278 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 279    architecture revisions.  Maybe an a configure option to disable them.  */
 280 #define TARGET_PAGE_BITS 10
 281 #endif
 282 #include "cpu-all.h"
 283
 284 #endif