target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cachetype;
 111         uint32_t c0_ccsid[16]; /* Cache size.  */
 112         uint32_t c0_clid; /* Cache level.  */
 113         uint32_t c0_cssel; /* Cache size selection.  */
 114         uint32_t c0_c1[8]; /* Feature registers.  */
 115         uint32_t c0_c2[8]; /* Instruction set registers.  */
 116         uint32_t c1_sys; /* System control register.  */
 117         uint32_t c1_coproc; /* Coprocessor access register.  */
 118         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 119         uint32_t c1_scr; /* secure config register.  */
 120         uint32_t c2_base0; /* MMU translation table base 0.  */
 121         uint32_t c2_base1; /* MMU translation table base 1.  */
 122         uint32_t c2_control; /* MMU translation table base control.  */
 123         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 124         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 125         uint32_t c2_data; /* MPU data cachable bits.  */
 126         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 127         uint32_t c3; /* MMU domain access control register
 128                         MPU write buffer control.  */
 129         uint32_t c5_insn; /* Fault status registers.  */
 130         uint32_t c5_data;
 131         uint32_t c6_region[8]; /* MPU base/size registers.  */
 132         uint32_t c6_insn; /* Fault address registers.  */
 133         uint32_t c6_data;
 134         uint32_t c7_par;  /* Translation result. */
 135         uint32_t c9_insn; /* Cache lockdown registers.  */
 136         uint32_t c9_data;
 137         uint32_t c9_pmcr; /* performance monitor control register */
 138         uint32_t c9_pmcnten; /* perf monitor counter enables */
 139         uint32_t c9_pmovsr; /* perf monitor overflow status */
 140         uint32_t c9_pmxevtyper; /* perf monitor event type */
 141         uint32_t c9_pmuserenr; /* perf monitor user enable */
 142         uint32_t c9_pminten; /* perf monitor interrupt enables */
 143         uint32_t c13_fcse; /* FCSE PID.  */
 144         uint32_t c13_context; /* Context ID.  */
 145         uint32_t c13_tls1; /* User RW Thread register.  */
 146         uint32_t c13_tls2; /* User RO Thread register.  */
 147         uint32_t c13_tls3; /* Privileged Thread register.  */
 148         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 149         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 150         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 151         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 152         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 153         uint32_t c15_config_base_address; /* SCU base address.  */
 154         uint32_t c15_diagnostic; /* diagnostic register */
 155         uint32_t c15_power_diagnostic;
 156         uint32_t c15_power_control; /* power control */
 157     } cp15;
 158
 159     struct {
 160         uint32_t other_sp;
 161         uint32_t vecbase;
 162         uint32_t basepri;
 163         uint32_t control;
 164         int current_sp;
 165         int exception;
 166         int pending_exception;
 167     } v7m;
 168
 169     /* Thumb-2 EE state.  */
 170     uint32_t teecr;
 171     uint32_t teehbr;
 172
 173     /* Internal CPU feature flags.  */
 174     uint32_t features;
 175
 176     /* VFP coprocessor state.  */
 177     struct {
 178         float64 regs[32];
 179
 180         uint32_t xregs[16];
 181         /* We store these fpcsr fields separately for convenience.  */
 182         int vec_len;
 183         int vec_stride;
 184
 185         /* scratch space when Tn are not sufficient.  */
 186         uint32_t scratch[8];
 187
 188         /* fp_status is the "normal" fp status. standard_fp_status retains
 189          * values corresponding to the ARM "Standard FPSCR Value", ie
 190          * default-NaN, flush-to-zero, round-to-nearest and is used by
 191          * any operations (generally Neon) which the architecture defines
 192          * as controlled by the standard FPSCR value rather than the FPSCR.
 193          *
 194          * To avoid having to transfer exception bits around, we simply
 195          * say that the FPSCR cumulative exception flags are the logical
 196          * OR of the flags in the two fp statuses. This relies on the
 197          * only thing which needs to read the exception flags being
 198          * an explicit FPSCR read.
 199          */
 200         float_status fp_status;
 201         float_status standard_fp_status;
 202     } vfp;
 203     uint32_t exclusive_addr;
 204     uint32_t exclusive_val;
 205     uint32_t exclusive_high;
 206 #if defined(CONFIG_USER_ONLY)
 207     uint32_t exclusive_test;
 208     uint32_t exclusive_info;
 209 #endif
 210
 211     /* iwMMXt coprocessor state.  */
 212     struct {
 213         uint64_t regs[16];
 214         uint64_t val;
 215
 216         uint32_t cregs[16];
 217     } iwmmxt;
 218
 219     /* For mixed endian mode.  */
 220     bool bswap_code;
 221
 222 #if defined(CONFIG_USER_ONLY)
 223     /* For usermode syscall translation.  */
 224     int eabi;
 225 #endif
 226
 227     CPU_COMMON
 228
 229     /* These fields after the common ones so they are preserved on reset.  */
 230
 231     /* Coprocessor IO used by peripherals */
 232     struct {
 233         ARMReadCPFunc *cp_read;
 234         ARMWriteCPFunc *cp_write;
 235         void *opaque;
 236     } cp[15];
 237     void *nvic;
 238     const struct arm_boot_info *boot_info;
 239 } CPUARMState;
 240
 241 CPUARMState *cpu_arm_init(const char *cpu_model);
 242 void arm_translate_init(void);
 243 int cpu_arm_exec(CPUARMState *s);
 244 void do_interrupt(CPUARMState *);
 245 void switch_mode(CPUARMState *, int);
 246 uint32_t do_arm_semihosting(CPUARMState *env);
 247
 248 /* you can call this signal handler from your SIGBUS and SIGSEGV
 249    signal handlers to inform the virtual CPU of exceptions. non zero
 250    is returned if the signal was handled by the virtual CPU.  */
 251 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 252                            void *puc);
 253 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 254                               int mmu_idx);
 255 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 256
 257 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 258 {
 259   env->cp15.c13_tls2 = newtls;
 260 }
 261
 262 #define CPSR_M (0x1f)
 263 #define CPSR_T (1 << 5)
 264 #define CPSR_F (1 << 6)
 265 #define CPSR_I (1 << 7)
 266 #define CPSR_A (1 << 8)
 267 #define CPSR_E (1 << 9)
 268 #define CPSR_IT_2_7 (0xfc00)
 269 #define CPSR_GE (0xf << 16)
 270 #define CPSR_RESERVED (0xf << 20)
 271 #define CPSR_J (1 << 24)
 272 #define CPSR_IT_0_1 (3 << 25)
 273 #define CPSR_Q (1 << 27)
 274 #define CPSR_V (1 << 28)
 275 #define CPSR_C (1 << 29)
 276 #define CPSR_Z (1 << 30)
 277 #define CPSR_N (1 << 31)
 278 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 279
 280 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 281 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 282 /* Bits writable in user mode.  */
 283 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 284 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 285 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 286
 287 /* Return the current CPSR value.  */
 288 uint32_t cpsr_read(CPUARMState *env);
 289 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 290 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 291
 292 /* Return the current xPSR value.  */
 293 static inline uint32_t xpsr_read(CPUARMState *env)
 294 {
 295     int ZF;
 296     ZF = (env->ZF == 0);
 297     return (env->NF & 0x80000000) | (ZF << 30)
 298         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 299         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 300         | ((env->condexec_bits & 0xfc) << 8)
 301         | env->v7m.exception;
 302 }
 303
 304 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 305 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 306 {
 307     if (mask & CPSR_NZCV) {
 308         env->ZF = (~val) & CPSR_Z;
 309         env->NF = val;
 310         env->CF = (val >> 29) & 1;
 311         env->VF = (val << 3) & 0x80000000;
 312     }
 313     if (mask & CPSR_Q)
 314         env->QF = ((val & CPSR_Q) != 0);
 315     if (mask & (1 << 24))
 316         env->thumb = ((val & (1 << 24)) != 0);
 317     if (mask & CPSR_IT_0_1) {
 318         env->condexec_bits &= ~3;
 319         env->condexec_bits |= (val >> 25) & 3;
 320     }
 321     if (mask & CPSR_IT_2_7) {
 322         env->condexec_bits &= 3;
 323         env->condexec_bits |= (val >> 8) & 0xfc;
 324     }
 325     if (mask & 0x1ff) {
 326         env->v7m.exception = val & 0x1ff;
 327     }
 328 }
 329
 330 /* Return the current FPSCR value.  */
 331 uint32_t vfp_get_fpscr(CPUARMState *env);
 332 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 333
 334 enum arm_cpu_mode {
 335   ARM_CPU_MODE_USR = 0x10,
 336   ARM_CPU_MODE_FIQ = 0x11,
 337   ARM_CPU_MODE_IRQ = 0x12,
 338   ARM_CPU_MODE_SVC = 0x13,
 339   ARM_CPU_MODE_ABT = 0x17,
 340   ARM_CPU_MODE_UND = 0x1b,
 341   ARM_CPU_MODE_SYS = 0x1f
 342 };
 343
 344 /* VFP system registers.  */
 345 #define ARM_VFP_FPSID   0
 346 #define ARM_VFP_FPSCR   1
 347 #define ARM_VFP_MVFR1   6
 348 #define ARM_VFP_MVFR0   7
 349 #define ARM_VFP_FPEXC   8
 350 #define ARM_VFP_FPINST  9
 351 #define ARM_VFP_FPINST2 10
 352
 353 /* iwMMXt coprocessor control registers.  */
 354 #define ARM_IWMMXT_wCID         0
 355 #define ARM_IWMMXT_wCon         1
 356 #define ARM_IWMMXT_wCSSF        2
 357 #define ARM_IWMMXT_wCASF        3
 358 #define ARM_IWMMXT_wCGR0        8
 359 #define ARM_IWMMXT_wCGR1        9
 360 #define ARM_IWMMXT_wCGR2        10
 361 #define ARM_IWMMXT_wCGR3        11
 362
 363 enum arm_features {
 364     ARM_FEATURE_VFP,
 365     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 366     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 367     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 368     ARM_FEATURE_V6,
 369     ARM_FEATURE_V6K,
 370     ARM_FEATURE_V7,
 371     ARM_FEATURE_THUMB2,
 372     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 373     ARM_FEATURE_VFP3,
 374     ARM_FEATURE_VFP_FP16,
 375     ARM_FEATURE_NEON,
 376     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 377     ARM_FEATURE_M, /* Microcontroller profile.  */
 378     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 379     ARM_FEATURE_THUMB2EE,
 380     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 381     ARM_FEATURE_V4T,
 382     ARM_FEATURE_V5,
 383     ARM_FEATURE_STRONGARM,
 384     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 385     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 386     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 387     ARM_FEATURE_GENERIC_TIMER,
 388     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 389 };
 390
 391 static inline int arm_feature(CPUARMState *env, int feature)
 392 {
 393     return (env->features & (1u << feature)) != 0;
 394 }
 395
 396 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 397
 398 /* Interface between CPU and Interrupt controller.  */
 399 void armv7m_nvic_set_pending(void *opaque, int irq);
 400 int armv7m_nvic_acknowledge_irq(void *opaque);
 401 void armv7m_nvic_complete_irq(void *opaque, int irq);
 402
 403 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 404                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 405                        void *opaque);
 406
 407 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 408    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 409    conventional cores (ie. Application or Realtime profile).  */
 410
 411 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 412 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 413
 414 #define ARM_CPUID_ARM1026     0x4106a262
 415 #define ARM_CPUID_ARM926      0x41069265
 416 #define ARM_CPUID_ARM946      0x41059461
 417 #define ARM_CPUID_TI915T      0x54029152
 418 #define ARM_CPUID_TI925T      0x54029252
 419 #define ARM_CPUID_SA1100      0x4401A11B
 420 #define ARM_CPUID_SA1110      0x6901B119
 421 #define ARM_CPUID_PXA250      0x69052100
 422 #define ARM_CPUID_PXA255      0x69052d00
 423 #define ARM_CPUID_PXA260      0x69052903
 424 #define ARM_CPUID_PXA261      0x69052d05
 425 #define ARM_CPUID_PXA262      0x69052d06
 426 #define ARM_CPUID_PXA270      0x69054110
 427 #define ARM_CPUID_PXA270_A0   0x69054110
 428 #define ARM_CPUID_PXA270_A1   0x69054111
 429 #define ARM_CPUID_PXA270_B0   0x69054112
 430 #define ARM_CPUID_PXA270_B1   0x69054113
 431 #define ARM_CPUID_PXA270_C0   0x69054114
 432 #define ARM_CPUID_PXA270_C5   0x69054117
 433 #define ARM_CPUID_ARM1136     0x4117b363
 434 #define ARM_CPUID_ARM1136_R2  0x4107b362
 435 #define ARM_CPUID_ARM1176     0x410fb767
 436 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 437 #define ARM_CPUID_CORTEXA8    0x410fc080
 438 #define ARM_CPUID_CORTEXA9    0x410fc090
 439 #define ARM_CPUID_CORTEXA15   0x412fc0f1
 440 #define ARM_CPUID_CORTEXM3    0x410fc231
 441 #define ARM_CPUID_ANY         0xffffffff
 442
 443 #if defined(CONFIG_USER_ONLY)
 444 #define TARGET_PAGE_BITS 12
 445 #else
 446 /* The ARM MMU allows 1k pages.  */
 447 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 448    architecture revisions.  Maybe a configure option to disable them.  */
 449 #define TARGET_PAGE_BITS 10
 450 #endif
 451
 452 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 453 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 454
 455 #define cpu_init cpu_arm_init
 456 #define cpu_exec cpu_arm_exec
 457 #define cpu_gen_code cpu_arm_gen_code
 458 #define cpu_signal_handler cpu_arm_signal_handler
 459 #define cpu_list arm_cpu_list
 460
 461 #define CPU_SAVE_VERSION 6
 462
 463 /* MMU modes definitions */
 464 #define MMU_MODE0_SUFFIX _kernel
 465 #define MMU_MODE1_SUFFIX _user
 466 #define MMU_USER_IDX 1
 467 static inline int cpu_mmu_index (CPUARMState *env)
 468 {
 469     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 470 }
 471
 472 #if defined(CONFIG_USER_ONLY)
 473 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 474 {
 475     if (newsp)
 476         env->regs[13] = newsp;
 477     env->regs[0] = 0;
 478 }
 479 #endif
 480
 481 #include "cpu-all.h"
 482 #include "cpu-qom.h"
 483
 484 /* Bit usage in the TB flags field: */
 485 #define ARM_TBFLAG_THUMB_SHIFT      0
 486 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 487 #define ARM_TBFLAG_VECLEN_SHIFT     1
 488 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 489 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 490 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 491 #define ARM_TBFLAG_PRIV_SHIFT       6
 492 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 493 #define ARM_TBFLAG_VFPEN_SHIFT      7
 494 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 495 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 496 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 497 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 498 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 499 /* Bits 31..17 are currently unused. */
 500
 501 /* some convenience accessor macros */
 502 #define ARM_TBFLAG_THUMB(F) \
 503     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 504 #define ARM_TBFLAG_VECLEN(F) \
 505     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 506 #define ARM_TBFLAG_VECSTRIDE(F) \
 507     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 508 #define ARM_TBFLAG_PRIV(F) \
 509     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 510 #define ARM_TBFLAG_VFPEN(F) \
 511     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 512 #define ARM_TBFLAG_CONDEXEC(F) \
 513     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 514 #define ARM_TBFLAG_BSWAP_CODE(F) \
 515     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 516
 517 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 518                                         target_ulong *cs_base, int *flags)
 519 {
 520     int privmode;
 521     *pc = env->regs[15];
 522     *cs_base = 0;
 523     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 524         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 525         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 526         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 527         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 528     if (arm_feature(env, ARM_FEATURE_M)) {
 529         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 530     } else {
 531         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 532     }
 533     if (privmode) {
 534         *flags |= ARM_TBFLAG_PRIV_MASK;
 535     }
 536     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 537         *flags |= ARM_TBFLAG_VFPEN_MASK;
 538     }
 539 }
 540
 541 static inline bool cpu_has_work(CPUARMState *env)
 542 {
 543     return env->interrupt_request &
 544         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 545 }
 546
 547 #include "exec-all.h"
 548
 549 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 550 {
 551     env->regs[15] = tb->pc;
 552 }
 553
 554 /* Load an instruction and return it in the standard little-endian order */
 555 static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
 556 {
 557     uint32_t insn = ldl_code(addr);
 558     if (do_swap) {
 559         return bswap32(insn);
 560     }
 561     return insn;
 562 }
 563
 564 /* Ditto, for a halfword (Thumb) instruction */
 565 static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
 566 {
 567     uint16_t insn = lduw_code(addr);
 568     if (do_swap) {
 569         return bswap16(insn);
 570     }
 571     return insn;
 572 }
 573
 574 #endif