]>
git.proxmox.com Git - qemu.git/blob - target-arm/helper.c
9 #include "qemu-common.h"
11 static uint32_t cortexa8_cp15_c0_c1
[8] =
12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14 static uint32_t cortexa8_cp15_c0_c2
[8] =
15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17 static uint32_t mpcore_cp15_c0_c1
[8] =
18 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
20 static uint32_t mpcore_cp15_c0_c2
[8] =
21 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
23 static uint32_t arm1136_cp15_c0_c1
[8] =
24 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
26 static uint32_t arm1136_cp15_c0_c2
[8] =
27 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
29 static uint32_t cpu_arm_find_by_name(const char *name
);
31 static inline void set_feature(CPUARMState
*env
, int feature
)
33 env
->features
|= 1u << feature
;
36 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
38 env
->cp15
.c0_cpuid
= id
;
40 case ARM_CPUID_ARM926
:
41 set_feature(env
, ARM_FEATURE_VFP
);
42 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
43 env
->cp15
.c0_cachetype
= 0x1dd20d2;
44 env
->cp15
.c1_sys
= 0x00090078;
46 case ARM_CPUID_ARM946
:
47 set_feature(env
, ARM_FEATURE_MPU
);
48 env
->cp15
.c0_cachetype
= 0x0f004006;
49 env
->cp15
.c1_sys
= 0x00000078;
51 case ARM_CPUID_ARM1026
:
52 set_feature(env
, ARM_FEATURE_VFP
);
53 set_feature(env
, ARM_FEATURE_AUXCR
);
54 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
55 env
->cp15
.c0_cachetype
= 0x1dd20d2;
56 env
->cp15
.c1_sys
= 0x00090078;
58 case ARM_CPUID_ARM1136
:
59 set_feature(env
, ARM_FEATURE_V6
);
60 set_feature(env
, ARM_FEATURE_VFP
);
61 set_feature(env
, ARM_FEATURE_AUXCR
);
62 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
63 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
64 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
65 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
66 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
67 env
->cp15
.c0_cachetype
= 0x1dd20d2;
69 case ARM_CPUID_ARM11MPCORE
:
70 set_feature(env
, ARM_FEATURE_V6
);
71 set_feature(env
, ARM_FEATURE_V6K
);
72 set_feature(env
, ARM_FEATURE_VFP
);
73 set_feature(env
, ARM_FEATURE_AUXCR
);
74 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
75 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
76 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
77 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
78 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
79 env
->cp15
.c0_cachetype
= 0x1dd20d2;
81 case ARM_CPUID_CORTEXA8
:
82 set_feature(env
, ARM_FEATURE_V6
);
83 set_feature(env
, ARM_FEATURE_V6K
);
84 set_feature(env
, ARM_FEATURE_V7
);
85 set_feature(env
, ARM_FEATURE_AUXCR
);
86 set_feature(env
, ARM_FEATURE_THUMB2
);
87 set_feature(env
, ARM_FEATURE_VFP
);
88 set_feature(env
, ARM_FEATURE_VFP3
);
89 set_feature(env
, ARM_FEATURE_NEON
);
90 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
91 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
92 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
93 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
94 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
95 env
->cp15
.c0_cachetype
= 0x1dd20d2;
97 case ARM_CPUID_CORTEXM3
:
98 set_feature(env
, ARM_FEATURE_V6
);
99 set_feature(env
, ARM_FEATURE_THUMB2
);
100 set_feature(env
, ARM_FEATURE_V7
);
101 set_feature(env
, ARM_FEATURE_M
);
102 set_feature(env
, ARM_FEATURE_DIV
);
104 case ARM_CPUID_ANY
: /* For userspace emulation. */
105 set_feature(env
, ARM_FEATURE_V6
);
106 set_feature(env
, ARM_FEATURE_V6K
);
107 set_feature(env
, ARM_FEATURE_V7
);
108 set_feature(env
, ARM_FEATURE_THUMB2
);
109 set_feature(env
, ARM_FEATURE_VFP
);
110 set_feature(env
, ARM_FEATURE_VFP3
);
111 set_feature(env
, ARM_FEATURE_NEON
);
112 set_feature(env
, ARM_FEATURE_DIV
);
114 case ARM_CPUID_TI915T
:
115 case ARM_CPUID_TI925T
:
116 set_feature(env
, ARM_FEATURE_OMAPCP
);
117 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
118 env
->cp15
.c0_cachetype
= 0x5109149;
119 env
->cp15
.c1_sys
= 0x00000070;
120 env
->cp15
.c15_i_max
= 0x000;
121 env
->cp15
.c15_i_min
= 0xff0;
123 case ARM_CPUID_PXA250
:
124 case ARM_CPUID_PXA255
:
125 case ARM_CPUID_PXA260
:
126 case ARM_CPUID_PXA261
:
127 case ARM_CPUID_PXA262
:
128 set_feature(env
, ARM_FEATURE_XSCALE
);
129 /* JTAG_ID is ((id << 28) | 0x09265013) */
130 env
->cp15
.c0_cachetype
= 0xd172172;
131 env
->cp15
.c1_sys
= 0x00000078;
133 case ARM_CPUID_PXA270_A0
:
134 case ARM_CPUID_PXA270_A1
:
135 case ARM_CPUID_PXA270_B0
:
136 case ARM_CPUID_PXA270_B1
:
137 case ARM_CPUID_PXA270_C0
:
138 case ARM_CPUID_PXA270_C5
:
139 set_feature(env
, ARM_FEATURE_XSCALE
);
140 /* JTAG_ID is ((id << 28) | 0x09265013) */
141 set_feature(env
, ARM_FEATURE_IWMMXT
);
142 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
143 env
->cp15
.c0_cachetype
= 0xd172172;
144 env
->cp15
.c1_sys
= 0x00000078;
147 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
152 void cpu_reset(CPUARMState
*env
)
155 id
= env
->cp15
.c0_cpuid
;
156 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
158 cpu_reset_model_id(env
, id
);
159 #if defined (CONFIG_USER_ONLY)
160 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
161 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
163 /* SVC mode with interrupts disabled. */
164 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
165 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
168 env
->uncached_cpsr
&= ~CPSR_I
;
169 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
175 CPUARMState
*cpu_arm_init(const char *cpu_model
)
179 static int inited
= 0;
181 id
= cpu_arm_find_by_name(cpu_model
);
184 env
= qemu_mallocz(sizeof(CPUARMState
));
190 arm_translate_init();
193 env
->cpu_model_str
= cpu_model
;
194 env
->cp15
.c0_cpuid
= id
;
204 static const struct arm_cpu_t arm_cpu_names
[] = {
205 { ARM_CPUID_ARM926
, "arm926"},
206 { ARM_CPUID_ARM946
, "arm946"},
207 { ARM_CPUID_ARM1026
, "arm1026"},
208 { ARM_CPUID_ARM1136
, "arm1136"},
209 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
210 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
211 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
212 { ARM_CPUID_TI925T
, "ti925t" },
213 { ARM_CPUID_PXA250
, "pxa250" },
214 { ARM_CPUID_PXA255
, "pxa255" },
215 { ARM_CPUID_PXA260
, "pxa260" },
216 { ARM_CPUID_PXA261
, "pxa261" },
217 { ARM_CPUID_PXA262
, "pxa262" },
218 { ARM_CPUID_PXA270
, "pxa270" },
219 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
220 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
221 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
222 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
223 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
224 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
225 { ARM_CPUID_ANY
, "any"},
229 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
233 (*cpu_fprintf
)(f
, "Available CPUs:\n");
234 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
235 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
239 /* return 0 if not found */
240 static uint32_t cpu_arm_find_by_name(const char *name
)
246 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
247 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
248 id
= arm_cpu_names
[i
].id
;
255 void cpu_arm_close(CPUARMState
*env
)
260 uint32_t cpsr_read(CPUARMState
*env
)
264 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
265 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
266 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
267 | ((env
->condexec_bits
& 0xfc) << 8)
271 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
273 if (mask
& CPSR_NZCV
) {
274 env
->ZF
= (~val
) & CPSR_Z
;
276 env
->CF
= (val
>> 29) & 1;
277 env
->VF
= (val
<< 3) & 0x80000000;
280 env
->QF
= ((val
& CPSR_Q
) != 0);
282 env
->thumb
= ((val
& CPSR_T
) != 0);
283 if (mask
& CPSR_IT_0_1
) {
284 env
->condexec_bits
&= ~3;
285 env
->condexec_bits
|= (val
>> 25) & 3;
287 if (mask
& CPSR_IT_2_7
) {
288 env
->condexec_bits
&= 3;
289 env
->condexec_bits
|= (val
>> 8) & 0xfc;
291 if (mask
& CPSR_GE
) {
292 env
->GE
= (val
>> 16) & 0xf;
295 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
296 switch_mode(env
, val
& CPSR_M
);
298 mask
&= ~CACHED_CPSR_BITS
;
299 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
302 /* Sign/zero extend */
303 uint32_t HELPER(sxtb16
)(uint32_t x
)
306 res
= (uint16_t)(int8_t)x
;
307 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
311 uint32_t HELPER(uxtb16
)(uint32_t x
)
314 res
= (uint16_t)(uint8_t)x
;
315 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
319 uint32_t HELPER(clz
)(uint32_t x
)
322 for (count
= 32; x
; count
--)
327 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
334 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
341 uint32_t HELPER(rbit
)(uint32_t x
)
343 x
= ((x
& 0xff000000) >> 24)
344 | ((x
& 0x00ff0000) >> 8)
345 | ((x
& 0x0000ff00) << 8)
346 | ((x
& 0x000000ff) << 24);
347 x
= ((x
& 0xf0f0f0f0) >> 4)
348 | ((x
& 0x0f0f0f0f) << 4);
349 x
= ((x
& 0x88888888) >> 3)
350 | ((x
& 0x44444444) >> 1)
351 | ((x
& 0x22222222) << 1)
352 | ((x
& 0x11111111) << 3);
356 uint32_t HELPER(abs
)(uint32_t x
)
358 return ((int32_t)x
< 0) ? -x
: x
;
361 #if defined(CONFIG_USER_ONLY)
363 void do_interrupt (CPUState
*env
)
365 env
->exception_index
= -1;
368 /* Structure used to record exclusive memory locations. */
369 typedef struct mmon_state
{
370 struct mmon_state
*next
;
371 CPUARMState
*cpu_env
;
375 /* Chain of current locks. */
376 static mmon_state
* mmon_head
= NULL
;
378 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
379 int mmu_idx
, int is_softmmu
)
382 env
->exception_index
= EXCP_PREFETCH_ABORT
;
383 env
->cp15
.c6_insn
= address
;
385 env
->exception_index
= EXCP_DATA_ABORT
;
386 env
->cp15
.c6_data
= address
;
391 static void allocate_mmon_state(CPUState
*env
)
393 env
->mmon_entry
= malloc(sizeof (mmon_state
));
394 if (!env
->mmon_entry
)
396 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
397 env
->mmon_entry
->cpu_env
= env
;
398 mmon_head
= env
->mmon_entry
;
401 /* Flush any monitor locks for the specified address. */
402 static void flush_mmon(uint32_t addr
)
406 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
408 if (mon
->addr
!= addr
)
416 /* Mark an address for exclusive access. */
417 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
419 if (!env
->mmon_entry
)
420 allocate_mmon_state(env
);
421 /* Clear any previous locks. */
423 env
->mmon_entry
->addr
= addr
;
426 /* Test if an exclusive address is still exclusive. Returns zero
427 if the address is still exclusive. */
428 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
432 if (!env
->mmon_entry
)
434 if (env
->mmon_entry
->addr
== addr
)
442 void HELPER(clrex
)(CPUState
*env
)
444 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
446 flush_mmon(env
->mmon_entry
->addr
);
449 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
454 /* These should probably raise undefined insn exceptions. */
455 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
457 int op1
= (insn
>> 8) & 0xf;
458 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
462 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
464 int op1
= (insn
>> 8) & 0xf;
465 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
469 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
471 cpu_abort(env
, "cp15 insn %08x\n", insn
);
474 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
476 cpu_abort(env
, "cp15 insn %08x\n", insn
);
480 /* These should probably raise undefined insn exceptions. */
481 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
483 cpu_abort(env
, "v7m_mrs %d\n", reg
);
486 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
488 cpu_abort(env
, "v7m_mrs %d\n", reg
);
492 void switch_mode(CPUState
*env
, int mode
)
494 if (mode
!= ARM_CPU_MODE_USR
)
495 cpu_abort(env
, "Tried to switch out of user mode\n");
498 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
500 cpu_abort(env
, "banked r13 write\n");
503 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
505 cpu_abort(env
, "banked r13 read\n");
511 extern int semihosting_enabled
;
513 /* Map CPU modes onto saved register banks. */
514 static inline int bank_number (int mode
)
517 case ARM_CPU_MODE_USR
:
518 case ARM_CPU_MODE_SYS
:
520 case ARM_CPU_MODE_SVC
:
522 case ARM_CPU_MODE_ABT
:
524 case ARM_CPU_MODE_UND
:
526 case ARM_CPU_MODE_IRQ
:
528 case ARM_CPU_MODE_FIQ
:
531 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
535 void switch_mode(CPUState
*env
, int mode
)
540 old_mode
= env
->uncached_cpsr
& CPSR_M
;
541 if (mode
== old_mode
)
544 if (old_mode
== ARM_CPU_MODE_FIQ
) {
545 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
546 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
547 } else if (mode
== ARM_CPU_MODE_FIQ
) {
548 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
549 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
552 i
= bank_number(old_mode
);
553 env
->banked_r13
[i
] = env
->regs
[13];
554 env
->banked_r14
[i
] = env
->regs
[14];
555 env
->banked_spsr
[i
] = env
->spsr
;
557 i
= bank_number(mode
);
558 env
->regs
[13] = env
->banked_r13
[i
];
559 env
->regs
[14] = env
->banked_r14
[i
];
560 env
->spsr
= env
->banked_spsr
[i
];
563 static void v7m_push(CPUARMState
*env
, uint32_t val
)
566 stl_phys(env
->regs
[13], val
);
569 static uint32_t v7m_pop(CPUARMState
*env
)
572 val
= ldl_phys(env
->regs
[13]);
577 /* Switch to V7M main or process stack pointer. */
578 static void switch_v7m_sp(CPUARMState
*env
, int process
)
581 if (env
->v7m
.current_sp
!= process
) {
582 tmp
= env
->v7m
.other_sp
;
583 env
->v7m
.other_sp
= env
->regs
[13];
585 env
->v7m
.current_sp
= process
;
589 static void do_v7m_exception_exit(CPUARMState
*env
)
594 type
= env
->regs
[15];
595 if (env
->v7m
.exception
!= 0)
596 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
598 /* Switch to the target stack. */
599 switch_v7m_sp(env
, (type
& 4) != 0);
601 env
->regs
[0] = v7m_pop(env
);
602 env
->regs
[1] = v7m_pop(env
);
603 env
->regs
[2] = v7m_pop(env
);
604 env
->regs
[3] = v7m_pop(env
);
605 env
->regs
[12] = v7m_pop(env
);
606 env
->regs
[14] = v7m_pop(env
);
607 env
->regs
[15] = v7m_pop(env
);
609 xpsr_write(env
, xpsr
, 0xfffffdff);
610 /* Undo stack alignment. */
613 /* ??? The exception return type specifies Thread/Handler mode. However
614 this is also implied by the xPSR value. Not sure what to do
615 if there is a mismatch. */
616 /* ??? Likewise for mismatches between the CONTROL register and the stack
620 void do_interrupt_v7m(CPUARMState
*env
)
622 uint32_t xpsr
= xpsr_read(env
);
627 if (env
->v7m
.current_sp
)
629 if (env
->v7m
.exception
== 0)
632 /* For exceptions we just mark as pending on the NVIC, and let that
634 /* TODO: Need to escalate if the current priority is higher than the
635 one we're raising. */
636 switch (env
->exception_index
) {
638 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
642 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
644 case EXCP_PREFETCH_ABORT
:
645 case EXCP_DATA_ABORT
:
646 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
649 if (semihosting_enabled
) {
651 nr
= lduw_code(env
->regs
[15]) & 0xff;
654 env
->regs
[0] = do_arm_semihosting(env
);
658 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
661 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
663 case EXCP_EXCEPTION_EXIT
:
664 do_v7m_exception_exit(env
);
667 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
668 return; /* Never happens. Keep compiler happy. */
671 /* Align stack pointer. */
672 /* ??? Should only do this if Configuration Control Register
673 STACKALIGN bit is set. */
674 if (env
->regs
[13] & 4) {
678 /* Switch to the hander mode. */
680 v7m_push(env
, env
->regs
[15]);
681 v7m_push(env
, env
->regs
[14]);
682 v7m_push(env
, env
->regs
[12]);
683 v7m_push(env
, env
->regs
[3]);
684 v7m_push(env
, env
->regs
[2]);
685 v7m_push(env
, env
->regs
[1]);
686 v7m_push(env
, env
->regs
[0]);
687 switch_v7m_sp(env
, 0);
688 env
->uncached_cpsr
&= ~CPSR_IT
;
690 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
691 env
->regs
[15] = addr
& 0xfffffffe;
692 env
->thumb
= addr
& 1;
695 /* Handle a CPU exception. */
696 void do_interrupt(CPUARMState
*env
)
704 do_interrupt_v7m(env
);
707 /* TODO: Vectored interrupt controller. */
708 switch (env
->exception_index
) {
710 new_mode
= ARM_CPU_MODE_UND
;
719 if (semihosting_enabled
) {
720 /* Check for semihosting interrupt. */
722 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
724 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
726 /* Only intercept calls from privileged modes, to provide some
727 semblance of security. */
728 if (((mask
== 0x123456 && !env
->thumb
)
729 || (mask
== 0xab && env
->thumb
))
730 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
731 env
->regs
[0] = do_arm_semihosting(env
);
735 new_mode
= ARM_CPU_MODE_SVC
;
738 /* The PC already points to the next instructon. */
742 /* See if this is a semihosting syscall. */
743 if (env
->thumb
&& semihosting_enabled
) {
744 mask
= lduw_code(env
->regs
[15]) & 0xff;
746 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
748 env
->regs
[0] = do_arm_semihosting(env
);
752 /* Fall through to prefetch abort. */
753 case EXCP_PREFETCH_ABORT
:
754 new_mode
= ARM_CPU_MODE_ABT
;
756 mask
= CPSR_A
| CPSR_I
;
759 case EXCP_DATA_ABORT
:
760 new_mode
= ARM_CPU_MODE_ABT
;
762 mask
= CPSR_A
| CPSR_I
;
766 new_mode
= ARM_CPU_MODE_IRQ
;
768 /* Disable IRQ and imprecise data aborts. */
769 mask
= CPSR_A
| CPSR_I
;
773 new_mode
= ARM_CPU_MODE_FIQ
;
775 /* Disable FIQ, IRQ and imprecise data aborts. */
776 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
780 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
781 return; /* Never happens. Keep compiler happy. */
784 if (env
->cp15
.c1_sys
& (1 << 13)) {
787 switch_mode (env
, new_mode
);
788 env
->spsr
= cpsr_read(env
);
790 env
->condexec_bits
= 0;
791 /* Switch to the new mode, and switch to Arm mode. */
792 /* ??? Thumb interrupt handlers not implemented. */
793 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
794 env
->uncached_cpsr
|= mask
;
796 env
->regs
[14] = env
->regs
[15] + offset
;
797 env
->regs
[15] = addr
;
798 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
801 /* Check section/page access permissions.
802 Returns the page protection flags, or zero if the access is not
804 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
810 return PAGE_READ
| PAGE_WRITE
;
812 if (access_type
== 1)
819 if (access_type
== 1)
821 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
823 return is_user
? 0 : PAGE_READ
;
830 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
835 return PAGE_READ
| PAGE_WRITE
;
837 return PAGE_READ
| PAGE_WRITE
;
838 case 4: case 7: /* Reserved. */
841 return is_user
? 0 : prot_ro
;
849 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
850 int is_user
, uint32_t *phys_ptr
, int *prot
)
860 /* Pagetable walk. */
861 /* Lookup l1 descriptor. */
862 if (address
& env
->cp15
.c2_mask
)
863 table
= env
->cp15
.c2_base1
;
865 table
= env
->cp15
.c2_base0
;
866 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
867 desc
= ldl_phys(table
);
869 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
871 /* Secton translation fault. */
875 if (domain
== 0 || domain
== 2) {
877 code
= 9; /* Section domain fault. */
879 code
= 11; /* Page domain fault. */
884 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
885 ap
= (desc
>> 10) & 3;
888 /* Lookup l2 entry. */
890 /* Coarse pagetable. */
891 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
893 /* Fine pagetable. */
894 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
896 desc
= ldl_phys(table
);
898 case 0: /* Page translation fault. */
901 case 1: /* 64k page. */
902 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
903 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
905 case 2: /* 4k page. */
906 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
907 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
909 case 3: /* 1k page. */
911 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
912 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
914 /* Page translation fault. */
919 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
921 ap
= (desc
>> 4) & 3;
924 /* Never happens, but compiler isn't smart enough to tell. */
929 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
931 /* Access permission fault. */
934 *phys_ptr
= phys_addr
;
937 return code
| (domain
<< 4);
940 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
941 int is_user
, uint32_t *phys_ptr
, int *prot
)
952 /* Pagetable walk. */
953 /* Lookup l1 descriptor. */
954 if (address
& env
->cp15
.c2_mask
)
955 table
= env
->cp15
.c2_base1
;
957 table
= env
->cp15
.c2_base0
;
958 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
959 desc
= ldl_phys(table
);
962 /* Secton translation fault. */
966 } else if (type
== 2 && (desc
& (1 << 18))) {
970 /* Section or page. */
971 domain
= (desc
>> 4) & 0x1e;
973 domain
= (env
->cp15
.c3
>> domain
) & 3;
974 if (domain
== 0 || domain
== 2) {
976 code
= 9; /* Section domain fault. */
978 code
= 11; /* Page domain fault. */
982 if (desc
& (1 << 18)) {
984 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
987 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
989 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
990 xn
= desc
& (1 << 4);
993 /* Lookup l2 entry. */
994 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
995 desc
= ldl_phys(table
);
996 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
998 case 0: /* Page translation fault. */
1001 case 1: /* 64k page. */
1002 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1003 xn
= desc
& (1 << 15);
1005 case 2: case 3: /* 4k page. */
1006 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1010 /* Never happens, but compiler isn't smart enough to tell. */
1015 if (xn
&& access_type
== 2)
1018 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1020 /* Access permission fault. */
1023 *phys_ptr
= phys_addr
;
1026 return code
| (domain
<< 4);
1029 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1030 int is_user
, uint32_t *phys_ptr
, int *prot
)
1036 *phys_ptr
= address
;
1037 for (n
= 7; n
>= 0; n
--) {
1038 base
= env
->cp15
.c6_region
[n
];
1039 if ((base
& 1) == 0)
1041 mask
= 1 << ((base
>> 1) & 0x1f);
1042 /* Keep this shift separate from the above to avoid an
1043 (undefined) << 32. */
1044 mask
= (mask
<< 1) - 1;
1045 if (((base
^ address
) & ~mask
) == 0)
1051 if (access_type
== 2) {
1052 mask
= env
->cp15
.c5_insn
;
1054 mask
= env
->cp15
.c5_data
;
1056 mask
= (mask
>> (n
* 4)) & 0xf;
1063 *prot
= PAGE_READ
| PAGE_WRITE
;
1068 *prot
|= PAGE_WRITE
;
1071 *prot
= PAGE_READ
| PAGE_WRITE
;
1082 /* Bad permission. */
1088 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1089 int access_type
, int is_user
,
1090 uint32_t *phys_ptr
, int *prot
)
1092 /* Fast Context Switch Extension. */
1093 if (address
< 0x02000000)
1094 address
+= env
->cp15
.c13_fcse
;
1096 if ((env
->cp15
.c1_sys
& 1) == 0) {
1097 /* MMU/MPU disabled. */
1098 *phys_ptr
= address
;
1099 *prot
= PAGE_READ
| PAGE_WRITE
;
1101 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1102 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1104 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1105 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1108 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1113 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1114 int access_type
, int mmu_idx
, int is_softmmu
)
1120 is_user
= mmu_idx
== MMU_USER_IDX
;
1121 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1123 /* Map a single [sub]page. */
1124 phys_addr
&= ~(uint32_t)0x3ff;
1125 address
&= ~(uint32_t)0x3ff;
1126 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1130 if (access_type
== 2) {
1131 env
->cp15
.c5_insn
= ret
;
1132 env
->cp15
.c6_insn
= address
;
1133 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1135 env
->cp15
.c5_data
= ret
;
1136 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1137 env
->cp15
.c5_data
|= (1 << 11);
1138 env
->cp15
.c6_data
= address
;
1139 env
->exception_index
= EXCP_DATA_ABORT
;
1144 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1150 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1158 /* Not really implemented. Need to figure out a sane way of doing this.
1159 Maybe add generic watchpoint support and use that. */
1161 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
1163 env
->mmon_addr
= addr
;
1166 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
1168 return (env
->mmon_addr
!= addr
);
1171 void HELPER(clrex
)(CPUState
*env
)
1173 env
->mmon_addr
= -1;
1176 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1178 int cp_num
= (insn
>> 8) & 0xf;
1179 int cp_info
= (insn
>> 5) & 7;
1180 int src
= (insn
>> 16) & 0xf;
1181 int operand
= insn
& 0xf;
1183 if (env
->cp
[cp_num
].cp_write
)
1184 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1185 cp_info
, src
, operand
, val
);
1188 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1190 int cp_num
= (insn
>> 8) & 0xf;
1191 int cp_info
= (insn
>> 5) & 7;
1192 int dest
= (insn
>> 16) & 0xf;
1193 int operand
= insn
& 0xf;
1195 if (env
->cp
[cp_num
].cp_read
)
1196 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1197 cp_info
, dest
, operand
);
1201 /* Return basic MPU access permission bits. */
1202 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1209 for (i
= 0; i
< 16; i
+= 2) {
1210 ret
|= (val
>> i
) & mask
;
1216 /* Pad basic MPU access permission bits to extended format. */
1217 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1224 for (i
= 0; i
< 16; i
+= 2) {
1225 ret
|= (val
& mask
) << i
;
1231 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1237 op1
= (insn
>> 21) & 7;
1238 op2
= (insn
>> 5) & 7;
1240 switch ((insn
>> 16) & 0xf) {
1242 if (((insn
>> 21) & 7) == 2) {
1243 /* ??? Select cache level. Ignore. */
1247 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1249 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1252 case 1: /* System configuration. */
1253 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1257 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1258 env
->cp15
.c1_sys
= val
;
1259 /* ??? Lots of these bits are not implemented. */
1260 /* This may enable/disable the MMU, so do a TLB flush. */
1263 case 1: /* Auxiliary cotrol register. */
1264 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1265 env
->cp15
.c1_xscaleauxcr
= val
;
1268 /* Not implemented. */
1271 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1273 env
->cp15
.c1_coproc
= val
;
1274 /* ??? Is this safe when called from within a TB? */
1281 case 2: /* MMU Page table control / MPU cache control. */
1282 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1285 env
->cp15
.c2_data
= val
;
1288 env
->cp15
.c2_insn
= val
;
1296 env
->cp15
.c2_base0
= val
;
1299 env
->cp15
.c2_base1
= val
;
1302 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1309 case 3: /* MMU Domain access control / MPU write buffer control. */
1311 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1313 case 4: /* Reserved. */
1315 case 5: /* MMU Fault status / MPU access permission. */
1316 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1320 if (arm_feature(env
, ARM_FEATURE_MPU
))
1321 val
= extended_mpu_ap_bits(val
);
1322 env
->cp15
.c5_data
= val
;
1325 if (arm_feature(env
, ARM_FEATURE_MPU
))
1326 val
= extended_mpu_ap_bits(val
);
1327 env
->cp15
.c5_insn
= val
;
1330 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1332 env
->cp15
.c5_data
= val
;
1335 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1337 env
->cp15
.c5_insn
= val
;
1343 case 6: /* MMU Fault address / MPU base/size. */
1344 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1347 env
->cp15
.c6_region
[crm
] = val
;
1349 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1353 env
->cp15
.c6_data
= val
;
1355 case 1: /* ??? This is WFAR on armv6 */
1357 env
->cp15
.c6_insn
= val
;
1364 case 7: /* Cache control. */
1365 env
->cp15
.c15_i_max
= 0x000;
1366 env
->cp15
.c15_i_min
= 0xff0;
1367 /* No cache, so nothing to do. */
1368 /* ??? MPCore has VA to PA translation functions. */
1370 case 8: /* MMU TLB control. */
1372 case 0: /* Invalidate all. */
1375 case 1: /* Invalidate single TLB entry. */
1377 /* ??? This is wrong for large pages and sections. */
1378 /* As an ugly hack to make linux work we always flush a 4K
1381 tlb_flush_page(env
, val
);
1382 tlb_flush_page(env
, val
+ 0x400);
1383 tlb_flush_page(env
, val
+ 0x800);
1384 tlb_flush_page(env
, val
+ 0xc00);
1389 case 2: /* Invalidate on ASID. */
1390 tlb_flush(env
, val
== 0);
1392 case 3: /* Invalidate single entry on MVA. */
1393 /* ??? This is like case 1, but ignores ASID. */
1401 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1404 case 0: /* Cache lockdown. */
1406 case 0: /* L1 cache. */
1409 env
->cp15
.c9_data
= val
;
1412 env
->cp15
.c9_insn
= val
;
1418 case 1: /* L2 cache. */
1419 /* Ignore writes to L2 lockdown/auxiliary registers. */
1425 case 1: /* TCM memory region registers. */
1426 /* Not implemented. */
1432 case 10: /* MMU TLB lockdown. */
1433 /* ??? TLB lockdown not implemented. */
1435 case 12: /* Reserved. */
1437 case 13: /* Process ID. */
1440 /* Unlike real hardware the qemu TLB uses virtual addresses,
1441 not modified virtual addresses, so this causes a TLB flush.
1443 if (env
->cp15
.c13_fcse
!= val
)
1445 env
->cp15
.c13_fcse
= val
;
1448 /* This changes the ASID, so do a TLB flush. */
1449 if (env
->cp15
.c13_context
!= val
1450 && !arm_feature(env
, ARM_FEATURE_MPU
))
1452 env
->cp15
.c13_context
= val
;
1455 env
->cp15
.c13_tls1
= val
;
1458 env
->cp15
.c13_tls2
= val
;
1461 env
->cp15
.c13_tls3
= val
;
1467 case 14: /* Reserved. */
1469 case 15: /* Implementation specific. */
1470 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1471 if (op2
== 0 && crm
== 1) {
1472 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1473 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1475 env
->cp15
.c15_cpar
= val
& 0x3fff;
1481 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1485 case 1: /* Set TI925T configuration. */
1486 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1487 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1488 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1490 case 2: /* Set I_max. */
1491 env
->cp15
.c15_i_max
= val
;
1493 case 3: /* Set I_min. */
1494 env
->cp15
.c15_i_min
= val
;
1496 case 4: /* Set thread-ID. */
1497 env
->cp15
.c15_threadid
= val
& 0xffff;
1499 case 8: /* Wait-for-interrupt (deprecated). */
1500 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1510 /* ??? For debugging only. Should raise illegal instruction exception. */
1511 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1512 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1515 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1521 op1
= (insn
>> 21) & 7;
1522 op2
= (insn
>> 5) & 7;
1524 switch ((insn
>> 16) & 0xf) {
1525 case 0: /* ID codes. */
1531 case 0: /* Device ID. */
1532 return env
->cp15
.c0_cpuid
;
1533 case 1: /* Cache Type. */
1534 return env
->cp15
.c0_cachetype
;
1535 case 2: /* TCM status. */
1537 case 3: /* TLB type register. */
1538 return 0; /* No lockable TLB entries. */
1539 case 5: /* CPU ID */
1540 return env
->cpu_index
;
1545 if (!arm_feature(env
, ARM_FEATURE_V6
))
1547 return env
->cp15
.c0_c1
[op2
];
1549 if (!arm_feature(env
, ARM_FEATURE_V6
))
1551 return env
->cp15
.c0_c2
[op2
];
1552 case 3: case 4: case 5: case 6: case 7:
1558 /* These registers aren't documented on arm11 cores. However
1559 Linux looks at them anyway. */
1560 if (!arm_feature(env
, ARM_FEATURE_V6
))
1564 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1570 case 1: /* System configuration. */
1571 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1574 case 0: /* Control register. */
1575 return env
->cp15
.c1_sys
;
1576 case 1: /* Auxiliary control register. */
1577 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1578 return env
->cp15
.c1_xscaleauxcr
;
1579 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1581 switch (ARM_CPUID(env
)) {
1582 case ARM_CPUID_ARM1026
:
1584 case ARM_CPUID_ARM1136
:
1586 case ARM_CPUID_ARM11MPCORE
:
1588 case ARM_CPUID_CORTEXA8
:
1593 case 2: /* Coprocessor access register. */
1594 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1596 return env
->cp15
.c1_coproc
;
1600 case 2: /* MMU Page table control / MPU cache control. */
1601 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1604 return env
->cp15
.c2_data
;
1607 return env
->cp15
.c2_insn
;
1615 return env
->cp15
.c2_base0
;
1617 return env
->cp15
.c2_base1
;
1623 mask
= env
->cp15
.c2_mask
;
1634 case 3: /* MMU Domain access control / MPU write buffer control. */
1635 return env
->cp15
.c3
;
1636 case 4: /* Reserved. */
1638 case 5: /* MMU Fault status / MPU access permission. */
1639 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1643 if (arm_feature(env
, ARM_FEATURE_MPU
))
1644 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1645 return env
->cp15
.c5_data
;
1647 if (arm_feature(env
, ARM_FEATURE_MPU
))
1648 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1649 return env
->cp15
.c5_insn
;
1651 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1653 return env
->cp15
.c5_data
;
1655 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1657 return env
->cp15
.c5_insn
;
1661 case 6: /* MMU Fault address. */
1662 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1665 return env
->cp15
.c6_region
[crm
];
1667 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1671 return env
->cp15
.c6_data
;
1673 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1674 /* Watchpoint Fault Adrress. */
1675 return 0; /* Not implemented. */
1677 /* Instruction Fault Adrress. */
1678 /* Arm9 doesn't have an IFAR, but implementing it anyway
1679 shouldn't do any harm. */
1680 return env
->cp15
.c6_insn
;
1683 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1684 /* Instruction Fault Adrress. */
1685 return env
->cp15
.c6_insn
;
1693 case 7: /* Cache control. */
1694 /* FIXME: Should only clear Z flag if destination is r15. */
1697 case 8: /* MMU TLB control. */
1699 case 9: /* Cache lockdown. */
1701 case 0: /* L1 cache. */
1702 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1706 return env
->cp15
.c9_data
;
1708 return env
->cp15
.c9_insn
;
1712 case 1: /* L2 cache */
1715 /* L2 Lockdown and Auxiliary control. */
1720 case 10: /* MMU TLB lockdown. */
1721 /* ??? TLB lockdown not implemented. */
1723 case 11: /* TCM DMA control. */
1724 case 12: /* Reserved. */
1726 case 13: /* Process ID. */
1729 return env
->cp15
.c13_fcse
;
1731 return env
->cp15
.c13_context
;
1733 return env
->cp15
.c13_tls1
;
1735 return env
->cp15
.c13_tls2
;
1737 return env
->cp15
.c13_tls3
;
1741 case 14: /* Reserved. */
1743 case 15: /* Implementation specific. */
1744 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1745 if (op2
== 0 && crm
== 1)
1746 return env
->cp15
.c15_cpar
;
1750 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1754 case 1: /* Read TI925T configuration. */
1755 return env
->cp15
.c15_ticonfig
;
1756 case 2: /* Read I_max. */
1757 return env
->cp15
.c15_i_max
;
1758 case 3: /* Read I_min. */
1759 return env
->cp15
.c15_i_min
;
1760 case 4: /* Read thread-ID. */
1761 return env
->cp15
.c15_threadid
;
1762 case 8: /* TI925T_status */
1770 /* ??? For debugging only. Should raise illegal instruction exception. */
1771 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1772 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1776 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1778 env
->banked_r13
[bank_number(mode
)] = val
;
1781 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1783 return env
->banked_r13
[bank_number(mode
)];
1786 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1790 return xpsr_read(env
) & 0xf8000000;
1792 return xpsr_read(env
) & 0xf80001ff;
1794 return xpsr_read(env
) & 0xff00fc00;
1796 return xpsr_read(env
) & 0xff00fdff;
1798 return xpsr_read(env
) & 0x000001ff;
1800 return xpsr_read(env
) & 0x0700fc00;
1802 return xpsr_read(env
) & 0x0700edff;
1804 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1806 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1807 case 16: /* PRIMASK */
1808 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1809 case 17: /* FAULTMASK */
1810 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1811 case 18: /* BASEPRI */
1812 case 19: /* BASEPRI_MAX */
1813 return env
->v7m
.basepri
;
1814 case 20: /* CONTROL */
1815 return env
->v7m
.control
;
1817 /* ??? For debugging only. */
1818 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1823 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1827 xpsr_write(env
, val
, 0xf8000000);
1830 xpsr_write(env
, val
, 0xf8000000);
1833 xpsr_write(env
, val
, 0xfe00fc00);
1836 xpsr_write(env
, val
, 0xfe00fc00);
1839 /* IPSR bits are readonly. */
1842 xpsr_write(env
, val
, 0x0600fc00);
1845 xpsr_write(env
, val
, 0x0600fc00);
1848 if (env
->v7m
.current_sp
)
1849 env
->v7m
.other_sp
= val
;
1851 env
->regs
[13] = val
;
1854 if (env
->v7m
.current_sp
)
1855 env
->regs
[13] = val
;
1857 env
->v7m
.other_sp
= val
;
1859 case 16: /* PRIMASK */
1861 env
->uncached_cpsr
|= CPSR_I
;
1863 env
->uncached_cpsr
&= ~CPSR_I
;
1865 case 17: /* FAULTMASK */
1867 env
->uncached_cpsr
|= CPSR_F
;
1869 env
->uncached_cpsr
&= ~CPSR_F
;
1871 case 18: /* BASEPRI */
1872 env
->v7m
.basepri
= val
& 0xff;
1874 case 19: /* BASEPRI_MAX */
1876 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1877 env
->v7m
.basepri
= val
;
1879 case 20: /* CONTROL */
1880 env
->v7m
.control
= val
& 3;
1881 switch_v7m_sp(env
, (val
& 2) != 0);
1884 /* ??? For debugging only. */
1885 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1890 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1891 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1894 if (cpnum
< 0 || cpnum
> 14) {
1895 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1899 env
->cp
[cpnum
].cp_read
= cp_read
;
1900 env
->cp
[cpnum
].cp_write
= cp_write
;
1901 env
->cp
[cpnum
].opaque
= opaque
;
1906 /* Note that signed overflow is undefined in C. The following routines are
1907 careful to use unsigned types where modulo arithmetic is required.
1908 Failure to do so _will_ break on newer gcc. */
1910 /* Signed saturating arithmetic. */
1912 /* Perform 16-bit signed saturating addition. */
1913 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
1918 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
1927 /* Perform 8-bit signed saturating addition. */
1928 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
1933 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
1942 /* Perform 16-bit signed saturating subtraction. */
1943 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
1948 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
1957 /* Perform 8-bit signed saturating subtraction. */
1958 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
1963 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
1972 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
1973 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
1974 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
1975 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
1978 #include "op_addsub.h"
1980 /* Unsigned saturating arithmetic. */
1981 static inline uint16_t add16_usat(uint16_t a
, uint8_t b
)
1990 static inline uint16_t sub16_usat(uint16_t a
, uint8_t b
)
1998 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2007 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2015 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2016 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2017 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2018 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2021 #include "op_addsub.h"
2023 /* Signed modulo arithmetic. */
2024 #define SARITH16(a, b, n, op) do { \
2026 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2027 RESULT(sum, n, 16); \
2029 ge |= 3 << (n * 2); \
2032 #define SARITH8(a, b, n, op) do { \
2034 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2035 RESULT(sum, n, 8); \
2041 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2042 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2043 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2044 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2048 #include "op_addsub.h"
2050 /* Unsigned modulo arithmetic. */
2051 #define ADD16(a, b, n) do { \
2053 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2054 RESULT(sum, n, 16); \
2055 if ((sum >> 16) == 0) \
2056 ge |= 3 << (n * 2); \
2059 #define ADD8(a, b, n) do { \
2061 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2062 RESULT(sum, n, 8); \
2063 if ((sum >> 8) == 0) \
2064 ge |= 3 << (n * 2); \
2067 #define SUB16(a, b, n) do { \
2069 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2070 RESULT(sum, n, 16); \
2071 if ((sum >> 16) == 0) \
2072 ge |= 3 << (n * 2); \
2075 #define SUB8(a, b, n) do { \
2077 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2078 RESULT(sum, n, 8); \
2079 if ((sum >> 8) == 0) \
2080 ge |= 3 << (n * 2); \
2086 #include "op_addsub.h"
2088 /* Halved signed arithmetic. */
2089 #define ADD16(a, b, n) \
2090 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2091 #define SUB16(a, b, n) \
2092 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2093 #define ADD8(a, b, n) \
2094 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2095 #define SUB8(a, b, n) \
2096 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2099 #include "op_addsub.h"
2101 /* Halved unsigned arithmetic. */
2102 #define ADD16(a, b, n) \
2103 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2104 #define SUB16(a, b, n) \
2105 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2106 #define ADD8(a, b, n) \
2107 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2108 #define SUB8(a, b, n) \
2109 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2112 #include "op_addsub.h"
2114 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2122 /* Unsigned sum of absolute byte differences. */
2123 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2126 sum
= do_usad(a
, b
);
2127 sum
+= do_usad(a
>> 8, b
>> 8);
2128 sum
+= do_usad(a
>> 16, b
>>16);
2129 sum
+= do_usad(a
>> 24, b
>> 24);
2133 /* For ARMv6 SEL instruction. */
2134 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2147 return (a
& mask
) | (b
& ~mask
);
2150 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2152 return (val
>> 32) | (val
!= 0);
2155 /* VFP support. We follow the convention used for VFP instrunctions:
2156 Single precition routines have a "s" suffix, double precision a
2159 /* Convert host exception flags to vfp form. */
2160 static inline int vfp_exceptbits_from_host(int host_bits
)
2162 int target_bits
= 0;
2164 if (host_bits
& float_flag_invalid
)
2166 if (host_bits
& float_flag_divbyzero
)
2168 if (host_bits
& float_flag_overflow
)
2170 if (host_bits
& float_flag_underflow
)
2172 if (host_bits
& float_flag_inexact
)
2173 target_bits
|= 0x10;
2177 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2182 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2183 | (env
->vfp
.vec_len
<< 16)
2184 | (env
->vfp
.vec_stride
<< 20);
2185 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2186 fpscr
|= vfp_exceptbits_from_host(i
);
2190 /* Convert vfp exception flags to target form. */
2191 static inline int vfp_exceptbits_to_host(int target_bits
)
2195 if (target_bits
& 1)
2196 host_bits
|= float_flag_invalid
;
2197 if (target_bits
& 2)
2198 host_bits
|= float_flag_divbyzero
;
2199 if (target_bits
& 4)
2200 host_bits
|= float_flag_overflow
;
2201 if (target_bits
& 8)
2202 host_bits
|= float_flag_underflow
;
2203 if (target_bits
& 0x10)
2204 host_bits
|= float_flag_inexact
;
2208 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2213 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2214 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2215 env
->vfp
.vec_len
= (val
>> 16) & 7;
2216 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2219 if (changed
& (3 << 22)) {
2220 i
= (val
>> 22) & 3;
2223 i
= float_round_nearest_even
;
2229 i
= float_round_down
;
2232 i
= float_round_to_zero
;
2235 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2238 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2239 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2240 /* XXX: FZ and DN are not implemented. */
2243 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2245 #define VFP_BINOP(name) \
2246 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2248 return float32_ ## name (a, b, &env->vfp.fp_status); \
2250 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2252 return float64_ ## name (a, b, &env->vfp.fp_status); \
2260 float32
VFP_HELPER(neg
, s
)(float32 a
)
2262 return float32_chs(a
);
2265 float64
VFP_HELPER(neg
, d
)(float64 a
)
2267 return float32_chs(a
);
2270 float32
VFP_HELPER(abs
, s
)(float32 a
)
2272 return float32_abs(a
);
2275 float64
VFP_HELPER(abs
, d
)(float64 a
)
2277 return float32_abs(a
);
2280 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2282 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2285 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2287 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2290 /* XXX: check quiet/signaling case */
2291 #define DO_VFP_cmp(p, type) \
2292 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2295 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2296 case 0: flags = 0x6; break; \
2297 case -1: flags = 0x8; break; \
2298 case 1: flags = 0x2; break; \
2299 default: case 2: flags = 0x3; break; \
2301 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2302 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2304 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2307 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2308 case 0: flags = 0x6; break; \
2309 case -1: flags = 0x8; break; \
2310 case 1: flags = 0x2; break; \
2311 default: case 2: flags = 0x3; break; \
2313 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2314 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2316 DO_VFP_cmp(s
, float32
)
2317 DO_VFP_cmp(d
, float64
)
2320 /* Helper routines to perform bitwise copies between float and int. */
2321 static inline float32
vfp_itos(uint32_t i
)
2332 static inline uint32_t vfp_stoi(float32 s
)
2343 static inline float64
vfp_itod(uint64_t i
)
2354 static inline uint64_t vfp_dtoi(float64 d
)
2365 /* Integer to float conversion. */
2366 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2368 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2371 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2373 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2376 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2378 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2381 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2383 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2386 /* Float to integer conversion. */
2387 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2389 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2392 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2394 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2397 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2399 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2402 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2404 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2407 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2409 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2412 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2414 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2417 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2419 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2422 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2424 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2427 /* floating point conversion */
2428 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2430 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2433 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2435 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2438 /* VFP3 fixed point conversion. */
2439 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2440 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2443 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2444 &env->vfp.fp_status); \
2445 return ftype##_scalbn(tmp, shift, &env->vfp.fp_status); \
2447 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2450 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2451 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2452 &env->vfp.fp_status)); \
2455 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2456 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2457 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2458 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2459 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2460 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2461 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2462 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2465 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2467 float_status
*s
= &env
->vfp
.fp_status
;
2468 float32 two
= int32_to_float32(2, s
);
2469 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2472 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2474 float_status
*s
= &env
->vfp
.fp_status
;
2475 float32 three
= int32_to_float32(3, s
);
2476 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2481 /* TODO: The architecture specifies the value that the estimate functions
2482 should return. We return the exact reciprocal/root instead. */
2483 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2485 float_status
*s
= &env
->vfp
.fp_status
;
2486 float32 one
= int32_to_float32(1, s
);
2487 return float32_div(one
, a
, s
);
2490 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2492 float_status
*s
= &env
->vfp
.fp_status
;
2493 float32 one
= int32_to_float32(1, s
);
2494 return float32_div(one
, float32_sqrt(a
, s
), s
);
2497 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2499 float_status
*s
= &env
->vfp
.fp_status
;
2501 tmp
= int32_to_float32(a
, s
);
2502 tmp
= float32_scalbn(tmp
, -32, s
);
2503 tmp
= helper_recpe_f32(tmp
, env
);
2504 tmp
= float32_scalbn(tmp
, 31, s
);
2505 return float32_to_int32(tmp
, s
);
2508 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2510 float_status
*s
= &env
->vfp
.fp_status
;
2512 tmp
= int32_to_float32(a
, s
);
2513 tmp
= float32_scalbn(tmp
, -32, s
);
2514 tmp
= helper_rsqrte_f32(tmp
, env
);
2515 tmp
= float32_scalbn(tmp
, 31, s
);
2516 return float32_to_int32(tmp
, s
);