4 #include "host-utils.h"
7 #ifndef CONFIG_USER_ONLY
8 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
9 int access_type
, int is_user
,
10 uint32_t *phys_ptr
, int *prot
,
11 target_ulong
*page_size
);
14 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
18 /* VFP data registers are always little-endian. */
19 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
21 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
24 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
25 /* Aliases for Q regs. */
28 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
29 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
33 switch (reg
- nregs
) {
34 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
35 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
36 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
41 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
53 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
54 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
58 switch (reg
- nregs
) {
59 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
60 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
61 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
66 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
69 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
73 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
75 if (env
->cp15
.c13_fcse
!= value
) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
80 env
->cp15
.c13_fcse
= value
;
84 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
94 env
->cp15
.c13_context
= value
;
98 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Invalidate all (TLBIALL) */
106 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
114 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env
, value
== 0);
122 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
130 static const ARMCPRegInfo cp_reginfo
[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
135 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
136 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
137 /* MMU Domain access control / MPU write buffer control */
138 { .name
= "DACR", .cp
= 15,
139 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
140 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
141 .resetvalue
= 0, .writefn
= dacr_write
},
142 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
143 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
144 .resetvalue
= 0, .writefn
= fcse_write
},
145 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
147 .resetvalue
= 0, .writefn
= contextidr_write
},
148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
152 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
157 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
158 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
159 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
160 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
161 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
162 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
163 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
166 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
167 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
171 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
175 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
176 .access
= PL1_W
, .type
= ARM_CP_WFI
},
180 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
185 .access
= PL1_W
, .type
= ARM_CP_WFI
},
189 static const ARMCPRegInfo v6_cp_reginfo
[] = {
190 /* prefetch by MVA in v6, NOP in v7 */
191 { .name
= "MVA_prefetch",
192 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
193 .access
= PL1_W
, .type
= ARM_CP_NOP
},
194 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
195 .access
= PL0_W
, .type
= ARM_CP_NOP
},
196 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
197 .access
= PL0_W
, .type
= ARM_CP_NOP
},
198 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
199 .access
= PL0_W
, .type
= ARM_CP_NOP
},
200 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
201 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
203 /* Watchpoint Fault Address Register : should actually only be present
204 * for 1136, 1176, 11MPCore.
206 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
207 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
211 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
214 /* Generic performance monitor register read function for where
215 * user access may be allowed by PMUSERENR.
217 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
220 *value
= CPREG_FIELD32(env
, ri
);
224 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
227 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
230 /* only the DP, X, D and E bits are writable */
231 env
->cp15
.c9_pmcr
&= ~0x39;
232 env
->cp15
.c9_pmcr
|= (value
& 0x39);
236 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
239 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
243 env
->cp15
.c9_pmcnten
|= value
;
247 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
250 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
254 env
->cp15
.c9_pmcnten
&= ~value
;
258 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
261 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
264 env
->cp15
.c9_pmovsr
&= ~value
;
268 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
271 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
274 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
278 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
281 env
->cp15
.c9_pmuserenr
= value
& 1;
285 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
288 /* We have no event counters so only the C bit can be changed */
290 env
->cp15
.c9_pminten
|= value
;
294 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
298 env
->cp15
.c9_pminten
&= ~value
;
302 static const ARMCPRegInfo v7_cp_reginfo
[] = {
303 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
306 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
307 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
308 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
309 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
310 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
311 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
312 .access
= PL1_W
, .type
= ARM_CP_NOP
},
313 /* Performance monitors are implementation defined in v7,
314 * but with an ARM recommended set of registers, which we
315 * follow (although we don't actually implement any counters)
317 * Performance registers fall into three categories:
318 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
319 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
320 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
321 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
322 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
324 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
325 .access
= PL0_RW
, .resetvalue
= 0,
326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
327 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
328 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
329 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
330 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
331 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
332 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
333 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
334 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
337 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
338 .access
= PL0_W
, .type
= ARM_CP_NOP
},
339 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
340 * We choose to RAZ/WI. XXX should respect PMUSERENR.
342 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
343 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
344 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
345 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
346 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
347 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
349 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
350 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
351 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
352 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
353 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
354 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
355 .access
= PL0_R
| PL1_RW
,
356 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
358 .writefn
= pmuserenr_write
},
359 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
361 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
363 .writefn
= pmintenset_write
},
364 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
366 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
368 .writefn
= pmintenclr_write
},
372 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
379 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
382 /* This is a helper function because the user access rights
383 * depend on the value of the TEECR.
385 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
388 *value
= env
->teehbr
;
392 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
395 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
402 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
403 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
404 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
406 .writefn
= teecr_write
},
407 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
408 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
410 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
414 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
415 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
417 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
419 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
420 .access
= PL0_R
|PL1_W
,
421 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
423 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
425 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
430 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
431 /* Dummy implementation: RAZ/WI the whole crn=14 space */
432 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
433 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
434 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
438 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
440 if (arm_feature(env
, ARM_FEATURE_V7
)) {
441 env
->cp15
.c7_par
= value
& 0xfffff6ff;
443 env
->cp15
.c7_par
= value
& 0xfffff1ff;
448 #ifndef CONFIG_USER_ONLY
449 /* get_phys_addr() isn't present for user-mode-only targets */
450 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
453 target_ulong page_size
;
455 int ret
, is_user
= ri
->opc2
& 2;
456 int access_type
= ri
->opc2
& 1;
459 /* Other states are only available with TrustZone */
462 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
463 &phys_addr
, &prot
, &page_size
);
465 /* We do not set any attribute bits in the PAR */
466 if (page_size
== (1 << 24)
467 && arm_feature(env
, ARM_FEATURE_V7
)) {
468 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
470 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
473 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
474 ((ret
& (12 << 1)) >> 6) |
475 ((ret
& 0xf) << 1) | 1;
481 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
482 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
483 .access
= PL1_RW
, .resetvalue
= 0,
484 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
485 .writefn
= par_write
},
486 #ifndef CONFIG_USER_ONLY
487 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
488 .access
= PL1_W
, .writefn
= ats_write
},
493 /* Return basic MPU access permission bits. */
494 static uint32_t simple_mpu_ap_bits(uint32_t val
)
501 for (i
= 0; i
< 16; i
+= 2) {
502 ret
|= (val
>> i
) & mask
;
508 /* Pad basic MPU access permission bits to extended format. */
509 static uint32_t extended_mpu_ap_bits(uint32_t val
)
516 for (i
= 0; i
< 16; i
+= 2) {
517 ret
|= (val
& mask
) << i
;
523 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
526 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
530 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
533 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
537 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
540 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
544 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
547 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
551 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
557 *value
= env
->cp15
.c6_region
[ri
->crm
];
561 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 env
->cp15
.c6_region
[ri
->crm
] = value
;
571 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
572 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
574 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
575 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
576 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
578 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
579 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
580 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
582 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
583 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
585 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
586 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
588 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
589 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
591 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
592 /* Protection region base and size registers */
593 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
594 .opc2
= CP_ANY
, .access
= PL1_RW
,
595 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
599 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 env
->cp15
.c2_control
= value
;
604 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
605 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
609 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
611 env
->cp15
.c2_base_mask
= 0xffffc000u
;
612 env
->cp15
.c2_control
= 0;
613 env
->cp15
.c2_mask
= 0;
616 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
617 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
619 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
620 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
622 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
623 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
625 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
626 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
628 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
629 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
630 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
631 .resetfn
= vmsa_ttbcr_reset
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
633 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
634 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
639 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
642 env
->cp15
.c15_ticonfig
= value
& 0xe7;
643 /* The OS_TYPE bit in this register changes the reported CPUID! */
644 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
645 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
649 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
652 env
->cp15
.c15_threadid
= value
& 0xffff;
656 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
659 /* Wait-for-interrupt (deprecated) */
660 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
664 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
667 /* On OMAP there are registers indicating the max/min index of dcache lines
668 * containing a dirty line; cache flush operations have to reset these.
670 env
->cp15
.c15_i_max
= 0x000;
671 env
->cp15
.c15_i_min
= 0xff0;
675 static const ARMCPRegInfo omap_cp_reginfo
[] = {
676 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
677 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
678 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
679 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
680 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
681 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
683 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
684 .writefn
= omap_ticonfig_write
},
685 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
687 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
688 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
689 .access
= PL1_RW
, .resetvalue
= 0xff0,
690 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
691 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
693 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
694 .writefn
= omap_threadid_write
},
695 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
696 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
697 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
698 /* TODO: Peripheral port remap register:
699 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
700 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
703 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
704 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
705 .writefn
= omap_cachemaint_write
},
709 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
713 if (env
->cp15
.c15_cpar
!= value
) {
714 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
716 env
->cp15
.c15_cpar
= value
;
721 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
722 { .name
= "XSCALE_CPAR",
723 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
724 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
725 .writefn
= xscale_cpar_write
, },
729 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
730 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
731 * implementation of this implementation-defined space.
732 * Ideally this should eventually disappear in favour of actually
733 * implementing the correct behaviour for all cores.
735 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
736 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
737 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
741 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
742 /* Cache status: RAZ because we have no cache so it's always clean */
743 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
744 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
748 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
749 /* We never have a a block transfer operation in progress */
750 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
751 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
755 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
756 /* The cache test-and-clean instructions always return (1 << 30)
757 * to indicate that there are no dirty cache lines.
759 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
760 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
761 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
762 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
766 void register_cp_regs_for_features(ARMCPU
*cpu
)
768 /* Register all the coprocessor registers based on feature bits */
769 CPUARMState
*env
= &cpu
->env
;
770 if (arm_feature(env
, ARM_FEATURE_M
)) {
771 /* M profile has no coprocessor registers */
775 define_arm_cp_regs(cpu
, cp_reginfo
);
776 if (arm_feature(env
, ARM_FEATURE_V6
)) {
777 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
779 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
781 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
782 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
784 if (arm_feature(env
, ARM_FEATURE_V7
)) {
785 /* v7 performance monitor control register: same implementor
786 * field as main ID register, and we implement no event counters.
788 ARMCPRegInfo pmcr
= {
789 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
790 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
791 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
792 .readfn
= pmreg_read
, .writefn
= pmcr_write
794 define_one_arm_cp_reg(cpu
, &pmcr
);
795 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
797 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
799 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
800 /* These are the MPU registers prior to PMSAv6. Any new
801 * PMSA core later than the ARM946 will require that we
802 * implement the PMSAv6 or PMSAv7 registers, which are
803 * completely different.
805 assert(!arm_feature(env
, ARM_FEATURE_V6
));
806 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
808 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
810 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
811 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
813 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
814 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
816 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
817 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
819 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
820 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
822 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
823 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
825 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
826 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
828 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
829 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
831 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
832 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
834 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
835 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
839 ARMCPU
*cpu_arm_init(const char *cpu_model
)
843 static int inited
= 0;
845 if (!object_class_by_name(cpu_model
)) {
848 cpu
= ARM_CPU(object_new(cpu_model
));
850 env
->cpu_model_str
= cpu_model
;
851 arm_cpu_realize(cpu
);
853 if (tcg_enabled() && !inited
) {
855 arm_translate_init();
859 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
860 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
861 51, "arm-neon.xml", 0);
862 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
863 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
864 35, "arm-vfp3.xml", 0);
865 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
866 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
867 19, "arm-vfp.xml", 0);
873 typedef struct ARMCPUListState
{
874 fprintf_function cpu_fprintf
;
878 /* Sort alphabetically by type name, except for "any". */
879 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
881 ObjectClass
*class_a
= (ObjectClass
*)a
;
882 ObjectClass
*class_b
= (ObjectClass
*)b
;
883 const char *name_a
, *name_b
;
885 name_a
= object_class_get_name(class_a
);
886 name_b
= object_class_get_name(class_b
);
887 if (strcmp(name_a
, "any") == 0) {
889 } else if (strcmp(name_b
, "any") == 0) {
892 return strcmp(name_a
, name_b
);
896 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
898 ObjectClass
*oc
= data
;
899 ARMCPUListState
*s
= user_data
;
901 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
902 object_class_get_name(oc
));
905 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
907 ARMCPUListState s
= {
909 .cpu_fprintf
= cpu_fprintf
,
913 list
= object_class_get_list(TYPE_ARM_CPU
, false);
914 list
= g_slist_sort(list
, arm_cpu_list_compare
);
915 (*cpu_fprintf
)(f
, "Available CPUs:\n");
916 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
920 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
921 const ARMCPRegInfo
*r
, void *opaque
)
923 /* Define implementations of coprocessor registers.
924 * We store these in a hashtable because typically
925 * there are less than 150 registers in a space which
926 * is 16*16*16*8*8 = 262144 in size.
927 * Wildcarding is supported for the crm, opc1 and opc2 fields.
928 * If a register is defined twice then the second definition is
929 * used, so this can be used to define some generic registers and
930 * then override them with implementation specific variations.
931 * At least one of the original and the second definition should
932 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
933 * against accidental use.
936 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
937 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
938 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
939 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
940 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
941 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
942 /* 64 bit registers have only CRm and Opc1 fields */
943 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
944 /* Check that the register definition has enough info to handle
945 * reads and writes if they are permitted.
947 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
948 if (r
->access
& PL3_R
) {
949 assert(r
->fieldoffset
|| r
->readfn
);
951 if (r
->access
& PL3_W
) {
952 assert(r
->fieldoffset
|| r
->writefn
);
955 /* Bad type field probably means missing sentinel at end of reg list */
956 assert(cptype_valid(r
->type
));
957 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
958 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
959 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
960 uint32_t *key
= g_new(uint32_t, 1);
961 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
962 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
963 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
965 /* Make sure reginfo passed to helpers for wildcarded regs
966 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
971 /* Overriding of an existing definition must be explicitly
974 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
975 ARMCPRegInfo
*oldreg
;
976 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
977 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
978 fprintf(stderr
, "Register redefined: cp=%d %d bit "
979 "crn=%d crm=%d opc1=%d opc2=%d, "
980 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
981 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
982 oldreg
->name
, r2
->name
);
986 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
992 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
993 const ARMCPRegInfo
*regs
, void *opaque
)
995 /* Define a whole list of registers */
996 const ARMCPRegInfo
*r
;
997 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
998 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1002 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1004 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1007 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1010 /* Helper coprocessor write function for write-ignore registers */
1014 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1016 /* Helper coprocessor write function for read-as-zero registers */
1021 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1023 /* Return true if it is not valid for us to switch to
1024 * this CPU mode (ie all the UNPREDICTABLE cases in
1025 * the ARM ARM CPSRWriteByInstr pseudocode).
1028 case ARM_CPU_MODE_USR
:
1029 case ARM_CPU_MODE_SYS
:
1030 case ARM_CPU_MODE_SVC
:
1031 case ARM_CPU_MODE_ABT
:
1032 case ARM_CPU_MODE_UND
:
1033 case ARM_CPU_MODE_IRQ
:
1034 case ARM_CPU_MODE_FIQ
:
1041 uint32_t cpsr_read(CPUARMState
*env
)
1044 ZF
= (env
->ZF
== 0);
1045 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1046 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1047 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1048 | ((env
->condexec_bits
& 0xfc) << 8)
1052 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1054 if (mask
& CPSR_NZCV
) {
1055 env
->ZF
= (~val
) & CPSR_Z
;
1057 env
->CF
= (val
>> 29) & 1;
1058 env
->VF
= (val
<< 3) & 0x80000000;
1061 env
->QF
= ((val
& CPSR_Q
) != 0);
1063 env
->thumb
= ((val
& CPSR_T
) != 0);
1064 if (mask
& CPSR_IT_0_1
) {
1065 env
->condexec_bits
&= ~3;
1066 env
->condexec_bits
|= (val
>> 25) & 3;
1068 if (mask
& CPSR_IT_2_7
) {
1069 env
->condexec_bits
&= 3;
1070 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1072 if (mask
& CPSR_GE
) {
1073 env
->GE
= (val
>> 16) & 0xf;
1076 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1077 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1078 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1079 * We choose to ignore the attempt and leave the CPSR M field
1084 switch_mode(env
, val
& CPSR_M
);
1087 mask
&= ~CACHED_CPSR_BITS
;
1088 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1091 /* Sign/zero extend */
1092 uint32_t HELPER(sxtb16
)(uint32_t x
)
1095 res
= (uint16_t)(int8_t)x
;
1096 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1100 uint32_t HELPER(uxtb16
)(uint32_t x
)
1103 res
= (uint16_t)(uint8_t)x
;
1104 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1108 uint32_t HELPER(clz
)(uint32_t x
)
1113 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1117 if (num
== INT_MIN
&& den
== -1)
1122 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1129 uint32_t HELPER(rbit
)(uint32_t x
)
1131 x
= ((x
& 0xff000000) >> 24)
1132 | ((x
& 0x00ff0000) >> 8)
1133 | ((x
& 0x0000ff00) << 8)
1134 | ((x
& 0x000000ff) << 24);
1135 x
= ((x
& 0xf0f0f0f0) >> 4)
1136 | ((x
& 0x0f0f0f0f) << 4);
1137 x
= ((x
& 0x88888888) >> 3)
1138 | ((x
& 0x44444444) >> 1)
1139 | ((x
& 0x22222222) << 1)
1140 | ((x
& 0x11111111) << 3);
1144 uint32_t HELPER(abs
)(uint32_t x
)
1146 return ((int32_t)x
< 0) ? -x
: x
;
1149 #if defined(CONFIG_USER_ONLY)
1151 void do_interrupt (CPUARMState
*env
)
1153 env
->exception_index
= -1;
1156 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1160 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1161 env
->cp15
.c6_insn
= address
;
1163 env
->exception_index
= EXCP_DATA_ABORT
;
1164 env
->cp15
.c6_data
= address
;
1169 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1171 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1174 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1176 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1179 /* These should probably raise undefined insn exceptions. */
1180 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1182 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1185 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1187 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1191 void switch_mode(CPUARMState
*env
, int mode
)
1193 if (mode
!= ARM_CPU_MODE_USR
)
1194 cpu_abort(env
, "Tried to switch out of user mode\n");
1197 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1199 cpu_abort(env
, "banked r13 write\n");
1202 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1204 cpu_abort(env
, "banked r13 read\n");
1210 /* Map CPU modes onto saved register banks. */
1211 static inline int bank_number(CPUARMState
*env
, int mode
)
1214 case ARM_CPU_MODE_USR
:
1215 case ARM_CPU_MODE_SYS
:
1217 case ARM_CPU_MODE_SVC
:
1219 case ARM_CPU_MODE_ABT
:
1221 case ARM_CPU_MODE_UND
:
1223 case ARM_CPU_MODE_IRQ
:
1225 case ARM_CPU_MODE_FIQ
:
1228 cpu_abort(env
, "Bad mode %x\n", mode
);
1232 void switch_mode(CPUARMState
*env
, int mode
)
1237 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1238 if (mode
== old_mode
)
1241 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1242 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1243 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1244 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1245 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1246 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1249 i
= bank_number(env
, old_mode
);
1250 env
->banked_r13
[i
] = env
->regs
[13];
1251 env
->banked_r14
[i
] = env
->regs
[14];
1252 env
->banked_spsr
[i
] = env
->spsr
;
1254 i
= bank_number(env
, mode
);
1255 env
->regs
[13] = env
->banked_r13
[i
];
1256 env
->regs
[14] = env
->banked_r14
[i
];
1257 env
->spsr
= env
->banked_spsr
[i
];
1260 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1263 stl_phys(env
->regs
[13], val
);
1266 static uint32_t v7m_pop(CPUARMState
*env
)
1269 val
= ldl_phys(env
->regs
[13]);
1274 /* Switch to V7M main or process stack pointer. */
1275 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1278 if (env
->v7m
.current_sp
!= process
) {
1279 tmp
= env
->v7m
.other_sp
;
1280 env
->v7m
.other_sp
= env
->regs
[13];
1281 env
->regs
[13] = tmp
;
1282 env
->v7m
.current_sp
= process
;
1286 static void do_v7m_exception_exit(CPUARMState
*env
)
1291 type
= env
->regs
[15];
1292 if (env
->v7m
.exception
!= 0)
1293 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1295 /* Switch to the target stack. */
1296 switch_v7m_sp(env
, (type
& 4) != 0);
1297 /* Pop registers. */
1298 env
->regs
[0] = v7m_pop(env
);
1299 env
->regs
[1] = v7m_pop(env
);
1300 env
->regs
[2] = v7m_pop(env
);
1301 env
->regs
[3] = v7m_pop(env
);
1302 env
->regs
[12] = v7m_pop(env
);
1303 env
->regs
[14] = v7m_pop(env
);
1304 env
->regs
[15] = v7m_pop(env
);
1305 xpsr
= v7m_pop(env
);
1306 xpsr_write(env
, xpsr
, 0xfffffdff);
1307 /* Undo stack alignment. */
1310 /* ??? The exception return type specifies Thread/Handler mode. However
1311 this is also implied by the xPSR value. Not sure what to do
1312 if there is a mismatch. */
1313 /* ??? Likewise for mismatches between the CONTROL register and the stack
1317 static void do_interrupt_v7m(CPUARMState
*env
)
1319 uint32_t xpsr
= xpsr_read(env
);
1324 if (env
->v7m
.current_sp
)
1326 if (env
->v7m
.exception
== 0)
1329 /* For exceptions we just mark as pending on the NVIC, and let that
1331 /* TODO: Need to escalate if the current priority is higher than the
1332 one we're raising. */
1333 switch (env
->exception_index
) {
1335 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1339 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1341 case EXCP_PREFETCH_ABORT
:
1342 case EXCP_DATA_ABORT
:
1343 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1346 if (semihosting_enabled
) {
1348 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1351 env
->regs
[0] = do_arm_semihosting(env
);
1355 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1358 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1360 case EXCP_EXCEPTION_EXIT
:
1361 do_v7m_exception_exit(env
);
1364 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1365 return; /* Never happens. Keep compiler happy. */
1368 /* Align stack pointer. */
1369 /* ??? Should only do this if Configuration Control Register
1370 STACKALIGN bit is set. */
1371 if (env
->regs
[13] & 4) {
1375 /* Switch to the handler mode. */
1376 v7m_push(env
, xpsr
);
1377 v7m_push(env
, env
->regs
[15]);
1378 v7m_push(env
, env
->regs
[14]);
1379 v7m_push(env
, env
->regs
[12]);
1380 v7m_push(env
, env
->regs
[3]);
1381 v7m_push(env
, env
->regs
[2]);
1382 v7m_push(env
, env
->regs
[1]);
1383 v7m_push(env
, env
->regs
[0]);
1384 switch_v7m_sp(env
, 0);
1386 env
->condexec_bits
= 0;
1388 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1389 env
->regs
[15] = addr
& 0xfffffffe;
1390 env
->thumb
= addr
& 1;
1393 /* Handle a CPU exception. */
1394 void do_interrupt(CPUARMState
*env
)
1402 do_interrupt_v7m(env
);
1405 /* TODO: Vectored interrupt controller. */
1406 switch (env
->exception_index
) {
1408 new_mode
= ARM_CPU_MODE_UND
;
1417 if (semihosting_enabled
) {
1418 /* Check for semihosting interrupt. */
1420 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1422 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1425 /* Only intercept calls from privileged modes, to provide some
1426 semblance of security. */
1427 if (((mask
== 0x123456 && !env
->thumb
)
1428 || (mask
== 0xab && env
->thumb
))
1429 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1430 env
->regs
[0] = do_arm_semihosting(env
);
1434 new_mode
= ARM_CPU_MODE_SVC
;
1437 /* The PC already points to the next instruction. */
1441 /* See if this is a semihosting syscall. */
1442 if (env
->thumb
&& semihosting_enabled
) {
1443 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1445 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1447 env
->regs
[0] = do_arm_semihosting(env
);
1451 env
->cp15
.c5_insn
= 2;
1452 /* Fall through to prefetch abort. */
1453 case EXCP_PREFETCH_ABORT
:
1454 new_mode
= ARM_CPU_MODE_ABT
;
1456 mask
= CPSR_A
| CPSR_I
;
1459 case EXCP_DATA_ABORT
:
1460 new_mode
= ARM_CPU_MODE_ABT
;
1462 mask
= CPSR_A
| CPSR_I
;
1466 new_mode
= ARM_CPU_MODE_IRQ
;
1468 /* Disable IRQ and imprecise data aborts. */
1469 mask
= CPSR_A
| CPSR_I
;
1473 new_mode
= ARM_CPU_MODE_FIQ
;
1475 /* Disable FIQ, IRQ and imprecise data aborts. */
1476 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1480 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1481 return; /* Never happens. Keep compiler happy. */
1484 if (env
->cp15
.c1_sys
& (1 << 13)) {
1487 switch_mode (env
, new_mode
);
1488 env
->spsr
= cpsr_read(env
);
1489 /* Clear IT bits. */
1490 env
->condexec_bits
= 0;
1491 /* Switch to the new mode, and to the correct instruction set. */
1492 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1493 env
->uncached_cpsr
|= mask
;
1494 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1495 * and we should just guard the thumb mode on V4 */
1496 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1497 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1499 env
->regs
[14] = env
->regs
[15] + offset
;
1500 env
->regs
[15] = addr
;
1501 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1504 /* Check section/page access permissions.
1505 Returns the page protection flags, or zero if the access is not
1507 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1508 int access_type
, int is_user
)
1512 if (domain_prot
== 3) {
1513 return PAGE_READ
| PAGE_WRITE
;
1516 if (access_type
== 1)
1519 prot_ro
= PAGE_READ
;
1523 if (access_type
== 1)
1525 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1527 return is_user
? 0 : PAGE_READ
;
1534 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1539 return PAGE_READ
| PAGE_WRITE
;
1541 return PAGE_READ
| PAGE_WRITE
;
1542 case 4: /* Reserved. */
1545 return is_user
? 0 : prot_ro
;
1549 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1557 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1561 if (address
& env
->cp15
.c2_mask
)
1562 table
= env
->cp15
.c2_base1
& 0xffffc000;
1564 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1566 table
|= (address
>> 18) & 0x3ffc;
1570 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1571 int is_user
, uint32_t *phys_ptr
, int *prot
,
1572 target_ulong
*page_size
)
1583 /* Pagetable walk. */
1584 /* Lookup l1 descriptor. */
1585 table
= get_level1_table_address(env
, address
);
1586 desc
= ldl_phys(table
);
1588 domain
= (desc
>> 5) & 0x0f;
1589 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1591 /* Section translation fault. */
1595 if (domain_prot
== 0 || domain_prot
== 2) {
1597 code
= 9; /* Section domain fault. */
1599 code
= 11; /* Page domain fault. */
1604 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1605 ap
= (desc
>> 10) & 3;
1607 *page_size
= 1024 * 1024;
1609 /* Lookup l2 entry. */
1611 /* Coarse pagetable. */
1612 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1614 /* Fine pagetable. */
1615 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1617 desc
= ldl_phys(table
);
1619 case 0: /* Page translation fault. */
1622 case 1: /* 64k page. */
1623 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1624 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1625 *page_size
= 0x10000;
1627 case 2: /* 4k page. */
1628 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1629 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1630 *page_size
= 0x1000;
1632 case 3: /* 1k page. */
1634 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1635 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1637 /* Page translation fault. */
1642 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1644 ap
= (desc
>> 4) & 3;
1648 /* Never happens, but compiler isn't smart enough to tell. */
1653 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1655 /* Access permission fault. */
1659 *phys_ptr
= phys_addr
;
1662 return code
| (domain
<< 4);
1665 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1666 int is_user
, uint32_t *phys_ptr
, int *prot
,
1667 target_ulong
*page_size
)
1679 /* Pagetable walk. */
1680 /* Lookup l1 descriptor. */
1681 table
= get_level1_table_address(env
, address
);
1682 desc
= ldl_phys(table
);
1685 /* Section translation fault. */
1689 } else if (type
== 2 && (desc
& (1 << 18))) {
1693 /* Section or page. */
1694 domain
= (desc
>> 5) & 0x0f;
1696 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1697 if (domain_prot
== 0 || domain_prot
== 2) {
1699 code
= 9; /* Section domain fault. */
1701 code
= 11; /* Page domain fault. */
1705 if (desc
& (1 << 18)) {
1707 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1708 *page_size
= 0x1000000;
1711 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1712 *page_size
= 0x100000;
1714 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1715 xn
= desc
& (1 << 4);
1718 /* Lookup l2 entry. */
1719 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1720 desc
= ldl_phys(table
);
1721 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1723 case 0: /* Page translation fault. */
1726 case 1: /* 64k page. */
1727 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1728 xn
= desc
& (1 << 15);
1729 *page_size
= 0x10000;
1731 case 2: case 3: /* 4k page. */
1732 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1734 *page_size
= 0x1000;
1737 /* Never happens, but compiler isn't smart enough to tell. */
1742 if (domain_prot
== 3) {
1743 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1745 if (xn
&& access_type
== 2)
1748 /* The simplified model uses AP[0] as an access control bit. */
1749 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1750 /* Access flag fault. */
1751 code
= (code
== 15) ? 6 : 3;
1754 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1756 /* Access permission fault. */
1763 *phys_ptr
= phys_addr
;
1766 return code
| (domain
<< 4);
1769 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1770 int is_user
, uint32_t *phys_ptr
, int *prot
)
1776 *phys_ptr
= address
;
1777 for (n
= 7; n
>= 0; n
--) {
1778 base
= env
->cp15
.c6_region
[n
];
1779 if ((base
& 1) == 0)
1781 mask
= 1 << ((base
>> 1) & 0x1f);
1782 /* Keep this shift separate from the above to avoid an
1783 (undefined) << 32. */
1784 mask
= (mask
<< 1) - 1;
1785 if (((base
^ address
) & ~mask
) == 0)
1791 if (access_type
== 2) {
1792 mask
= env
->cp15
.c5_insn
;
1794 mask
= env
->cp15
.c5_data
;
1796 mask
= (mask
>> (n
* 4)) & 0xf;
1803 *prot
= PAGE_READ
| PAGE_WRITE
;
1808 *prot
|= PAGE_WRITE
;
1811 *prot
= PAGE_READ
| PAGE_WRITE
;
1822 /* Bad permission. */
1829 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1830 int access_type
, int is_user
,
1831 uint32_t *phys_ptr
, int *prot
,
1832 target_ulong
*page_size
)
1834 /* Fast Context Switch Extension. */
1835 if (address
< 0x02000000)
1836 address
+= env
->cp15
.c13_fcse
;
1838 if ((env
->cp15
.c1_sys
& 1) == 0) {
1839 /* MMU/MPU disabled. */
1840 *phys_ptr
= address
;
1841 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1842 *page_size
= TARGET_PAGE_SIZE
;
1844 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1845 *page_size
= TARGET_PAGE_SIZE
;
1846 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1848 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1849 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1852 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1857 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1858 int access_type
, int mmu_idx
)
1861 target_ulong page_size
;
1865 is_user
= mmu_idx
== MMU_USER_IDX
;
1866 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1869 /* Map a single [sub]page. */
1870 phys_addr
&= ~(uint32_t)0x3ff;
1871 address
&= ~(uint32_t)0x3ff;
1872 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1876 if (access_type
== 2) {
1877 env
->cp15
.c5_insn
= ret
;
1878 env
->cp15
.c6_insn
= address
;
1879 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1881 env
->cp15
.c5_data
= ret
;
1882 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1883 env
->cp15
.c5_data
|= (1 << 11);
1884 env
->cp15
.c6_data
= address
;
1885 env
->exception_index
= EXCP_DATA_ABORT
;
1890 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1893 target_ulong page_size
;
1897 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1905 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1911 op1
= (insn
>> 21) & 7;
1912 op2
= (insn
>> 5) & 7;
1914 switch ((insn
>> 16) & 0xf) {
1917 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1919 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1921 if (arm_feature(env
, ARM_FEATURE_V7
)
1922 && op1
== 2 && crm
== 0 && op2
== 0) {
1923 env
->cp15
.c0_cssel
= val
& 0xf;
1927 case 1: /* System configuration. */
1928 if (arm_feature(env
, ARM_FEATURE_V7
)
1929 && op1
== 0 && crm
== 1 && op2
== 0) {
1930 env
->cp15
.c1_scr
= val
;
1933 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1937 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1938 env
->cp15
.c1_sys
= val
;
1939 /* ??? Lots of these bits are not implemented. */
1940 /* This may enable/disable the MMU, so do a TLB flush. */
1943 case 1: /* Auxiliary control register. */
1944 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1945 env
->cp15
.c1_xscaleauxcr
= val
;
1948 /* Not implemented. */
1951 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1953 if (env
->cp15
.c1_coproc
!= val
) {
1954 env
->cp15
.c1_coproc
= val
;
1955 /* ??? Is this safe when called from within a TB? */
1963 case 4: /* Reserved. */
1966 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1968 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1969 break; /* Ignore ReadBuffer access */
1971 case 0: /* Cache lockdown. */
1973 case 0: /* L1 cache. */
1976 env
->cp15
.c9_data
= val
;
1979 env
->cp15
.c9_insn
= val
;
1985 case 1: /* L2 cache. */
1986 /* Ignore writes to L2 lockdown/auxiliary registers. */
1992 case 1: /* TCM memory region registers. */
1993 /* Not implemented. */
1999 case 12: /* Reserved. */
2004 /* ??? For debugging only. Should raise illegal instruction exception. */
2005 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
2006 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2009 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
2015 op1
= (insn
>> 21) & 7;
2016 op2
= (insn
>> 5) & 7;
2018 switch ((insn
>> 16) & 0xf) {
2019 case 0: /* ID codes. */
2025 case 0: /* Device ID. */
2026 return env
->cp15
.c0_cpuid
;
2027 case 1: /* Cache Type. */
2028 return env
->cp15
.c0_cachetype
;
2029 case 2: /* TCM status. */
2031 case 3: /* TLB type register. */
2032 return 0; /* No lockable TLB entries. */
2034 /* The MPIDR was standardised in v7; prior to
2035 * this it was implemented only in the 11MPCore.
2036 * For all other pre-v7 cores it does not exist.
2038 if (arm_feature(env
, ARM_FEATURE_V7
) ||
2039 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
2040 int mpidr
= env
->cpu_index
;
2041 /* We don't support setting cluster ID ([8..11])
2042 * so these bits always RAZ.
2044 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2046 /* Cores which are uniprocessor (non-coherent)
2047 * but still implement the MP extensions set
2048 * bit 30. (For instance, A9UP.) However we do
2049 * not currently model any of those cores.
2054 /* otherwise fall through to the unimplemented-reg case */
2059 if (!arm_feature(env
, ARM_FEATURE_V6
))
2061 return env
->cp15
.c0_c1
[op2
];
2063 if (!arm_feature(env
, ARM_FEATURE_V6
))
2065 return env
->cp15
.c0_c2
[op2
];
2066 case 3: case 4: case 5: case 6: case 7:
2072 /* These registers aren't documented on arm11 cores. However
2073 Linux looks at them anyway. */
2074 if (!arm_feature(env
, ARM_FEATURE_V6
))
2078 if (!arm_feature(env
, ARM_FEATURE_V7
))
2083 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
2085 return env
->cp15
.c0_clid
;
2091 if (op2
!= 0 || crm
!= 0)
2093 return env
->cp15
.c0_cssel
;
2097 case 1: /* System configuration. */
2098 if (arm_feature(env
, ARM_FEATURE_V7
)
2099 && op1
== 0 && crm
== 1 && op2
== 0) {
2100 return env
->cp15
.c1_scr
;
2102 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2105 case 0: /* Control register. */
2106 return env
->cp15
.c1_sys
;
2107 case 1: /* Auxiliary control register. */
2108 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2109 return env
->cp15
.c1_xscaleauxcr
;
2110 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
2112 switch (ARM_CPUID(env
)) {
2113 case ARM_CPUID_ARM1026
:
2115 case ARM_CPUID_ARM1136
:
2116 case ARM_CPUID_ARM1136_R2
:
2117 case ARM_CPUID_ARM1176
:
2119 case ARM_CPUID_ARM11MPCORE
:
2121 case ARM_CPUID_CORTEXA8
:
2123 case ARM_CPUID_CORTEXA9
:
2124 case ARM_CPUID_CORTEXA15
:
2129 case 2: /* Coprocessor access register. */
2130 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2132 return env
->cp15
.c1_coproc
;
2136 case 4: /* Reserved. */
2140 case 0: /* Cache lockdown */
2142 case 0: /* L1 cache. */
2143 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2148 return env
->cp15
.c9_data
;
2150 return env
->cp15
.c9_insn
;
2154 case 1: /* L2 cache */
2155 /* L2 Lockdown and Auxiliary control. */
2158 /* L2 cache lockdown (A8 only) */
2161 /* L2 cache auxiliary control (A8) or control (A15) */
2162 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
2163 /* Linux wants the number of processors from here.
2164 * Might as well set the interrupt-controller bit too.
2166 return ((smp_cpus
- 1) << 24) | (1 << 23);
2170 /* L2 cache extended control (A15) */
2183 case 11: /* TCM DMA control. */
2184 case 12: /* Reserved. */
2188 /* ??? For debugging only. Should raise illegal instruction exception. */
2189 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2190 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2194 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2196 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2197 env
->regs
[13] = val
;
2199 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2203 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2205 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2206 return env
->regs
[13];
2208 return env
->banked_r13
[bank_number(env
, mode
)];
2212 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2216 return xpsr_read(env
) & 0xf8000000;
2218 return xpsr_read(env
) & 0xf80001ff;
2220 return xpsr_read(env
) & 0xff00fc00;
2222 return xpsr_read(env
) & 0xff00fdff;
2224 return xpsr_read(env
) & 0x000001ff;
2226 return xpsr_read(env
) & 0x0700fc00;
2228 return xpsr_read(env
) & 0x0700edff;
2230 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2232 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2233 case 16: /* PRIMASK */
2234 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2235 case 17: /* BASEPRI */
2236 case 18: /* BASEPRI_MAX */
2237 return env
->v7m
.basepri
;
2238 case 19: /* FAULTMASK */
2239 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2240 case 20: /* CONTROL */
2241 return env
->v7m
.control
;
2243 /* ??? For debugging only. */
2244 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2249 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2253 xpsr_write(env
, val
, 0xf8000000);
2256 xpsr_write(env
, val
, 0xf8000000);
2259 xpsr_write(env
, val
, 0xfe00fc00);
2262 xpsr_write(env
, val
, 0xfe00fc00);
2265 /* IPSR bits are readonly. */
2268 xpsr_write(env
, val
, 0x0600fc00);
2271 xpsr_write(env
, val
, 0x0600fc00);
2274 if (env
->v7m
.current_sp
)
2275 env
->v7m
.other_sp
= val
;
2277 env
->regs
[13] = val
;
2280 if (env
->v7m
.current_sp
)
2281 env
->regs
[13] = val
;
2283 env
->v7m
.other_sp
= val
;
2285 case 16: /* PRIMASK */
2287 env
->uncached_cpsr
|= CPSR_I
;
2289 env
->uncached_cpsr
&= ~CPSR_I
;
2291 case 17: /* BASEPRI */
2292 env
->v7m
.basepri
= val
& 0xff;
2294 case 18: /* BASEPRI_MAX */
2296 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2297 env
->v7m
.basepri
= val
;
2299 case 19: /* FAULTMASK */
2301 env
->uncached_cpsr
|= CPSR_F
;
2303 env
->uncached_cpsr
&= ~CPSR_F
;
2305 case 20: /* CONTROL */
2306 env
->v7m
.control
= val
& 3;
2307 switch_v7m_sp(env
, (val
& 2) != 0);
2310 /* ??? For debugging only. */
2311 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2318 /* Note that signed overflow is undefined in C. The following routines are
2319 careful to use unsigned types where modulo arithmetic is required.
2320 Failure to do so _will_ break on newer gcc. */
2322 /* Signed saturating arithmetic. */
2324 /* Perform 16-bit signed saturating addition. */
2325 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2330 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2339 /* Perform 8-bit signed saturating addition. */
2340 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2345 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2354 /* Perform 16-bit signed saturating subtraction. */
2355 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2360 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2369 /* Perform 8-bit signed saturating subtraction. */
2370 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2375 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2384 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2385 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2386 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2387 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2390 #include "op_addsub.h"
2392 /* Unsigned saturating arithmetic. */
2393 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2402 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2410 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2419 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2427 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2428 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2429 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2430 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2433 #include "op_addsub.h"
2435 /* Signed modulo arithmetic. */
2436 #define SARITH16(a, b, n, op) do { \
2438 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2439 RESULT(sum, n, 16); \
2441 ge |= 3 << (n * 2); \
2444 #define SARITH8(a, b, n, op) do { \
2446 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2447 RESULT(sum, n, 8); \
2453 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2454 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2455 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2456 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2460 #include "op_addsub.h"
2462 /* Unsigned modulo arithmetic. */
2463 #define ADD16(a, b, n) do { \
2465 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2466 RESULT(sum, n, 16); \
2467 if ((sum >> 16) == 1) \
2468 ge |= 3 << (n * 2); \
2471 #define ADD8(a, b, n) do { \
2473 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2474 RESULT(sum, n, 8); \
2475 if ((sum >> 8) == 1) \
2479 #define SUB16(a, b, n) do { \
2481 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2482 RESULT(sum, n, 16); \
2483 if ((sum >> 16) == 0) \
2484 ge |= 3 << (n * 2); \
2487 #define SUB8(a, b, n) do { \
2489 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2490 RESULT(sum, n, 8); \
2491 if ((sum >> 8) == 0) \
2498 #include "op_addsub.h"
2500 /* Halved signed arithmetic. */
2501 #define ADD16(a, b, n) \
2502 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2503 #define SUB16(a, b, n) \
2504 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2505 #define ADD8(a, b, n) \
2506 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2507 #define SUB8(a, b, n) \
2508 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2511 #include "op_addsub.h"
2513 /* Halved unsigned arithmetic. */
2514 #define ADD16(a, b, n) \
2515 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2516 #define SUB16(a, b, n) \
2517 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2518 #define ADD8(a, b, n) \
2519 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2520 #define SUB8(a, b, n) \
2521 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2524 #include "op_addsub.h"
2526 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2534 /* Unsigned sum of absolute byte differences. */
2535 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2538 sum
= do_usad(a
, b
);
2539 sum
+= do_usad(a
>> 8, b
>> 8);
2540 sum
+= do_usad(a
>> 16, b
>>16);
2541 sum
+= do_usad(a
>> 24, b
>> 24);
2545 /* For ARMv6 SEL instruction. */
2546 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2559 return (a
& mask
) | (b
& ~mask
);
2562 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2564 return (val
>> 32) | (val
!= 0);
2567 /* VFP support. We follow the convention used for VFP instrunctions:
2568 Single precition routines have a "s" suffix, double precision a
2571 /* Convert host exception flags to vfp form. */
2572 static inline int vfp_exceptbits_from_host(int host_bits
)
2574 int target_bits
= 0;
2576 if (host_bits
& float_flag_invalid
)
2578 if (host_bits
& float_flag_divbyzero
)
2580 if (host_bits
& float_flag_overflow
)
2582 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2584 if (host_bits
& float_flag_inexact
)
2585 target_bits
|= 0x10;
2586 if (host_bits
& float_flag_input_denormal
)
2587 target_bits
|= 0x80;
2591 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2596 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2597 | (env
->vfp
.vec_len
<< 16)
2598 | (env
->vfp
.vec_stride
<< 20);
2599 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2600 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2601 fpscr
|= vfp_exceptbits_from_host(i
);
2605 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2607 return HELPER(vfp_get_fpscr
)(env
);
2610 /* Convert vfp exception flags to target form. */
2611 static inline int vfp_exceptbits_to_host(int target_bits
)
2615 if (target_bits
& 1)
2616 host_bits
|= float_flag_invalid
;
2617 if (target_bits
& 2)
2618 host_bits
|= float_flag_divbyzero
;
2619 if (target_bits
& 4)
2620 host_bits
|= float_flag_overflow
;
2621 if (target_bits
& 8)
2622 host_bits
|= float_flag_underflow
;
2623 if (target_bits
& 0x10)
2624 host_bits
|= float_flag_inexact
;
2625 if (target_bits
& 0x80)
2626 host_bits
|= float_flag_input_denormal
;
2630 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2635 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2636 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2637 env
->vfp
.vec_len
= (val
>> 16) & 7;
2638 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2641 if (changed
& (3 << 22)) {
2642 i
= (val
>> 22) & 3;
2645 i
= float_round_nearest_even
;
2651 i
= float_round_down
;
2654 i
= float_round_to_zero
;
2657 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2659 if (changed
& (1 << 24)) {
2660 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2661 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2663 if (changed
& (1 << 25))
2664 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2666 i
= vfp_exceptbits_to_host(val
);
2667 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2668 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2671 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2673 HELPER(vfp_set_fpscr
)(env
, val
);
2676 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2678 #define VFP_BINOP(name) \
2679 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2681 float_status *fpst = fpstp; \
2682 return float32_ ## name(a, b, fpst); \
2684 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2686 float_status *fpst = fpstp; \
2687 return float64_ ## name(a, b, fpst); \
2695 float32
VFP_HELPER(neg
, s
)(float32 a
)
2697 return float32_chs(a
);
2700 float64
VFP_HELPER(neg
, d
)(float64 a
)
2702 return float64_chs(a
);
2705 float32
VFP_HELPER(abs
, s
)(float32 a
)
2707 return float32_abs(a
);
2710 float64
VFP_HELPER(abs
, d
)(float64 a
)
2712 return float64_abs(a
);
2715 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2717 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2720 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2722 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2725 /* XXX: check quiet/signaling case */
2726 #define DO_VFP_cmp(p, type) \
2727 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2730 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2731 case 0: flags = 0x6; break; \
2732 case -1: flags = 0x8; break; \
2733 case 1: flags = 0x2; break; \
2734 default: case 2: flags = 0x3; break; \
2736 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2737 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2739 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2742 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2743 case 0: flags = 0x6; break; \
2744 case -1: flags = 0x8; break; \
2745 case 1: flags = 0x2; break; \
2746 default: case 2: flags = 0x3; break; \
2748 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2749 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2751 DO_VFP_cmp(s
, float32
)
2752 DO_VFP_cmp(d
, float64
)
2755 /* Integer to float and float to integer conversions */
2757 #define CONV_ITOF(name, fsz, sign) \
2758 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2760 float_status *fpst = fpstp; \
2761 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2764 #define CONV_FTOI(name, fsz, sign, round) \
2765 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2767 float_status *fpst = fpstp; \
2768 if (float##fsz##_is_any_nan(x)) { \
2769 float_raise(float_flag_invalid, fpst); \
2772 return float##fsz##_to_##sign##int32##round(x, fpst); \
2775 #define FLOAT_CONVS(name, p, fsz, sign) \
2776 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2777 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2778 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2780 FLOAT_CONVS(si
, s
, 32, )
2781 FLOAT_CONVS(si
, d
, 64, )
2782 FLOAT_CONVS(ui
, s
, 32, u
)
2783 FLOAT_CONVS(ui
, d
, 64, u
)
2789 /* floating point conversion */
2790 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2792 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2793 /* ARM requires that S<->D conversion of any kind of NaN generates
2794 * a quiet NaN by forcing the most significant frac bit to 1.
2796 return float64_maybe_silence_nan(r
);
2799 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2801 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2802 /* ARM requires that S<->D conversion of any kind of NaN generates
2803 * a quiet NaN by forcing the most significant frac bit to 1.
2805 return float32_maybe_silence_nan(r
);
2808 /* VFP3 fixed point conversion. */
2809 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2810 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2813 float_status *fpst = fpstp; \
2815 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2816 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2818 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2821 float_status *fpst = fpstp; \
2823 if (float##fsz##_is_any_nan(x)) { \
2824 float_raise(float_flag_invalid, fpst); \
2827 tmp = float##fsz##_scalbn(x, shift, fpst); \
2828 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2831 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2832 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2833 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2834 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2835 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2836 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2837 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2838 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2841 /* Half precision conversions. */
2842 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2844 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2845 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2847 return float32_maybe_silence_nan(r
);
2852 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2854 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2855 float16 r
= float32_to_float16(a
, ieee
, s
);
2857 r
= float16_maybe_silence_nan(r
);
2859 return float16_val(r
);
2862 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2864 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2867 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2869 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2872 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2874 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2877 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2879 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2882 #define float32_two make_float32(0x40000000)
2883 #define float32_three make_float32(0x40400000)
2884 #define float32_one_point_five make_float32(0x3fc00000)
2886 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2888 float_status
*s
= &env
->vfp
.standard_fp_status
;
2889 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2890 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2891 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2892 float_raise(float_flag_input_denormal
, s
);
2896 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2899 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2901 float_status
*s
= &env
->vfp
.standard_fp_status
;
2903 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2904 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2905 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2906 float_raise(float_flag_input_denormal
, s
);
2908 return float32_one_point_five
;
2910 product
= float32_mul(a
, b
, s
);
2911 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2916 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2917 * int->float conversions at run-time. */
2918 #define float64_256 make_float64(0x4070000000000000LL)
2919 #define float64_512 make_float64(0x4080000000000000LL)
2921 /* The algorithm that must be used to calculate the estimate
2922 * is specified by the ARM ARM.
2924 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2926 /* These calculations mustn't set any fp exception flags,
2927 * so we use a local copy of the fp_status.
2929 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2930 float_status
*s
= &dummy_status
;
2931 /* q = (int)(a * 512.0) */
2932 float64 q
= float64_mul(float64_512
, a
, s
);
2933 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2935 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2936 q
= int64_to_float64(q_int
, s
);
2937 q
= float64_add(q
, float64_half
, s
);
2938 q
= float64_div(q
, float64_512
, s
);
2939 q
= float64_div(float64_one
, q
, s
);
2941 /* s = (int)(256.0 * r + 0.5) */
2942 q
= float64_mul(q
, float64_256
, s
);
2943 q
= float64_add(q
, float64_half
, s
);
2944 q_int
= float64_to_int64_round_to_zero(q
, s
);
2946 /* return (double)s / 256.0 */
2947 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2950 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2952 float_status
*s
= &env
->vfp
.standard_fp_status
;
2954 uint32_t val32
= float32_val(a
);
2957 int a_exp
= (val32
& 0x7f800000) >> 23;
2958 int sign
= val32
& 0x80000000;
2960 if (float32_is_any_nan(a
)) {
2961 if (float32_is_signaling_nan(a
)) {
2962 float_raise(float_flag_invalid
, s
);
2964 return float32_default_nan
;
2965 } else if (float32_is_infinity(a
)) {
2966 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2967 } else if (float32_is_zero_or_denormal(a
)) {
2968 if (!float32_is_zero(a
)) {
2969 float_raise(float_flag_input_denormal
, s
);
2971 float_raise(float_flag_divbyzero
, s
);
2972 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2973 } else if (a_exp
>= 253) {
2974 float_raise(float_flag_underflow
, s
);
2975 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2978 f64
= make_float64((0x3feULL
<< 52)
2979 | ((int64_t)(val32
& 0x7fffff) << 29));
2981 result_exp
= 253 - a_exp
;
2983 f64
= recip_estimate(f64
, env
);
2986 | ((result_exp
& 0xff) << 23)
2987 | ((float64_val(f64
) >> 29) & 0x7fffff);
2988 return make_float32(val32
);
2991 /* The algorithm that must be used to calculate the estimate
2992 * is specified by the ARM ARM.
2994 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2996 /* These calculations mustn't set any fp exception flags,
2997 * so we use a local copy of the fp_status.
2999 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3000 float_status
*s
= &dummy_status
;
3004 if (float64_lt(a
, float64_half
, s
)) {
3005 /* range 0.25 <= a < 0.5 */
3007 /* a in units of 1/512 rounded down */
3008 /* q0 = (int)(a * 512.0); */
3009 q
= float64_mul(float64_512
, a
, s
);
3010 q_int
= float64_to_int64_round_to_zero(q
, s
);
3012 /* reciprocal root r */
3013 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3014 q
= int64_to_float64(q_int
, s
);
3015 q
= float64_add(q
, float64_half
, s
);
3016 q
= float64_div(q
, float64_512
, s
);
3017 q
= float64_sqrt(q
, s
);
3018 q
= float64_div(float64_one
, q
, s
);
3020 /* range 0.5 <= a < 1.0 */
3022 /* a in units of 1/256 rounded down */
3023 /* q1 = (int)(a * 256.0); */
3024 q
= float64_mul(float64_256
, a
, s
);
3025 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3027 /* reciprocal root r */
3028 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3029 q
= int64_to_float64(q_int
, s
);
3030 q
= float64_add(q
, float64_half
, s
);
3031 q
= float64_div(q
, float64_256
, s
);
3032 q
= float64_sqrt(q
, s
);
3033 q
= float64_div(float64_one
, q
, s
);
3035 /* r in units of 1/256 rounded to nearest */
3036 /* s = (int)(256.0 * r + 0.5); */
3038 q
= float64_mul(q
, float64_256
,s
);
3039 q
= float64_add(q
, float64_half
, s
);
3040 q_int
= float64_to_int64_round_to_zero(q
, s
);
3042 /* return (double)s / 256.0;*/
3043 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3046 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3048 float_status
*s
= &env
->vfp
.standard_fp_status
;
3054 val
= float32_val(a
);
3056 if (float32_is_any_nan(a
)) {
3057 if (float32_is_signaling_nan(a
)) {
3058 float_raise(float_flag_invalid
, s
);
3060 return float32_default_nan
;
3061 } else if (float32_is_zero_or_denormal(a
)) {
3062 if (!float32_is_zero(a
)) {
3063 float_raise(float_flag_input_denormal
, s
);
3065 float_raise(float_flag_divbyzero
, s
);
3066 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3067 } else if (float32_is_neg(a
)) {
3068 float_raise(float_flag_invalid
, s
);
3069 return float32_default_nan
;
3070 } else if (float32_is_infinity(a
)) {
3071 return float32_zero
;
3074 /* Normalize to a double-precision value between 0.25 and 1.0,
3075 * preserving the parity of the exponent. */
3076 if ((val
& 0x800000) == 0) {
3077 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3079 | ((uint64_t)(val
& 0x7fffff) << 29));
3081 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3083 | ((uint64_t)(val
& 0x7fffff) << 29));
3086 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3088 f64
= recip_sqrt_estimate(f64
, env
);
3090 val64
= float64_val(f64
);
3092 val
= ((result_exp
& 0xff) << 23)
3093 | ((val64
>> 29) & 0x7fffff);
3094 return make_float32(val
);
3097 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3101 if ((a
& 0x80000000) == 0) {
3105 f64
= make_float64((0x3feULL
<< 52)
3106 | ((int64_t)(a
& 0x7fffffff) << 21));
3108 f64
= recip_estimate (f64
, env
);
3110 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3113 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3117 if ((a
& 0xc0000000) == 0) {
3121 if (a
& 0x80000000) {
3122 f64
= make_float64((0x3feULL
<< 52)
3123 | ((uint64_t)(a
& 0x7fffffff) << 21));
3124 } else { /* bits 31-30 == '01' */
3125 f64
= make_float64((0x3fdULL
<< 52)
3126 | ((uint64_t)(a
& 0x3fffffff) << 22));
3129 f64
= recip_sqrt_estimate(f64
, env
);
3131 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3134 /* VFPv4 fused multiply-accumulate */
3135 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3137 float_status
*fpst
= fpstp
;
3138 return float32_muladd(a
, b
, c
, 0, fpst
);
3141 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3143 float_status
*fpst
= fpstp
;
3144 return float64_muladd(a
, b
, c
, 0, fpst
);