4 #include "host-utils.h"
7 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
11 /* VFP data registers are always little-endian. */
12 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
14 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
17 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
18 /* Aliases for Q regs. */
21 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
22 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
26 switch (reg
- nregs
) {
27 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
28 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
29 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
34 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
38 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
40 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
43 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
46 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
47 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
51 switch (reg
- nregs
) {
52 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
53 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
54 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
59 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
62 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
66 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
68 if (env
->cp15
.c13_fcse
!= value
) {
69 /* Unlike real hardware the qemu TLB uses virtual addresses,
70 * not modified virtual addresses, so this causes a TLB flush.
73 env
->cp15
.c13_fcse
= value
;
77 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
80 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
81 /* For VMSA (when not using the LPAE long descriptor page table
82 * format) this register includes the ASID, so do a TLB flush.
83 * For PMSA it is purely a process ID and no action is needed.
87 env
->cp15
.c13_context
= value
;
91 static const ARMCPRegInfo cp_reginfo
[] = {
92 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
93 * version" bits will read as a reserved value, which should cause
94 * Linux to not try to use the debug hardware.
96 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
97 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
98 /* MMU Domain access control / MPU write buffer control */
99 { .name
= "DACR", .cp
= 15,
100 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
101 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
102 .resetvalue
= 0, .writefn
= dacr_write
},
103 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
104 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
105 .resetvalue
= 0, .writefn
= fcse_write
},
106 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
107 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
108 .resetvalue
= 0, .writefn
= contextidr_write
},
109 /* ??? This covers not just the impdef TLB lockdown registers but also
110 * some v7VMSA registers relating to TEX remap, so it is overly broad.
112 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
113 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
117 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
118 /* Not all pre-v6 cores implemented this WFI, so this is slightly
121 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
122 .access
= PL1_W
, .type
= ARM_CP_WFI
},
126 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
127 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
128 * is UNPREDICTABLE; we choose to NOP as most implementations do).
130 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
131 .access
= PL1_W
, .type
= ARM_CP_WFI
},
135 static const ARMCPRegInfo v6_cp_reginfo
[] = {
136 /* prefetch by MVA in v6, NOP in v7 */
137 { .name
= "MVA_prefetch",
138 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
139 .access
= PL1_W
, .type
= ARM_CP_NOP
},
140 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
141 .access
= PL0_W
, .type
= ARM_CP_NOP
},
142 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
143 .access
= PL0_W
, .type
= ARM_CP_NOP
},
144 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
145 .access
= PL0_W
, .type
= ARM_CP_NOP
},
149 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
152 /* Generic performance monitor register read function for where
153 * user access may be allowed by PMUSERENR.
155 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
158 *value
= CPREG_FIELD32(env
, ri
);
162 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
165 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
168 /* only the DP, X, D and E bits are writable */
169 env
->cp15
.c9_pmcr
&= ~0x39;
170 env
->cp15
.c9_pmcr
|= (value
& 0x39);
174 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
177 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
181 env
->cp15
.c9_pmcnten
|= value
;
185 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
188 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
192 env
->cp15
.c9_pmcnten
&= ~value
;
196 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
199 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
202 env
->cp15
.c9_pmovsr
&= ~value
;
206 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
209 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
212 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
216 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
219 env
->cp15
.c9_pmuserenr
= value
& 1;
223 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
226 /* We have no event counters so only the C bit can be changed */
228 env
->cp15
.c9_pminten
|= value
;
232 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
236 env
->cp15
.c9_pminten
&= ~value
;
240 static const ARMCPRegInfo v7_cp_reginfo
[] = {
241 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
244 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
245 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
246 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
247 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
248 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
249 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
250 .access
= PL1_W
, .type
= ARM_CP_NOP
},
251 /* Performance monitors are implementation defined in v7,
252 * but with an ARM recommended set of registers, which we
253 * follow (although we don't actually implement any counters)
255 * Performance registers fall into three categories:
256 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
257 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
258 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
259 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
260 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
262 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
263 .access
= PL0_RW
, .resetvalue
= 0,
264 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
265 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
266 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
267 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
268 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
269 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
270 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
271 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
272 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
275 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
276 .access
= PL0_W
, .type
= ARM_CP_NOP
},
277 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
278 * We choose to RAZ/WI. XXX should respect PMUSERENR.
280 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
281 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
282 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
283 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
284 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
285 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
287 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
288 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
289 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
290 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
291 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
292 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
293 .access
= PL0_R
| PL1_RW
,
294 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
296 .writefn
= pmuserenr_write
},
297 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
299 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
301 .writefn
= pmintenset_write
},
302 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
306 .writefn
= pmintenclr_write
},
310 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
317 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
320 /* This is a helper function because the user access rights
321 * depend on the value of the TEECR.
323 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
326 *value
= env
->teehbr
;
330 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
333 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
340 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
341 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
342 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
344 .writefn
= teecr_write
},
345 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
346 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
348 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
352 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
353 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
355 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
357 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
358 .access
= PL0_R
|PL1_W
,
359 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
361 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
363 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
368 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
369 /* Dummy implementation: RAZ/WI the whole crn=14 space */
370 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
371 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
372 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
376 /* Return basic MPU access permission bits. */
377 static uint32_t simple_mpu_ap_bits(uint32_t val
)
384 for (i
= 0; i
< 16; i
+= 2) {
385 ret
|= (val
>> i
) & mask
;
391 /* Pad basic MPU access permission bits to extended format. */
392 static uint32_t extended_mpu_ap_bits(uint32_t val
)
399 for (i
= 0; i
< 16; i
+= 2) {
400 ret
|= (val
& mask
) << i
;
406 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
409 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
413 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
416 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
420 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
423 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
427 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
430 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
434 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
435 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
437 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
438 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
439 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
441 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
442 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
443 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
445 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
446 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
448 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
449 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
451 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
452 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
454 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
458 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
462 env
->cp15
.c2_control
= value
;
463 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
464 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
468 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
470 env
->cp15
.c2_base_mask
= 0xffffc000u
;
471 env
->cp15
.c2_control
= 0;
472 env
->cp15
.c2_mask
= 0;
475 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
476 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
478 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
479 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
481 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
482 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
484 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
485 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
487 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
488 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
489 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
490 .resetfn
= vmsa_ttbcr_reset
,
491 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
495 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
498 env
->cp15
.c15_ticonfig
= value
& 0xe7;
499 /* The OS_TYPE bit in this register changes the reported CPUID! */
500 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
501 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
505 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
508 env
->cp15
.c15_threadid
= value
& 0xffff;
512 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 /* Wait-for-interrupt (deprecated) */
516 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
520 static const ARMCPRegInfo omap_cp_reginfo
[] = {
521 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
522 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
523 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
524 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
525 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
526 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
528 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
529 .writefn
= omap_ticonfig_write
},
530 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
532 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
533 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
534 .access
= PL1_RW
, .resetvalue
= 0xff0,
535 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
536 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
539 .writefn
= omap_threadid_write
},
540 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
541 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
542 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
543 /* TODO: Peripheral port remap register:
544 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
545 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
551 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 if (env
->cp15
.c15_cpar
!= value
) {
556 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
558 env
->cp15
.c15_cpar
= value
;
563 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
564 { .name
= "XSCALE_CPAR",
565 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
566 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
567 .writefn
= xscale_cpar_write
, },
571 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
572 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
573 * implementation of this implementation-defined space.
574 * Ideally this should eventually disappear in favour of actually
575 * implementing the correct behaviour for all cores.
577 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
578 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
579 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
583 void register_cp_regs_for_features(ARMCPU
*cpu
)
585 /* Register all the coprocessor registers based on feature bits */
586 CPUARMState
*env
= &cpu
->env
;
587 if (arm_feature(env
, ARM_FEATURE_M
)) {
588 /* M profile has no coprocessor registers */
592 define_arm_cp_regs(cpu
, cp_reginfo
);
593 if (arm_feature(env
, ARM_FEATURE_V6
)) {
594 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
596 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
598 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
599 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
601 if (arm_feature(env
, ARM_FEATURE_V7
)) {
602 /* v7 performance monitor control register: same implementor
603 * field as main ID register, and we implement no event counters.
605 ARMCPRegInfo pmcr
= {
606 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
607 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
608 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
609 .readfn
= pmreg_read
, .writefn
= pmcr_write
611 define_one_arm_cp_reg(cpu
, &pmcr
);
612 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
614 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
616 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
617 /* These are the MPU registers prior to PMSAv6. Any new
618 * PMSA core later than the ARM946 will require that we
619 * implement the PMSAv6 or PMSAv7 registers, which are
620 * completely different.
622 assert(!arm_feature(env
, ARM_FEATURE_V6
));
623 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
625 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
627 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
628 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
630 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
631 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
633 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
634 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
636 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
637 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
639 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
640 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
644 ARMCPU
*cpu_arm_init(const char *cpu_model
)
648 static int inited
= 0;
650 if (!object_class_by_name(cpu_model
)) {
653 cpu
= ARM_CPU(object_new(cpu_model
));
655 env
->cpu_model_str
= cpu_model
;
656 arm_cpu_realize(cpu
);
658 if (tcg_enabled() && !inited
) {
660 arm_translate_init();
664 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
665 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
666 51, "arm-neon.xml", 0);
667 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
668 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
669 35, "arm-vfp3.xml", 0);
670 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
671 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
672 19, "arm-vfp.xml", 0);
678 typedef struct ARMCPUListState
{
679 fprintf_function cpu_fprintf
;
683 /* Sort alphabetically by type name, except for "any". */
684 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
686 ObjectClass
*class_a
= (ObjectClass
*)a
;
687 ObjectClass
*class_b
= (ObjectClass
*)b
;
688 const char *name_a
, *name_b
;
690 name_a
= object_class_get_name(class_a
);
691 name_b
= object_class_get_name(class_b
);
692 if (strcmp(name_a
, "any") == 0) {
694 } else if (strcmp(name_b
, "any") == 0) {
697 return strcmp(name_a
, name_b
);
701 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
703 ObjectClass
*oc
= data
;
704 ARMCPUListState
*s
= user_data
;
706 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
707 object_class_get_name(oc
));
710 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
712 ARMCPUListState s
= {
714 .cpu_fprintf
= cpu_fprintf
,
718 list
= object_class_get_list(TYPE_ARM_CPU
, false);
719 list
= g_slist_sort(list
, arm_cpu_list_compare
);
720 (*cpu_fprintf
)(f
, "Available CPUs:\n");
721 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
725 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
726 const ARMCPRegInfo
*r
, void *opaque
)
728 /* Define implementations of coprocessor registers.
729 * We store these in a hashtable because typically
730 * there are less than 150 registers in a space which
731 * is 16*16*16*8*8 = 262144 in size.
732 * Wildcarding is supported for the crm, opc1 and opc2 fields.
733 * If a register is defined twice then the second definition is
734 * used, so this can be used to define some generic registers and
735 * then override them with implementation specific variations.
736 * At least one of the original and the second definition should
737 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
738 * against accidental use.
741 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
742 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
743 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
744 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
745 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
746 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
747 /* 64 bit registers have only CRm and Opc1 fields */
748 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
749 /* Check that the register definition has enough info to handle
750 * reads and writes if they are permitted.
752 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
753 if (r
->access
& PL3_R
) {
754 assert(r
->fieldoffset
|| r
->readfn
);
756 if (r
->access
& PL3_W
) {
757 assert(r
->fieldoffset
|| r
->writefn
);
760 /* Bad type field probably means missing sentinel at end of reg list */
761 assert(cptype_valid(r
->type
));
762 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
763 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
764 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
765 uint32_t *key
= g_new(uint32_t, 1);
766 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
767 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
768 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
770 /* Make sure reginfo passed to helpers for wildcarded regs
771 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
776 /* Overriding of an existing definition must be explicitly
779 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
780 ARMCPRegInfo
*oldreg
;
781 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
782 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
783 fprintf(stderr
, "Register redefined: cp=%d %d bit "
784 "crn=%d crm=%d opc1=%d opc2=%d, "
785 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
786 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
787 oldreg
->name
, r2
->name
);
791 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
797 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
798 const ARMCPRegInfo
*regs
, void *opaque
)
800 /* Define a whole list of registers */
801 const ARMCPRegInfo
*r
;
802 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
803 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
807 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
809 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
812 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
815 /* Helper coprocessor write function for write-ignore registers */
819 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
821 /* Helper coprocessor write function for read-as-zero registers */
826 static int bad_mode_switch(CPUARMState
*env
, int mode
)
828 /* Return true if it is not valid for us to switch to
829 * this CPU mode (ie all the UNPREDICTABLE cases in
830 * the ARM ARM CPSRWriteByInstr pseudocode).
833 case ARM_CPU_MODE_USR
:
834 case ARM_CPU_MODE_SYS
:
835 case ARM_CPU_MODE_SVC
:
836 case ARM_CPU_MODE_ABT
:
837 case ARM_CPU_MODE_UND
:
838 case ARM_CPU_MODE_IRQ
:
839 case ARM_CPU_MODE_FIQ
:
846 uint32_t cpsr_read(CPUARMState
*env
)
850 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
851 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
852 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
853 | ((env
->condexec_bits
& 0xfc) << 8)
857 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
859 if (mask
& CPSR_NZCV
) {
860 env
->ZF
= (~val
) & CPSR_Z
;
862 env
->CF
= (val
>> 29) & 1;
863 env
->VF
= (val
<< 3) & 0x80000000;
866 env
->QF
= ((val
& CPSR_Q
) != 0);
868 env
->thumb
= ((val
& CPSR_T
) != 0);
869 if (mask
& CPSR_IT_0_1
) {
870 env
->condexec_bits
&= ~3;
871 env
->condexec_bits
|= (val
>> 25) & 3;
873 if (mask
& CPSR_IT_2_7
) {
874 env
->condexec_bits
&= 3;
875 env
->condexec_bits
|= (val
>> 8) & 0xfc;
877 if (mask
& CPSR_GE
) {
878 env
->GE
= (val
>> 16) & 0xf;
881 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
882 if (bad_mode_switch(env
, val
& CPSR_M
)) {
883 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
884 * We choose to ignore the attempt and leave the CPSR M field
889 switch_mode(env
, val
& CPSR_M
);
892 mask
&= ~CACHED_CPSR_BITS
;
893 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
896 /* Sign/zero extend */
897 uint32_t HELPER(sxtb16
)(uint32_t x
)
900 res
= (uint16_t)(int8_t)x
;
901 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
905 uint32_t HELPER(uxtb16
)(uint32_t x
)
908 res
= (uint16_t)(uint8_t)x
;
909 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
913 uint32_t HELPER(clz
)(uint32_t x
)
918 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
922 if (num
== INT_MIN
&& den
== -1)
927 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
934 uint32_t HELPER(rbit
)(uint32_t x
)
936 x
= ((x
& 0xff000000) >> 24)
937 | ((x
& 0x00ff0000) >> 8)
938 | ((x
& 0x0000ff00) << 8)
939 | ((x
& 0x000000ff) << 24);
940 x
= ((x
& 0xf0f0f0f0) >> 4)
941 | ((x
& 0x0f0f0f0f) << 4);
942 x
= ((x
& 0x88888888) >> 3)
943 | ((x
& 0x44444444) >> 1)
944 | ((x
& 0x22222222) << 1)
945 | ((x
& 0x11111111) << 3);
949 uint32_t HELPER(abs
)(uint32_t x
)
951 return ((int32_t)x
< 0) ? -x
: x
;
954 #if defined(CONFIG_USER_ONLY)
956 void do_interrupt (CPUARMState
*env
)
958 env
->exception_index
= -1;
961 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
965 env
->exception_index
= EXCP_PREFETCH_ABORT
;
966 env
->cp15
.c6_insn
= address
;
968 env
->exception_index
= EXCP_DATA_ABORT
;
969 env
->cp15
.c6_data
= address
;
974 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
976 cpu_abort(env
, "cp15 insn %08x\n", insn
);
979 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
981 cpu_abort(env
, "cp15 insn %08x\n", insn
);
984 /* These should probably raise undefined insn exceptions. */
985 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
987 cpu_abort(env
, "v7m_mrs %d\n", reg
);
990 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
992 cpu_abort(env
, "v7m_mrs %d\n", reg
);
996 void switch_mode(CPUARMState
*env
, int mode
)
998 if (mode
!= ARM_CPU_MODE_USR
)
999 cpu_abort(env
, "Tried to switch out of user mode\n");
1002 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1004 cpu_abort(env
, "banked r13 write\n");
1007 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1009 cpu_abort(env
, "banked r13 read\n");
1015 /* Map CPU modes onto saved register banks. */
1016 static inline int bank_number(CPUARMState
*env
, int mode
)
1019 case ARM_CPU_MODE_USR
:
1020 case ARM_CPU_MODE_SYS
:
1022 case ARM_CPU_MODE_SVC
:
1024 case ARM_CPU_MODE_ABT
:
1026 case ARM_CPU_MODE_UND
:
1028 case ARM_CPU_MODE_IRQ
:
1030 case ARM_CPU_MODE_FIQ
:
1033 cpu_abort(env
, "Bad mode %x\n", mode
);
1037 void switch_mode(CPUARMState
*env
, int mode
)
1042 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1043 if (mode
== old_mode
)
1046 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1047 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1048 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1049 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1050 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1051 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1054 i
= bank_number(env
, old_mode
);
1055 env
->banked_r13
[i
] = env
->regs
[13];
1056 env
->banked_r14
[i
] = env
->regs
[14];
1057 env
->banked_spsr
[i
] = env
->spsr
;
1059 i
= bank_number(env
, mode
);
1060 env
->regs
[13] = env
->banked_r13
[i
];
1061 env
->regs
[14] = env
->banked_r14
[i
];
1062 env
->spsr
= env
->banked_spsr
[i
];
1065 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1068 stl_phys(env
->regs
[13], val
);
1071 static uint32_t v7m_pop(CPUARMState
*env
)
1074 val
= ldl_phys(env
->regs
[13]);
1079 /* Switch to V7M main or process stack pointer. */
1080 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1083 if (env
->v7m
.current_sp
!= process
) {
1084 tmp
= env
->v7m
.other_sp
;
1085 env
->v7m
.other_sp
= env
->regs
[13];
1086 env
->regs
[13] = tmp
;
1087 env
->v7m
.current_sp
= process
;
1091 static void do_v7m_exception_exit(CPUARMState
*env
)
1096 type
= env
->regs
[15];
1097 if (env
->v7m
.exception
!= 0)
1098 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1100 /* Switch to the target stack. */
1101 switch_v7m_sp(env
, (type
& 4) != 0);
1102 /* Pop registers. */
1103 env
->regs
[0] = v7m_pop(env
);
1104 env
->regs
[1] = v7m_pop(env
);
1105 env
->regs
[2] = v7m_pop(env
);
1106 env
->regs
[3] = v7m_pop(env
);
1107 env
->regs
[12] = v7m_pop(env
);
1108 env
->regs
[14] = v7m_pop(env
);
1109 env
->regs
[15] = v7m_pop(env
);
1110 xpsr
= v7m_pop(env
);
1111 xpsr_write(env
, xpsr
, 0xfffffdff);
1112 /* Undo stack alignment. */
1115 /* ??? The exception return type specifies Thread/Handler mode. However
1116 this is also implied by the xPSR value. Not sure what to do
1117 if there is a mismatch. */
1118 /* ??? Likewise for mismatches between the CONTROL register and the stack
1122 static void do_interrupt_v7m(CPUARMState
*env
)
1124 uint32_t xpsr
= xpsr_read(env
);
1129 if (env
->v7m
.current_sp
)
1131 if (env
->v7m
.exception
== 0)
1134 /* For exceptions we just mark as pending on the NVIC, and let that
1136 /* TODO: Need to escalate if the current priority is higher than the
1137 one we're raising. */
1138 switch (env
->exception_index
) {
1140 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1144 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1146 case EXCP_PREFETCH_ABORT
:
1147 case EXCP_DATA_ABORT
:
1148 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1151 if (semihosting_enabled
) {
1153 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1156 env
->regs
[0] = do_arm_semihosting(env
);
1160 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1163 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1165 case EXCP_EXCEPTION_EXIT
:
1166 do_v7m_exception_exit(env
);
1169 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1170 return; /* Never happens. Keep compiler happy. */
1173 /* Align stack pointer. */
1174 /* ??? Should only do this if Configuration Control Register
1175 STACKALIGN bit is set. */
1176 if (env
->regs
[13] & 4) {
1180 /* Switch to the handler mode. */
1181 v7m_push(env
, xpsr
);
1182 v7m_push(env
, env
->regs
[15]);
1183 v7m_push(env
, env
->regs
[14]);
1184 v7m_push(env
, env
->regs
[12]);
1185 v7m_push(env
, env
->regs
[3]);
1186 v7m_push(env
, env
->regs
[2]);
1187 v7m_push(env
, env
->regs
[1]);
1188 v7m_push(env
, env
->regs
[0]);
1189 switch_v7m_sp(env
, 0);
1191 env
->condexec_bits
= 0;
1193 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1194 env
->regs
[15] = addr
& 0xfffffffe;
1195 env
->thumb
= addr
& 1;
1198 /* Handle a CPU exception. */
1199 void do_interrupt(CPUARMState
*env
)
1207 do_interrupt_v7m(env
);
1210 /* TODO: Vectored interrupt controller. */
1211 switch (env
->exception_index
) {
1213 new_mode
= ARM_CPU_MODE_UND
;
1222 if (semihosting_enabled
) {
1223 /* Check for semihosting interrupt. */
1225 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1227 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1230 /* Only intercept calls from privileged modes, to provide some
1231 semblance of security. */
1232 if (((mask
== 0x123456 && !env
->thumb
)
1233 || (mask
== 0xab && env
->thumb
))
1234 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1235 env
->regs
[0] = do_arm_semihosting(env
);
1239 new_mode
= ARM_CPU_MODE_SVC
;
1242 /* The PC already points to the next instruction. */
1246 /* See if this is a semihosting syscall. */
1247 if (env
->thumb
&& semihosting_enabled
) {
1248 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1250 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1252 env
->regs
[0] = do_arm_semihosting(env
);
1256 env
->cp15
.c5_insn
= 2;
1257 /* Fall through to prefetch abort. */
1258 case EXCP_PREFETCH_ABORT
:
1259 new_mode
= ARM_CPU_MODE_ABT
;
1261 mask
= CPSR_A
| CPSR_I
;
1264 case EXCP_DATA_ABORT
:
1265 new_mode
= ARM_CPU_MODE_ABT
;
1267 mask
= CPSR_A
| CPSR_I
;
1271 new_mode
= ARM_CPU_MODE_IRQ
;
1273 /* Disable IRQ and imprecise data aborts. */
1274 mask
= CPSR_A
| CPSR_I
;
1278 new_mode
= ARM_CPU_MODE_FIQ
;
1280 /* Disable FIQ, IRQ and imprecise data aborts. */
1281 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1285 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1286 return; /* Never happens. Keep compiler happy. */
1289 if (env
->cp15
.c1_sys
& (1 << 13)) {
1292 switch_mode (env
, new_mode
);
1293 env
->spsr
= cpsr_read(env
);
1294 /* Clear IT bits. */
1295 env
->condexec_bits
= 0;
1296 /* Switch to the new mode, and to the correct instruction set. */
1297 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1298 env
->uncached_cpsr
|= mask
;
1299 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1300 * and we should just guard the thumb mode on V4 */
1301 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1302 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1304 env
->regs
[14] = env
->regs
[15] + offset
;
1305 env
->regs
[15] = addr
;
1306 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1309 /* Check section/page access permissions.
1310 Returns the page protection flags, or zero if the access is not
1312 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1313 int access_type
, int is_user
)
1317 if (domain_prot
== 3) {
1318 return PAGE_READ
| PAGE_WRITE
;
1321 if (access_type
== 1)
1324 prot_ro
= PAGE_READ
;
1328 if (access_type
== 1)
1330 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1332 return is_user
? 0 : PAGE_READ
;
1339 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1344 return PAGE_READ
| PAGE_WRITE
;
1346 return PAGE_READ
| PAGE_WRITE
;
1347 case 4: /* Reserved. */
1350 return is_user
? 0 : prot_ro
;
1354 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1362 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1366 if (address
& env
->cp15
.c2_mask
)
1367 table
= env
->cp15
.c2_base1
& 0xffffc000;
1369 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1371 table
|= (address
>> 18) & 0x3ffc;
1375 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1376 int is_user
, uint32_t *phys_ptr
, int *prot
,
1377 target_ulong
*page_size
)
1388 /* Pagetable walk. */
1389 /* Lookup l1 descriptor. */
1390 table
= get_level1_table_address(env
, address
);
1391 desc
= ldl_phys(table
);
1393 domain
= (desc
>> 5) & 0x0f;
1394 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1396 /* Section translation fault. */
1400 if (domain_prot
== 0 || domain_prot
== 2) {
1402 code
= 9; /* Section domain fault. */
1404 code
= 11; /* Page domain fault. */
1409 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1410 ap
= (desc
>> 10) & 3;
1412 *page_size
= 1024 * 1024;
1414 /* Lookup l2 entry. */
1416 /* Coarse pagetable. */
1417 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1419 /* Fine pagetable. */
1420 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1422 desc
= ldl_phys(table
);
1424 case 0: /* Page translation fault. */
1427 case 1: /* 64k page. */
1428 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1429 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1430 *page_size
= 0x10000;
1432 case 2: /* 4k page. */
1433 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1434 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1435 *page_size
= 0x1000;
1437 case 3: /* 1k page. */
1439 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1440 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1442 /* Page translation fault. */
1447 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1449 ap
= (desc
>> 4) & 3;
1453 /* Never happens, but compiler isn't smart enough to tell. */
1458 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1460 /* Access permission fault. */
1464 *phys_ptr
= phys_addr
;
1467 return code
| (domain
<< 4);
1470 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1471 int is_user
, uint32_t *phys_ptr
, int *prot
,
1472 target_ulong
*page_size
)
1484 /* Pagetable walk. */
1485 /* Lookup l1 descriptor. */
1486 table
= get_level1_table_address(env
, address
);
1487 desc
= ldl_phys(table
);
1490 /* Section translation fault. */
1494 } else if (type
== 2 && (desc
& (1 << 18))) {
1498 /* Section or page. */
1499 domain
= (desc
>> 5) & 0x0f;
1501 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1502 if (domain_prot
== 0 || domain_prot
== 2) {
1504 code
= 9; /* Section domain fault. */
1506 code
= 11; /* Page domain fault. */
1510 if (desc
& (1 << 18)) {
1512 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1513 *page_size
= 0x1000000;
1516 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1517 *page_size
= 0x100000;
1519 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1520 xn
= desc
& (1 << 4);
1523 /* Lookup l2 entry. */
1524 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1525 desc
= ldl_phys(table
);
1526 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1528 case 0: /* Page translation fault. */
1531 case 1: /* 64k page. */
1532 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1533 xn
= desc
& (1 << 15);
1534 *page_size
= 0x10000;
1536 case 2: case 3: /* 4k page. */
1537 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1539 *page_size
= 0x1000;
1542 /* Never happens, but compiler isn't smart enough to tell. */
1547 if (domain_prot
== 3) {
1548 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1550 if (xn
&& access_type
== 2)
1553 /* The simplified model uses AP[0] as an access control bit. */
1554 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1555 /* Access flag fault. */
1556 code
= (code
== 15) ? 6 : 3;
1559 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1561 /* Access permission fault. */
1568 *phys_ptr
= phys_addr
;
1571 return code
| (domain
<< 4);
1574 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1575 int is_user
, uint32_t *phys_ptr
, int *prot
)
1581 *phys_ptr
= address
;
1582 for (n
= 7; n
>= 0; n
--) {
1583 base
= env
->cp15
.c6_region
[n
];
1584 if ((base
& 1) == 0)
1586 mask
= 1 << ((base
>> 1) & 0x1f);
1587 /* Keep this shift separate from the above to avoid an
1588 (undefined) << 32. */
1589 mask
= (mask
<< 1) - 1;
1590 if (((base
^ address
) & ~mask
) == 0)
1596 if (access_type
== 2) {
1597 mask
= env
->cp15
.c5_insn
;
1599 mask
= env
->cp15
.c5_data
;
1601 mask
= (mask
>> (n
* 4)) & 0xf;
1608 *prot
= PAGE_READ
| PAGE_WRITE
;
1613 *prot
|= PAGE_WRITE
;
1616 *prot
= PAGE_READ
| PAGE_WRITE
;
1627 /* Bad permission. */
1634 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1635 int access_type
, int is_user
,
1636 uint32_t *phys_ptr
, int *prot
,
1637 target_ulong
*page_size
)
1639 /* Fast Context Switch Extension. */
1640 if (address
< 0x02000000)
1641 address
+= env
->cp15
.c13_fcse
;
1643 if ((env
->cp15
.c1_sys
& 1) == 0) {
1644 /* MMU/MPU disabled. */
1645 *phys_ptr
= address
;
1646 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1647 *page_size
= TARGET_PAGE_SIZE
;
1649 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1650 *page_size
= TARGET_PAGE_SIZE
;
1651 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1653 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1654 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1657 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1662 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1663 int access_type
, int mmu_idx
)
1666 target_ulong page_size
;
1670 is_user
= mmu_idx
== MMU_USER_IDX
;
1671 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1674 /* Map a single [sub]page. */
1675 phys_addr
&= ~(uint32_t)0x3ff;
1676 address
&= ~(uint32_t)0x3ff;
1677 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1681 if (access_type
== 2) {
1682 env
->cp15
.c5_insn
= ret
;
1683 env
->cp15
.c6_insn
= address
;
1684 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1686 env
->cp15
.c5_data
= ret
;
1687 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1688 env
->cp15
.c5_data
|= (1 << 11);
1689 env
->cp15
.c6_data
= address
;
1690 env
->exception_index
= EXCP_DATA_ABORT
;
1695 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1698 target_ulong page_size
;
1702 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1710 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1716 op1
= (insn
>> 21) & 7;
1717 op2
= (insn
>> 5) & 7;
1719 switch ((insn
>> 16) & 0xf) {
1722 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1724 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1726 if (arm_feature(env
, ARM_FEATURE_V7
)
1727 && op1
== 2 && crm
== 0 && op2
== 0) {
1728 env
->cp15
.c0_cssel
= val
& 0xf;
1732 case 1: /* System configuration. */
1733 if (arm_feature(env
, ARM_FEATURE_V7
)
1734 && op1
== 0 && crm
== 1 && op2
== 0) {
1735 env
->cp15
.c1_scr
= val
;
1738 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1742 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1743 env
->cp15
.c1_sys
= val
;
1744 /* ??? Lots of these bits are not implemented. */
1745 /* This may enable/disable the MMU, so do a TLB flush. */
1748 case 1: /* Auxiliary control register. */
1749 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1750 env
->cp15
.c1_xscaleauxcr
= val
;
1753 /* Not implemented. */
1756 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1758 if (env
->cp15
.c1_coproc
!= val
) {
1759 env
->cp15
.c1_coproc
= val
;
1760 /* ??? Is this safe when called from within a TB? */
1768 case 4: /* Reserved. */
1770 case 6: /* MMU Fault address / MPU base/size. */
1771 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1774 env
->cp15
.c6_region
[crm
] = val
;
1776 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1780 env
->cp15
.c6_data
= val
;
1782 case 1: /* ??? This is WFAR on armv6 */
1784 env
->cp15
.c6_insn
= val
;
1791 case 7: /* Cache control. */
1792 env
->cp15
.c15_i_max
= 0x000;
1793 env
->cp15
.c15_i_min
= 0xff0;
1797 /* No cache, so nothing to do except VA->PA translations. */
1798 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1801 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1802 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1804 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1809 target_ulong page_size
;
1811 int ret
, is_user
= op2
& 2;
1812 int access_type
= op2
& 1;
1815 /* Other states are only available with TrustZone */
1818 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1819 &phys_addr
, &prot
, &page_size
);
1821 /* We do not set any attribute bits in the PAR */
1822 if (page_size
== (1 << 24)
1823 && arm_feature(env
, ARM_FEATURE_V7
)) {
1824 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1826 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1829 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1830 ((ret
& (12 << 1)) >> 6) |
1831 ((ret
& 0xf) << 1) | 1;
1838 case 8: /* MMU TLB control. */
1840 case 0: /* Invalidate all (TLBIALL) */
1843 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
1844 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1846 case 2: /* Invalidate by ASID (TLBIASID) */
1847 tlb_flush(env
, val
== 0);
1849 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1850 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1857 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1859 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1860 break; /* Ignore ReadBuffer access */
1862 case 0: /* Cache lockdown. */
1864 case 0: /* L1 cache. */
1867 env
->cp15
.c9_data
= val
;
1870 env
->cp15
.c9_insn
= val
;
1876 case 1: /* L2 cache. */
1877 /* Ignore writes to L2 lockdown/auxiliary registers. */
1883 case 1: /* TCM memory region registers. */
1884 /* Not implemented. */
1890 case 12: /* Reserved. */
1895 /* ??? For debugging only. Should raise illegal instruction exception. */
1896 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1897 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1900 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1906 op1
= (insn
>> 21) & 7;
1907 op2
= (insn
>> 5) & 7;
1909 switch ((insn
>> 16) & 0xf) {
1910 case 0: /* ID codes. */
1916 case 0: /* Device ID. */
1917 return env
->cp15
.c0_cpuid
;
1918 case 1: /* Cache Type. */
1919 return env
->cp15
.c0_cachetype
;
1920 case 2: /* TCM status. */
1922 case 3: /* TLB type register. */
1923 return 0; /* No lockable TLB entries. */
1925 /* The MPIDR was standardised in v7; prior to
1926 * this it was implemented only in the 11MPCore.
1927 * For all other pre-v7 cores it does not exist.
1929 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1930 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1931 int mpidr
= env
->cpu_index
;
1932 /* We don't support setting cluster ID ([8..11])
1933 * so these bits always RAZ.
1935 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1937 /* Cores which are uniprocessor (non-coherent)
1938 * but still implement the MP extensions set
1939 * bit 30. (For instance, A9UP.) However we do
1940 * not currently model any of those cores.
1945 /* otherwise fall through to the unimplemented-reg case */
1950 if (!arm_feature(env
, ARM_FEATURE_V6
))
1952 return env
->cp15
.c0_c1
[op2
];
1954 if (!arm_feature(env
, ARM_FEATURE_V6
))
1956 return env
->cp15
.c0_c2
[op2
];
1957 case 3: case 4: case 5: case 6: case 7:
1963 /* These registers aren't documented on arm11 cores. However
1964 Linux looks at them anyway. */
1965 if (!arm_feature(env
, ARM_FEATURE_V6
))
1969 if (!arm_feature(env
, ARM_FEATURE_V7
))
1974 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1976 return env
->cp15
.c0_clid
;
1982 if (op2
!= 0 || crm
!= 0)
1984 return env
->cp15
.c0_cssel
;
1988 case 1: /* System configuration. */
1989 if (arm_feature(env
, ARM_FEATURE_V7
)
1990 && op1
== 0 && crm
== 1 && op2
== 0) {
1991 return env
->cp15
.c1_scr
;
1993 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1996 case 0: /* Control register. */
1997 return env
->cp15
.c1_sys
;
1998 case 1: /* Auxiliary control register. */
1999 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2000 return env
->cp15
.c1_xscaleauxcr
;
2001 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
2003 switch (ARM_CPUID(env
)) {
2004 case ARM_CPUID_ARM1026
:
2006 case ARM_CPUID_ARM1136
:
2007 case ARM_CPUID_ARM1136_R2
:
2008 case ARM_CPUID_ARM1176
:
2010 case ARM_CPUID_ARM11MPCORE
:
2012 case ARM_CPUID_CORTEXA8
:
2014 case ARM_CPUID_CORTEXA9
:
2015 case ARM_CPUID_CORTEXA15
:
2020 case 2: /* Coprocessor access register. */
2021 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2023 return env
->cp15
.c1_coproc
;
2027 case 4: /* Reserved. */
2029 case 6: /* MMU Fault address. */
2030 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2033 return env
->cp15
.c6_region
[crm
];
2035 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2039 return env
->cp15
.c6_data
;
2041 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2042 /* Watchpoint Fault Adrress. */
2043 return 0; /* Not implemented. */
2045 /* Instruction Fault Adrress. */
2046 /* Arm9 doesn't have an IFAR, but implementing it anyway
2047 shouldn't do any harm. */
2048 return env
->cp15
.c6_insn
;
2051 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2052 /* Instruction Fault Adrress. */
2053 return env
->cp15
.c6_insn
;
2061 case 7: /* Cache control. */
2062 if (crm
== 4 && op1
== 0 && op2
== 0) {
2063 return env
->cp15
.c7_par
;
2065 /* FIXME: Should only clear Z flag if destination is r15. */
2068 case 8: /* MMU TLB control. */
2072 case 0: /* Cache lockdown */
2074 case 0: /* L1 cache. */
2075 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2080 return env
->cp15
.c9_data
;
2082 return env
->cp15
.c9_insn
;
2086 case 1: /* L2 cache */
2087 /* L2 Lockdown and Auxiliary control. */
2090 /* L2 cache lockdown (A8 only) */
2093 /* L2 cache auxiliary control (A8) or control (A15) */
2094 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
2095 /* Linux wants the number of processors from here.
2096 * Might as well set the interrupt-controller bit too.
2098 return ((smp_cpus
- 1) << 24) | (1 << 23);
2102 /* L2 cache extended control (A15) */
2115 case 11: /* TCM DMA control. */
2116 case 12: /* Reserved. */
2120 /* ??? For debugging only. Should raise illegal instruction exception. */
2121 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2122 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2126 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2128 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2129 env
->regs
[13] = val
;
2131 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2135 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2137 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2138 return env
->regs
[13];
2140 return env
->banked_r13
[bank_number(env
, mode
)];
2144 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2148 return xpsr_read(env
) & 0xf8000000;
2150 return xpsr_read(env
) & 0xf80001ff;
2152 return xpsr_read(env
) & 0xff00fc00;
2154 return xpsr_read(env
) & 0xff00fdff;
2156 return xpsr_read(env
) & 0x000001ff;
2158 return xpsr_read(env
) & 0x0700fc00;
2160 return xpsr_read(env
) & 0x0700edff;
2162 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2164 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2165 case 16: /* PRIMASK */
2166 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2167 case 17: /* BASEPRI */
2168 case 18: /* BASEPRI_MAX */
2169 return env
->v7m
.basepri
;
2170 case 19: /* FAULTMASK */
2171 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2172 case 20: /* CONTROL */
2173 return env
->v7m
.control
;
2175 /* ??? For debugging only. */
2176 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2181 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2185 xpsr_write(env
, val
, 0xf8000000);
2188 xpsr_write(env
, val
, 0xf8000000);
2191 xpsr_write(env
, val
, 0xfe00fc00);
2194 xpsr_write(env
, val
, 0xfe00fc00);
2197 /* IPSR bits are readonly. */
2200 xpsr_write(env
, val
, 0x0600fc00);
2203 xpsr_write(env
, val
, 0x0600fc00);
2206 if (env
->v7m
.current_sp
)
2207 env
->v7m
.other_sp
= val
;
2209 env
->regs
[13] = val
;
2212 if (env
->v7m
.current_sp
)
2213 env
->regs
[13] = val
;
2215 env
->v7m
.other_sp
= val
;
2217 case 16: /* PRIMASK */
2219 env
->uncached_cpsr
|= CPSR_I
;
2221 env
->uncached_cpsr
&= ~CPSR_I
;
2223 case 17: /* BASEPRI */
2224 env
->v7m
.basepri
= val
& 0xff;
2226 case 18: /* BASEPRI_MAX */
2228 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2229 env
->v7m
.basepri
= val
;
2231 case 19: /* FAULTMASK */
2233 env
->uncached_cpsr
|= CPSR_F
;
2235 env
->uncached_cpsr
&= ~CPSR_F
;
2237 case 20: /* CONTROL */
2238 env
->v7m
.control
= val
& 3;
2239 switch_v7m_sp(env
, (val
& 2) != 0);
2242 /* ??? For debugging only. */
2243 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2250 /* Note that signed overflow is undefined in C. The following routines are
2251 careful to use unsigned types where modulo arithmetic is required.
2252 Failure to do so _will_ break on newer gcc. */
2254 /* Signed saturating arithmetic. */
2256 /* Perform 16-bit signed saturating addition. */
2257 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2262 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2271 /* Perform 8-bit signed saturating addition. */
2272 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2277 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2286 /* Perform 16-bit signed saturating subtraction. */
2287 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2292 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2301 /* Perform 8-bit signed saturating subtraction. */
2302 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2307 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2316 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2317 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2318 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2319 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2322 #include "op_addsub.h"
2324 /* Unsigned saturating arithmetic. */
2325 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2334 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2342 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2351 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2359 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2360 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2361 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2362 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2365 #include "op_addsub.h"
2367 /* Signed modulo arithmetic. */
2368 #define SARITH16(a, b, n, op) do { \
2370 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2371 RESULT(sum, n, 16); \
2373 ge |= 3 << (n * 2); \
2376 #define SARITH8(a, b, n, op) do { \
2378 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2379 RESULT(sum, n, 8); \
2385 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2386 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2387 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2388 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2392 #include "op_addsub.h"
2394 /* Unsigned modulo arithmetic. */
2395 #define ADD16(a, b, n) do { \
2397 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2398 RESULT(sum, n, 16); \
2399 if ((sum >> 16) == 1) \
2400 ge |= 3 << (n * 2); \
2403 #define ADD8(a, b, n) do { \
2405 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2406 RESULT(sum, n, 8); \
2407 if ((sum >> 8) == 1) \
2411 #define SUB16(a, b, n) do { \
2413 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2414 RESULT(sum, n, 16); \
2415 if ((sum >> 16) == 0) \
2416 ge |= 3 << (n * 2); \
2419 #define SUB8(a, b, n) do { \
2421 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2422 RESULT(sum, n, 8); \
2423 if ((sum >> 8) == 0) \
2430 #include "op_addsub.h"
2432 /* Halved signed arithmetic. */
2433 #define ADD16(a, b, n) \
2434 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2435 #define SUB16(a, b, n) \
2436 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2437 #define ADD8(a, b, n) \
2438 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2439 #define SUB8(a, b, n) \
2440 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2443 #include "op_addsub.h"
2445 /* Halved unsigned arithmetic. */
2446 #define ADD16(a, b, n) \
2447 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2448 #define SUB16(a, b, n) \
2449 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2450 #define ADD8(a, b, n) \
2451 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2452 #define SUB8(a, b, n) \
2453 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2456 #include "op_addsub.h"
2458 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2466 /* Unsigned sum of absolute byte differences. */
2467 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2470 sum
= do_usad(a
, b
);
2471 sum
+= do_usad(a
>> 8, b
>> 8);
2472 sum
+= do_usad(a
>> 16, b
>>16);
2473 sum
+= do_usad(a
>> 24, b
>> 24);
2477 /* For ARMv6 SEL instruction. */
2478 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2491 return (a
& mask
) | (b
& ~mask
);
2494 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2496 return (val
>> 32) | (val
!= 0);
2499 /* VFP support. We follow the convention used for VFP instrunctions:
2500 Single precition routines have a "s" suffix, double precision a
2503 /* Convert host exception flags to vfp form. */
2504 static inline int vfp_exceptbits_from_host(int host_bits
)
2506 int target_bits
= 0;
2508 if (host_bits
& float_flag_invalid
)
2510 if (host_bits
& float_flag_divbyzero
)
2512 if (host_bits
& float_flag_overflow
)
2514 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2516 if (host_bits
& float_flag_inexact
)
2517 target_bits
|= 0x10;
2518 if (host_bits
& float_flag_input_denormal
)
2519 target_bits
|= 0x80;
2523 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2528 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2529 | (env
->vfp
.vec_len
<< 16)
2530 | (env
->vfp
.vec_stride
<< 20);
2531 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2532 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2533 fpscr
|= vfp_exceptbits_from_host(i
);
2537 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2539 return HELPER(vfp_get_fpscr
)(env
);
2542 /* Convert vfp exception flags to target form. */
2543 static inline int vfp_exceptbits_to_host(int target_bits
)
2547 if (target_bits
& 1)
2548 host_bits
|= float_flag_invalid
;
2549 if (target_bits
& 2)
2550 host_bits
|= float_flag_divbyzero
;
2551 if (target_bits
& 4)
2552 host_bits
|= float_flag_overflow
;
2553 if (target_bits
& 8)
2554 host_bits
|= float_flag_underflow
;
2555 if (target_bits
& 0x10)
2556 host_bits
|= float_flag_inexact
;
2557 if (target_bits
& 0x80)
2558 host_bits
|= float_flag_input_denormal
;
2562 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2567 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2568 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2569 env
->vfp
.vec_len
= (val
>> 16) & 7;
2570 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2573 if (changed
& (3 << 22)) {
2574 i
= (val
>> 22) & 3;
2577 i
= float_round_nearest_even
;
2583 i
= float_round_down
;
2586 i
= float_round_to_zero
;
2589 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2591 if (changed
& (1 << 24)) {
2592 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2593 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2595 if (changed
& (1 << 25))
2596 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2598 i
= vfp_exceptbits_to_host(val
);
2599 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2600 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2603 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2605 HELPER(vfp_set_fpscr
)(env
, val
);
2608 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2610 #define VFP_BINOP(name) \
2611 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2613 float_status *fpst = fpstp; \
2614 return float32_ ## name(a, b, fpst); \
2616 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2618 float_status *fpst = fpstp; \
2619 return float64_ ## name(a, b, fpst); \
2627 float32
VFP_HELPER(neg
, s
)(float32 a
)
2629 return float32_chs(a
);
2632 float64
VFP_HELPER(neg
, d
)(float64 a
)
2634 return float64_chs(a
);
2637 float32
VFP_HELPER(abs
, s
)(float32 a
)
2639 return float32_abs(a
);
2642 float64
VFP_HELPER(abs
, d
)(float64 a
)
2644 return float64_abs(a
);
2647 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2649 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2652 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2654 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2657 /* XXX: check quiet/signaling case */
2658 #define DO_VFP_cmp(p, type) \
2659 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2662 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2663 case 0: flags = 0x6; break; \
2664 case -1: flags = 0x8; break; \
2665 case 1: flags = 0x2; break; \
2666 default: case 2: flags = 0x3; break; \
2668 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2669 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2671 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2674 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2675 case 0: flags = 0x6; break; \
2676 case -1: flags = 0x8; break; \
2677 case 1: flags = 0x2; break; \
2678 default: case 2: flags = 0x3; break; \
2680 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2681 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2683 DO_VFP_cmp(s
, float32
)
2684 DO_VFP_cmp(d
, float64
)
2687 /* Integer to float and float to integer conversions */
2689 #define CONV_ITOF(name, fsz, sign) \
2690 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2692 float_status *fpst = fpstp; \
2693 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2696 #define CONV_FTOI(name, fsz, sign, round) \
2697 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2699 float_status *fpst = fpstp; \
2700 if (float##fsz##_is_any_nan(x)) { \
2701 float_raise(float_flag_invalid, fpst); \
2704 return float##fsz##_to_##sign##int32##round(x, fpst); \
2707 #define FLOAT_CONVS(name, p, fsz, sign) \
2708 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2709 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2710 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2712 FLOAT_CONVS(si
, s
, 32, )
2713 FLOAT_CONVS(si
, d
, 64, )
2714 FLOAT_CONVS(ui
, s
, 32, u
)
2715 FLOAT_CONVS(ui
, d
, 64, u
)
2721 /* floating point conversion */
2722 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2724 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2725 /* ARM requires that S<->D conversion of any kind of NaN generates
2726 * a quiet NaN by forcing the most significant frac bit to 1.
2728 return float64_maybe_silence_nan(r
);
2731 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2733 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2734 /* ARM requires that S<->D conversion of any kind of NaN generates
2735 * a quiet NaN by forcing the most significant frac bit to 1.
2737 return float32_maybe_silence_nan(r
);
2740 /* VFP3 fixed point conversion. */
2741 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2742 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2745 float_status *fpst = fpstp; \
2747 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2748 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2750 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2753 float_status *fpst = fpstp; \
2755 if (float##fsz##_is_any_nan(x)) { \
2756 float_raise(float_flag_invalid, fpst); \
2759 tmp = float##fsz##_scalbn(x, shift, fpst); \
2760 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2763 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2764 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2765 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2766 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2767 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2768 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2769 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2770 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2773 /* Half precision conversions. */
2774 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2776 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2777 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2779 return float32_maybe_silence_nan(r
);
2784 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2786 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2787 float16 r
= float32_to_float16(a
, ieee
, s
);
2789 r
= float16_maybe_silence_nan(r
);
2791 return float16_val(r
);
2794 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2796 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2799 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2801 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2804 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2806 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2809 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2811 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2814 #define float32_two make_float32(0x40000000)
2815 #define float32_three make_float32(0x40400000)
2816 #define float32_one_point_five make_float32(0x3fc00000)
2818 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2820 float_status
*s
= &env
->vfp
.standard_fp_status
;
2821 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2822 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2823 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2824 float_raise(float_flag_input_denormal
, s
);
2828 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2831 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2833 float_status
*s
= &env
->vfp
.standard_fp_status
;
2835 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2836 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2837 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2838 float_raise(float_flag_input_denormal
, s
);
2840 return float32_one_point_five
;
2842 product
= float32_mul(a
, b
, s
);
2843 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2848 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2849 * int->float conversions at run-time. */
2850 #define float64_256 make_float64(0x4070000000000000LL)
2851 #define float64_512 make_float64(0x4080000000000000LL)
2853 /* The algorithm that must be used to calculate the estimate
2854 * is specified by the ARM ARM.
2856 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2858 /* These calculations mustn't set any fp exception flags,
2859 * so we use a local copy of the fp_status.
2861 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2862 float_status
*s
= &dummy_status
;
2863 /* q = (int)(a * 512.0) */
2864 float64 q
= float64_mul(float64_512
, a
, s
);
2865 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2867 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2868 q
= int64_to_float64(q_int
, s
);
2869 q
= float64_add(q
, float64_half
, s
);
2870 q
= float64_div(q
, float64_512
, s
);
2871 q
= float64_div(float64_one
, q
, s
);
2873 /* s = (int)(256.0 * r + 0.5) */
2874 q
= float64_mul(q
, float64_256
, s
);
2875 q
= float64_add(q
, float64_half
, s
);
2876 q_int
= float64_to_int64_round_to_zero(q
, s
);
2878 /* return (double)s / 256.0 */
2879 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2882 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2884 float_status
*s
= &env
->vfp
.standard_fp_status
;
2886 uint32_t val32
= float32_val(a
);
2889 int a_exp
= (val32
& 0x7f800000) >> 23;
2890 int sign
= val32
& 0x80000000;
2892 if (float32_is_any_nan(a
)) {
2893 if (float32_is_signaling_nan(a
)) {
2894 float_raise(float_flag_invalid
, s
);
2896 return float32_default_nan
;
2897 } else if (float32_is_infinity(a
)) {
2898 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2899 } else if (float32_is_zero_or_denormal(a
)) {
2900 if (!float32_is_zero(a
)) {
2901 float_raise(float_flag_input_denormal
, s
);
2903 float_raise(float_flag_divbyzero
, s
);
2904 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2905 } else if (a_exp
>= 253) {
2906 float_raise(float_flag_underflow
, s
);
2907 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2910 f64
= make_float64((0x3feULL
<< 52)
2911 | ((int64_t)(val32
& 0x7fffff) << 29));
2913 result_exp
= 253 - a_exp
;
2915 f64
= recip_estimate(f64
, env
);
2918 | ((result_exp
& 0xff) << 23)
2919 | ((float64_val(f64
) >> 29) & 0x7fffff);
2920 return make_float32(val32
);
2923 /* The algorithm that must be used to calculate the estimate
2924 * is specified by the ARM ARM.
2926 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2928 /* These calculations mustn't set any fp exception flags,
2929 * so we use a local copy of the fp_status.
2931 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2932 float_status
*s
= &dummy_status
;
2936 if (float64_lt(a
, float64_half
, s
)) {
2937 /* range 0.25 <= a < 0.5 */
2939 /* a in units of 1/512 rounded down */
2940 /* q0 = (int)(a * 512.0); */
2941 q
= float64_mul(float64_512
, a
, s
);
2942 q_int
= float64_to_int64_round_to_zero(q
, s
);
2944 /* reciprocal root r */
2945 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2946 q
= int64_to_float64(q_int
, s
);
2947 q
= float64_add(q
, float64_half
, s
);
2948 q
= float64_div(q
, float64_512
, s
);
2949 q
= float64_sqrt(q
, s
);
2950 q
= float64_div(float64_one
, q
, s
);
2952 /* range 0.5 <= a < 1.0 */
2954 /* a in units of 1/256 rounded down */
2955 /* q1 = (int)(a * 256.0); */
2956 q
= float64_mul(float64_256
, a
, s
);
2957 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2959 /* reciprocal root r */
2960 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2961 q
= int64_to_float64(q_int
, s
);
2962 q
= float64_add(q
, float64_half
, s
);
2963 q
= float64_div(q
, float64_256
, s
);
2964 q
= float64_sqrt(q
, s
);
2965 q
= float64_div(float64_one
, q
, s
);
2967 /* r in units of 1/256 rounded to nearest */
2968 /* s = (int)(256.0 * r + 0.5); */
2970 q
= float64_mul(q
, float64_256
,s
);
2971 q
= float64_add(q
, float64_half
, s
);
2972 q_int
= float64_to_int64_round_to_zero(q
, s
);
2974 /* return (double)s / 256.0;*/
2975 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2978 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
2980 float_status
*s
= &env
->vfp
.standard_fp_status
;
2986 val
= float32_val(a
);
2988 if (float32_is_any_nan(a
)) {
2989 if (float32_is_signaling_nan(a
)) {
2990 float_raise(float_flag_invalid
, s
);
2992 return float32_default_nan
;
2993 } else if (float32_is_zero_or_denormal(a
)) {
2994 if (!float32_is_zero(a
)) {
2995 float_raise(float_flag_input_denormal
, s
);
2997 float_raise(float_flag_divbyzero
, s
);
2998 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2999 } else if (float32_is_neg(a
)) {
3000 float_raise(float_flag_invalid
, s
);
3001 return float32_default_nan
;
3002 } else if (float32_is_infinity(a
)) {
3003 return float32_zero
;
3006 /* Normalize to a double-precision value between 0.25 and 1.0,
3007 * preserving the parity of the exponent. */
3008 if ((val
& 0x800000) == 0) {
3009 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3011 | ((uint64_t)(val
& 0x7fffff) << 29));
3013 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3015 | ((uint64_t)(val
& 0x7fffff) << 29));
3018 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3020 f64
= recip_sqrt_estimate(f64
, env
);
3022 val64
= float64_val(f64
);
3024 val
= ((result_exp
& 0xff) << 23)
3025 | ((val64
>> 29) & 0x7fffff);
3026 return make_float32(val
);
3029 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3033 if ((a
& 0x80000000) == 0) {
3037 f64
= make_float64((0x3feULL
<< 52)
3038 | ((int64_t)(a
& 0x7fffffff) << 21));
3040 f64
= recip_estimate (f64
, env
);
3042 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3045 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3049 if ((a
& 0xc0000000) == 0) {
3053 if (a
& 0x80000000) {
3054 f64
= make_float64((0x3feULL
<< 52)
3055 | ((uint64_t)(a
& 0x7fffffff) << 21));
3056 } else { /* bits 31-30 == '01' */
3057 f64
= make_float64((0x3fdULL
<< 52)
3058 | ((uint64_t)(a
& 0x3fffffff) << 22));
3061 f64
= recip_sqrt_estimate(f64
, env
);
3063 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3066 /* VFPv4 fused multiply-accumulate */
3067 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3069 float_status
*fpst
= fpstp
;
3070 return float32_muladd(a
, b
, c
, 0, fpst
);
3073 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3075 float_status
*fpst
= fpstp
;
3076 return float64_muladd(a
, b
, c
, 0, fpst
);