4 #include "host-utils.h"
7 #ifndef CONFIG_USER_ONLY
8 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
9 int access_type
, int is_user
,
10 uint32_t *phys_ptr
, int *prot
,
11 target_ulong
*page_size
);
14 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
18 /* VFP data registers are always little-endian. */
19 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
21 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
24 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
25 /* Aliases for Q regs. */
28 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
29 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
33 switch (reg
- nregs
) {
34 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
35 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
36 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
41 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
53 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
54 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
58 switch (reg
- nregs
) {
59 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
60 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
61 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
66 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
69 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
73 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
75 if (env
->cp15
.c13_fcse
!= value
) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
80 env
->cp15
.c13_fcse
= value
;
84 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
94 env
->cp15
.c13_context
= value
;
98 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Invalidate all (TLBIALL) */
106 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
114 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env
, value
== 0);
122 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
130 static const ARMCPRegInfo cp_reginfo
[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
135 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
136 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
137 /* MMU Domain access control / MPU write buffer control */
138 { .name
= "DACR", .cp
= 15,
139 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
140 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
141 .resetvalue
= 0, .writefn
= dacr_write
},
142 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
143 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
144 .resetvalue
= 0, .writefn
= fcse_write
},
145 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
147 .resetvalue
= 0, .writefn
= contextidr_write
},
148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
152 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
157 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
158 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
159 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
160 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
161 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
162 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
163 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
166 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
167 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
171 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
175 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
176 .access
= PL1_W
, .type
= ARM_CP_WFI
},
180 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
185 .access
= PL1_W
, .type
= ARM_CP_WFI
},
186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
190 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
191 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
193 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
194 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
199 static const ARMCPRegInfo v6_cp_reginfo
[] = {
200 /* prefetch by MVA in v6, NOP in v7 */
201 { .name
= "MVA_prefetch",
202 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
203 .access
= PL1_W
, .type
= ARM_CP_NOP
},
204 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
205 .access
= PL0_W
, .type
= ARM_CP_NOP
},
206 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
207 .access
= PL0_W
, .type
= ARM_CP_NOP
},
208 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
209 .access
= PL0_W
, .type
= ARM_CP_NOP
},
210 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
211 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
213 /* Watchpoint Fault Address Register : should actually only be present
214 * for 1136, 1176, 11MPCore.
216 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
217 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
221 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
224 /* Generic performance monitor register read function for where
225 * user access may be allowed by PMUSERENR.
227 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
230 *value
= CPREG_FIELD32(env
, ri
);
234 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
237 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
240 /* only the DP, X, D and E bits are writable */
241 env
->cp15
.c9_pmcr
&= ~0x39;
242 env
->cp15
.c9_pmcr
|= (value
& 0x39);
246 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
249 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
253 env
->cp15
.c9_pmcnten
|= value
;
257 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
260 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
264 env
->cp15
.c9_pmcnten
&= ~value
;
268 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
271 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
274 env
->cp15
.c9_pmovsr
&= ~value
;
278 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
281 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
284 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
288 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
291 env
->cp15
.c9_pmuserenr
= value
& 1;
295 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
298 /* We have no event counters so only the C bit can be changed */
300 env
->cp15
.c9_pminten
|= value
;
304 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
308 env
->cp15
.c9_pminten
&= ~value
;
312 static const ARMCPRegInfo v7_cp_reginfo
[] = {
313 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
316 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
317 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
318 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
319 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
320 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
321 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
322 .access
= PL1_W
, .type
= ARM_CP_NOP
},
323 /* Performance monitors are implementation defined in v7,
324 * but with an ARM recommended set of registers, which we
325 * follow (although we don't actually implement any counters)
327 * Performance registers fall into three categories:
328 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
329 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
330 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
331 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
332 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
334 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
335 .access
= PL0_RW
, .resetvalue
= 0,
336 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
337 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
338 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
339 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
340 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
341 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
342 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
343 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
344 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
347 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
348 .access
= PL0_W
, .type
= ARM_CP_NOP
},
349 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
350 * We choose to RAZ/WI. XXX should respect PMUSERENR.
352 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
353 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
354 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
355 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
356 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
357 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
359 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
360 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
361 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
362 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
363 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
364 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
365 .access
= PL0_R
| PL1_RW
,
366 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
368 .writefn
= pmuserenr_write
},
369 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
371 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
373 .writefn
= pmintenset_write
},
374 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
376 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
378 .writefn
= pmintenclr_write
},
382 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
389 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
392 /* This is a helper function because the user access rights
393 * depend on the value of the TEECR.
395 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
398 *value
= env
->teehbr
;
402 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
405 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
412 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
413 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
414 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
416 .writefn
= teecr_write
},
417 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
418 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
420 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
424 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
425 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
427 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
429 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
430 .access
= PL0_R
|PL1_W
,
431 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
433 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
435 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
440 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
441 /* Dummy implementation: RAZ/WI the whole crn=14 space */
442 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
443 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
444 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
448 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
450 if (arm_feature(env
, ARM_FEATURE_V7
)) {
451 env
->cp15
.c7_par
= value
& 0xfffff6ff;
453 env
->cp15
.c7_par
= value
& 0xfffff1ff;
458 #ifndef CONFIG_USER_ONLY
459 /* get_phys_addr() isn't present for user-mode-only targets */
460 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
463 target_ulong page_size
;
465 int ret
, is_user
= ri
->opc2
& 2;
466 int access_type
= ri
->opc2
& 1;
469 /* Other states are only available with TrustZone */
472 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
473 &phys_addr
, &prot
, &page_size
);
475 /* We do not set any attribute bits in the PAR */
476 if (page_size
== (1 << 24)
477 && arm_feature(env
, ARM_FEATURE_V7
)) {
478 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
480 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
483 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
484 ((ret
& (12 << 1)) >> 6) |
485 ((ret
& 0xf) << 1) | 1;
491 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
492 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
493 .access
= PL1_RW
, .resetvalue
= 0,
494 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
495 .writefn
= par_write
},
496 #ifndef CONFIG_USER_ONLY
497 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
498 .access
= PL1_W
, .writefn
= ats_write
},
503 /* Return basic MPU access permission bits. */
504 static uint32_t simple_mpu_ap_bits(uint32_t val
)
511 for (i
= 0; i
< 16; i
+= 2) {
512 ret
|= (val
>> i
) & mask
;
518 /* Pad basic MPU access permission bits to extended format. */
519 static uint32_t extended_mpu_ap_bits(uint32_t val
)
526 for (i
= 0; i
< 16; i
+= 2) {
527 ret
|= (val
& mask
) << i
;
533 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
536 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
540 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
547 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
554 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
557 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
561 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 *value
= env
->cp15
.c6_region
[ri
->crm
];
571 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
577 env
->cp15
.c6_region
[ri
->crm
] = value
;
581 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
582 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
584 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
585 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
586 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
588 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
589 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
590 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
592 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
593 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
595 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
596 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
598 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
599 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
601 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
602 /* Protection region base and size registers */
603 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
604 .opc2
= CP_ANY
, .access
= PL1_RW
,
605 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
609 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
613 env
->cp15
.c2_control
= value
;
614 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
615 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
619 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
621 env
->cp15
.c2_base_mask
= 0xffffc000u
;
622 env
->cp15
.c2_control
= 0;
623 env
->cp15
.c2_mask
= 0;
626 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
627 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
629 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
630 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
633 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
635 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
636 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
638 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
639 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
640 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
641 .resetfn
= vmsa_ttbcr_reset
,
642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
643 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
644 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
649 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
652 env
->cp15
.c15_ticonfig
= value
& 0xe7;
653 /* The OS_TYPE bit in this register changes the reported CPUID! */
654 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
655 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
659 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
662 env
->cp15
.c15_threadid
= value
& 0xffff;
666 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
669 /* Wait-for-interrupt (deprecated) */
670 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
674 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
677 /* On OMAP there are registers indicating the max/min index of dcache lines
678 * containing a dirty line; cache flush operations have to reset these.
680 env
->cp15
.c15_i_max
= 0x000;
681 env
->cp15
.c15_i_min
= 0xff0;
685 static const ARMCPRegInfo omap_cp_reginfo
[] = {
686 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
687 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
688 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
689 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
690 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
691 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
693 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
694 .writefn
= omap_ticonfig_write
},
695 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
697 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
698 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
699 .access
= PL1_RW
, .resetvalue
= 0xff0,
700 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
701 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
703 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
704 .writefn
= omap_threadid_write
},
705 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
706 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
707 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
708 /* TODO: Peripheral port remap register:
709 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
710 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
713 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
714 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
715 .writefn
= omap_cachemaint_write
},
716 { .name
= "C9", .cp
= 15, .crn
= 9,
717 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
718 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
722 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
726 if (env
->cp15
.c15_cpar
!= value
) {
727 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
729 env
->cp15
.c15_cpar
= value
;
734 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
735 { .name
= "XSCALE_CPAR",
736 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
738 .writefn
= xscale_cpar_write
, },
742 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
743 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
744 * implementation of this implementation-defined space.
745 * Ideally this should eventually disappear in favour of actually
746 * implementing the correct behaviour for all cores.
748 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
749 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
750 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
754 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
755 /* Cache status: RAZ because we have no cache so it's always clean */
756 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
757 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
761 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
762 /* We never have a a block transfer operation in progress */
763 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
764 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
768 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
769 /* The cache test-and-clean instructions always return (1 << 30)
770 * to indicate that there are no dirty cache lines.
772 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
773 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
774 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
775 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
779 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
780 /* Ignore ReadBuffer accesses */
781 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
782 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
783 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
788 void register_cp_regs_for_features(ARMCPU
*cpu
)
790 /* Register all the coprocessor registers based on feature bits */
791 CPUARMState
*env
= &cpu
->env
;
792 if (arm_feature(env
, ARM_FEATURE_M
)) {
793 /* M profile has no coprocessor registers */
797 define_arm_cp_regs(cpu
, cp_reginfo
);
798 if (arm_feature(env
, ARM_FEATURE_V6
)) {
799 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
801 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
803 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
804 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
806 if (arm_feature(env
, ARM_FEATURE_V7
)) {
807 /* v7 performance monitor control register: same implementor
808 * field as main ID register, and we implement no event counters.
810 ARMCPRegInfo pmcr
= {
811 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
812 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
813 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
814 .readfn
= pmreg_read
, .writefn
= pmcr_write
816 define_one_arm_cp_reg(cpu
, &pmcr
);
817 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
819 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
821 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
822 /* These are the MPU registers prior to PMSAv6. Any new
823 * PMSA core later than the ARM946 will require that we
824 * implement the PMSAv6 or PMSAv7 registers, which are
825 * completely different.
827 assert(!arm_feature(env
, ARM_FEATURE_V6
));
828 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
830 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
832 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
833 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
835 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
836 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
838 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
839 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
841 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
842 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
844 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
845 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
847 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
848 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
850 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
851 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
853 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
854 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
856 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
857 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
859 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
860 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
864 ARMCPU
*cpu_arm_init(const char *cpu_model
)
868 static int inited
= 0;
870 if (!object_class_by_name(cpu_model
)) {
873 cpu
= ARM_CPU(object_new(cpu_model
));
875 env
->cpu_model_str
= cpu_model
;
876 arm_cpu_realize(cpu
);
878 if (tcg_enabled() && !inited
) {
880 arm_translate_init();
884 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
885 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
886 51, "arm-neon.xml", 0);
887 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
888 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
889 35, "arm-vfp3.xml", 0);
890 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
891 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
892 19, "arm-vfp.xml", 0);
898 typedef struct ARMCPUListState
{
899 fprintf_function cpu_fprintf
;
903 /* Sort alphabetically by type name, except for "any". */
904 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
906 ObjectClass
*class_a
= (ObjectClass
*)a
;
907 ObjectClass
*class_b
= (ObjectClass
*)b
;
908 const char *name_a
, *name_b
;
910 name_a
= object_class_get_name(class_a
);
911 name_b
= object_class_get_name(class_b
);
912 if (strcmp(name_a
, "any") == 0) {
914 } else if (strcmp(name_b
, "any") == 0) {
917 return strcmp(name_a
, name_b
);
921 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
923 ObjectClass
*oc
= data
;
924 ARMCPUListState
*s
= user_data
;
926 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
927 object_class_get_name(oc
));
930 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
932 ARMCPUListState s
= {
934 .cpu_fprintf
= cpu_fprintf
,
938 list
= object_class_get_list(TYPE_ARM_CPU
, false);
939 list
= g_slist_sort(list
, arm_cpu_list_compare
);
940 (*cpu_fprintf
)(f
, "Available CPUs:\n");
941 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
945 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
946 const ARMCPRegInfo
*r
, void *opaque
)
948 /* Define implementations of coprocessor registers.
949 * We store these in a hashtable because typically
950 * there are less than 150 registers in a space which
951 * is 16*16*16*8*8 = 262144 in size.
952 * Wildcarding is supported for the crm, opc1 and opc2 fields.
953 * If a register is defined twice then the second definition is
954 * used, so this can be used to define some generic registers and
955 * then override them with implementation specific variations.
956 * At least one of the original and the second definition should
957 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
958 * against accidental use.
961 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
962 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
963 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
964 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
965 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
966 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
967 /* 64 bit registers have only CRm and Opc1 fields */
968 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
969 /* Check that the register definition has enough info to handle
970 * reads and writes if they are permitted.
972 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
973 if (r
->access
& PL3_R
) {
974 assert(r
->fieldoffset
|| r
->readfn
);
976 if (r
->access
& PL3_W
) {
977 assert(r
->fieldoffset
|| r
->writefn
);
980 /* Bad type field probably means missing sentinel at end of reg list */
981 assert(cptype_valid(r
->type
));
982 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
983 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
984 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
985 uint32_t *key
= g_new(uint32_t, 1);
986 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
987 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
988 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
990 /* Make sure reginfo passed to helpers for wildcarded regs
991 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
996 /* Overriding of an existing definition must be explicitly
999 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1000 ARMCPRegInfo
*oldreg
;
1001 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1002 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1003 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1004 "crn=%d crm=%d opc1=%d opc2=%d, "
1005 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1006 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1007 oldreg
->name
, r2
->name
);
1011 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1017 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1018 const ARMCPRegInfo
*regs
, void *opaque
)
1020 /* Define a whole list of registers */
1021 const ARMCPRegInfo
*r
;
1022 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1023 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1027 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1029 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1032 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1035 /* Helper coprocessor write function for write-ignore registers */
1039 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1041 /* Helper coprocessor write function for read-as-zero registers */
1046 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1048 /* Return true if it is not valid for us to switch to
1049 * this CPU mode (ie all the UNPREDICTABLE cases in
1050 * the ARM ARM CPSRWriteByInstr pseudocode).
1053 case ARM_CPU_MODE_USR
:
1054 case ARM_CPU_MODE_SYS
:
1055 case ARM_CPU_MODE_SVC
:
1056 case ARM_CPU_MODE_ABT
:
1057 case ARM_CPU_MODE_UND
:
1058 case ARM_CPU_MODE_IRQ
:
1059 case ARM_CPU_MODE_FIQ
:
1066 uint32_t cpsr_read(CPUARMState
*env
)
1069 ZF
= (env
->ZF
== 0);
1070 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1071 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1072 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1073 | ((env
->condexec_bits
& 0xfc) << 8)
1077 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1079 if (mask
& CPSR_NZCV
) {
1080 env
->ZF
= (~val
) & CPSR_Z
;
1082 env
->CF
= (val
>> 29) & 1;
1083 env
->VF
= (val
<< 3) & 0x80000000;
1086 env
->QF
= ((val
& CPSR_Q
) != 0);
1088 env
->thumb
= ((val
& CPSR_T
) != 0);
1089 if (mask
& CPSR_IT_0_1
) {
1090 env
->condexec_bits
&= ~3;
1091 env
->condexec_bits
|= (val
>> 25) & 3;
1093 if (mask
& CPSR_IT_2_7
) {
1094 env
->condexec_bits
&= 3;
1095 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1097 if (mask
& CPSR_GE
) {
1098 env
->GE
= (val
>> 16) & 0xf;
1101 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1102 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1103 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1104 * We choose to ignore the attempt and leave the CPSR M field
1109 switch_mode(env
, val
& CPSR_M
);
1112 mask
&= ~CACHED_CPSR_BITS
;
1113 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1116 /* Sign/zero extend */
1117 uint32_t HELPER(sxtb16
)(uint32_t x
)
1120 res
= (uint16_t)(int8_t)x
;
1121 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1125 uint32_t HELPER(uxtb16
)(uint32_t x
)
1128 res
= (uint16_t)(uint8_t)x
;
1129 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1133 uint32_t HELPER(clz
)(uint32_t x
)
1138 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1142 if (num
== INT_MIN
&& den
== -1)
1147 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1154 uint32_t HELPER(rbit
)(uint32_t x
)
1156 x
= ((x
& 0xff000000) >> 24)
1157 | ((x
& 0x00ff0000) >> 8)
1158 | ((x
& 0x0000ff00) << 8)
1159 | ((x
& 0x000000ff) << 24);
1160 x
= ((x
& 0xf0f0f0f0) >> 4)
1161 | ((x
& 0x0f0f0f0f) << 4);
1162 x
= ((x
& 0x88888888) >> 3)
1163 | ((x
& 0x44444444) >> 1)
1164 | ((x
& 0x22222222) << 1)
1165 | ((x
& 0x11111111) << 3);
1169 uint32_t HELPER(abs
)(uint32_t x
)
1171 return ((int32_t)x
< 0) ? -x
: x
;
1174 #if defined(CONFIG_USER_ONLY)
1176 void do_interrupt (CPUARMState
*env
)
1178 env
->exception_index
= -1;
1181 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1185 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1186 env
->cp15
.c6_insn
= address
;
1188 env
->exception_index
= EXCP_DATA_ABORT
;
1189 env
->cp15
.c6_data
= address
;
1194 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1196 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1199 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1201 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1204 /* These should probably raise undefined insn exceptions. */
1205 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1207 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1210 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1212 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1216 void switch_mode(CPUARMState
*env
, int mode
)
1218 if (mode
!= ARM_CPU_MODE_USR
)
1219 cpu_abort(env
, "Tried to switch out of user mode\n");
1222 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1224 cpu_abort(env
, "banked r13 write\n");
1227 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1229 cpu_abort(env
, "banked r13 read\n");
1235 /* Map CPU modes onto saved register banks. */
1236 static inline int bank_number(CPUARMState
*env
, int mode
)
1239 case ARM_CPU_MODE_USR
:
1240 case ARM_CPU_MODE_SYS
:
1242 case ARM_CPU_MODE_SVC
:
1244 case ARM_CPU_MODE_ABT
:
1246 case ARM_CPU_MODE_UND
:
1248 case ARM_CPU_MODE_IRQ
:
1250 case ARM_CPU_MODE_FIQ
:
1253 cpu_abort(env
, "Bad mode %x\n", mode
);
1257 void switch_mode(CPUARMState
*env
, int mode
)
1262 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1263 if (mode
== old_mode
)
1266 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1267 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1268 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1269 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1270 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1271 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1274 i
= bank_number(env
, old_mode
);
1275 env
->banked_r13
[i
] = env
->regs
[13];
1276 env
->banked_r14
[i
] = env
->regs
[14];
1277 env
->banked_spsr
[i
] = env
->spsr
;
1279 i
= bank_number(env
, mode
);
1280 env
->regs
[13] = env
->banked_r13
[i
];
1281 env
->regs
[14] = env
->banked_r14
[i
];
1282 env
->spsr
= env
->banked_spsr
[i
];
1285 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1288 stl_phys(env
->regs
[13], val
);
1291 static uint32_t v7m_pop(CPUARMState
*env
)
1294 val
= ldl_phys(env
->regs
[13]);
1299 /* Switch to V7M main or process stack pointer. */
1300 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1303 if (env
->v7m
.current_sp
!= process
) {
1304 tmp
= env
->v7m
.other_sp
;
1305 env
->v7m
.other_sp
= env
->regs
[13];
1306 env
->regs
[13] = tmp
;
1307 env
->v7m
.current_sp
= process
;
1311 static void do_v7m_exception_exit(CPUARMState
*env
)
1316 type
= env
->regs
[15];
1317 if (env
->v7m
.exception
!= 0)
1318 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1320 /* Switch to the target stack. */
1321 switch_v7m_sp(env
, (type
& 4) != 0);
1322 /* Pop registers. */
1323 env
->regs
[0] = v7m_pop(env
);
1324 env
->regs
[1] = v7m_pop(env
);
1325 env
->regs
[2] = v7m_pop(env
);
1326 env
->regs
[3] = v7m_pop(env
);
1327 env
->regs
[12] = v7m_pop(env
);
1328 env
->regs
[14] = v7m_pop(env
);
1329 env
->regs
[15] = v7m_pop(env
);
1330 xpsr
= v7m_pop(env
);
1331 xpsr_write(env
, xpsr
, 0xfffffdff);
1332 /* Undo stack alignment. */
1335 /* ??? The exception return type specifies Thread/Handler mode. However
1336 this is also implied by the xPSR value. Not sure what to do
1337 if there is a mismatch. */
1338 /* ??? Likewise for mismatches between the CONTROL register and the stack
1342 static void do_interrupt_v7m(CPUARMState
*env
)
1344 uint32_t xpsr
= xpsr_read(env
);
1349 if (env
->v7m
.current_sp
)
1351 if (env
->v7m
.exception
== 0)
1354 /* For exceptions we just mark as pending on the NVIC, and let that
1356 /* TODO: Need to escalate if the current priority is higher than the
1357 one we're raising. */
1358 switch (env
->exception_index
) {
1360 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1364 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1366 case EXCP_PREFETCH_ABORT
:
1367 case EXCP_DATA_ABORT
:
1368 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1371 if (semihosting_enabled
) {
1373 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1376 env
->regs
[0] = do_arm_semihosting(env
);
1380 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1383 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1385 case EXCP_EXCEPTION_EXIT
:
1386 do_v7m_exception_exit(env
);
1389 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1390 return; /* Never happens. Keep compiler happy. */
1393 /* Align stack pointer. */
1394 /* ??? Should only do this if Configuration Control Register
1395 STACKALIGN bit is set. */
1396 if (env
->regs
[13] & 4) {
1400 /* Switch to the handler mode. */
1401 v7m_push(env
, xpsr
);
1402 v7m_push(env
, env
->regs
[15]);
1403 v7m_push(env
, env
->regs
[14]);
1404 v7m_push(env
, env
->regs
[12]);
1405 v7m_push(env
, env
->regs
[3]);
1406 v7m_push(env
, env
->regs
[2]);
1407 v7m_push(env
, env
->regs
[1]);
1408 v7m_push(env
, env
->regs
[0]);
1409 switch_v7m_sp(env
, 0);
1411 env
->condexec_bits
= 0;
1413 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1414 env
->regs
[15] = addr
& 0xfffffffe;
1415 env
->thumb
= addr
& 1;
1418 /* Handle a CPU exception. */
1419 void do_interrupt(CPUARMState
*env
)
1427 do_interrupt_v7m(env
);
1430 /* TODO: Vectored interrupt controller. */
1431 switch (env
->exception_index
) {
1433 new_mode
= ARM_CPU_MODE_UND
;
1442 if (semihosting_enabled
) {
1443 /* Check for semihosting interrupt. */
1445 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1447 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1450 /* Only intercept calls from privileged modes, to provide some
1451 semblance of security. */
1452 if (((mask
== 0x123456 && !env
->thumb
)
1453 || (mask
== 0xab && env
->thumb
))
1454 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1455 env
->regs
[0] = do_arm_semihosting(env
);
1459 new_mode
= ARM_CPU_MODE_SVC
;
1462 /* The PC already points to the next instruction. */
1466 /* See if this is a semihosting syscall. */
1467 if (env
->thumb
&& semihosting_enabled
) {
1468 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1470 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1472 env
->regs
[0] = do_arm_semihosting(env
);
1476 env
->cp15
.c5_insn
= 2;
1477 /* Fall through to prefetch abort. */
1478 case EXCP_PREFETCH_ABORT
:
1479 new_mode
= ARM_CPU_MODE_ABT
;
1481 mask
= CPSR_A
| CPSR_I
;
1484 case EXCP_DATA_ABORT
:
1485 new_mode
= ARM_CPU_MODE_ABT
;
1487 mask
= CPSR_A
| CPSR_I
;
1491 new_mode
= ARM_CPU_MODE_IRQ
;
1493 /* Disable IRQ and imprecise data aborts. */
1494 mask
= CPSR_A
| CPSR_I
;
1498 new_mode
= ARM_CPU_MODE_FIQ
;
1500 /* Disable FIQ, IRQ and imprecise data aborts. */
1501 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1505 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1506 return; /* Never happens. Keep compiler happy. */
1509 if (env
->cp15
.c1_sys
& (1 << 13)) {
1512 switch_mode (env
, new_mode
);
1513 env
->spsr
= cpsr_read(env
);
1514 /* Clear IT bits. */
1515 env
->condexec_bits
= 0;
1516 /* Switch to the new mode, and to the correct instruction set. */
1517 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1518 env
->uncached_cpsr
|= mask
;
1519 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1520 * and we should just guard the thumb mode on V4 */
1521 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1522 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1524 env
->regs
[14] = env
->regs
[15] + offset
;
1525 env
->regs
[15] = addr
;
1526 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1529 /* Check section/page access permissions.
1530 Returns the page protection flags, or zero if the access is not
1532 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1533 int access_type
, int is_user
)
1537 if (domain_prot
== 3) {
1538 return PAGE_READ
| PAGE_WRITE
;
1541 if (access_type
== 1)
1544 prot_ro
= PAGE_READ
;
1548 if (access_type
== 1)
1550 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1552 return is_user
? 0 : PAGE_READ
;
1559 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1564 return PAGE_READ
| PAGE_WRITE
;
1566 return PAGE_READ
| PAGE_WRITE
;
1567 case 4: /* Reserved. */
1570 return is_user
? 0 : prot_ro
;
1574 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1582 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1586 if (address
& env
->cp15
.c2_mask
)
1587 table
= env
->cp15
.c2_base1
& 0xffffc000;
1589 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1591 table
|= (address
>> 18) & 0x3ffc;
1595 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1596 int is_user
, uint32_t *phys_ptr
, int *prot
,
1597 target_ulong
*page_size
)
1608 /* Pagetable walk. */
1609 /* Lookup l1 descriptor. */
1610 table
= get_level1_table_address(env
, address
);
1611 desc
= ldl_phys(table
);
1613 domain
= (desc
>> 5) & 0x0f;
1614 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1616 /* Section translation fault. */
1620 if (domain_prot
== 0 || domain_prot
== 2) {
1622 code
= 9; /* Section domain fault. */
1624 code
= 11; /* Page domain fault. */
1629 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1630 ap
= (desc
>> 10) & 3;
1632 *page_size
= 1024 * 1024;
1634 /* Lookup l2 entry. */
1636 /* Coarse pagetable. */
1637 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1639 /* Fine pagetable. */
1640 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1642 desc
= ldl_phys(table
);
1644 case 0: /* Page translation fault. */
1647 case 1: /* 64k page. */
1648 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1649 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1650 *page_size
= 0x10000;
1652 case 2: /* 4k page. */
1653 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1654 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1655 *page_size
= 0x1000;
1657 case 3: /* 1k page. */
1659 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1660 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1662 /* Page translation fault. */
1667 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1669 ap
= (desc
>> 4) & 3;
1673 /* Never happens, but compiler isn't smart enough to tell. */
1678 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1680 /* Access permission fault. */
1684 *phys_ptr
= phys_addr
;
1687 return code
| (domain
<< 4);
1690 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1691 int is_user
, uint32_t *phys_ptr
, int *prot
,
1692 target_ulong
*page_size
)
1704 /* Pagetable walk. */
1705 /* Lookup l1 descriptor. */
1706 table
= get_level1_table_address(env
, address
);
1707 desc
= ldl_phys(table
);
1710 /* Section translation fault. */
1714 } else if (type
== 2 && (desc
& (1 << 18))) {
1718 /* Section or page. */
1719 domain
= (desc
>> 5) & 0x0f;
1721 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1722 if (domain_prot
== 0 || domain_prot
== 2) {
1724 code
= 9; /* Section domain fault. */
1726 code
= 11; /* Page domain fault. */
1730 if (desc
& (1 << 18)) {
1732 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1733 *page_size
= 0x1000000;
1736 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1737 *page_size
= 0x100000;
1739 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1740 xn
= desc
& (1 << 4);
1743 /* Lookup l2 entry. */
1744 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1745 desc
= ldl_phys(table
);
1746 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1748 case 0: /* Page translation fault. */
1751 case 1: /* 64k page. */
1752 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1753 xn
= desc
& (1 << 15);
1754 *page_size
= 0x10000;
1756 case 2: case 3: /* 4k page. */
1757 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1759 *page_size
= 0x1000;
1762 /* Never happens, but compiler isn't smart enough to tell. */
1767 if (domain_prot
== 3) {
1768 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1770 if (xn
&& access_type
== 2)
1773 /* The simplified model uses AP[0] as an access control bit. */
1774 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1775 /* Access flag fault. */
1776 code
= (code
== 15) ? 6 : 3;
1779 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1781 /* Access permission fault. */
1788 *phys_ptr
= phys_addr
;
1791 return code
| (domain
<< 4);
1794 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1795 int is_user
, uint32_t *phys_ptr
, int *prot
)
1801 *phys_ptr
= address
;
1802 for (n
= 7; n
>= 0; n
--) {
1803 base
= env
->cp15
.c6_region
[n
];
1804 if ((base
& 1) == 0)
1806 mask
= 1 << ((base
>> 1) & 0x1f);
1807 /* Keep this shift separate from the above to avoid an
1808 (undefined) << 32. */
1809 mask
= (mask
<< 1) - 1;
1810 if (((base
^ address
) & ~mask
) == 0)
1816 if (access_type
== 2) {
1817 mask
= env
->cp15
.c5_insn
;
1819 mask
= env
->cp15
.c5_data
;
1821 mask
= (mask
>> (n
* 4)) & 0xf;
1828 *prot
= PAGE_READ
| PAGE_WRITE
;
1833 *prot
|= PAGE_WRITE
;
1836 *prot
= PAGE_READ
| PAGE_WRITE
;
1847 /* Bad permission. */
1854 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1855 int access_type
, int is_user
,
1856 uint32_t *phys_ptr
, int *prot
,
1857 target_ulong
*page_size
)
1859 /* Fast Context Switch Extension. */
1860 if (address
< 0x02000000)
1861 address
+= env
->cp15
.c13_fcse
;
1863 if ((env
->cp15
.c1_sys
& 1) == 0) {
1864 /* MMU/MPU disabled. */
1865 *phys_ptr
= address
;
1866 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1867 *page_size
= TARGET_PAGE_SIZE
;
1869 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1870 *page_size
= TARGET_PAGE_SIZE
;
1871 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1873 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1874 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1877 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1882 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1883 int access_type
, int mmu_idx
)
1886 target_ulong page_size
;
1890 is_user
= mmu_idx
== MMU_USER_IDX
;
1891 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1894 /* Map a single [sub]page. */
1895 phys_addr
&= ~(uint32_t)0x3ff;
1896 address
&= ~(uint32_t)0x3ff;
1897 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1901 if (access_type
== 2) {
1902 env
->cp15
.c5_insn
= ret
;
1903 env
->cp15
.c6_insn
= address
;
1904 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1906 env
->cp15
.c5_data
= ret
;
1907 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1908 env
->cp15
.c5_data
|= (1 << 11);
1909 env
->cp15
.c6_data
= address
;
1910 env
->exception_index
= EXCP_DATA_ABORT
;
1915 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1918 target_ulong page_size
;
1922 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1930 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1936 op1
= (insn
>> 21) & 7;
1937 op2
= (insn
>> 5) & 7;
1939 switch ((insn
>> 16) & 0xf) {
1942 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1944 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1946 if (arm_feature(env
, ARM_FEATURE_V7
)
1947 && op1
== 2 && crm
== 0 && op2
== 0) {
1948 env
->cp15
.c0_cssel
= val
& 0xf;
1952 case 1: /* System configuration. */
1953 if (arm_feature(env
, ARM_FEATURE_V7
)
1954 && op1
== 0 && crm
== 1 && op2
== 0) {
1955 env
->cp15
.c1_scr
= val
;
1958 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1962 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1963 env
->cp15
.c1_sys
= val
;
1964 /* ??? Lots of these bits are not implemented. */
1965 /* This may enable/disable the MMU, so do a TLB flush. */
1968 case 1: /* Auxiliary control register. */
1969 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1970 env
->cp15
.c1_xscaleauxcr
= val
;
1973 /* Not implemented. */
1976 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1978 if (env
->cp15
.c1_coproc
!= val
) {
1979 env
->cp15
.c1_coproc
= val
;
1980 /* ??? Is this safe when called from within a TB? */
1988 case 4: /* Reserved. */
1990 case 12: /* Reserved. */
1995 /* ??? For debugging only. Should raise illegal instruction exception. */
1996 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1997 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2000 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
2006 op1
= (insn
>> 21) & 7;
2007 op2
= (insn
>> 5) & 7;
2009 switch ((insn
>> 16) & 0xf) {
2010 case 0: /* ID codes. */
2016 case 0: /* Device ID. */
2017 return env
->cp15
.c0_cpuid
;
2018 case 1: /* Cache Type. */
2019 return env
->cp15
.c0_cachetype
;
2020 case 2: /* TCM status. */
2022 case 3: /* TLB type register. */
2023 return 0; /* No lockable TLB entries. */
2025 /* The MPIDR was standardised in v7; prior to
2026 * this it was implemented only in the 11MPCore.
2027 * For all other pre-v7 cores it does not exist.
2029 if (arm_feature(env
, ARM_FEATURE_V7
) ||
2030 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
2031 int mpidr
= env
->cpu_index
;
2032 /* We don't support setting cluster ID ([8..11])
2033 * so these bits always RAZ.
2035 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2037 /* Cores which are uniprocessor (non-coherent)
2038 * but still implement the MP extensions set
2039 * bit 30. (For instance, A9UP.) However we do
2040 * not currently model any of those cores.
2045 /* otherwise fall through to the unimplemented-reg case */
2050 if (!arm_feature(env
, ARM_FEATURE_V6
))
2052 return env
->cp15
.c0_c1
[op2
];
2054 if (!arm_feature(env
, ARM_FEATURE_V6
))
2056 return env
->cp15
.c0_c2
[op2
];
2057 case 3: case 4: case 5: case 6: case 7:
2063 /* These registers aren't documented on arm11 cores. However
2064 Linux looks at them anyway. */
2065 if (!arm_feature(env
, ARM_FEATURE_V6
))
2069 if (!arm_feature(env
, ARM_FEATURE_V7
))
2074 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
2076 return env
->cp15
.c0_clid
;
2082 if (op2
!= 0 || crm
!= 0)
2084 return env
->cp15
.c0_cssel
;
2088 case 1: /* System configuration. */
2089 if (arm_feature(env
, ARM_FEATURE_V7
)
2090 && op1
== 0 && crm
== 1 && op2
== 0) {
2091 return env
->cp15
.c1_scr
;
2093 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2096 case 0: /* Control register. */
2097 return env
->cp15
.c1_sys
;
2098 case 1: /* Auxiliary control register. */
2099 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2100 return env
->cp15
.c1_xscaleauxcr
;
2101 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
2103 switch (ARM_CPUID(env
)) {
2104 case ARM_CPUID_ARM1026
:
2106 case ARM_CPUID_ARM1136
:
2107 case ARM_CPUID_ARM1136_R2
:
2108 case ARM_CPUID_ARM1176
:
2110 case ARM_CPUID_ARM11MPCORE
:
2112 case ARM_CPUID_CORTEXA8
:
2114 case ARM_CPUID_CORTEXA9
:
2115 case ARM_CPUID_CORTEXA15
:
2120 case 2: /* Coprocessor access register. */
2121 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2123 return env
->cp15
.c1_coproc
;
2127 case 4: /* Reserved. */
2129 case 11: /* TCM DMA control. */
2130 case 12: /* Reserved. */
2134 /* ??? For debugging only. Should raise illegal instruction exception. */
2135 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2136 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2140 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2142 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2143 env
->regs
[13] = val
;
2145 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2149 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2151 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2152 return env
->regs
[13];
2154 return env
->banked_r13
[bank_number(env
, mode
)];
2158 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2162 return xpsr_read(env
) & 0xf8000000;
2164 return xpsr_read(env
) & 0xf80001ff;
2166 return xpsr_read(env
) & 0xff00fc00;
2168 return xpsr_read(env
) & 0xff00fdff;
2170 return xpsr_read(env
) & 0x000001ff;
2172 return xpsr_read(env
) & 0x0700fc00;
2174 return xpsr_read(env
) & 0x0700edff;
2176 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2178 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2179 case 16: /* PRIMASK */
2180 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2181 case 17: /* BASEPRI */
2182 case 18: /* BASEPRI_MAX */
2183 return env
->v7m
.basepri
;
2184 case 19: /* FAULTMASK */
2185 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2186 case 20: /* CONTROL */
2187 return env
->v7m
.control
;
2189 /* ??? For debugging only. */
2190 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2195 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2199 xpsr_write(env
, val
, 0xf8000000);
2202 xpsr_write(env
, val
, 0xf8000000);
2205 xpsr_write(env
, val
, 0xfe00fc00);
2208 xpsr_write(env
, val
, 0xfe00fc00);
2211 /* IPSR bits are readonly. */
2214 xpsr_write(env
, val
, 0x0600fc00);
2217 xpsr_write(env
, val
, 0x0600fc00);
2220 if (env
->v7m
.current_sp
)
2221 env
->v7m
.other_sp
= val
;
2223 env
->regs
[13] = val
;
2226 if (env
->v7m
.current_sp
)
2227 env
->regs
[13] = val
;
2229 env
->v7m
.other_sp
= val
;
2231 case 16: /* PRIMASK */
2233 env
->uncached_cpsr
|= CPSR_I
;
2235 env
->uncached_cpsr
&= ~CPSR_I
;
2237 case 17: /* BASEPRI */
2238 env
->v7m
.basepri
= val
& 0xff;
2240 case 18: /* BASEPRI_MAX */
2242 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2243 env
->v7m
.basepri
= val
;
2245 case 19: /* FAULTMASK */
2247 env
->uncached_cpsr
|= CPSR_F
;
2249 env
->uncached_cpsr
&= ~CPSR_F
;
2251 case 20: /* CONTROL */
2252 env
->v7m
.control
= val
& 3;
2253 switch_v7m_sp(env
, (val
& 2) != 0);
2256 /* ??? For debugging only. */
2257 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2264 /* Note that signed overflow is undefined in C. The following routines are
2265 careful to use unsigned types where modulo arithmetic is required.
2266 Failure to do so _will_ break on newer gcc. */
2268 /* Signed saturating arithmetic. */
2270 /* Perform 16-bit signed saturating addition. */
2271 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2276 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2285 /* Perform 8-bit signed saturating addition. */
2286 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2291 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2300 /* Perform 16-bit signed saturating subtraction. */
2301 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2306 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2315 /* Perform 8-bit signed saturating subtraction. */
2316 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2321 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2330 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2331 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2332 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2333 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2336 #include "op_addsub.h"
2338 /* Unsigned saturating arithmetic. */
2339 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2348 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2356 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2365 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2373 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2374 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2375 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2376 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2379 #include "op_addsub.h"
2381 /* Signed modulo arithmetic. */
2382 #define SARITH16(a, b, n, op) do { \
2384 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2385 RESULT(sum, n, 16); \
2387 ge |= 3 << (n * 2); \
2390 #define SARITH8(a, b, n, op) do { \
2392 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2393 RESULT(sum, n, 8); \
2399 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2400 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2401 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2402 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2406 #include "op_addsub.h"
2408 /* Unsigned modulo arithmetic. */
2409 #define ADD16(a, b, n) do { \
2411 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2412 RESULT(sum, n, 16); \
2413 if ((sum >> 16) == 1) \
2414 ge |= 3 << (n * 2); \
2417 #define ADD8(a, b, n) do { \
2419 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2420 RESULT(sum, n, 8); \
2421 if ((sum >> 8) == 1) \
2425 #define SUB16(a, b, n) do { \
2427 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2428 RESULT(sum, n, 16); \
2429 if ((sum >> 16) == 0) \
2430 ge |= 3 << (n * 2); \
2433 #define SUB8(a, b, n) do { \
2435 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2436 RESULT(sum, n, 8); \
2437 if ((sum >> 8) == 0) \
2444 #include "op_addsub.h"
2446 /* Halved signed arithmetic. */
2447 #define ADD16(a, b, n) \
2448 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2449 #define SUB16(a, b, n) \
2450 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2451 #define ADD8(a, b, n) \
2452 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2453 #define SUB8(a, b, n) \
2454 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2457 #include "op_addsub.h"
2459 /* Halved unsigned arithmetic. */
2460 #define ADD16(a, b, n) \
2461 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2462 #define SUB16(a, b, n) \
2463 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2464 #define ADD8(a, b, n) \
2465 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2466 #define SUB8(a, b, n) \
2467 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2470 #include "op_addsub.h"
2472 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2480 /* Unsigned sum of absolute byte differences. */
2481 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2484 sum
= do_usad(a
, b
);
2485 sum
+= do_usad(a
>> 8, b
>> 8);
2486 sum
+= do_usad(a
>> 16, b
>>16);
2487 sum
+= do_usad(a
>> 24, b
>> 24);
2491 /* For ARMv6 SEL instruction. */
2492 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2505 return (a
& mask
) | (b
& ~mask
);
2508 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2510 return (val
>> 32) | (val
!= 0);
2513 /* VFP support. We follow the convention used for VFP instrunctions:
2514 Single precition routines have a "s" suffix, double precision a
2517 /* Convert host exception flags to vfp form. */
2518 static inline int vfp_exceptbits_from_host(int host_bits
)
2520 int target_bits
= 0;
2522 if (host_bits
& float_flag_invalid
)
2524 if (host_bits
& float_flag_divbyzero
)
2526 if (host_bits
& float_flag_overflow
)
2528 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2530 if (host_bits
& float_flag_inexact
)
2531 target_bits
|= 0x10;
2532 if (host_bits
& float_flag_input_denormal
)
2533 target_bits
|= 0x80;
2537 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2542 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2543 | (env
->vfp
.vec_len
<< 16)
2544 | (env
->vfp
.vec_stride
<< 20);
2545 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2546 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2547 fpscr
|= vfp_exceptbits_from_host(i
);
2551 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2553 return HELPER(vfp_get_fpscr
)(env
);
2556 /* Convert vfp exception flags to target form. */
2557 static inline int vfp_exceptbits_to_host(int target_bits
)
2561 if (target_bits
& 1)
2562 host_bits
|= float_flag_invalid
;
2563 if (target_bits
& 2)
2564 host_bits
|= float_flag_divbyzero
;
2565 if (target_bits
& 4)
2566 host_bits
|= float_flag_overflow
;
2567 if (target_bits
& 8)
2568 host_bits
|= float_flag_underflow
;
2569 if (target_bits
& 0x10)
2570 host_bits
|= float_flag_inexact
;
2571 if (target_bits
& 0x80)
2572 host_bits
|= float_flag_input_denormal
;
2576 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2581 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2582 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2583 env
->vfp
.vec_len
= (val
>> 16) & 7;
2584 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2587 if (changed
& (3 << 22)) {
2588 i
= (val
>> 22) & 3;
2591 i
= float_round_nearest_even
;
2597 i
= float_round_down
;
2600 i
= float_round_to_zero
;
2603 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2605 if (changed
& (1 << 24)) {
2606 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2607 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2609 if (changed
& (1 << 25))
2610 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2612 i
= vfp_exceptbits_to_host(val
);
2613 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2614 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2617 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2619 HELPER(vfp_set_fpscr
)(env
, val
);
2622 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2624 #define VFP_BINOP(name) \
2625 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2627 float_status *fpst = fpstp; \
2628 return float32_ ## name(a, b, fpst); \
2630 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2632 float_status *fpst = fpstp; \
2633 return float64_ ## name(a, b, fpst); \
2641 float32
VFP_HELPER(neg
, s
)(float32 a
)
2643 return float32_chs(a
);
2646 float64
VFP_HELPER(neg
, d
)(float64 a
)
2648 return float64_chs(a
);
2651 float32
VFP_HELPER(abs
, s
)(float32 a
)
2653 return float32_abs(a
);
2656 float64
VFP_HELPER(abs
, d
)(float64 a
)
2658 return float64_abs(a
);
2661 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2663 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2666 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2668 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2671 /* XXX: check quiet/signaling case */
2672 #define DO_VFP_cmp(p, type) \
2673 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2676 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2677 case 0: flags = 0x6; break; \
2678 case -1: flags = 0x8; break; \
2679 case 1: flags = 0x2; break; \
2680 default: case 2: flags = 0x3; break; \
2682 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2683 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2685 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2688 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2689 case 0: flags = 0x6; break; \
2690 case -1: flags = 0x8; break; \
2691 case 1: flags = 0x2; break; \
2692 default: case 2: flags = 0x3; break; \
2694 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2695 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2697 DO_VFP_cmp(s
, float32
)
2698 DO_VFP_cmp(d
, float64
)
2701 /* Integer to float and float to integer conversions */
2703 #define CONV_ITOF(name, fsz, sign) \
2704 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2706 float_status *fpst = fpstp; \
2707 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2710 #define CONV_FTOI(name, fsz, sign, round) \
2711 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2713 float_status *fpst = fpstp; \
2714 if (float##fsz##_is_any_nan(x)) { \
2715 float_raise(float_flag_invalid, fpst); \
2718 return float##fsz##_to_##sign##int32##round(x, fpst); \
2721 #define FLOAT_CONVS(name, p, fsz, sign) \
2722 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2723 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2724 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2726 FLOAT_CONVS(si
, s
, 32, )
2727 FLOAT_CONVS(si
, d
, 64, )
2728 FLOAT_CONVS(ui
, s
, 32, u
)
2729 FLOAT_CONVS(ui
, d
, 64, u
)
2735 /* floating point conversion */
2736 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2738 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2739 /* ARM requires that S<->D conversion of any kind of NaN generates
2740 * a quiet NaN by forcing the most significant frac bit to 1.
2742 return float64_maybe_silence_nan(r
);
2745 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2747 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2748 /* ARM requires that S<->D conversion of any kind of NaN generates
2749 * a quiet NaN by forcing the most significant frac bit to 1.
2751 return float32_maybe_silence_nan(r
);
2754 /* VFP3 fixed point conversion. */
2755 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2756 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2759 float_status *fpst = fpstp; \
2761 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2762 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2764 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2767 float_status *fpst = fpstp; \
2769 if (float##fsz##_is_any_nan(x)) { \
2770 float_raise(float_flag_invalid, fpst); \
2773 tmp = float##fsz##_scalbn(x, shift, fpst); \
2774 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2777 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2778 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2779 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2780 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2781 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2782 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2783 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2784 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2787 /* Half precision conversions. */
2788 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2790 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2791 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2793 return float32_maybe_silence_nan(r
);
2798 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2800 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2801 float16 r
= float32_to_float16(a
, ieee
, s
);
2803 r
= float16_maybe_silence_nan(r
);
2805 return float16_val(r
);
2808 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2810 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2813 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2815 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2818 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2820 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2823 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2825 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2828 #define float32_two make_float32(0x40000000)
2829 #define float32_three make_float32(0x40400000)
2830 #define float32_one_point_five make_float32(0x3fc00000)
2832 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2834 float_status
*s
= &env
->vfp
.standard_fp_status
;
2835 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2836 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2837 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2838 float_raise(float_flag_input_denormal
, s
);
2842 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2845 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2847 float_status
*s
= &env
->vfp
.standard_fp_status
;
2849 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2850 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2851 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2852 float_raise(float_flag_input_denormal
, s
);
2854 return float32_one_point_five
;
2856 product
= float32_mul(a
, b
, s
);
2857 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2862 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2863 * int->float conversions at run-time. */
2864 #define float64_256 make_float64(0x4070000000000000LL)
2865 #define float64_512 make_float64(0x4080000000000000LL)
2867 /* The algorithm that must be used to calculate the estimate
2868 * is specified by the ARM ARM.
2870 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2872 /* These calculations mustn't set any fp exception flags,
2873 * so we use a local copy of the fp_status.
2875 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2876 float_status
*s
= &dummy_status
;
2877 /* q = (int)(a * 512.0) */
2878 float64 q
= float64_mul(float64_512
, a
, s
);
2879 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2881 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2882 q
= int64_to_float64(q_int
, s
);
2883 q
= float64_add(q
, float64_half
, s
);
2884 q
= float64_div(q
, float64_512
, s
);
2885 q
= float64_div(float64_one
, q
, s
);
2887 /* s = (int)(256.0 * r + 0.5) */
2888 q
= float64_mul(q
, float64_256
, s
);
2889 q
= float64_add(q
, float64_half
, s
);
2890 q_int
= float64_to_int64_round_to_zero(q
, s
);
2892 /* return (double)s / 256.0 */
2893 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2896 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2898 float_status
*s
= &env
->vfp
.standard_fp_status
;
2900 uint32_t val32
= float32_val(a
);
2903 int a_exp
= (val32
& 0x7f800000) >> 23;
2904 int sign
= val32
& 0x80000000;
2906 if (float32_is_any_nan(a
)) {
2907 if (float32_is_signaling_nan(a
)) {
2908 float_raise(float_flag_invalid
, s
);
2910 return float32_default_nan
;
2911 } else if (float32_is_infinity(a
)) {
2912 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2913 } else if (float32_is_zero_or_denormal(a
)) {
2914 if (!float32_is_zero(a
)) {
2915 float_raise(float_flag_input_denormal
, s
);
2917 float_raise(float_flag_divbyzero
, s
);
2918 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2919 } else if (a_exp
>= 253) {
2920 float_raise(float_flag_underflow
, s
);
2921 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2924 f64
= make_float64((0x3feULL
<< 52)
2925 | ((int64_t)(val32
& 0x7fffff) << 29));
2927 result_exp
= 253 - a_exp
;
2929 f64
= recip_estimate(f64
, env
);
2932 | ((result_exp
& 0xff) << 23)
2933 | ((float64_val(f64
) >> 29) & 0x7fffff);
2934 return make_float32(val32
);
2937 /* The algorithm that must be used to calculate the estimate
2938 * is specified by the ARM ARM.
2940 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2942 /* These calculations mustn't set any fp exception flags,
2943 * so we use a local copy of the fp_status.
2945 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2946 float_status
*s
= &dummy_status
;
2950 if (float64_lt(a
, float64_half
, s
)) {
2951 /* range 0.25 <= a < 0.5 */
2953 /* a in units of 1/512 rounded down */
2954 /* q0 = (int)(a * 512.0); */
2955 q
= float64_mul(float64_512
, a
, s
);
2956 q_int
= float64_to_int64_round_to_zero(q
, s
);
2958 /* reciprocal root r */
2959 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2960 q
= int64_to_float64(q_int
, s
);
2961 q
= float64_add(q
, float64_half
, s
);
2962 q
= float64_div(q
, float64_512
, s
);
2963 q
= float64_sqrt(q
, s
);
2964 q
= float64_div(float64_one
, q
, s
);
2966 /* range 0.5 <= a < 1.0 */
2968 /* a in units of 1/256 rounded down */
2969 /* q1 = (int)(a * 256.0); */
2970 q
= float64_mul(float64_256
, a
, s
);
2971 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2973 /* reciprocal root r */
2974 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2975 q
= int64_to_float64(q_int
, s
);
2976 q
= float64_add(q
, float64_half
, s
);
2977 q
= float64_div(q
, float64_256
, s
);
2978 q
= float64_sqrt(q
, s
);
2979 q
= float64_div(float64_one
, q
, s
);
2981 /* r in units of 1/256 rounded to nearest */
2982 /* s = (int)(256.0 * r + 0.5); */
2984 q
= float64_mul(q
, float64_256
,s
);
2985 q
= float64_add(q
, float64_half
, s
);
2986 q_int
= float64_to_int64_round_to_zero(q
, s
);
2988 /* return (double)s / 256.0;*/
2989 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2992 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
2994 float_status
*s
= &env
->vfp
.standard_fp_status
;
3000 val
= float32_val(a
);
3002 if (float32_is_any_nan(a
)) {
3003 if (float32_is_signaling_nan(a
)) {
3004 float_raise(float_flag_invalid
, s
);
3006 return float32_default_nan
;
3007 } else if (float32_is_zero_or_denormal(a
)) {
3008 if (!float32_is_zero(a
)) {
3009 float_raise(float_flag_input_denormal
, s
);
3011 float_raise(float_flag_divbyzero
, s
);
3012 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3013 } else if (float32_is_neg(a
)) {
3014 float_raise(float_flag_invalid
, s
);
3015 return float32_default_nan
;
3016 } else if (float32_is_infinity(a
)) {
3017 return float32_zero
;
3020 /* Normalize to a double-precision value between 0.25 and 1.0,
3021 * preserving the parity of the exponent. */
3022 if ((val
& 0x800000) == 0) {
3023 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3025 | ((uint64_t)(val
& 0x7fffff) << 29));
3027 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3029 | ((uint64_t)(val
& 0x7fffff) << 29));
3032 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3034 f64
= recip_sqrt_estimate(f64
, env
);
3036 val64
= float64_val(f64
);
3038 val
= ((result_exp
& 0xff) << 23)
3039 | ((val64
>> 29) & 0x7fffff);
3040 return make_float32(val
);
3043 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3047 if ((a
& 0x80000000) == 0) {
3051 f64
= make_float64((0x3feULL
<< 52)
3052 | ((int64_t)(a
& 0x7fffffff) << 21));
3054 f64
= recip_estimate (f64
, env
);
3056 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3059 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3063 if ((a
& 0xc0000000) == 0) {
3067 if (a
& 0x80000000) {
3068 f64
= make_float64((0x3feULL
<< 52)
3069 | ((uint64_t)(a
& 0x7fffffff) << 21));
3070 } else { /* bits 31-30 == '01' */
3071 f64
= make_float64((0x3fdULL
<< 52)
3072 | ((uint64_t)(a
& 0x3fffffff) << 22));
3075 f64
= recip_sqrt_estimate(f64
, env
);
3077 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3080 /* VFPv4 fused multiply-accumulate */
3081 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3083 float_status
*fpst
= fpstp
;
3084 return float32_muladd(a
, b
, c
, 0, fpst
);
3087 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3089 float_status
*fpst
= fpstp
;
3090 return float64_muladd(a
, b
, c
, 0, fpst
);