]>
git.proxmox.com Git - qemu.git/blob - target-arm/helper.c
9 #include "qemu-common.h"
11 static uint32_t cortexa8_cp15_c0_c1
[8] =
12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14 static uint32_t cortexa8_cp15_c0_c2
[8] =
15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17 static uint32_t mpcore_cp15_c0_c1
[8] =
18 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
20 static uint32_t mpcore_cp15_c0_c2
[8] =
21 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
23 static uint32_t arm1136_cp15_c0_c1
[8] =
24 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
26 static uint32_t arm1136_cp15_c0_c2
[8] =
27 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
29 static uint32_t cpu_arm_find_by_name(const char *name
);
31 static inline void set_feature(CPUARMState
*env
, int feature
)
33 env
->features
|= 1u << feature
;
36 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
38 env
->cp15
.c0_cpuid
= id
;
40 case ARM_CPUID_ARM926
:
41 set_feature(env
, ARM_FEATURE_VFP
);
42 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
43 env
->cp15
.c0_cachetype
= 0x1dd20d2;
44 env
->cp15
.c1_sys
= 0x00090078;
46 case ARM_CPUID_ARM946
:
47 set_feature(env
, ARM_FEATURE_MPU
);
48 env
->cp15
.c0_cachetype
= 0x0f004006;
49 env
->cp15
.c1_sys
= 0x00000078;
51 case ARM_CPUID_ARM1026
:
52 set_feature(env
, ARM_FEATURE_VFP
);
53 set_feature(env
, ARM_FEATURE_AUXCR
);
54 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
55 env
->cp15
.c0_cachetype
= 0x1dd20d2;
56 env
->cp15
.c1_sys
= 0x00090078;
58 case ARM_CPUID_ARM1136_R2
:
59 case ARM_CPUID_ARM1136
:
60 set_feature(env
, ARM_FEATURE_V6
);
61 set_feature(env
, ARM_FEATURE_VFP
);
62 set_feature(env
, ARM_FEATURE_AUXCR
);
63 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
64 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
65 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
66 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
67 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
68 env
->cp15
.c0_cachetype
= 0x1dd20d2;
70 case ARM_CPUID_ARM11MPCORE
:
71 set_feature(env
, ARM_FEATURE_V6
);
72 set_feature(env
, ARM_FEATURE_V6K
);
73 set_feature(env
, ARM_FEATURE_VFP
);
74 set_feature(env
, ARM_FEATURE_AUXCR
);
75 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
76 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
77 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
78 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
79 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
80 env
->cp15
.c0_cachetype
= 0x1dd20d2;
82 case ARM_CPUID_CORTEXA8
:
83 set_feature(env
, ARM_FEATURE_V6
);
84 set_feature(env
, ARM_FEATURE_V6K
);
85 set_feature(env
, ARM_FEATURE_V7
);
86 set_feature(env
, ARM_FEATURE_AUXCR
);
87 set_feature(env
, ARM_FEATURE_THUMB2
);
88 set_feature(env
, ARM_FEATURE_VFP
);
89 set_feature(env
, ARM_FEATURE_VFP3
);
90 set_feature(env
, ARM_FEATURE_NEON
);
91 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
92 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
93 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
94 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
95 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
96 env
->cp15
.c0_cachetype
= 0x1dd20d2;
98 case ARM_CPUID_CORTEXM3
:
99 set_feature(env
, ARM_FEATURE_V6
);
100 set_feature(env
, ARM_FEATURE_THUMB2
);
101 set_feature(env
, ARM_FEATURE_V7
);
102 set_feature(env
, ARM_FEATURE_M
);
103 set_feature(env
, ARM_FEATURE_DIV
);
105 case ARM_CPUID_ANY
: /* For userspace emulation. */
106 set_feature(env
, ARM_FEATURE_V6
);
107 set_feature(env
, ARM_FEATURE_V6K
);
108 set_feature(env
, ARM_FEATURE_V7
);
109 set_feature(env
, ARM_FEATURE_THUMB2
);
110 set_feature(env
, ARM_FEATURE_VFP
);
111 set_feature(env
, ARM_FEATURE_VFP3
);
112 set_feature(env
, ARM_FEATURE_NEON
);
113 set_feature(env
, ARM_FEATURE_DIV
);
115 case ARM_CPUID_TI915T
:
116 case ARM_CPUID_TI925T
:
117 set_feature(env
, ARM_FEATURE_OMAPCP
);
118 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
119 env
->cp15
.c0_cachetype
= 0x5109149;
120 env
->cp15
.c1_sys
= 0x00000070;
121 env
->cp15
.c15_i_max
= 0x000;
122 env
->cp15
.c15_i_min
= 0xff0;
124 case ARM_CPUID_PXA250
:
125 case ARM_CPUID_PXA255
:
126 case ARM_CPUID_PXA260
:
127 case ARM_CPUID_PXA261
:
128 case ARM_CPUID_PXA262
:
129 set_feature(env
, ARM_FEATURE_XSCALE
);
130 /* JTAG_ID is ((id << 28) | 0x09265013) */
131 env
->cp15
.c0_cachetype
= 0xd172172;
132 env
->cp15
.c1_sys
= 0x00000078;
134 case ARM_CPUID_PXA270_A0
:
135 case ARM_CPUID_PXA270_A1
:
136 case ARM_CPUID_PXA270_B0
:
137 case ARM_CPUID_PXA270_B1
:
138 case ARM_CPUID_PXA270_C0
:
139 case ARM_CPUID_PXA270_C5
:
140 set_feature(env
, ARM_FEATURE_XSCALE
);
141 /* JTAG_ID is ((id << 28) | 0x09265013) */
142 set_feature(env
, ARM_FEATURE_IWMMXT
);
143 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
144 env
->cp15
.c0_cachetype
= 0xd172172;
145 env
->cp15
.c1_sys
= 0x00000078;
148 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
153 void cpu_reset(CPUARMState
*env
)
156 id
= env
->cp15
.c0_cpuid
;
157 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
159 cpu_reset_model_id(env
, id
);
160 #if defined (CONFIG_USER_ONLY)
161 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
162 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
164 /* SVC mode with interrupts disabled. */
165 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
166 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
169 env
->uncached_cpsr
&= ~CPSR_I
;
170 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
176 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
180 /* VFP data registers are always little-endian. */
181 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
183 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
186 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
187 /* Aliases for Q regs. */
190 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
191 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
195 switch (reg
- nregs
) {
196 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
197 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
198 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
203 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
207 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
209 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
212 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
215 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
216 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
220 switch (reg
- nregs
) {
221 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
222 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
223 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
); return 4;
228 CPUARMState
*cpu_arm_init(const char *cpu_model
)
232 static int inited
= 0;
234 id
= cpu_arm_find_by_name(cpu_model
);
237 env
= qemu_mallocz(sizeof(CPUARMState
));
243 arm_translate_init();
246 env
->cpu_model_str
= cpu_model
;
247 env
->cp15
.c0_cpuid
= id
;
249 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
250 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
251 51, "arm-neon.xml", 0);
252 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
253 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
254 35, "arm-vfp3.xml", 0);
255 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
256 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
257 19, "arm-vfp.xml", 0);
267 static const struct arm_cpu_t arm_cpu_names
[] = {
268 { ARM_CPUID_ARM926
, "arm926"},
269 { ARM_CPUID_ARM946
, "arm946"},
270 { ARM_CPUID_ARM1026
, "arm1026"},
271 { ARM_CPUID_ARM1136
, "arm1136"},
272 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
273 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
274 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
275 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
276 { ARM_CPUID_TI925T
, "ti925t" },
277 { ARM_CPUID_PXA250
, "pxa250" },
278 { ARM_CPUID_PXA255
, "pxa255" },
279 { ARM_CPUID_PXA260
, "pxa260" },
280 { ARM_CPUID_PXA261
, "pxa261" },
281 { ARM_CPUID_PXA262
, "pxa262" },
282 { ARM_CPUID_PXA270
, "pxa270" },
283 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
284 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
285 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
286 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
287 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
288 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
289 { ARM_CPUID_ANY
, "any"},
293 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
297 (*cpu_fprintf
)(f
, "Available CPUs:\n");
298 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
299 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
303 /* return 0 if not found */
304 static uint32_t cpu_arm_find_by_name(const char *name
)
310 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
311 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
312 id
= arm_cpu_names
[i
].id
;
319 void cpu_arm_close(CPUARMState
*env
)
324 uint32_t cpsr_read(CPUARMState
*env
)
328 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
329 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
330 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
331 | ((env
->condexec_bits
& 0xfc) << 8)
335 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
337 if (mask
& CPSR_NZCV
) {
338 env
->ZF
= (~val
) & CPSR_Z
;
340 env
->CF
= (val
>> 29) & 1;
341 env
->VF
= (val
<< 3) & 0x80000000;
344 env
->QF
= ((val
& CPSR_Q
) != 0);
346 env
->thumb
= ((val
& CPSR_T
) != 0);
347 if (mask
& CPSR_IT_0_1
) {
348 env
->condexec_bits
&= ~3;
349 env
->condexec_bits
|= (val
>> 25) & 3;
351 if (mask
& CPSR_IT_2_7
) {
352 env
->condexec_bits
&= 3;
353 env
->condexec_bits
|= (val
>> 8) & 0xfc;
355 if (mask
& CPSR_GE
) {
356 env
->GE
= (val
>> 16) & 0xf;
359 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
360 switch_mode(env
, val
& CPSR_M
);
362 mask
&= ~CACHED_CPSR_BITS
;
363 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
366 /* Sign/zero extend */
367 uint32_t HELPER(sxtb16
)(uint32_t x
)
370 res
= (uint16_t)(int8_t)x
;
371 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
375 uint32_t HELPER(uxtb16
)(uint32_t x
)
378 res
= (uint16_t)(uint8_t)x
;
379 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
383 uint32_t HELPER(clz
)(uint32_t x
)
386 for (count
= 32; x
; count
--)
391 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
398 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
405 uint32_t HELPER(rbit
)(uint32_t x
)
407 x
= ((x
& 0xff000000) >> 24)
408 | ((x
& 0x00ff0000) >> 8)
409 | ((x
& 0x0000ff00) << 8)
410 | ((x
& 0x000000ff) << 24);
411 x
= ((x
& 0xf0f0f0f0) >> 4)
412 | ((x
& 0x0f0f0f0f) << 4);
413 x
= ((x
& 0x88888888) >> 3)
414 | ((x
& 0x44444444) >> 1)
415 | ((x
& 0x22222222) << 1)
416 | ((x
& 0x11111111) << 3);
420 uint32_t HELPER(abs
)(uint32_t x
)
422 return ((int32_t)x
< 0) ? -x
: x
;
425 #if defined(CONFIG_USER_ONLY)
427 void do_interrupt (CPUState
*env
)
429 env
->exception_index
= -1;
432 /* Structure used to record exclusive memory locations. */
433 typedef struct mmon_state
{
434 struct mmon_state
*next
;
435 CPUARMState
*cpu_env
;
439 /* Chain of current locks. */
440 static mmon_state
* mmon_head
= NULL
;
442 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
443 int mmu_idx
, int is_softmmu
)
446 env
->exception_index
= EXCP_PREFETCH_ABORT
;
447 env
->cp15
.c6_insn
= address
;
449 env
->exception_index
= EXCP_DATA_ABORT
;
450 env
->cp15
.c6_data
= address
;
455 static void allocate_mmon_state(CPUState
*env
)
457 env
->mmon_entry
= malloc(sizeof (mmon_state
));
458 if (!env
->mmon_entry
)
460 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
461 env
->mmon_entry
->cpu_env
= env
;
462 mmon_head
= env
->mmon_entry
;
465 /* Flush any monitor locks for the specified address. */
466 static void flush_mmon(uint32_t addr
)
470 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
472 if (mon
->addr
!= addr
)
480 /* Mark an address for exclusive access. */
481 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
483 if (!env
->mmon_entry
)
484 allocate_mmon_state(env
);
485 /* Clear any previous locks. */
487 env
->mmon_entry
->addr
= addr
;
490 /* Test if an exclusive address is still exclusive. Returns zero
491 if the address is still exclusive. */
492 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
496 if (!env
->mmon_entry
)
498 if (env
->mmon_entry
->addr
== addr
)
506 void HELPER(clrex
)(CPUState
*env
)
508 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
510 flush_mmon(env
->mmon_entry
->addr
);
513 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
518 /* These should probably raise undefined insn exceptions. */
519 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
521 int op1
= (insn
>> 8) & 0xf;
522 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
526 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
528 int op1
= (insn
>> 8) & 0xf;
529 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
533 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
535 cpu_abort(env
, "cp15 insn %08x\n", insn
);
538 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
540 cpu_abort(env
, "cp15 insn %08x\n", insn
);
544 /* These should probably raise undefined insn exceptions. */
545 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
547 cpu_abort(env
, "v7m_mrs %d\n", reg
);
550 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
552 cpu_abort(env
, "v7m_mrs %d\n", reg
);
556 void switch_mode(CPUState
*env
, int mode
)
558 if (mode
!= ARM_CPU_MODE_USR
)
559 cpu_abort(env
, "Tried to switch out of user mode\n");
562 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
564 cpu_abort(env
, "banked r13 write\n");
567 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
569 cpu_abort(env
, "banked r13 read\n");
575 extern int semihosting_enabled
;
577 /* Map CPU modes onto saved register banks. */
578 static inline int bank_number (int mode
)
581 case ARM_CPU_MODE_USR
:
582 case ARM_CPU_MODE_SYS
:
584 case ARM_CPU_MODE_SVC
:
586 case ARM_CPU_MODE_ABT
:
588 case ARM_CPU_MODE_UND
:
590 case ARM_CPU_MODE_IRQ
:
592 case ARM_CPU_MODE_FIQ
:
595 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
599 void switch_mode(CPUState
*env
, int mode
)
604 old_mode
= env
->uncached_cpsr
& CPSR_M
;
605 if (mode
== old_mode
)
608 if (old_mode
== ARM_CPU_MODE_FIQ
) {
609 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
610 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
611 } else if (mode
== ARM_CPU_MODE_FIQ
) {
612 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
613 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
616 i
= bank_number(old_mode
);
617 env
->banked_r13
[i
] = env
->regs
[13];
618 env
->banked_r14
[i
] = env
->regs
[14];
619 env
->banked_spsr
[i
] = env
->spsr
;
621 i
= bank_number(mode
);
622 env
->regs
[13] = env
->banked_r13
[i
];
623 env
->regs
[14] = env
->banked_r14
[i
];
624 env
->spsr
= env
->banked_spsr
[i
];
627 static void v7m_push(CPUARMState
*env
, uint32_t val
)
630 stl_phys(env
->regs
[13], val
);
633 static uint32_t v7m_pop(CPUARMState
*env
)
636 val
= ldl_phys(env
->regs
[13]);
641 /* Switch to V7M main or process stack pointer. */
642 static void switch_v7m_sp(CPUARMState
*env
, int process
)
645 if (env
->v7m
.current_sp
!= process
) {
646 tmp
= env
->v7m
.other_sp
;
647 env
->v7m
.other_sp
= env
->regs
[13];
649 env
->v7m
.current_sp
= process
;
653 static void do_v7m_exception_exit(CPUARMState
*env
)
658 type
= env
->regs
[15];
659 if (env
->v7m
.exception
!= 0)
660 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
662 /* Switch to the target stack. */
663 switch_v7m_sp(env
, (type
& 4) != 0);
665 env
->regs
[0] = v7m_pop(env
);
666 env
->regs
[1] = v7m_pop(env
);
667 env
->regs
[2] = v7m_pop(env
);
668 env
->regs
[3] = v7m_pop(env
);
669 env
->regs
[12] = v7m_pop(env
);
670 env
->regs
[14] = v7m_pop(env
);
671 env
->regs
[15] = v7m_pop(env
);
673 xpsr_write(env
, xpsr
, 0xfffffdff);
674 /* Undo stack alignment. */
677 /* ??? The exception return type specifies Thread/Handler mode. However
678 this is also implied by the xPSR value. Not sure what to do
679 if there is a mismatch. */
680 /* ??? Likewise for mismatches between the CONTROL register and the stack
684 void do_interrupt_v7m(CPUARMState
*env
)
686 uint32_t xpsr
= xpsr_read(env
);
691 if (env
->v7m
.current_sp
)
693 if (env
->v7m
.exception
== 0)
696 /* For exceptions we just mark as pending on the NVIC, and let that
698 /* TODO: Need to escalate if the current priority is higher than the
699 one we're raising. */
700 switch (env
->exception_index
) {
702 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
706 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
708 case EXCP_PREFETCH_ABORT
:
709 case EXCP_DATA_ABORT
:
710 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
713 if (semihosting_enabled
) {
715 nr
= lduw_code(env
->regs
[15]) & 0xff;
718 env
->regs
[0] = do_arm_semihosting(env
);
722 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
725 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
727 case EXCP_EXCEPTION_EXIT
:
728 do_v7m_exception_exit(env
);
731 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
732 return; /* Never happens. Keep compiler happy. */
735 /* Align stack pointer. */
736 /* ??? Should only do this if Configuration Control Register
737 STACKALIGN bit is set. */
738 if (env
->regs
[13] & 4) {
742 /* Switch to the handler mode. */
744 v7m_push(env
, env
->regs
[15]);
745 v7m_push(env
, env
->regs
[14]);
746 v7m_push(env
, env
->regs
[12]);
747 v7m_push(env
, env
->regs
[3]);
748 v7m_push(env
, env
->regs
[2]);
749 v7m_push(env
, env
->regs
[1]);
750 v7m_push(env
, env
->regs
[0]);
751 switch_v7m_sp(env
, 0);
752 env
->uncached_cpsr
&= ~CPSR_IT
;
754 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
755 env
->regs
[15] = addr
& 0xfffffffe;
756 env
->thumb
= addr
& 1;
759 /* Handle a CPU exception. */
760 void do_interrupt(CPUARMState
*env
)
768 do_interrupt_v7m(env
);
771 /* TODO: Vectored interrupt controller. */
772 switch (env
->exception_index
) {
774 new_mode
= ARM_CPU_MODE_UND
;
783 if (semihosting_enabled
) {
784 /* Check for semihosting interrupt. */
786 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
788 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
790 /* Only intercept calls from privileged modes, to provide some
791 semblance of security. */
792 if (((mask
== 0x123456 && !env
->thumb
)
793 || (mask
== 0xab && env
->thumb
))
794 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
795 env
->regs
[0] = do_arm_semihosting(env
);
799 new_mode
= ARM_CPU_MODE_SVC
;
802 /* The PC already points to the next instruction. */
806 /* See if this is a semihosting syscall. */
807 if (env
->thumb
&& semihosting_enabled
) {
808 mask
= lduw_code(env
->regs
[15]) & 0xff;
810 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
812 env
->regs
[0] = do_arm_semihosting(env
);
816 /* Fall through to prefetch abort. */
817 case EXCP_PREFETCH_ABORT
:
818 new_mode
= ARM_CPU_MODE_ABT
;
820 mask
= CPSR_A
| CPSR_I
;
823 case EXCP_DATA_ABORT
:
824 new_mode
= ARM_CPU_MODE_ABT
;
826 mask
= CPSR_A
| CPSR_I
;
830 new_mode
= ARM_CPU_MODE_IRQ
;
832 /* Disable IRQ and imprecise data aborts. */
833 mask
= CPSR_A
| CPSR_I
;
837 new_mode
= ARM_CPU_MODE_FIQ
;
839 /* Disable FIQ, IRQ and imprecise data aborts. */
840 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
844 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
845 return; /* Never happens. Keep compiler happy. */
848 if (env
->cp15
.c1_sys
& (1 << 13)) {
851 switch_mode (env
, new_mode
);
852 env
->spsr
= cpsr_read(env
);
854 env
->condexec_bits
= 0;
855 /* Switch to the new mode, and switch to Arm mode. */
856 /* ??? Thumb interrupt handlers not implemented. */
857 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
858 env
->uncached_cpsr
|= mask
;
860 env
->regs
[14] = env
->regs
[15] + offset
;
861 env
->regs
[15] = addr
;
862 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
865 /* Check section/page access permissions.
866 Returns the page protection flags, or zero if the access is not
868 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
874 return PAGE_READ
| PAGE_WRITE
;
876 if (access_type
== 1)
883 if (access_type
== 1)
885 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
887 return is_user
? 0 : PAGE_READ
;
894 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
899 return PAGE_READ
| PAGE_WRITE
;
901 return PAGE_READ
| PAGE_WRITE
;
902 case 4: case 7: /* Reserved. */
905 return is_user
? 0 : prot_ro
;
913 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
914 int is_user
, uint32_t *phys_ptr
, int *prot
)
924 /* Pagetable walk. */
925 /* Lookup l1 descriptor. */
926 if (address
& env
->cp15
.c2_mask
)
927 table
= env
->cp15
.c2_base1
;
929 table
= env
->cp15
.c2_base0
;
930 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
931 desc
= ldl_phys(table
);
933 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
935 /* Section translation fault. */
939 if (domain
== 0 || domain
== 2) {
941 code
= 9; /* Section domain fault. */
943 code
= 11; /* Page domain fault. */
948 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
949 ap
= (desc
>> 10) & 3;
952 /* Lookup l2 entry. */
954 /* Coarse pagetable. */
955 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
957 /* Fine pagetable. */
958 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
960 desc
= ldl_phys(table
);
962 case 0: /* Page translation fault. */
965 case 1: /* 64k page. */
966 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
967 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
969 case 2: /* 4k page. */
970 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
971 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
973 case 3: /* 1k page. */
975 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
976 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
978 /* Page translation fault. */
983 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
985 ap
= (desc
>> 4) & 3;
988 /* Never happens, but compiler isn't smart enough to tell. */
993 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
995 /* Access permission fault. */
998 *phys_ptr
= phys_addr
;
1001 return code
| (domain
<< 4);
1004 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1005 int is_user
, uint32_t *phys_ptr
, int *prot
)
1016 /* Pagetable walk. */
1017 /* Lookup l1 descriptor. */
1018 if (address
& env
->cp15
.c2_mask
)
1019 table
= env
->cp15
.c2_base1
;
1021 table
= env
->cp15
.c2_base0
;
1022 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
1023 desc
= ldl_phys(table
);
1026 /* Section translation fault. */
1030 } else if (type
== 2 && (desc
& (1 << 18))) {
1034 /* Section or page. */
1035 domain
= (desc
>> 4) & 0x1e;
1037 domain
= (env
->cp15
.c3
>> domain
) & 3;
1038 if (domain
== 0 || domain
== 2) {
1040 code
= 9; /* Section domain fault. */
1042 code
= 11; /* Page domain fault. */
1046 if (desc
& (1 << 18)) {
1048 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1051 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1053 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1054 xn
= desc
& (1 << 4);
1057 /* Lookup l2 entry. */
1058 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1059 desc
= ldl_phys(table
);
1060 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1062 case 0: /* Page translation fault. */
1065 case 1: /* 64k page. */
1066 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1067 xn
= desc
& (1 << 15);
1069 case 2: case 3: /* 4k page. */
1070 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1074 /* Never happens, but compiler isn't smart enough to tell. */
1079 if (xn
&& access_type
== 2)
1082 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1084 /* Access permission fault. */
1087 *phys_ptr
= phys_addr
;
1090 return code
| (domain
<< 4);
1093 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1094 int is_user
, uint32_t *phys_ptr
, int *prot
)
1100 *phys_ptr
= address
;
1101 for (n
= 7; n
>= 0; n
--) {
1102 base
= env
->cp15
.c6_region
[n
];
1103 if ((base
& 1) == 0)
1105 mask
= 1 << ((base
>> 1) & 0x1f);
1106 /* Keep this shift separate from the above to avoid an
1107 (undefined) << 32. */
1108 mask
= (mask
<< 1) - 1;
1109 if (((base
^ address
) & ~mask
) == 0)
1115 if (access_type
== 2) {
1116 mask
= env
->cp15
.c5_insn
;
1118 mask
= env
->cp15
.c5_data
;
1120 mask
= (mask
>> (n
* 4)) & 0xf;
1127 *prot
= PAGE_READ
| PAGE_WRITE
;
1132 *prot
|= PAGE_WRITE
;
1135 *prot
= PAGE_READ
| PAGE_WRITE
;
1146 /* Bad permission. */
1152 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1153 int access_type
, int is_user
,
1154 uint32_t *phys_ptr
, int *prot
)
1156 /* Fast Context Switch Extension. */
1157 if (address
< 0x02000000)
1158 address
+= env
->cp15
.c13_fcse
;
1160 if ((env
->cp15
.c1_sys
& 1) == 0) {
1161 /* MMU/MPU disabled. */
1162 *phys_ptr
= address
;
1163 *prot
= PAGE_READ
| PAGE_WRITE
;
1165 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1166 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1168 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1169 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1172 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1177 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1178 int access_type
, int mmu_idx
, int is_softmmu
)
1184 is_user
= mmu_idx
== MMU_USER_IDX
;
1185 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1187 /* Map a single [sub]page. */
1188 phys_addr
&= ~(uint32_t)0x3ff;
1189 address
&= ~(uint32_t)0x3ff;
1190 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1194 if (access_type
== 2) {
1195 env
->cp15
.c5_insn
= ret
;
1196 env
->cp15
.c6_insn
= address
;
1197 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1199 env
->cp15
.c5_data
= ret
;
1200 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1201 env
->cp15
.c5_data
|= (1 << 11);
1202 env
->cp15
.c6_data
= address
;
1203 env
->exception_index
= EXCP_DATA_ABORT
;
1208 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1214 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1222 /* Not really implemented. Need to figure out a sane way of doing this.
1223 Maybe add generic watchpoint support and use that. */
1225 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
1227 env
->mmon_addr
= addr
;
1230 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
1232 return (env
->mmon_addr
!= addr
);
1235 void HELPER(clrex
)(CPUState
*env
)
1237 env
->mmon_addr
= -1;
1240 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1242 int cp_num
= (insn
>> 8) & 0xf;
1243 int cp_info
= (insn
>> 5) & 7;
1244 int src
= (insn
>> 16) & 0xf;
1245 int operand
= insn
& 0xf;
1247 if (env
->cp
[cp_num
].cp_write
)
1248 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1249 cp_info
, src
, operand
, val
);
1252 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1254 int cp_num
= (insn
>> 8) & 0xf;
1255 int cp_info
= (insn
>> 5) & 7;
1256 int dest
= (insn
>> 16) & 0xf;
1257 int operand
= insn
& 0xf;
1259 if (env
->cp
[cp_num
].cp_read
)
1260 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1261 cp_info
, dest
, operand
);
1265 /* Return basic MPU access permission bits. */
1266 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1273 for (i
= 0; i
< 16; i
+= 2) {
1274 ret
|= (val
>> i
) & mask
;
1280 /* Pad basic MPU access permission bits to extended format. */
1281 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1288 for (i
= 0; i
< 16; i
+= 2) {
1289 ret
|= (val
& mask
) << i
;
1295 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1301 op1
= (insn
>> 21) & 7;
1302 op2
= (insn
>> 5) & 7;
1304 switch ((insn
>> 16) & 0xf) {
1306 if (((insn
>> 21) & 7) == 2) {
1307 /* ??? Select cache level. Ignore. */
1311 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1313 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1316 case 1: /* System configuration. */
1317 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1321 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1322 env
->cp15
.c1_sys
= val
;
1323 /* ??? Lots of these bits are not implemented. */
1324 /* This may enable/disable the MMU, so do a TLB flush. */
1327 case 1: /* Auxiliary cotrol register. */
1328 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1329 env
->cp15
.c1_xscaleauxcr
= val
;
1332 /* Not implemented. */
1335 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1337 if (env
->cp15
.c1_coproc
!= val
) {
1338 env
->cp15
.c1_coproc
= val
;
1339 /* ??? Is this safe when called from within a TB? */
1347 case 2: /* MMU Page table control / MPU cache control. */
1348 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1351 env
->cp15
.c2_data
= val
;
1354 env
->cp15
.c2_insn
= val
;
1362 env
->cp15
.c2_base0
= val
;
1365 env
->cp15
.c2_base1
= val
;
1368 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1375 case 3: /* MMU Domain access control / MPU write buffer control. */
1377 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1379 case 4: /* Reserved. */
1381 case 5: /* MMU Fault status / MPU access permission. */
1382 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1386 if (arm_feature(env
, ARM_FEATURE_MPU
))
1387 val
= extended_mpu_ap_bits(val
);
1388 env
->cp15
.c5_data
= val
;
1391 if (arm_feature(env
, ARM_FEATURE_MPU
))
1392 val
= extended_mpu_ap_bits(val
);
1393 env
->cp15
.c5_insn
= val
;
1396 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1398 env
->cp15
.c5_data
= val
;
1401 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1403 env
->cp15
.c5_insn
= val
;
1409 case 6: /* MMU Fault address / MPU base/size. */
1410 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1413 env
->cp15
.c6_region
[crm
] = val
;
1415 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1419 env
->cp15
.c6_data
= val
;
1421 case 1: /* ??? This is WFAR on armv6 */
1423 env
->cp15
.c6_insn
= val
;
1430 case 7: /* Cache control. */
1431 env
->cp15
.c15_i_max
= 0x000;
1432 env
->cp15
.c15_i_min
= 0xff0;
1433 /* No cache, so nothing to do. */
1434 /* ??? MPCore has VA to PA translation functions. */
1436 case 8: /* MMU TLB control. */
1438 case 0: /* Invalidate all. */
1441 case 1: /* Invalidate single TLB entry. */
1443 /* ??? This is wrong for large pages and sections. */
1444 /* As an ugly hack to make linux work we always flush a 4K
1447 tlb_flush_page(env
, val
);
1448 tlb_flush_page(env
, val
+ 0x400);
1449 tlb_flush_page(env
, val
+ 0x800);
1450 tlb_flush_page(env
, val
+ 0xc00);
1455 case 2: /* Invalidate on ASID. */
1456 tlb_flush(env
, val
== 0);
1458 case 3: /* Invalidate single entry on MVA. */
1459 /* ??? This is like case 1, but ignores ASID. */
1467 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1470 case 0: /* Cache lockdown. */
1472 case 0: /* L1 cache. */
1475 env
->cp15
.c9_data
= val
;
1478 env
->cp15
.c9_insn
= val
;
1484 case 1: /* L2 cache. */
1485 /* Ignore writes to L2 lockdown/auxiliary registers. */
1491 case 1: /* TCM memory region registers. */
1492 /* Not implemented. */
1498 case 10: /* MMU TLB lockdown. */
1499 /* ??? TLB lockdown not implemented. */
1501 case 12: /* Reserved. */
1503 case 13: /* Process ID. */
1506 /* Unlike real hardware the qemu TLB uses virtual addresses,
1507 not modified virtual addresses, so this causes a TLB flush.
1509 if (env
->cp15
.c13_fcse
!= val
)
1511 env
->cp15
.c13_fcse
= val
;
1514 /* This changes the ASID, so do a TLB flush. */
1515 if (env
->cp15
.c13_context
!= val
1516 && !arm_feature(env
, ARM_FEATURE_MPU
))
1518 env
->cp15
.c13_context
= val
;
1521 env
->cp15
.c13_tls1
= val
;
1524 env
->cp15
.c13_tls2
= val
;
1527 env
->cp15
.c13_tls3
= val
;
1533 case 14: /* Reserved. */
1535 case 15: /* Implementation specific. */
1536 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1537 if (op2
== 0 && crm
== 1) {
1538 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1539 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1541 env
->cp15
.c15_cpar
= val
& 0x3fff;
1547 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1551 case 1: /* Set TI925T configuration. */
1552 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1553 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1554 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1556 case 2: /* Set I_max. */
1557 env
->cp15
.c15_i_max
= val
;
1559 case 3: /* Set I_min. */
1560 env
->cp15
.c15_i_min
= val
;
1562 case 4: /* Set thread-ID. */
1563 env
->cp15
.c15_threadid
= val
& 0xffff;
1565 case 8: /* Wait-for-interrupt (deprecated). */
1566 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1576 /* ??? For debugging only. Should raise illegal instruction exception. */
1577 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1578 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1581 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1587 op1
= (insn
>> 21) & 7;
1588 op2
= (insn
>> 5) & 7;
1590 switch ((insn
>> 16) & 0xf) {
1591 case 0: /* ID codes. */
1597 case 0: /* Device ID. */
1598 return env
->cp15
.c0_cpuid
;
1599 case 1: /* Cache Type. */
1600 return env
->cp15
.c0_cachetype
;
1601 case 2: /* TCM status. */
1603 case 3: /* TLB type register. */
1604 return 0; /* No lockable TLB entries. */
1605 case 5: /* CPU ID */
1606 return env
->cpu_index
;
1611 if (!arm_feature(env
, ARM_FEATURE_V6
))
1613 return env
->cp15
.c0_c1
[op2
];
1615 if (!arm_feature(env
, ARM_FEATURE_V6
))
1617 return env
->cp15
.c0_c2
[op2
];
1618 case 3: case 4: case 5: case 6: case 7:
1624 /* These registers aren't documented on arm11 cores. However
1625 Linux looks at them anyway. */
1626 if (!arm_feature(env
, ARM_FEATURE_V6
))
1630 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1636 case 1: /* System configuration. */
1637 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1640 case 0: /* Control register. */
1641 return env
->cp15
.c1_sys
;
1642 case 1: /* Auxiliary control register. */
1643 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1644 return env
->cp15
.c1_xscaleauxcr
;
1645 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1647 switch (ARM_CPUID(env
)) {
1648 case ARM_CPUID_ARM1026
:
1650 case ARM_CPUID_ARM1136
:
1651 case ARM_CPUID_ARM1136_R2
:
1653 case ARM_CPUID_ARM11MPCORE
:
1655 case ARM_CPUID_CORTEXA8
:
1660 case 2: /* Coprocessor access register. */
1661 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1663 return env
->cp15
.c1_coproc
;
1667 case 2: /* MMU Page table control / MPU cache control. */
1668 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1671 return env
->cp15
.c2_data
;
1674 return env
->cp15
.c2_insn
;
1682 return env
->cp15
.c2_base0
;
1684 return env
->cp15
.c2_base1
;
1690 mask
= env
->cp15
.c2_mask
;
1701 case 3: /* MMU Domain access control / MPU write buffer control. */
1702 return env
->cp15
.c3
;
1703 case 4: /* Reserved. */
1705 case 5: /* MMU Fault status / MPU access permission. */
1706 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1710 if (arm_feature(env
, ARM_FEATURE_MPU
))
1711 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1712 return env
->cp15
.c5_data
;
1714 if (arm_feature(env
, ARM_FEATURE_MPU
))
1715 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1716 return env
->cp15
.c5_insn
;
1718 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1720 return env
->cp15
.c5_data
;
1722 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1724 return env
->cp15
.c5_insn
;
1728 case 6: /* MMU Fault address. */
1729 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1732 return env
->cp15
.c6_region
[crm
];
1734 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1738 return env
->cp15
.c6_data
;
1740 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1741 /* Watchpoint Fault Adrress. */
1742 return 0; /* Not implemented. */
1744 /* Instruction Fault Adrress. */
1745 /* Arm9 doesn't have an IFAR, but implementing it anyway
1746 shouldn't do any harm. */
1747 return env
->cp15
.c6_insn
;
1750 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1751 /* Instruction Fault Adrress. */
1752 return env
->cp15
.c6_insn
;
1760 case 7: /* Cache control. */
1761 /* FIXME: Should only clear Z flag if destination is r15. */
1764 case 8: /* MMU TLB control. */
1766 case 9: /* Cache lockdown. */
1768 case 0: /* L1 cache. */
1769 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1773 return env
->cp15
.c9_data
;
1775 return env
->cp15
.c9_insn
;
1779 case 1: /* L2 cache */
1782 /* L2 Lockdown and Auxiliary control. */
1787 case 10: /* MMU TLB lockdown. */
1788 /* ??? TLB lockdown not implemented. */
1790 case 11: /* TCM DMA control. */
1791 case 12: /* Reserved. */
1793 case 13: /* Process ID. */
1796 return env
->cp15
.c13_fcse
;
1798 return env
->cp15
.c13_context
;
1800 return env
->cp15
.c13_tls1
;
1802 return env
->cp15
.c13_tls2
;
1804 return env
->cp15
.c13_tls3
;
1808 case 14: /* Reserved. */
1810 case 15: /* Implementation specific. */
1811 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1812 if (op2
== 0 && crm
== 1)
1813 return env
->cp15
.c15_cpar
;
1817 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1821 case 1: /* Read TI925T configuration. */
1822 return env
->cp15
.c15_ticonfig
;
1823 case 2: /* Read I_max. */
1824 return env
->cp15
.c15_i_max
;
1825 case 3: /* Read I_min. */
1826 return env
->cp15
.c15_i_min
;
1827 case 4: /* Read thread-ID. */
1828 return env
->cp15
.c15_threadid
;
1829 case 8: /* TI925T_status */
1832 /* TODO: Peripheral port remap register:
1833 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1834 * controller base address at $rn & ~0xfff and map size of
1835 * 0x200 << ($rn & 0xfff), when MMU is off. */
1841 /* ??? For debugging only. Should raise illegal instruction exception. */
1842 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1843 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1847 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1849 env
->banked_r13
[bank_number(mode
)] = val
;
1852 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1854 return env
->banked_r13
[bank_number(mode
)];
1857 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1861 return xpsr_read(env
) & 0xf8000000;
1863 return xpsr_read(env
) & 0xf80001ff;
1865 return xpsr_read(env
) & 0xff00fc00;
1867 return xpsr_read(env
) & 0xff00fdff;
1869 return xpsr_read(env
) & 0x000001ff;
1871 return xpsr_read(env
) & 0x0700fc00;
1873 return xpsr_read(env
) & 0x0700edff;
1875 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1877 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1878 case 16: /* PRIMASK */
1879 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1880 case 17: /* FAULTMASK */
1881 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1882 case 18: /* BASEPRI */
1883 case 19: /* BASEPRI_MAX */
1884 return env
->v7m
.basepri
;
1885 case 20: /* CONTROL */
1886 return env
->v7m
.control
;
1888 /* ??? For debugging only. */
1889 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1894 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1898 xpsr_write(env
, val
, 0xf8000000);
1901 xpsr_write(env
, val
, 0xf8000000);
1904 xpsr_write(env
, val
, 0xfe00fc00);
1907 xpsr_write(env
, val
, 0xfe00fc00);
1910 /* IPSR bits are readonly. */
1913 xpsr_write(env
, val
, 0x0600fc00);
1916 xpsr_write(env
, val
, 0x0600fc00);
1919 if (env
->v7m
.current_sp
)
1920 env
->v7m
.other_sp
= val
;
1922 env
->regs
[13] = val
;
1925 if (env
->v7m
.current_sp
)
1926 env
->regs
[13] = val
;
1928 env
->v7m
.other_sp
= val
;
1930 case 16: /* PRIMASK */
1932 env
->uncached_cpsr
|= CPSR_I
;
1934 env
->uncached_cpsr
&= ~CPSR_I
;
1936 case 17: /* FAULTMASK */
1938 env
->uncached_cpsr
|= CPSR_F
;
1940 env
->uncached_cpsr
&= ~CPSR_F
;
1942 case 18: /* BASEPRI */
1943 env
->v7m
.basepri
= val
& 0xff;
1945 case 19: /* BASEPRI_MAX */
1947 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1948 env
->v7m
.basepri
= val
;
1950 case 20: /* CONTROL */
1951 env
->v7m
.control
= val
& 3;
1952 switch_v7m_sp(env
, (val
& 2) != 0);
1955 /* ??? For debugging only. */
1956 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1961 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1962 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1965 if (cpnum
< 0 || cpnum
> 14) {
1966 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1970 env
->cp
[cpnum
].cp_read
= cp_read
;
1971 env
->cp
[cpnum
].cp_write
= cp_write
;
1972 env
->cp
[cpnum
].opaque
= opaque
;
1977 /* Note that signed overflow is undefined in C. The following routines are
1978 careful to use unsigned types where modulo arithmetic is required.
1979 Failure to do so _will_ break on newer gcc. */
1981 /* Signed saturating arithmetic. */
1983 /* Perform 16-bit signed saturating addition. */
1984 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
1989 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
1998 /* Perform 8-bit signed saturating addition. */
1999 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2004 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2013 /* Perform 16-bit signed saturating subtraction. */
2014 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2019 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2028 /* Perform 8-bit signed saturating subtraction. */
2029 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2034 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2043 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2044 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2045 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2046 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2049 #include "op_addsub.h"
2051 /* Unsigned saturating arithmetic. */
2052 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2061 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2069 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2078 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2086 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2087 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2088 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2089 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2092 #include "op_addsub.h"
2094 /* Signed modulo arithmetic. */
2095 #define SARITH16(a, b, n, op) do { \
2097 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2098 RESULT(sum, n, 16); \
2100 ge |= 3 << (n * 2); \
2103 #define SARITH8(a, b, n, op) do { \
2105 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2106 RESULT(sum, n, 8); \
2112 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2113 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2114 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2115 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2119 #include "op_addsub.h"
2121 /* Unsigned modulo arithmetic. */
2122 #define ADD16(a, b, n) do { \
2124 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2125 RESULT(sum, n, 16); \
2126 if ((sum >> 16) == 1) \
2127 ge |= 3 << (n * 2); \
2130 #define ADD8(a, b, n) do { \
2132 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2133 RESULT(sum, n, 8); \
2134 if ((sum >> 8) == 1) \
2138 #define SUB16(a, b, n) do { \
2140 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2141 RESULT(sum, n, 16); \
2142 if ((sum >> 16) == 0) \
2143 ge |= 3 << (n * 2); \
2146 #define SUB8(a, b, n) do { \
2148 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2149 RESULT(sum, n, 8); \
2150 if ((sum >> 8) == 0) \
2157 #include "op_addsub.h"
2159 /* Halved signed arithmetic. */
2160 #define ADD16(a, b, n) \
2161 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2162 #define SUB16(a, b, n) \
2163 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2164 #define ADD8(a, b, n) \
2165 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2166 #define SUB8(a, b, n) \
2167 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2170 #include "op_addsub.h"
2172 /* Halved unsigned arithmetic. */
2173 #define ADD16(a, b, n) \
2174 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2175 #define SUB16(a, b, n) \
2176 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2177 #define ADD8(a, b, n) \
2178 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2179 #define SUB8(a, b, n) \
2180 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2183 #include "op_addsub.h"
2185 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2193 /* Unsigned sum of absolute byte differences. */
2194 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2197 sum
= do_usad(a
, b
);
2198 sum
+= do_usad(a
>> 8, b
>> 8);
2199 sum
+= do_usad(a
>> 16, b
>>16);
2200 sum
+= do_usad(a
>> 24, b
>> 24);
2204 /* For ARMv6 SEL instruction. */
2205 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2218 return (a
& mask
) | (b
& ~mask
);
2221 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2223 return (val
>> 32) | (val
!= 0);
2226 /* VFP support. We follow the convention used for VFP instrunctions:
2227 Single precition routines have a "s" suffix, double precision a
2230 /* Convert host exception flags to vfp form. */
2231 static inline int vfp_exceptbits_from_host(int host_bits
)
2233 int target_bits
= 0;
2235 if (host_bits
& float_flag_invalid
)
2237 if (host_bits
& float_flag_divbyzero
)
2239 if (host_bits
& float_flag_overflow
)
2241 if (host_bits
& float_flag_underflow
)
2243 if (host_bits
& float_flag_inexact
)
2244 target_bits
|= 0x10;
2248 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2253 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2254 | (env
->vfp
.vec_len
<< 16)
2255 | (env
->vfp
.vec_stride
<< 20);
2256 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2257 fpscr
|= vfp_exceptbits_from_host(i
);
2261 /* Convert vfp exception flags to target form. */
2262 static inline int vfp_exceptbits_to_host(int target_bits
)
2266 if (target_bits
& 1)
2267 host_bits
|= float_flag_invalid
;
2268 if (target_bits
& 2)
2269 host_bits
|= float_flag_divbyzero
;
2270 if (target_bits
& 4)
2271 host_bits
|= float_flag_overflow
;
2272 if (target_bits
& 8)
2273 host_bits
|= float_flag_underflow
;
2274 if (target_bits
& 0x10)
2275 host_bits
|= float_flag_inexact
;
2279 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2284 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2285 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2286 env
->vfp
.vec_len
= (val
>> 16) & 7;
2287 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2290 if (changed
& (3 << 22)) {
2291 i
= (val
>> 22) & 3;
2294 i
= float_round_nearest_even
;
2300 i
= float_round_down
;
2303 i
= float_round_to_zero
;
2306 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2309 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2310 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2311 /* XXX: FZ and DN are not implemented. */
2314 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2316 #define VFP_BINOP(name) \
2317 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2319 return float32_ ## name (a, b, &env->vfp.fp_status); \
2321 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2323 return float64_ ## name (a, b, &env->vfp.fp_status); \
2331 float32
VFP_HELPER(neg
, s
)(float32 a
)
2333 return float32_chs(a
);
2336 float64
VFP_HELPER(neg
, d
)(float64 a
)
2338 return float64_chs(a
);
2341 float32
VFP_HELPER(abs
, s
)(float32 a
)
2343 return float32_abs(a
);
2346 float64
VFP_HELPER(abs
, d
)(float64 a
)
2348 return float64_abs(a
);
2351 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2353 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2356 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2358 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2361 /* XXX: check quiet/signaling case */
2362 #define DO_VFP_cmp(p, type) \
2363 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2366 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2367 case 0: flags = 0x6; break; \
2368 case -1: flags = 0x8; break; \
2369 case 1: flags = 0x2; break; \
2370 default: case 2: flags = 0x3; break; \
2372 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2373 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2375 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2378 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2379 case 0: flags = 0x6; break; \
2380 case -1: flags = 0x8; break; \
2381 case 1: flags = 0x2; break; \
2382 default: case 2: flags = 0x3; break; \
2384 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2385 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2387 DO_VFP_cmp(s
, float32
)
2388 DO_VFP_cmp(d
, float64
)
2391 /* Helper routines to perform bitwise copies between float and int. */
2392 static inline float32
vfp_itos(uint32_t i
)
2403 static inline uint32_t vfp_stoi(float32 s
)
2414 static inline float64
vfp_itod(uint64_t i
)
2425 static inline uint64_t vfp_dtoi(float64 d
)
2436 /* Integer to float conversion. */
2437 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2439 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2442 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2444 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2447 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2449 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2452 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2454 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2457 /* Float to integer conversion. */
2458 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2460 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2463 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2465 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2468 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2470 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2473 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2475 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2478 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2480 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2483 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2485 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2488 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2490 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2493 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2495 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2498 /* floating point conversion */
2499 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2501 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2504 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2506 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2509 /* VFP3 fixed point conversion. */
2510 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2511 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2514 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2515 &env->vfp.fp_status); \
2516 return ftype##_scalbn(tmp, shift, &env->vfp.fp_status); \
2518 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2521 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2522 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2523 &env->vfp.fp_status)); \
2526 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2527 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2528 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2529 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2530 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2531 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2532 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2533 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2536 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2538 float_status
*s
= &env
->vfp
.fp_status
;
2539 float32 two
= int32_to_float32(2, s
);
2540 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2543 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2545 float_status
*s
= &env
->vfp
.fp_status
;
2546 float32 three
= int32_to_float32(3, s
);
2547 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2552 /* TODO: The architecture specifies the value that the estimate functions
2553 should return. We return the exact reciprocal/root instead. */
2554 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2556 float_status
*s
= &env
->vfp
.fp_status
;
2557 float32 one
= int32_to_float32(1, s
);
2558 return float32_div(one
, a
, s
);
2561 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2563 float_status
*s
= &env
->vfp
.fp_status
;
2564 float32 one
= int32_to_float32(1, s
);
2565 return float32_div(one
, float32_sqrt(a
, s
), s
);
2568 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2570 float_status
*s
= &env
->vfp
.fp_status
;
2572 tmp
= int32_to_float32(a
, s
);
2573 tmp
= float32_scalbn(tmp
, -32, s
);
2574 tmp
= helper_recpe_f32(tmp
, env
);
2575 tmp
= float32_scalbn(tmp
, 31, s
);
2576 return float32_to_int32(tmp
, s
);
2579 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2581 float_status
*s
= &env
->vfp
.fp_status
;
2583 tmp
= int32_to_float32(a
, s
);
2584 tmp
= float32_scalbn(tmp
, -32, s
);
2585 tmp
= helper_rsqrte_f32(tmp
, env
);
2586 tmp
= float32_scalbn(tmp
, 31, s
);
2587 return float32_to_int32(tmp
, s
);