]>
git.proxmox.com Git - qemu.git/blob - target-arm/helper.c
9 #include "qemu-common.h"
10 #include "host-utils.h"
12 static uint32_t cortexa9_cp15_c0_c1
[8] =
13 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
15 static uint32_t cortexa9_cp15_c0_c2
[8] =
16 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
18 static uint32_t cortexa8_cp15_c0_c1
[8] =
19 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
21 static uint32_t cortexa8_cp15_c0_c2
[8] =
22 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
24 static uint32_t mpcore_cp15_c0_c1
[8] =
25 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
27 static uint32_t mpcore_cp15_c0_c2
[8] =
28 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
30 static uint32_t arm1136_cp15_c0_c1
[8] =
31 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
33 static uint32_t arm1136_cp15_c0_c2
[8] =
34 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
36 static uint32_t cpu_arm_find_by_name(const char *name
);
38 static inline void set_feature(CPUARMState
*env
, int feature
)
40 env
->features
|= 1u << feature
;
43 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
45 env
->cp15
.c0_cpuid
= id
;
47 case ARM_CPUID_ARM926
:
48 set_feature(env
, ARM_FEATURE_VFP
);
49 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
50 env
->cp15
.c0_cachetype
= 0x1dd20d2;
51 env
->cp15
.c1_sys
= 0x00090078;
53 case ARM_CPUID_ARM946
:
54 set_feature(env
, ARM_FEATURE_MPU
);
55 env
->cp15
.c0_cachetype
= 0x0f004006;
56 env
->cp15
.c1_sys
= 0x00000078;
58 case ARM_CPUID_ARM1026
:
59 set_feature(env
, ARM_FEATURE_VFP
);
60 set_feature(env
, ARM_FEATURE_AUXCR
);
61 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
62 env
->cp15
.c0_cachetype
= 0x1dd20d2;
63 env
->cp15
.c1_sys
= 0x00090078;
65 case ARM_CPUID_ARM1136_R2
:
66 case ARM_CPUID_ARM1136
:
67 set_feature(env
, ARM_FEATURE_V6
);
68 set_feature(env
, ARM_FEATURE_VFP
);
69 set_feature(env
, ARM_FEATURE_AUXCR
);
70 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
71 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
72 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
73 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
74 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
75 env
->cp15
.c0_cachetype
= 0x1dd20d2;
77 case ARM_CPUID_ARM11MPCORE
:
78 set_feature(env
, ARM_FEATURE_V6
);
79 set_feature(env
, ARM_FEATURE_V6K
);
80 set_feature(env
, ARM_FEATURE_VFP
);
81 set_feature(env
, ARM_FEATURE_AUXCR
);
82 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
83 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
84 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
85 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
86 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
87 env
->cp15
.c0_cachetype
= 0x1dd20d2;
89 case ARM_CPUID_CORTEXA8
:
90 set_feature(env
, ARM_FEATURE_V6
);
91 set_feature(env
, ARM_FEATURE_V6K
);
92 set_feature(env
, ARM_FEATURE_V7
);
93 set_feature(env
, ARM_FEATURE_AUXCR
);
94 set_feature(env
, ARM_FEATURE_THUMB2
);
95 set_feature(env
, ARM_FEATURE_VFP
);
96 set_feature(env
, ARM_FEATURE_VFP3
);
97 set_feature(env
, ARM_FEATURE_NEON
);
98 set_feature(env
, ARM_FEATURE_THUMB2EE
);
99 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
100 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
101 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
102 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
103 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
104 env
->cp15
.c0_cachetype
= 0x82048004;
105 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
106 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
107 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
108 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
110 case ARM_CPUID_CORTEXA9
:
111 set_feature(env
, ARM_FEATURE_V6
);
112 set_feature(env
, ARM_FEATURE_V6K
);
113 set_feature(env
, ARM_FEATURE_V7
);
114 set_feature(env
, ARM_FEATURE_AUXCR
);
115 set_feature(env
, ARM_FEATURE_THUMB2
);
116 set_feature(env
, ARM_FEATURE_VFP
);
117 set_feature(env
, ARM_FEATURE_VFP3
);
118 set_feature(env
, ARM_FEATURE_VFP_FP16
);
119 set_feature(env
, ARM_FEATURE_NEON
);
120 set_feature(env
, ARM_FEATURE_THUMB2EE
);
121 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41034000; /* Guess */
122 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
123 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
124 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
125 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
126 env
->cp15
.c0_cachetype
= 0x80038003;
127 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
128 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
129 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
131 case ARM_CPUID_CORTEXM3
:
132 set_feature(env
, ARM_FEATURE_V6
);
133 set_feature(env
, ARM_FEATURE_THUMB2
);
134 set_feature(env
, ARM_FEATURE_V7
);
135 set_feature(env
, ARM_FEATURE_M
);
136 set_feature(env
, ARM_FEATURE_DIV
);
138 case ARM_CPUID_ANY
: /* For userspace emulation. */
139 set_feature(env
, ARM_FEATURE_V6
);
140 set_feature(env
, ARM_FEATURE_V6K
);
141 set_feature(env
, ARM_FEATURE_V7
);
142 set_feature(env
, ARM_FEATURE_THUMB2
);
143 set_feature(env
, ARM_FEATURE_VFP
);
144 set_feature(env
, ARM_FEATURE_VFP3
);
145 set_feature(env
, ARM_FEATURE_VFP_FP16
);
146 set_feature(env
, ARM_FEATURE_NEON
);
147 set_feature(env
, ARM_FEATURE_THUMB2EE
);
148 set_feature(env
, ARM_FEATURE_DIV
);
150 case ARM_CPUID_TI915T
:
151 case ARM_CPUID_TI925T
:
152 set_feature(env
, ARM_FEATURE_OMAPCP
);
153 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
154 env
->cp15
.c0_cachetype
= 0x5109149;
155 env
->cp15
.c1_sys
= 0x00000070;
156 env
->cp15
.c15_i_max
= 0x000;
157 env
->cp15
.c15_i_min
= 0xff0;
159 case ARM_CPUID_PXA250
:
160 case ARM_CPUID_PXA255
:
161 case ARM_CPUID_PXA260
:
162 case ARM_CPUID_PXA261
:
163 case ARM_CPUID_PXA262
:
164 set_feature(env
, ARM_FEATURE_XSCALE
);
165 /* JTAG_ID is ((id << 28) | 0x09265013) */
166 env
->cp15
.c0_cachetype
= 0xd172172;
167 env
->cp15
.c1_sys
= 0x00000078;
169 case ARM_CPUID_PXA270_A0
:
170 case ARM_CPUID_PXA270_A1
:
171 case ARM_CPUID_PXA270_B0
:
172 case ARM_CPUID_PXA270_B1
:
173 case ARM_CPUID_PXA270_C0
:
174 case ARM_CPUID_PXA270_C5
:
175 set_feature(env
, ARM_FEATURE_XSCALE
);
176 /* JTAG_ID is ((id << 28) | 0x09265013) */
177 set_feature(env
, ARM_FEATURE_IWMMXT
);
178 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
179 env
->cp15
.c0_cachetype
= 0xd172172;
180 env
->cp15
.c1_sys
= 0x00000078;
183 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
188 void cpu_reset(CPUARMState
*env
)
192 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
193 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
194 log_cpu_state(env
, 0);
197 id
= env
->cp15
.c0_cpuid
;
198 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
200 cpu_reset_model_id(env
, id
);
201 #if defined (CONFIG_USER_ONLY)
202 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
203 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
205 /* SVC mode with interrupts disabled. */
206 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
207 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
210 env
->uncached_cpsr
&= ~CPSR_I
;
211 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
212 env
->cp15
.c2_base_mask
= 0xffffc000u
;
218 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
222 /* VFP data registers are always little-endian. */
223 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
225 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
228 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
229 /* Aliases for Q regs. */
232 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
233 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
237 switch (reg
- nregs
) {
238 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
239 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
240 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
245 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
249 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
251 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
254 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
257 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
258 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
262 switch (reg
- nregs
) {
263 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
264 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
265 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
270 CPUARMState
*cpu_arm_init(const char *cpu_model
)
274 static int inited
= 0;
276 id
= cpu_arm_find_by_name(cpu_model
);
279 env
= qemu_mallocz(sizeof(CPUARMState
));
283 arm_translate_init();
286 env
->cpu_model_str
= cpu_model
;
287 env
->cp15
.c0_cpuid
= id
;
289 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
290 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
291 51, "arm-neon.xml", 0);
292 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
293 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
294 35, "arm-vfp3.xml", 0);
295 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
296 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
297 19, "arm-vfp.xml", 0);
308 static const struct arm_cpu_t arm_cpu_names
[] = {
309 { ARM_CPUID_ARM926
, "arm926"},
310 { ARM_CPUID_ARM946
, "arm946"},
311 { ARM_CPUID_ARM1026
, "arm1026"},
312 { ARM_CPUID_ARM1136
, "arm1136"},
313 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
314 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
315 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
316 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
317 { ARM_CPUID_CORTEXA9
, "cortex-a9"},
318 { ARM_CPUID_TI925T
, "ti925t" },
319 { ARM_CPUID_PXA250
, "pxa250" },
320 { ARM_CPUID_PXA255
, "pxa255" },
321 { ARM_CPUID_PXA260
, "pxa260" },
322 { ARM_CPUID_PXA261
, "pxa261" },
323 { ARM_CPUID_PXA262
, "pxa262" },
324 { ARM_CPUID_PXA270
, "pxa270" },
325 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
326 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
327 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
328 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
329 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
330 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
331 { ARM_CPUID_ANY
, "any"},
335 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
339 (*cpu_fprintf
)(f
, "Available CPUs:\n");
340 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
341 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
345 /* return 0 if not found */
346 static uint32_t cpu_arm_find_by_name(const char *name
)
352 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
353 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
354 id
= arm_cpu_names
[i
].id
;
361 void cpu_arm_close(CPUARMState
*env
)
366 uint32_t cpsr_read(CPUARMState
*env
)
370 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
371 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
372 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
373 | ((env
->condexec_bits
& 0xfc) << 8)
377 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
379 if (mask
& CPSR_NZCV
) {
380 env
->ZF
= (~val
) & CPSR_Z
;
382 env
->CF
= (val
>> 29) & 1;
383 env
->VF
= (val
<< 3) & 0x80000000;
386 env
->QF
= ((val
& CPSR_Q
) != 0);
388 env
->thumb
= ((val
& CPSR_T
) != 0);
389 if (mask
& CPSR_IT_0_1
) {
390 env
->condexec_bits
&= ~3;
391 env
->condexec_bits
|= (val
>> 25) & 3;
393 if (mask
& CPSR_IT_2_7
) {
394 env
->condexec_bits
&= 3;
395 env
->condexec_bits
|= (val
>> 8) & 0xfc;
397 if (mask
& CPSR_GE
) {
398 env
->GE
= (val
>> 16) & 0xf;
401 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
402 switch_mode(env
, val
& CPSR_M
);
404 mask
&= ~CACHED_CPSR_BITS
;
405 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
408 /* Sign/zero extend */
409 uint32_t HELPER(sxtb16
)(uint32_t x
)
412 res
= (uint16_t)(int8_t)x
;
413 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
417 uint32_t HELPER(uxtb16
)(uint32_t x
)
420 res
= (uint16_t)(uint8_t)x
;
421 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
425 uint32_t HELPER(clz
)(uint32_t x
)
430 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
434 if (num
== INT_MIN
&& den
== -1)
439 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
446 uint32_t HELPER(rbit
)(uint32_t x
)
448 x
= ((x
& 0xff000000) >> 24)
449 | ((x
& 0x00ff0000) >> 8)
450 | ((x
& 0x0000ff00) << 8)
451 | ((x
& 0x000000ff) << 24);
452 x
= ((x
& 0xf0f0f0f0) >> 4)
453 | ((x
& 0x0f0f0f0f) << 4);
454 x
= ((x
& 0x88888888) >> 3)
455 | ((x
& 0x44444444) >> 1)
456 | ((x
& 0x22222222) << 1)
457 | ((x
& 0x11111111) << 3);
461 uint32_t HELPER(abs
)(uint32_t x
)
463 return ((int32_t)x
< 0) ? -x
: x
;
466 #if defined(CONFIG_USER_ONLY)
468 void do_interrupt (CPUState
*env
)
470 env
->exception_index
= -1;
473 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
474 int mmu_idx
, int is_softmmu
)
477 env
->exception_index
= EXCP_PREFETCH_ABORT
;
478 env
->cp15
.c6_insn
= address
;
480 env
->exception_index
= EXCP_DATA_ABORT
;
481 env
->cp15
.c6_data
= address
;
486 /* These should probably raise undefined insn exceptions. */
487 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
489 int op1
= (insn
>> 8) & 0xf;
490 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
494 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
496 int op1
= (insn
>> 8) & 0xf;
497 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
501 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
503 cpu_abort(env
, "cp15 insn %08x\n", insn
);
506 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
508 cpu_abort(env
, "cp15 insn %08x\n", insn
);
511 /* These should probably raise undefined insn exceptions. */
512 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
514 cpu_abort(env
, "v7m_mrs %d\n", reg
);
517 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
519 cpu_abort(env
, "v7m_mrs %d\n", reg
);
523 void switch_mode(CPUState
*env
, int mode
)
525 if (mode
!= ARM_CPU_MODE_USR
)
526 cpu_abort(env
, "Tried to switch out of user mode\n");
529 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
531 cpu_abort(env
, "banked r13 write\n");
534 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
536 cpu_abort(env
, "banked r13 read\n");
542 extern int semihosting_enabled
;
544 /* Map CPU modes onto saved register banks. */
545 static inline int bank_number (int mode
)
548 case ARM_CPU_MODE_USR
:
549 case ARM_CPU_MODE_SYS
:
551 case ARM_CPU_MODE_SVC
:
553 case ARM_CPU_MODE_ABT
:
555 case ARM_CPU_MODE_UND
:
557 case ARM_CPU_MODE_IRQ
:
559 case ARM_CPU_MODE_FIQ
:
562 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
566 void switch_mode(CPUState
*env
, int mode
)
571 old_mode
= env
->uncached_cpsr
& CPSR_M
;
572 if (mode
== old_mode
)
575 if (old_mode
== ARM_CPU_MODE_FIQ
) {
576 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
577 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
578 } else if (mode
== ARM_CPU_MODE_FIQ
) {
579 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
580 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
583 i
= bank_number(old_mode
);
584 env
->banked_r13
[i
] = env
->regs
[13];
585 env
->banked_r14
[i
] = env
->regs
[14];
586 env
->banked_spsr
[i
] = env
->spsr
;
588 i
= bank_number(mode
);
589 env
->regs
[13] = env
->banked_r13
[i
];
590 env
->regs
[14] = env
->banked_r14
[i
];
591 env
->spsr
= env
->banked_spsr
[i
];
594 static void v7m_push(CPUARMState
*env
, uint32_t val
)
597 stl_phys(env
->regs
[13], val
);
600 static uint32_t v7m_pop(CPUARMState
*env
)
603 val
= ldl_phys(env
->regs
[13]);
608 /* Switch to V7M main or process stack pointer. */
609 static void switch_v7m_sp(CPUARMState
*env
, int process
)
612 if (env
->v7m
.current_sp
!= process
) {
613 tmp
= env
->v7m
.other_sp
;
614 env
->v7m
.other_sp
= env
->regs
[13];
616 env
->v7m
.current_sp
= process
;
620 static void do_v7m_exception_exit(CPUARMState
*env
)
625 type
= env
->regs
[15];
626 if (env
->v7m
.exception
!= 0)
627 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
629 /* Switch to the target stack. */
630 switch_v7m_sp(env
, (type
& 4) != 0);
632 env
->regs
[0] = v7m_pop(env
);
633 env
->regs
[1] = v7m_pop(env
);
634 env
->regs
[2] = v7m_pop(env
);
635 env
->regs
[3] = v7m_pop(env
);
636 env
->regs
[12] = v7m_pop(env
);
637 env
->regs
[14] = v7m_pop(env
);
638 env
->regs
[15] = v7m_pop(env
);
640 xpsr_write(env
, xpsr
, 0xfffffdff);
641 /* Undo stack alignment. */
644 /* ??? The exception return type specifies Thread/Handler mode. However
645 this is also implied by the xPSR value. Not sure what to do
646 if there is a mismatch. */
647 /* ??? Likewise for mismatches between the CONTROL register and the stack
651 static void do_interrupt_v7m(CPUARMState
*env
)
653 uint32_t xpsr
= xpsr_read(env
);
658 if (env
->v7m
.current_sp
)
660 if (env
->v7m
.exception
== 0)
663 /* For exceptions we just mark as pending on the NVIC, and let that
665 /* TODO: Need to escalate if the current priority is higher than the
666 one we're raising. */
667 switch (env
->exception_index
) {
669 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
673 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
675 case EXCP_PREFETCH_ABORT
:
676 case EXCP_DATA_ABORT
:
677 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
680 if (semihosting_enabled
) {
682 nr
= lduw_code(env
->regs
[15]) & 0xff;
685 env
->regs
[0] = do_arm_semihosting(env
);
689 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
692 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
694 case EXCP_EXCEPTION_EXIT
:
695 do_v7m_exception_exit(env
);
698 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
699 return; /* Never happens. Keep compiler happy. */
702 /* Align stack pointer. */
703 /* ??? Should only do this if Configuration Control Register
704 STACKALIGN bit is set. */
705 if (env
->regs
[13] & 4) {
709 /* Switch to the handler mode. */
711 v7m_push(env
, env
->regs
[15]);
712 v7m_push(env
, env
->regs
[14]);
713 v7m_push(env
, env
->regs
[12]);
714 v7m_push(env
, env
->regs
[3]);
715 v7m_push(env
, env
->regs
[2]);
716 v7m_push(env
, env
->regs
[1]);
717 v7m_push(env
, env
->regs
[0]);
718 switch_v7m_sp(env
, 0);
719 env
->uncached_cpsr
&= ~CPSR_IT
;
721 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
722 env
->regs
[15] = addr
& 0xfffffffe;
723 env
->thumb
= addr
& 1;
726 /* Handle a CPU exception. */
727 void do_interrupt(CPUARMState
*env
)
735 do_interrupt_v7m(env
);
738 /* TODO: Vectored interrupt controller. */
739 switch (env
->exception_index
) {
741 new_mode
= ARM_CPU_MODE_UND
;
750 if (semihosting_enabled
) {
751 /* Check for semihosting interrupt. */
753 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
755 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
757 /* Only intercept calls from privileged modes, to provide some
758 semblance of security. */
759 if (((mask
== 0x123456 && !env
->thumb
)
760 || (mask
== 0xab && env
->thumb
))
761 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
762 env
->regs
[0] = do_arm_semihosting(env
);
766 new_mode
= ARM_CPU_MODE_SVC
;
769 /* The PC already points to the next instruction. */
773 /* See if this is a semihosting syscall. */
774 if (env
->thumb
&& semihosting_enabled
) {
775 mask
= lduw_code(env
->regs
[15]) & 0xff;
777 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
779 env
->regs
[0] = do_arm_semihosting(env
);
783 /* Fall through to prefetch abort. */
784 case EXCP_PREFETCH_ABORT
:
785 new_mode
= ARM_CPU_MODE_ABT
;
787 mask
= CPSR_A
| CPSR_I
;
790 case EXCP_DATA_ABORT
:
791 new_mode
= ARM_CPU_MODE_ABT
;
793 mask
= CPSR_A
| CPSR_I
;
797 new_mode
= ARM_CPU_MODE_IRQ
;
799 /* Disable IRQ and imprecise data aborts. */
800 mask
= CPSR_A
| CPSR_I
;
804 new_mode
= ARM_CPU_MODE_FIQ
;
806 /* Disable FIQ, IRQ and imprecise data aborts. */
807 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
811 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
812 return; /* Never happens. Keep compiler happy. */
815 if (env
->cp15
.c1_sys
& (1 << 13)) {
818 switch_mode (env
, new_mode
);
819 env
->spsr
= cpsr_read(env
);
821 env
->condexec_bits
= 0;
822 /* Switch to the new mode, and to the correct instruction set. */
823 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
824 env
->uncached_cpsr
|= mask
;
825 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
826 env
->regs
[14] = env
->regs
[15] + offset
;
827 env
->regs
[15] = addr
;
828 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
831 /* Check section/page access permissions.
832 Returns the page protection flags, or zero if the access is not
834 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
840 return PAGE_READ
| PAGE_WRITE
;
842 if (access_type
== 1)
849 if (access_type
== 1)
851 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
853 return is_user
? 0 : PAGE_READ
;
860 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
865 return PAGE_READ
| PAGE_WRITE
;
867 return PAGE_READ
| PAGE_WRITE
;
868 case 4: /* Reserved. */
871 return is_user
? 0 : prot_ro
;
875 if (!arm_feature (env
, ARM_FEATURE_V7
))
883 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
887 if (address
& env
->cp15
.c2_mask
)
888 table
= env
->cp15
.c2_base1
& 0xffffc000;
890 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
892 table
|= (address
>> 18) & 0x3ffc;
896 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
897 int is_user
, uint32_t *phys_ptr
, int *prot
)
907 /* Pagetable walk. */
908 /* Lookup l1 descriptor. */
909 table
= get_level1_table_address(env
, address
);
910 desc
= ldl_phys(table
);
912 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
914 /* Section translation fault. */
918 if (domain
== 0 || domain
== 2) {
920 code
= 9; /* Section domain fault. */
922 code
= 11; /* Page domain fault. */
927 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
928 ap
= (desc
>> 10) & 3;
931 /* Lookup l2 entry. */
933 /* Coarse pagetable. */
934 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
936 /* Fine pagetable. */
937 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
939 desc
= ldl_phys(table
);
941 case 0: /* Page translation fault. */
944 case 1: /* 64k page. */
945 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
946 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
948 case 2: /* 4k page. */
949 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
950 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
952 case 3: /* 1k page. */
954 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
955 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
957 /* Page translation fault. */
962 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
964 ap
= (desc
>> 4) & 3;
967 /* Never happens, but compiler isn't smart enough to tell. */
972 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
974 /* Access permission fault. */
977 *phys_ptr
= phys_addr
;
980 return code
| (domain
<< 4);
983 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
984 int is_user
, uint32_t *phys_ptr
, int *prot
)
995 /* Pagetable walk. */
996 /* Lookup l1 descriptor. */
997 table
= get_level1_table_address(env
, address
);
998 desc
= ldl_phys(table
);
1001 /* Section translation fault. */
1005 } else if (type
== 2 && (desc
& (1 << 18))) {
1009 /* Section or page. */
1010 domain
= (desc
>> 4) & 0x1e;
1012 domain
= (env
->cp15
.c3
>> domain
) & 3;
1013 if (domain
== 0 || domain
== 2) {
1015 code
= 9; /* Section domain fault. */
1017 code
= 11; /* Page domain fault. */
1021 if (desc
& (1 << 18)) {
1023 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1026 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1028 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1029 xn
= desc
& (1 << 4);
1032 /* Lookup l2 entry. */
1033 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1034 desc
= ldl_phys(table
);
1035 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1037 case 0: /* Page translation fault. */
1040 case 1: /* 64k page. */
1041 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1042 xn
= desc
& (1 << 15);
1044 case 2: case 3: /* 4k page. */
1045 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1049 /* Never happens, but compiler isn't smart enough to tell. */
1054 if (xn
&& access_type
== 2)
1057 /* The simplified model uses AP[0] as an access control bit. */
1058 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1059 /* Access flag fault. */
1060 code
= (code
== 15) ? 6 : 3;
1063 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1065 /* Access permission fault. */
1068 *phys_ptr
= phys_addr
;
1071 return code
| (domain
<< 4);
1074 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1075 int is_user
, uint32_t *phys_ptr
, int *prot
)
1081 *phys_ptr
= address
;
1082 for (n
= 7; n
>= 0; n
--) {
1083 base
= env
->cp15
.c6_region
[n
];
1084 if ((base
& 1) == 0)
1086 mask
= 1 << ((base
>> 1) & 0x1f);
1087 /* Keep this shift separate from the above to avoid an
1088 (undefined) << 32. */
1089 mask
= (mask
<< 1) - 1;
1090 if (((base
^ address
) & ~mask
) == 0)
1096 if (access_type
== 2) {
1097 mask
= env
->cp15
.c5_insn
;
1099 mask
= env
->cp15
.c5_data
;
1101 mask
= (mask
>> (n
* 4)) & 0xf;
1108 *prot
= PAGE_READ
| PAGE_WRITE
;
1113 *prot
|= PAGE_WRITE
;
1116 *prot
= PAGE_READ
| PAGE_WRITE
;
1127 /* Bad permission. */
1133 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1134 int access_type
, int is_user
,
1135 uint32_t *phys_ptr
, int *prot
)
1137 /* Fast Context Switch Extension. */
1138 if (address
< 0x02000000)
1139 address
+= env
->cp15
.c13_fcse
;
1141 if ((env
->cp15
.c1_sys
& 1) == 0) {
1142 /* MMU/MPU disabled. */
1143 *phys_ptr
= address
;
1144 *prot
= PAGE_READ
| PAGE_WRITE
;
1146 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1147 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1149 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1150 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1153 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1158 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1159 int access_type
, int mmu_idx
, int is_softmmu
)
1165 is_user
= mmu_idx
== MMU_USER_IDX
;
1166 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1168 /* Map a single [sub]page. */
1169 phys_addr
&= ~(uint32_t)0x3ff;
1170 address
&= ~(uint32_t)0x3ff;
1171 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1175 if (access_type
== 2) {
1176 env
->cp15
.c5_insn
= ret
;
1177 env
->cp15
.c6_insn
= address
;
1178 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1180 env
->cp15
.c5_data
= ret
;
1181 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1182 env
->cp15
.c5_data
|= (1 << 11);
1183 env
->cp15
.c6_data
= address
;
1184 env
->exception_index
= EXCP_DATA_ABORT
;
1189 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1195 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1203 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1205 int cp_num
= (insn
>> 8) & 0xf;
1206 int cp_info
= (insn
>> 5) & 7;
1207 int src
= (insn
>> 16) & 0xf;
1208 int operand
= insn
& 0xf;
1210 if (env
->cp
[cp_num
].cp_write
)
1211 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1212 cp_info
, src
, operand
, val
);
1215 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1217 int cp_num
= (insn
>> 8) & 0xf;
1218 int cp_info
= (insn
>> 5) & 7;
1219 int dest
= (insn
>> 16) & 0xf;
1220 int operand
= insn
& 0xf;
1222 if (env
->cp
[cp_num
].cp_read
)
1223 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1224 cp_info
, dest
, operand
);
1228 /* Return basic MPU access permission bits. */
1229 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1236 for (i
= 0; i
< 16; i
+= 2) {
1237 ret
|= (val
>> i
) & mask
;
1243 /* Pad basic MPU access permission bits to extended format. */
1244 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1251 for (i
= 0; i
< 16; i
+= 2) {
1252 ret
|= (val
& mask
) << i
;
1258 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1264 op1
= (insn
>> 21) & 7;
1265 op2
= (insn
>> 5) & 7;
1267 switch ((insn
>> 16) & 0xf) {
1270 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1272 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1274 if (arm_feature(env
, ARM_FEATURE_V7
)
1275 && op1
== 2 && crm
== 0 && op2
== 0) {
1276 env
->cp15
.c0_cssel
= val
& 0xf;
1280 case 1: /* System configuration. */
1281 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1285 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1286 env
->cp15
.c1_sys
= val
;
1287 /* ??? Lots of these bits are not implemented. */
1288 /* This may enable/disable the MMU, so do a TLB flush. */
1291 case 1: /* Auxiliary cotrol register. */
1292 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1293 env
->cp15
.c1_xscaleauxcr
= val
;
1296 /* Not implemented. */
1299 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1301 if (env
->cp15
.c1_coproc
!= val
) {
1302 env
->cp15
.c1_coproc
= val
;
1303 /* ??? Is this safe when called from within a TB? */
1311 case 2: /* MMU Page table control / MPU cache control. */
1312 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1315 env
->cp15
.c2_data
= val
;
1318 env
->cp15
.c2_insn
= val
;
1326 env
->cp15
.c2_base0
= val
;
1329 env
->cp15
.c2_base1
= val
;
1333 env
->cp15
.c2_control
= val
;
1334 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1335 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1342 case 3: /* MMU Domain access control / MPU write buffer control. */
1344 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1346 case 4: /* Reserved. */
1348 case 5: /* MMU Fault status / MPU access permission. */
1349 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1353 if (arm_feature(env
, ARM_FEATURE_MPU
))
1354 val
= extended_mpu_ap_bits(val
);
1355 env
->cp15
.c5_data
= val
;
1358 if (arm_feature(env
, ARM_FEATURE_MPU
))
1359 val
= extended_mpu_ap_bits(val
);
1360 env
->cp15
.c5_insn
= val
;
1363 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1365 env
->cp15
.c5_data
= val
;
1368 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1370 env
->cp15
.c5_insn
= val
;
1376 case 6: /* MMU Fault address / MPU base/size. */
1377 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1380 env
->cp15
.c6_region
[crm
] = val
;
1382 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1386 env
->cp15
.c6_data
= val
;
1388 case 1: /* ??? This is WFAR on armv6 */
1390 env
->cp15
.c6_insn
= val
;
1397 case 7: /* Cache control. */
1398 env
->cp15
.c15_i_max
= 0x000;
1399 env
->cp15
.c15_i_min
= 0xff0;
1400 /* No cache, so nothing to do. */
1401 /* ??? MPCore has VA to PA translation functions. */
1403 case 8: /* MMU TLB control. */
1405 case 0: /* Invalidate all. */
1408 case 1: /* Invalidate single TLB entry. */
1410 /* ??? This is wrong for large pages and sections. */
1411 /* As an ugly hack to make linux work we always flush a 4K
1414 tlb_flush_page(env
, val
);
1415 tlb_flush_page(env
, val
+ 0x400);
1416 tlb_flush_page(env
, val
+ 0x800);
1417 tlb_flush_page(env
, val
+ 0xc00);
1422 case 2: /* Invalidate on ASID. */
1423 tlb_flush(env
, val
== 0);
1425 case 3: /* Invalidate single entry on MVA. */
1426 /* ??? This is like case 1, but ignores ASID. */
1434 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1437 case 0: /* Cache lockdown. */
1439 case 0: /* L1 cache. */
1442 env
->cp15
.c9_data
= val
;
1445 env
->cp15
.c9_insn
= val
;
1451 case 1: /* L2 cache. */
1452 /* Ignore writes to L2 lockdown/auxiliary registers. */
1458 case 1: /* TCM memory region registers. */
1459 /* Not implemented. */
1465 case 10: /* MMU TLB lockdown. */
1466 /* ??? TLB lockdown not implemented. */
1468 case 12: /* Reserved. */
1470 case 13: /* Process ID. */
1473 /* Unlike real hardware the qemu TLB uses virtual addresses,
1474 not modified virtual addresses, so this causes a TLB flush.
1476 if (env
->cp15
.c13_fcse
!= val
)
1478 env
->cp15
.c13_fcse
= val
;
1481 /* This changes the ASID, so do a TLB flush. */
1482 if (env
->cp15
.c13_context
!= val
1483 && !arm_feature(env
, ARM_FEATURE_MPU
))
1485 env
->cp15
.c13_context
= val
;
1491 case 14: /* Reserved. */
1493 case 15: /* Implementation specific. */
1494 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1495 if (op2
== 0 && crm
== 1) {
1496 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1497 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1499 env
->cp15
.c15_cpar
= val
& 0x3fff;
1505 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1509 case 1: /* Set TI925T configuration. */
1510 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1511 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1512 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1514 case 2: /* Set I_max. */
1515 env
->cp15
.c15_i_max
= val
;
1517 case 3: /* Set I_min. */
1518 env
->cp15
.c15_i_min
= val
;
1520 case 4: /* Set thread-ID. */
1521 env
->cp15
.c15_threadid
= val
& 0xffff;
1523 case 8: /* Wait-for-interrupt (deprecated). */
1524 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1534 /* ??? For debugging only. Should raise illegal instruction exception. */
1535 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1536 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1539 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1545 op1
= (insn
>> 21) & 7;
1546 op2
= (insn
>> 5) & 7;
1548 switch ((insn
>> 16) & 0xf) {
1549 case 0: /* ID codes. */
1555 case 0: /* Device ID. */
1556 return env
->cp15
.c0_cpuid
;
1557 case 1: /* Cache Type. */
1558 return env
->cp15
.c0_cachetype
;
1559 case 2: /* TCM status. */
1561 case 3: /* TLB type register. */
1562 return 0; /* No lockable TLB entries. */
1563 case 5: /* CPU ID */
1564 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1565 return env
->cpu_index
| 0x80000900;
1567 return env
->cpu_index
;
1573 if (!arm_feature(env
, ARM_FEATURE_V6
))
1575 return env
->cp15
.c0_c1
[op2
];
1577 if (!arm_feature(env
, ARM_FEATURE_V6
))
1579 return env
->cp15
.c0_c2
[op2
];
1580 case 3: case 4: case 5: case 6: case 7:
1586 /* These registers aren't documented on arm11 cores. However
1587 Linux looks at them anyway. */
1588 if (!arm_feature(env
, ARM_FEATURE_V6
))
1592 if (!arm_feature(env
, ARM_FEATURE_V7
))
1597 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1599 return env
->cp15
.c0_clid
;
1605 if (op2
!= 0 || crm
!= 0)
1607 return env
->cp15
.c0_cssel
;
1611 case 1: /* System configuration. */
1612 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1615 case 0: /* Control register. */
1616 return env
->cp15
.c1_sys
;
1617 case 1: /* Auxiliary control register. */
1618 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1619 return env
->cp15
.c1_xscaleauxcr
;
1620 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1622 switch (ARM_CPUID(env
)) {
1623 case ARM_CPUID_ARM1026
:
1625 case ARM_CPUID_ARM1136
:
1626 case ARM_CPUID_ARM1136_R2
:
1628 case ARM_CPUID_ARM11MPCORE
:
1630 case ARM_CPUID_CORTEXA8
:
1632 case ARM_CPUID_CORTEXA9
:
1637 case 2: /* Coprocessor access register. */
1638 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1640 return env
->cp15
.c1_coproc
;
1644 case 2: /* MMU Page table control / MPU cache control. */
1645 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1648 return env
->cp15
.c2_data
;
1651 return env
->cp15
.c2_insn
;
1659 return env
->cp15
.c2_base0
;
1661 return env
->cp15
.c2_base1
;
1663 return env
->cp15
.c2_control
;
1668 case 3: /* MMU Domain access control / MPU write buffer control. */
1669 return env
->cp15
.c3
;
1670 case 4: /* Reserved. */
1672 case 5: /* MMU Fault status / MPU access permission. */
1673 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1677 if (arm_feature(env
, ARM_FEATURE_MPU
))
1678 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1679 return env
->cp15
.c5_data
;
1681 if (arm_feature(env
, ARM_FEATURE_MPU
))
1682 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1683 return env
->cp15
.c5_insn
;
1685 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1687 return env
->cp15
.c5_data
;
1689 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1691 return env
->cp15
.c5_insn
;
1695 case 6: /* MMU Fault address. */
1696 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1699 return env
->cp15
.c6_region
[crm
];
1701 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1705 return env
->cp15
.c6_data
;
1707 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1708 /* Watchpoint Fault Adrress. */
1709 return 0; /* Not implemented. */
1711 /* Instruction Fault Adrress. */
1712 /* Arm9 doesn't have an IFAR, but implementing it anyway
1713 shouldn't do any harm. */
1714 return env
->cp15
.c6_insn
;
1717 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1718 /* Instruction Fault Adrress. */
1719 return env
->cp15
.c6_insn
;
1727 case 7: /* Cache control. */
1728 /* FIXME: Should only clear Z flag if destination is r15. */
1731 case 8: /* MMU TLB control. */
1733 case 9: /* Cache lockdown. */
1735 case 0: /* L1 cache. */
1736 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1740 return env
->cp15
.c9_data
;
1742 return env
->cp15
.c9_insn
;
1746 case 1: /* L2 cache */
1749 /* L2 Lockdown and Auxiliary control. */
1754 case 10: /* MMU TLB lockdown. */
1755 /* ??? TLB lockdown not implemented. */
1757 case 11: /* TCM DMA control. */
1758 case 12: /* Reserved. */
1760 case 13: /* Process ID. */
1763 return env
->cp15
.c13_fcse
;
1765 return env
->cp15
.c13_context
;
1769 case 14: /* Reserved. */
1771 case 15: /* Implementation specific. */
1772 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1773 if (op2
== 0 && crm
== 1)
1774 return env
->cp15
.c15_cpar
;
1778 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1782 case 1: /* Read TI925T configuration. */
1783 return env
->cp15
.c15_ticonfig
;
1784 case 2: /* Read I_max. */
1785 return env
->cp15
.c15_i_max
;
1786 case 3: /* Read I_min. */
1787 return env
->cp15
.c15_i_min
;
1788 case 4: /* Read thread-ID. */
1789 return env
->cp15
.c15_threadid
;
1790 case 8: /* TI925T_status */
1793 /* TODO: Peripheral port remap register:
1794 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1795 * controller base address at $rn & ~0xfff and map size of
1796 * 0x200 << ($rn & 0xfff), when MMU is off. */
1802 /* ??? For debugging only. Should raise illegal instruction exception. */
1803 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1804 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1808 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1810 env
->banked_r13
[bank_number(mode
)] = val
;
1813 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1815 return env
->banked_r13
[bank_number(mode
)];
1818 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1822 return xpsr_read(env
) & 0xf8000000;
1824 return xpsr_read(env
) & 0xf80001ff;
1826 return xpsr_read(env
) & 0xff00fc00;
1828 return xpsr_read(env
) & 0xff00fdff;
1830 return xpsr_read(env
) & 0x000001ff;
1832 return xpsr_read(env
) & 0x0700fc00;
1834 return xpsr_read(env
) & 0x0700edff;
1836 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1838 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1839 case 16: /* PRIMASK */
1840 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1841 case 17: /* FAULTMASK */
1842 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1843 case 18: /* BASEPRI */
1844 case 19: /* BASEPRI_MAX */
1845 return env
->v7m
.basepri
;
1846 case 20: /* CONTROL */
1847 return env
->v7m
.control
;
1849 /* ??? For debugging only. */
1850 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1855 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1859 xpsr_write(env
, val
, 0xf8000000);
1862 xpsr_write(env
, val
, 0xf8000000);
1865 xpsr_write(env
, val
, 0xfe00fc00);
1868 xpsr_write(env
, val
, 0xfe00fc00);
1871 /* IPSR bits are readonly. */
1874 xpsr_write(env
, val
, 0x0600fc00);
1877 xpsr_write(env
, val
, 0x0600fc00);
1880 if (env
->v7m
.current_sp
)
1881 env
->v7m
.other_sp
= val
;
1883 env
->regs
[13] = val
;
1886 if (env
->v7m
.current_sp
)
1887 env
->regs
[13] = val
;
1889 env
->v7m
.other_sp
= val
;
1891 case 16: /* PRIMASK */
1893 env
->uncached_cpsr
|= CPSR_I
;
1895 env
->uncached_cpsr
&= ~CPSR_I
;
1897 case 17: /* FAULTMASK */
1899 env
->uncached_cpsr
|= CPSR_F
;
1901 env
->uncached_cpsr
&= ~CPSR_F
;
1903 case 18: /* BASEPRI */
1904 env
->v7m
.basepri
= val
& 0xff;
1906 case 19: /* BASEPRI_MAX */
1908 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1909 env
->v7m
.basepri
= val
;
1911 case 20: /* CONTROL */
1912 env
->v7m
.control
= val
& 3;
1913 switch_v7m_sp(env
, (val
& 2) != 0);
1916 /* ??? For debugging only. */
1917 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1922 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1923 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1926 if (cpnum
< 0 || cpnum
> 14) {
1927 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1931 env
->cp
[cpnum
].cp_read
= cp_read
;
1932 env
->cp
[cpnum
].cp_write
= cp_write
;
1933 env
->cp
[cpnum
].opaque
= opaque
;
1938 /* Note that signed overflow is undefined in C. The following routines are
1939 careful to use unsigned types where modulo arithmetic is required.
1940 Failure to do so _will_ break on newer gcc. */
1942 /* Signed saturating arithmetic. */
1944 /* Perform 16-bit signed saturating addition. */
1945 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
1950 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
1959 /* Perform 8-bit signed saturating addition. */
1960 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
1965 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
1974 /* Perform 16-bit signed saturating subtraction. */
1975 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
1980 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
1989 /* Perform 8-bit signed saturating subtraction. */
1990 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
1995 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2004 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2005 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2006 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2007 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2010 #include "op_addsub.h"
2012 /* Unsigned saturating arithmetic. */
2013 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2022 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2030 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2039 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2047 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2048 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2049 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2050 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2053 #include "op_addsub.h"
2055 /* Signed modulo arithmetic. */
2056 #define SARITH16(a, b, n, op) do { \
2058 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2059 RESULT(sum, n, 16); \
2061 ge |= 3 << (n * 2); \
2064 #define SARITH8(a, b, n, op) do { \
2066 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2067 RESULT(sum, n, 8); \
2073 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2074 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2075 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2076 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2080 #include "op_addsub.h"
2082 /* Unsigned modulo arithmetic. */
2083 #define ADD16(a, b, n) do { \
2085 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2086 RESULT(sum, n, 16); \
2087 if ((sum >> 16) == 1) \
2088 ge |= 3 << (n * 2); \
2091 #define ADD8(a, b, n) do { \
2093 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2094 RESULT(sum, n, 8); \
2095 if ((sum >> 8) == 1) \
2099 #define SUB16(a, b, n) do { \
2101 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2102 RESULT(sum, n, 16); \
2103 if ((sum >> 16) == 0) \
2104 ge |= 3 << (n * 2); \
2107 #define SUB8(a, b, n) do { \
2109 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2110 RESULT(sum, n, 8); \
2111 if ((sum >> 8) == 0) \
2118 #include "op_addsub.h"
2120 /* Halved signed arithmetic. */
2121 #define ADD16(a, b, n) \
2122 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2123 #define SUB16(a, b, n) \
2124 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2125 #define ADD8(a, b, n) \
2126 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2127 #define SUB8(a, b, n) \
2128 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2131 #include "op_addsub.h"
2133 /* Halved unsigned arithmetic. */
2134 #define ADD16(a, b, n) \
2135 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2136 #define SUB16(a, b, n) \
2137 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2138 #define ADD8(a, b, n) \
2139 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2140 #define SUB8(a, b, n) \
2141 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2144 #include "op_addsub.h"
2146 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2154 /* Unsigned sum of absolute byte differences. */
2155 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2158 sum
= do_usad(a
, b
);
2159 sum
+= do_usad(a
>> 8, b
>> 8);
2160 sum
+= do_usad(a
>> 16, b
>>16);
2161 sum
+= do_usad(a
>> 24, b
>> 24);
2165 /* For ARMv6 SEL instruction. */
2166 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2179 return (a
& mask
) | (b
& ~mask
);
2182 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2184 return (val
>> 32) | (val
!= 0);
2187 /* VFP support. We follow the convention used for VFP instrunctions:
2188 Single precition routines have a "s" suffix, double precision a
2191 /* Convert host exception flags to vfp form. */
2192 static inline int vfp_exceptbits_from_host(int host_bits
)
2194 int target_bits
= 0;
2196 if (host_bits
& float_flag_invalid
)
2198 if (host_bits
& float_flag_divbyzero
)
2200 if (host_bits
& float_flag_overflow
)
2202 if (host_bits
& float_flag_underflow
)
2204 if (host_bits
& float_flag_inexact
)
2205 target_bits
|= 0x10;
2209 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2214 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2215 | (env
->vfp
.vec_len
<< 16)
2216 | (env
->vfp
.vec_stride
<< 20);
2217 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2218 fpscr
|= vfp_exceptbits_from_host(i
);
2222 /* Convert vfp exception flags to target form. */
2223 static inline int vfp_exceptbits_to_host(int target_bits
)
2227 if (target_bits
& 1)
2228 host_bits
|= float_flag_invalid
;
2229 if (target_bits
& 2)
2230 host_bits
|= float_flag_divbyzero
;
2231 if (target_bits
& 4)
2232 host_bits
|= float_flag_overflow
;
2233 if (target_bits
& 8)
2234 host_bits
|= float_flag_underflow
;
2235 if (target_bits
& 0x10)
2236 host_bits
|= float_flag_inexact
;
2240 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2245 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2246 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2247 env
->vfp
.vec_len
= (val
>> 16) & 7;
2248 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2251 if (changed
& (3 << 22)) {
2252 i
= (val
>> 22) & 3;
2255 i
= float_round_nearest_even
;
2261 i
= float_round_down
;
2264 i
= float_round_to_zero
;
2267 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2269 if (changed
& (1 << 24))
2270 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2271 if (changed
& (1 << 25))
2272 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2274 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2275 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2278 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2280 #define VFP_BINOP(name) \
2281 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2283 return float32_ ## name (a, b, &env->vfp.fp_status); \
2285 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2287 return float64_ ## name (a, b, &env->vfp.fp_status); \
2295 float32
VFP_HELPER(neg
, s
)(float32 a
)
2297 return float32_chs(a
);
2300 float64
VFP_HELPER(neg
, d
)(float64 a
)
2302 return float64_chs(a
);
2305 float32
VFP_HELPER(abs
, s
)(float32 a
)
2307 return float32_abs(a
);
2310 float64
VFP_HELPER(abs
, d
)(float64 a
)
2312 return float64_abs(a
);
2315 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2317 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2320 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2322 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2325 /* XXX: check quiet/signaling case */
2326 #define DO_VFP_cmp(p, type) \
2327 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2330 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2331 case 0: flags = 0x6; break; \
2332 case -1: flags = 0x8; break; \
2333 case 1: flags = 0x2; break; \
2334 default: case 2: flags = 0x3; break; \
2336 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2337 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2339 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2342 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2343 case 0: flags = 0x6; break; \
2344 case -1: flags = 0x8; break; \
2345 case 1: flags = 0x2; break; \
2346 default: case 2: flags = 0x3; break; \
2348 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2349 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2351 DO_VFP_cmp(s
, float32
)
2352 DO_VFP_cmp(d
, float64
)
2355 /* Helper routines to perform bitwise copies between float and int. */
2356 static inline float32
vfp_itos(uint32_t i
)
2367 static inline uint32_t vfp_stoi(float32 s
)
2378 static inline float64
vfp_itod(uint64_t i
)
2389 static inline uint64_t vfp_dtoi(float64 d
)
2400 /* Integer to float conversion. */
2401 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2403 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2406 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2408 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2411 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2413 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2416 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2418 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2421 /* Float to integer conversion. */
2422 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2424 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2427 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2429 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2432 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2434 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2437 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2439 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2442 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2444 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2447 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2449 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2452 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2454 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2457 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2459 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2462 /* floating point conversion */
2463 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2465 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2468 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2470 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2473 /* VFP3 fixed point conversion. */
2474 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2475 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2478 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2479 &env->vfp.fp_status); \
2480 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2482 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2485 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2486 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2487 &env->vfp.fp_status)); \
2490 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2491 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2492 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2493 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2494 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2495 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2496 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2497 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2500 /* Half precision conversions. */
2501 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2503 float_status
*s
= &env
->vfp
.fp_status
;
2504 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2505 return float16_to_float32(a
, ieee
, s
);
2508 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2510 float_status
*s
= &env
->vfp
.fp_status
;
2511 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2512 return float32_to_float16(a
, ieee
, s
);
2515 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2517 float_status
*s
= &env
->vfp
.fp_status
;
2518 float32 two
= int32_to_float32(2, s
);
2519 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2522 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2524 float_status
*s
= &env
->vfp
.fp_status
;
2525 float32 three
= int32_to_float32(3, s
);
2526 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2531 /* TODO: The architecture specifies the value that the estimate functions
2532 should return. We return the exact reciprocal/root instead. */
2533 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2535 float_status
*s
= &env
->vfp
.fp_status
;
2536 float32 one
= int32_to_float32(1, s
);
2537 return float32_div(one
, a
, s
);
2540 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2542 float_status
*s
= &env
->vfp
.fp_status
;
2543 float32 one
= int32_to_float32(1, s
);
2544 return float32_div(one
, float32_sqrt(a
, s
), s
);
2547 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2549 float_status
*s
= &env
->vfp
.fp_status
;
2551 tmp
= int32_to_float32(a
, s
);
2552 tmp
= float32_scalbn(tmp
, -32, s
);
2553 tmp
= helper_recpe_f32(tmp
, env
);
2554 tmp
= float32_scalbn(tmp
, 31, s
);
2555 return float32_to_int32(tmp
, s
);
2558 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2560 float_status
*s
= &env
->vfp
.fp_status
;
2562 tmp
= int32_to_float32(a
, s
);
2563 tmp
= float32_scalbn(tmp
, -32, s
);
2564 tmp
= helper_rsqrte_f32(tmp
, env
);
2565 tmp
= float32_scalbn(tmp
, 31, s
);
2566 return float32_to_int32(tmp
, s
);
2569 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2572 if (env
->teecr
!= val
) {