4 #include "host-utils.h"
7 #ifndef CONFIG_USER_ONLY
8 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
9 int access_type
, int is_user
,
10 target_phys_addr_t
*phys_ptr
, int *prot
,
11 target_ulong
*page_size
);
14 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
18 /* VFP data registers are always little-endian. */
19 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
21 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
24 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
25 /* Aliases for Q regs. */
28 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
29 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
33 switch (reg
- nregs
) {
34 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
35 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
36 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
41 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
53 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
54 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
58 switch (reg
- nregs
) {
59 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
60 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
61 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
66 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
69 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
73 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
75 if (env
->cp15
.c13_fcse
!= value
) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
80 env
->cp15
.c13_fcse
= value
;
84 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
94 env
->cp15
.c13_context
= value
;
98 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Invalidate all (TLBIALL) */
106 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
114 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env
, value
== 0);
122 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
130 static const ARMCPRegInfo cp_reginfo
[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
135 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
136 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
137 /* MMU Domain access control / MPU write buffer control */
138 { .name
= "DACR", .cp
= 15,
139 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
140 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
141 .resetvalue
= 0, .writefn
= dacr_write
},
142 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
143 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
144 .resetvalue
= 0, .writefn
= fcse_write
},
145 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
147 .resetvalue
= 0, .writefn
= contextidr_write
},
148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
152 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
157 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
158 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
159 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
160 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
161 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
162 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
163 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
166 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
167 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
171 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
175 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
176 .access
= PL1_W
, .type
= ARM_CP_WFI
},
180 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
185 .access
= PL1_W
, .type
= ARM_CP_WFI
},
186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
190 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
191 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
193 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
194 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
198 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
202 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
204 if (env
->cp15
.c1_coproc
!= value
) {
205 env
->cp15
.c1_coproc
= value
;
206 /* ??? Is this safe when called from within a TB? */
212 static const ARMCPRegInfo v6_cp_reginfo
[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name
= "MVA_prefetch",
215 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
216 .access
= PL1_W
, .type
= ARM_CP_NOP
},
217 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
218 .access
= PL0_W
, .type
= ARM_CP_NOP
},
219 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
220 .access
= PL0_W
, .type
= ARM_CP_NOP
},
221 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
222 .access
= PL0_W
, .type
= ARM_CP_NOP
},
223 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
224 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
229 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
230 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
231 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
232 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
233 .resetvalue
= 0, .writefn
= cpacr_write
},
237 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
243 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
246 *value
= CPREG_FIELD32(env
, ri
);
250 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
253 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
256 /* only the DP, X, D and E bits are writable */
257 env
->cp15
.c9_pmcr
&= ~0x39;
258 env
->cp15
.c9_pmcr
|= (value
& 0x39);
262 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
265 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
269 env
->cp15
.c9_pmcnten
|= value
;
273 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
276 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
280 env
->cp15
.c9_pmcnten
&= ~value
;
284 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
287 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
290 env
->cp15
.c9_pmovsr
&= ~value
;
294 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
297 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
300 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
304 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
307 env
->cp15
.c9_pmuserenr
= value
& 1;
311 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
314 /* We have no event counters so only the C bit can be changed */
316 env
->cp15
.c9_pminten
|= value
;
320 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
324 env
->cp15
.c9_pminten
&= ~value
;
328 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
331 ARMCPU
*cpu
= arm_env_get_cpu(env
);
332 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
336 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 env
->cp15
.c0_cssel
= value
& 0xf;
343 static const ARMCPRegInfo v7_cp_reginfo
[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
347 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
348 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
350 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
353 .access
= PL1_W
, .type
= ARM_CP_NOP
},
354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
366 .access
= PL0_RW
, .resetvalue
= 0,
367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
368 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
369 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
370 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
371 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
372 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
373 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
374 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
378 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
379 .access
= PL0_W
, .type
= ARM_CP_NOP
},
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
384 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
387 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
388 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
390 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
391 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
394 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
395 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
396 .access
= PL0_R
| PL1_RW
,
397 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
399 .writefn
= pmuserenr_write
},
400 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
402 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
404 .writefn
= pmintenset_write
},
405 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
409 .writefn
= pmintenclr_write
},
410 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
411 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
413 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
414 .access
= PL1_R
, .readfn
= ccsidr_read
},
415 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
416 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
417 .writefn
= csselr_write
, .resetvalue
= 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
421 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
422 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
426 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
433 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
439 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
442 *value
= env
->teehbr
;
446 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
449 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
456 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
457 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
458 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
460 .writefn
= teecr_write
},
461 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
462 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
464 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
468 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
469 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
471 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
473 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
474 .access
= PL0_R
|PL1_W
,
475 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
477 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
479 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
484 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
487 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
488 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
492 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
494 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
495 env
->cp15
.c7_par
= value
;
496 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
497 env
->cp15
.c7_par
= value
& 0xfffff6ff;
499 env
->cp15
.c7_par
= value
& 0xfffff1ff;
504 #ifndef CONFIG_USER_ONLY
505 /* get_phys_addr() isn't present for user-mode-only targets */
507 /* Return true if extended addresses are enabled, ie this is an
508 * LPAE implementation and we are using the long-descriptor translation
509 * table format because the TTBCR EAE bit is set.
511 static inline bool extended_addresses_enabled(CPUARMState
*env
)
513 return arm_feature(env
, ARM_FEATURE_LPAE
)
514 && (env
->cp15
.c2_control
& (1 << 31));
517 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
519 target_phys_addr_t phys_addr
;
520 target_ulong page_size
;
522 int ret
, is_user
= ri
->opc2
& 2;
523 int access_type
= ri
->opc2
& 1;
526 /* Other states are only available with TrustZone */
529 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
530 &phys_addr
, &prot
, &page_size
);
531 if (extended_addresses_enabled(env
)) {
532 /* ret is a DFSR/IFSR value for the long descriptor
533 * translation table format, but with WnR always clear.
534 * Convert it to a 64-bit PAR.
536 uint64_t par64
= (1 << 11); /* LPAE bit always set */
538 par64
|= phys_addr
& ~0xfffULL
;
539 /* We don't set the ATTR or SH fields in the PAR. */
542 par64
|= (ret
& 0x3f) << 1; /* FS */
543 /* Note that S2WLK and FSTAGE are always zero, because we don't
544 * implement virtualization and therefore there can't be a stage 2
548 env
->cp15
.c7_par
= par64
;
549 env
->cp15
.c7_par_hi
= par64
>> 32;
551 /* ret is a DFSR/IFSR value for the short descriptor
552 * translation table format (with WnR always clear).
553 * Convert it to a 32-bit PAR.
556 /* We do not set any attribute bits in the PAR */
557 if (page_size
== (1 << 24)
558 && arm_feature(env
, ARM_FEATURE_V7
)) {
559 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
561 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
564 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
565 ((ret
& (12 << 1)) >> 6) |
566 ((ret
& 0xf) << 1) | 1;
568 env
->cp15
.c7_par_hi
= 0;
574 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
575 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
576 .access
= PL1_RW
, .resetvalue
= 0,
577 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
578 .writefn
= par_write
},
579 #ifndef CONFIG_USER_ONLY
580 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
581 .access
= PL1_W
, .writefn
= ats_write
},
586 /* Return basic MPU access permission bits. */
587 static uint32_t simple_mpu_ap_bits(uint32_t val
)
594 for (i
= 0; i
< 16; i
+= 2) {
595 ret
|= (val
>> i
) & mask
;
601 /* Pad basic MPU access permission bits to extended format. */
602 static uint32_t extended_mpu_ap_bits(uint32_t val
)
609 for (i
= 0; i
< 16; i
+= 2) {
610 ret
|= (val
& mask
) << i
;
616 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
619 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
623 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
626 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
630 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
633 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
637 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
640 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
644 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
650 *value
= env
->cp15
.c6_region
[ri
->crm
];
654 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
660 env
->cp15
.c6_region
[ri
->crm
] = value
;
664 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
665 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
667 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
668 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
669 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
671 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
672 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
673 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
675 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
676 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
678 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
679 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
681 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
682 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
684 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
685 /* Protection region base and size registers */
686 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
687 .opc2
= CP_ANY
, .access
= PL1_RW
,
688 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
692 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 env
->cp15
.c2_control
= value
;
697 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
698 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
702 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
704 env
->cp15
.c2_base_mask
= 0xffffc000u
;
705 env
->cp15
.c2_control
= 0;
706 env
->cp15
.c2_mask
= 0;
709 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
710 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
712 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
713 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
715 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
716 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
718 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
719 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
721 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base1
), .resetvalue
= 0, },
722 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
723 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
724 .resetfn
= vmsa_ttbcr_reset
,
725 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
726 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
727 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
732 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
735 env
->cp15
.c15_ticonfig
= value
& 0xe7;
736 /* The OS_TYPE bit in this register changes the reported CPUID! */
737 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
738 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
742 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 env
->cp15
.c15_threadid
= value
& 0xffff;
749 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
752 /* Wait-for-interrupt (deprecated) */
753 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
757 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
760 /* On OMAP there are registers indicating the max/min index of dcache lines
761 * containing a dirty line; cache flush operations have to reset these.
763 env
->cp15
.c15_i_max
= 0x000;
764 env
->cp15
.c15_i_min
= 0xff0;
768 static const ARMCPRegInfo omap_cp_reginfo
[] = {
769 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
770 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
771 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
772 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
773 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
774 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
776 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
777 .writefn
= omap_ticonfig_write
},
778 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
780 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
781 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
782 .access
= PL1_RW
, .resetvalue
= 0xff0,
783 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
784 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
786 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
787 .writefn
= omap_threadid_write
},
788 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
789 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
790 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
791 /* TODO: Peripheral port remap register:
792 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
793 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
796 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
797 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
798 .writefn
= omap_cachemaint_write
},
799 { .name
= "C9", .cp
= 15, .crn
= 9,
800 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
801 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
805 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
809 if (env
->cp15
.c15_cpar
!= value
) {
810 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
812 env
->cp15
.c15_cpar
= value
;
817 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
818 { .name
= "XSCALE_CPAR",
819 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
820 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
821 .writefn
= xscale_cpar_write
, },
822 { .name
= "XSCALE_AUXCR",
823 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
824 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
829 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
830 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
831 * implementation of this implementation-defined space.
832 * Ideally this should eventually disappear in favour of actually
833 * implementing the correct behaviour for all cores.
835 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
836 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
837 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
841 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
842 /* Cache status: RAZ because we have no cache so it's always clean */
843 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
844 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
848 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
849 /* We never have a a block transfer operation in progress */
850 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
851 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
852 /* The cache ops themselves: these all NOP for QEMU */
853 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
854 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
855 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
856 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
857 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
859 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
860 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
861 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
862 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
863 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
864 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
868 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
869 /* The cache test-and-clean instructions always return (1 << 30)
870 * to indicate that there are no dirty cache lines.
872 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
873 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
874 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
875 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
879 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
880 /* Ignore ReadBuffer accesses */
881 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
882 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
883 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
888 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
891 uint32_t mpidr
= env
->cpu_index
;
892 /* We don't support setting cluster ID ([8..11])
893 * so these bits always RAZ.
895 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
897 /* Cores which are uniprocessor (non-coherent)
898 * but still implement the MP extensions set
899 * bit 30. (For instance, A9UP.) However we do
900 * not currently model any of those cores.
907 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
908 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
909 .access
= PL1_R
, .readfn
= mpidr_read
},
913 static int par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
915 *value
= ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
919 static int par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
921 env
->cp15
.c7_par_hi
= value
>> 32;
922 env
->cp15
.c7_par
= value
;
926 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
928 env
->cp15
.c7_par_hi
= 0;
929 env
->cp15
.c7_par
= 0;
932 static int ttbr064_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
935 *value
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
939 static int ttbr064_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
942 env
->cp15
.c2_base0_hi
= value
>> 32;
943 env
->cp15
.c2_base0
= value
;
944 /* Writes to the 64 bit format TTBRs may change the ASID */
949 static void ttbr064_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
951 env
->cp15
.c2_base0_hi
= 0;
952 env
->cp15
.c2_base0
= 0;
955 static int ttbr164_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
958 *value
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
962 static int ttbr164_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
965 env
->cp15
.c2_base1_hi
= value
>> 32;
966 env
->cp15
.c2_base1
= value
;
970 static void ttbr164_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
972 env
->cp15
.c2_base1_hi
= 0;
973 env
->cp15
.c2_base1
= 0;
976 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
977 /* NOP AMAIR0/1: the override is because these clash with tha rather
978 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
980 { .name
= "AMAIR0", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
981 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
983 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
984 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
986 /* 64 bit access versions of the (dummy) debug registers */
987 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
988 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
989 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
990 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
991 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
992 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
993 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
994 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
995 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr064_read
,
996 .writefn
= ttbr064_write
, .resetfn
= ttbr064_reset
},
997 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
998 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr164_read
,
999 .writefn
= ttbr164_write
, .resetfn
= ttbr164_reset
},
1003 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1005 env
->cp15
.c1_sys
= value
;
1006 /* ??? Lots of these bits are not implemented. */
1007 /* This may enable/disable the MMU, so do a TLB flush. */
1012 void register_cp_regs_for_features(ARMCPU
*cpu
)
1014 /* Register all the coprocessor registers based on feature bits */
1015 CPUARMState
*env
= &cpu
->env
;
1016 if (arm_feature(env
, ARM_FEATURE_M
)) {
1017 /* M profile has no coprocessor registers */
1021 define_arm_cp_regs(cpu
, cp_reginfo
);
1022 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1023 /* The ID registers all have impdef reset values */
1024 ARMCPRegInfo v6_idregs
[] = {
1025 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1026 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1027 .resetvalue
= cpu
->id_pfr0
},
1028 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1029 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1030 .resetvalue
= cpu
->id_pfr1
},
1031 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1032 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1033 .resetvalue
= cpu
->id_dfr0
},
1034 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1035 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1036 .resetvalue
= cpu
->id_afr0
},
1037 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1038 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1039 .resetvalue
= cpu
->id_mmfr0
},
1040 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1041 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1042 .resetvalue
= cpu
->id_mmfr1
},
1043 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1044 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1045 .resetvalue
= cpu
->id_mmfr2
},
1046 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1047 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1048 .resetvalue
= cpu
->id_mmfr3
},
1049 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1050 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1051 .resetvalue
= cpu
->id_isar0
},
1052 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1053 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1054 .resetvalue
= cpu
->id_isar1
},
1055 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1056 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1057 .resetvalue
= cpu
->id_isar2
},
1058 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1059 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1060 .resetvalue
= cpu
->id_isar3
},
1061 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1062 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1063 .resetvalue
= cpu
->id_isar4
},
1064 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1065 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1066 .resetvalue
= cpu
->id_isar5
},
1067 /* 6..7 are as yet unallocated and must RAZ */
1068 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1069 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1071 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1072 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1076 define_arm_cp_regs(cpu
, v6_idregs
);
1077 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1079 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1081 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1082 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1084 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1085 /* v7 performance monitor control register: same implementor
1086 * field as main ID register, and we implement no event counters.
1088 ARMCPRegInfo pmcr
= {
1089 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1090 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1091 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1092 .readfn
= pmreg_read
, .writefn
= pmcr_write
1094 ARMCPRegInfo clidr
= {
1095 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1096 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1098 define_one_arm_cp_reg(cpu
, &pmcr
);
1099 define_one_arm_cp_reg(cpu
, &clidr
);
1100 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
1102 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
1104 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1105 /* These are the MPU registers prior to PMSAv6. Any new
1106 * PMSA core later than the ARM946 will require that we
1107 * implement the PMSAv6 or PMSAv7 registers, which are
1108 * completely different.
1110 assert(!arm_feature(env
, ARM_FEATURE_V6
));
1111 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
1113 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
1115 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
1116 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
1118 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1119 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
1121 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1122 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
1124 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
1125 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
1127 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
1128 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1130 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1131 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1133 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1134 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1136 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1137 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1139 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1140 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1142 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1143 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1145 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1146 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1148 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1149 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
1151 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1152 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1153 * be read-only (ie write causes UNDEF exception).
1156 ARMCPRegInfo id_cp_reginfo
[] = {
1157 /* Note that the MIDR isn't a simple constant register because
1158 * of the TI925 behaviour where writes to another register can
1159 * cause the MIDR value to change.
1162 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
1163 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1164 .writefn
= arm_cp_write_ignore
,
1165 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
) },
1167 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1168 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1170 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1171 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1173 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1174 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1175 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1177 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1178 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1180 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1181 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1183 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1184 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1186 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1187 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1189 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1190 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1193 ARMCPRegInfo crn0_wi_reginfo
= {
1194 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1195 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1196 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1198 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1199 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1201 /* Register the blanket "writes ignored" value first to cover the
1202 * whole space. Then define the specific ID registers, but update
1203 * their access field to allow write access, so that they ignore
1204 * writes rather than causing them to UNDEF.
1206 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1207 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1209 define_one_arm_cp_reg(cpu
, r
);
1212 /* Just register the standard ID registers (read-only, meaning
1213 * that writes will UNDEF).
1215 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1219 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1220 ARMCPRegInfo auxcr
= {
1221 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1222 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1223 .resetvalue
= cpu
->reset_auxcr
1225 define_one_arm_cp_reg(cpu
, &auxcr
);
1228 /* Generic registers whose values depend on the implementation */
1230 ARMCPRegInfo sctlr
= {
1231 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1232 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1233 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
1235 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1236 /* Normally we would always end the TB on an SCTLR write, but Linux
1237 * arch/arm/mach-pxa/sleep.S expects two instructions following
1238 * an MMU enable to execute from cache. Imitate this behaviour.
1240 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1242 define_one_arm_cp_reg(cpu
, &sctlr
);
1246 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1250 static int inited
= 0;
1252 if (!object_class_by_name(cpu_model
)) {
1255 cpu
= ARM_CPU(object_new(cpu_model
));
1257 env
->cpu_model_str
= cpu_model
;
1258 arm_cpu_realize(cpu
);
1260 if (tcg_enabled() && !inited
) {
1262 arm_translate_init();
1265 cpu_reset(CPU(cpu
));
1266 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1267 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1268 51, "arm-neon.xml", 0);
1269 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1270 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1271 35, "arm-vfp3.xml", 0);
1272 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1273 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1274 19, "arm-vfp.xml", 0);
1276 qemu_init_vcpu(env
);
1280 typedef struct ARMCPUListState
{
1281 fprintf_function cpu_fprintf
;
1285 /* Sort alphabetically by type name, except for "any". */
1286 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1288 ObjectClass
*class_a
= (ObjectClass
*)a
;
1289 ObjectClass
*class_b
= (ObjectClass
*)b
;
1290 const char *name_a
, *name_b
;
1292 name_a
= object_class_get_name(class_a
);
1293 name_b
= object_class_get_name(class_b
);
1294 if (strcmp(name_a
, "any") == 0) {
1296 } else if (strcmp(name_b
, "any") == 0) {
1299 return strcmp(name_a
, name_b
);
1303 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1305 ObjectClass
*oc
= data
;
1306 ARMCPUListState
*s
= user_data
;
1308 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1309 object_class_get_name(oc
));
1312 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1314 ARMCPUListState s
= {
1316 .cpu_fprintf
= cpu_fprintf
,
1320 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1321 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1322 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1323 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1327 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1328 const ARMCPRegInfo
*r
, void *opaque
)
1330 /* Define implementations of coprocessor registers.
1331 * We store these in a hashtable because typically
1332 * there are less than 150 registers in a space which
1333 * is 16*16*16*8*8 = 262144 in size.
1334 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1335 * If a register is defined twice then the second definition is
1336 * used, so this can be used to define some generic registers and
1337 * then override them with implementation specific variations.
1338 * At least one of the original and the second definition should
1339 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1340 * against accidental use.
1342 int crm
, opc1
, opc2
;
1343 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1344 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1345 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1346 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1347 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1348 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1349 /* 64 bit registers have only CRm and Opc1 fields */
1350 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1351 /* Check that the register definition has enough info to handle
1352 * reads and writes if they are permitted.
1354 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1355 if (r
->access
& PL3_R
) {
1356 assert(r
->fieldoffset
|| r
->readfn
);
1358 if (r
->access
& PL3_W
) {
1359 assert(r
->fieldoffset
|| r
->writefn
);
1362 /* Bad type field probably means missing sentinel at end of reg list */
1363 assert(cptype_valid(r
->type
));
1364 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1365 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1366 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1367 uint32_t *key
= g_new(uint32_t, 1);
1368 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1369 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1370 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1371 r2
->opaque
= opaque
;
1372 /* Make sure reginfo passed to helpers for wildcarded regs
1373 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1378 /* Overriding of an existing definition must be explicitly
1381 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1382 ARMCPRegInfo
*oldreg
;
1383 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1384 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1385 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1386 "crn=%d crm=%d opc1=%d opc2=%d, "
1387 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1388 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1389 oldreg
->name
, r2
->name
);
1393 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1399 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1400 const ARMCPRegInfo
*regs
, void *opaque
)
1402 /* Define a whole list of registers */
1403 const ARMCPRegInfo
*r
;
1404 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1405 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1409 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1411 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1414 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1417 /* Helper coprocessor write function for write-ignore registers */
1421 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1423 /* Helper coprocessor write function for read-as-zero registers */
1428 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1430 /* Return true if it is not valid for us to switch to
1431 * this CPU mode (ie all the UNPREDICTABLE cases in
1432 * the ARM ARM CPSRWriteByInstr pseudocode).
1435 case ARM_CPU_MODE_USR
:
1436 case ARM_CPU_MODE_SYS
:
1437 case ARM_CPU_MODE_SVC
:
1438 case ARM_CPU_MODE_ABT
:
1439 case ARM_CPU_MODE_UND
:
1440 case ARM_CPU_MODE_IRQ
:
1441 case ARM_CPU_MODE_FIQ
:
1448 uint32_t cpsr_read(CPUARMState
*env
)
1451 ZF
= (env
->ZF
== 0);
1452 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1453 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1454 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1455 | ((env
->condexec_bits
& 0xfc) << 8)
1459 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1461 if (mask
& CPSR_NZCV
) {
1462 env
->ZF
= (~val
) & CPSR_Z
;
1464 env
->CF
= (val
>> 29) & 1;
1465 env
->VF
= (val
<< 3) & 0x80000000;
1468 env
->QF
= ((val
& CPSR_Q
) != 0);
1470 env
->thumb
= ((val
& CPSR_T
) != 0);
1471 if (mask
& CPSR_IT_0_1
) {
1472 env
->condexec_bits
&= ~3;
1473 env
->condexec_bits
|= (val
>> 25) & 3;
1475 if (mask
& CPSR_IT_2_7
) {
1476 env
->condexec_bits
&= 3;
1477 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1479 if (mask
& CPSR_GE
) {
1480 env
->GE
= (val
>> 16) & 0xf;
1483 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1484 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1485 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1486 * We choose to ignore the attempt and leave the CPSR M field
1491 switch_mode(env
, val
& CPSR_M
);
1494 mask
&= ~CACHED_CPSR_BITS
;
1495 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1498 /* Sign/zero extend */
1499 uint32_t HELPER(sxtb16
)(uint32_t x
)
1502 res
= (uint16_t)(int8_t)x
;
1503 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1507 uint32_t HELPER(uxtb16
)(uint32_t x
)
1510 res
= (uint16_t)(uint8_t)x
;
1511 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1515 uint32_t HELPER(clz
)(uint32_t x
)
1520 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1524 if (num
== INT_MIN
&& den
== -1)
1529 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1536 uint32_t HELPER(rbit
)(uint32_t x
)
1538 x
= ((x
& 0xff000000) >> 24)
1539 | ((x
& 0x00ff0000) >> 8)
1540 | ((x
& 0x0000ff00) << 8)
1541 | ((x
& 0x000000ff) << 24);
1542 x
= ((x
& 0xf0f0f0f0) >> 4)
1543 | ((x
& 0x0f0f0f0f) << 4);
1544 x
= ((x
& 0x88888888) >> 3)
1545 | ((x
& 0x44444444) >> 1)
1546 | ((x
& 0x22222222) << 1)
1547 | ((x
& 0x11111111) << 3);
1551 uint32_t HELPER(abs
)(uint32_t x
)
1553 return ((int32_t)x
< 0) ? -x
: x
;
1556 #if defined(CONFIG_USER_ONLY)
1558 void do_interrupt (CPUARMState
*env
)
1560 env
->exception_index
= -1;
1563 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1567 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1568 env
->cp15
.c6_insn
= address
;
1570 env
->exception_index
= EXCP_DATA_ABORT
;
1571 env
->cp15
.c6_data
= address
;
1576 /* These should probably raise undefined insn exceptions. */
1577 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1579 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1582 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1584 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1588 void switch_mode(CPUARMState
*env
, int mode
)
1590 if (mode
!= ARM_CPU_MODE_USR
)
1591 cpu_abort(env
, "Tried to switch out of user mode\n");
1594 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1596 cpu_abort(env
, "banked r13 write\n");
1599 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1601 cpu_abort(env
, "banked r13 read\n");
1607 /* Map CPU modes onto saved register banks. */
1608 static inline int bank_number(CPUARMState
*env
, int mode
)
1611 case ARM_CPU_MODE_USR
:
1612 case ARM_CPU_MODE_SYS
:
1614 case ARM_CPU_MODE_SVC
:
1616 case ARM_CPU_MODE_ABT
:
1618 case ARM_CPU_MODE_UND
:
1620 case ARM_CPU_MODE_IRQ
:
1622 case ARM_CPU_MODE_FIQ
:
1625 cpu_abort(env
, "Bad mode %x\n", mode
);
1629 void switch_mode(CPUARMState
*env
, int mode
)
1634 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1635 if (mode
== old_mode
)
1638 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1639 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1640 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1641 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1642 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1643 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1646 i
= bank_number(env
, old_mode
);
1647 env
->banked_r13
[i
] = env
->regs
[13];
1648 env
->banked_r14
[i
] = env
->regs
[14];
1649 env
->banked_spsr
[i
] = env
->spsr
;
1651 i
= bank_number(env
, mode
);
1652 env
->regs
[13] = env
->banked_r13
[i
];
1653 env
->regs
[14] = env
->banked_r14
[i
];
1654 env
->spsr
= env
->banked_spsr
[i
];
1657 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1660 stl_phys(env
->regs
[13], val
);
1663 static uint32_t v7m_pop(CPUARMState
*env
)
1666 val
= ldl_phys(env
->regs
[13]);
1671 /* Switch to V7M main or process stack pointer. */
1672 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1675 if (env
->v7m
.current_sp
!= process
) {
1676 tmp
= env
->v7m
.other_sp
;
1677 env
->v7m
.other_sp
= env
->regs
[13];
1678 env
->regs
[13] = tmp
;
1679 env
->v7m
.current_sp
= process
;
1683 static void do_v7m_exception_exit(CPUARMState
*env
)
1688 type
= env
->regs
[15];
1689 if (env
->v7m
.exception
!= 0)
1690 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1692 /* Switch to the target stack. */
1693 switch_v7m_sp(env
, (type
& 4) != 0);
1694 /* Pop registers. */
1695 env
->regs
[0] = v7m_pop(env
);
1696 env
->regs
[1] = v7m_pop(env
);
1697 env
->regs
[2] = v7m_pop(env
);
1698 env
->regs
[3] = v7m_pop(env
);
1699 env
->regs
[12] = v7m_pop(env
);
1700 env
->regs
[14] = v7m_pop(env
);
1701 env
->regs
[15] = v7m_pop(env
);
1702 xpsr
= v7m_pop(env
);
1703 xpsr_write(env
, xpsr
, 0xfffffdff);
1704 /* Undo stack alignment. */
1707 /* ??? The exception return type specifies Thread/Handler mode. However
1708 this is also implied by the xPSR value. Not sure what to do
1709 if there is a mismatch. */
1710 /* ??? Likewise for mismatches between the CONTROL register and the stack
1714 static void do_interrupt_v7m(CPUARMState
*env
)
1716 uint32_t xpsr
= xpsr_read(env
);
1721 if (env
->v7m
.current_sp
)
1723 if (env
->v7m
.exception
== 0)
1726 /* For exceptions we just mark as pending on the NVIC, and let that
1728 /* TODO: Need to escalate if the current priority is higher than the
1729 one we're raising. */
1730 switch (env
->exception_index
) {
1732 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1736 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1738 case EXCP_PREFETCH_ABORT
:
1739 case EXCP_DATA_ABORT
:
1740 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1743 if (semihosting_enabled
) {
1745 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1748 env
->regs
[0] = do_arm_semihosting(env
);
1752 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1755 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1757 case EXCP_EXCEPTION_EXIT
:
1758 do_v7m_exception_exit(env
);
1761 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1762 return; /* Never happens. Keep compiler happy. */
1765 /* Align stack pointer. */
1766 /* ??? Should only do this if Configuration Control Register
1767 STACKALIGN bit is set. */
1768 if (env
->regs
[13] & 4) {
1772 /* Switch to the handler mode. */
1773 v7m_push(env
, xpsr
);
1774 v7m_push(env
, env
->regs
[15]);
1775 v7m_push(env
, env
->regs
[14]);
1776 v7m_push(env
, env
->regs
[12]);
1777 v7m_push(env
, env
->regs
[3]);
1778 v7m_push(env
, env
->regs
[2]);
1779 v7m_push(env
, env
->regs
[1]);
1780 v7m_push(env
, env
->regs
[0]);
1781 switch_v7m_sp(env
, 0);
1783 env
->condexec_bits
= 0;
1785 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1786 env
->regs
[15] = addr
& 0xfffffffe;
1787 env
->thumb
= addr
& 1;
1790 /* Handle a CPU exception. */
1791 void do_interrupt(CPUARMState
*env
)
1799 do_interrupt_v7m(env
);
1802 /* TODO: Vectored interrupt controller. */
1803 switch (env
->exception_index
) {
1805 new_mode
= ARM_CPU_MODE_UND
;
1814 if (semihosting_enabled
) {
1815 /* Check for semihosting interrupt. */
1817 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1819 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1822 /* Only intercept calls from privileged modes, to provide some
1823 semblance of security. */
1824 if (((mask
== 0x123456 && !env
->thumb
)
1825 || (mask
== 0xab && env
->thumb
))
1826 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1827 env
->regs
[0] = do_arm_semihosting(env
);
1831 new_mode
= ARM_CPU_MODE_SVC
;
1834 /* The PC already points to the next instruction. */
1838 /* See if this is a semihosting syscall. */
1839 if (env
->thumb
&& semihosting_enabled
) {
1840 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1842 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1844 env
->regs
[0] = do_arm_semihosting(env
);
1848 env
->cp15
.c5_insn
= 2;
1849 /* Fall through to prefetch abort. */
1850 case EXCP_PREFETCH_ABORT
:
1851 new_mode
= ARM_CPU_MODE_ABT
;
1853 mask
= CPSR_A
| CPSR_I
;
1856 case EXCP_DATA_ABORT
:
1857 new_mode
= ARM_CPU_MODE_ABT
;
1859 mask
= CPSR_A
| CPSR_I
;
1863 new_mode
= ARM_CPU_MODE_IRQ
;
1865 /* Disable IRQ and imprecise data aborts. */
1866 mask
= CPSR_A
| CPSR_I
;
1870 new_mode
= ARM_CPU_MODE_FIQ
;
1872 /* Disable FIQ, IRQ and imprecise data aborts. */
1873 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1877 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1878 return; /* Never happens. Keep compiler happy. */
1881 if (env
->cp15
.c1_sys
& (1 << 13)) {
1884 switch_mode (env
, new_mode
);
1885 env
->spsr
= cpsr_read(env
);
1886 /* Clear IT bits. */
1887 env
->condexec_bits
= 0;
1888 /* Switch to the new mode, and to the correct instruction set. */
1889 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1890 env
->uncached_cpsr
|= mask
;
1891 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1892 * and we should just guard the thumb mode on V4 */
1893 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1894 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1896 env
->regs
[14] = env
->regs
[15] + offset
;
1897 env
->regs
[15] = addr
;
1898 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1901 /* Check section/page access permissions.
1902 Returns the page protection flags, or zero if the access is not
1904 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1905 int access_type
, int is_user
)
1909 if (domain_prot
== 3) {
1910 return PAGE_READ
| PAGE_WRITE
;
1913 if (access_type
== 1)
1916 prot_ro
= PAGE_READ
;
1920 if (access_type
== 1)
1922 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1924 return is_user
? 0 : PAGE_READ
;
1931 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1936 return PAGE_READ
| PAGE_WRITE
;
1938 return PAGE_READ
| PAGE_WRITE
;
1939 case 4: /* Reserved. */
1942 return is_user
? 0 : prot_ro
;
1946 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1954 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1958 if (address
& env
->cp15
.c2_mask
)
1959 table
= env
->cp15
.c2_base1
& 0xffffc000;
1961 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1963 table
|= (address
>> 18) & 0x3ffc;
1967 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1968 int is_user
, target_phys_addr_t
*phys_ptr
,
1969 int *prot
, target_ulong
*page_size
)
1978 target_phys_addr_t phys_addr
;
1980 /* Pagetable walk. */
1981 /* Lookup l1 descriptor. */
1982 table
= get_level1_table_address(env
, address
);
1983 desc
= ldl_phys(table
);
1985 domain
= (desc
>> 5) & 0x0f;
1986 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1988 /* Section translation fault. */
1992 if (domain_prot
== 0 || domain_prot
== 2) {
1994 code
= 9; /* Section domain fault. */
1996 code
= 11; /* Page domain fault. */
2001 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2002 ap
= (desc
>> 10) & 3;
2004 *page_size
= 1024 * 1024;
2006 /* Lookup l2 entry. */
2008 /* Coarse pagetable. */
2009 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2011 /* Fine pagetable. */
2012 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
2014 desc
= ldl_phys(table
);
2016 case 0: /* Page translation fault. */
2019 case 1: /* 64k page. */
2020 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2021 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2022 *page_size
= 0x10000;
2024 case 2: /* 4k page. */
2025 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2026 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2027 *page_size
= 0x1000;
2029 case 3: /* 1k page. */
2031 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2032 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2034 /* Page translation fault. */
2039 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
2041 ap
= (desc
>> 4) & 3;
2045 /* Never happens, but compiler isn't smart enough to tell. */
2050 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2052 /* Access permission fault. */
2056 *phys_ptr
= phys_addr
;
2059 return code
| (domain
<< 4);
2062 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
2063 int is_user
, target_phys_addr_t
*phys_ptr
,
2064 int *prot
, target_ulong
*page_size
)
2075 target_phys_addr_t phys_addr
;
2077 /* Pagetable walk. */
2078 /* Lookup l1 descriptor. */
2079 table
= get_level1_table_address(env
, address
);
2080 desc
= ldl_phys(table
);
2082 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
2083 /* Section translation fault, or attempt to use the encoding
2084 * which is Reserved on implementations without PXN.
2089 if ((type
== 1) || !(desc
& (1 << 18))) {
2090 /* Page or Section. */
2091 domain
= (desc
>> 5) & 0x0f;
2093 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2094 if (domain_prot
== 0 || domain_prot
== 2) {
2096 code
= 9; /* Section domain fault. */
2098 code
= 11; /* Page domain fault. */
2103 if (desc
& (1 << 18)) {
2105 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
2106 *page_size
= 0x1000000;
2109 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2110 *page_size
= 0x100000;
2112 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
2113 xn
= desc
& (1 << 4);
2117 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
2118 pxn
= (desc
>> 2) & 1;
2120 /* Lookup l2 entry. */
2121 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2122 desc
= ldl_phys(table
);
2123 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
2125 case 0: /* Page translation fault. */
2128 case 1: /* 64k page. */
2129 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2130 xn
= desc
& (1 << 15);
2131 *page_size
= 0x10000;
2133 case 2: case 3: /* 4k page. */
2134 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2136 *page_size
= 0x1000;
2139 /* Never happens, but compiler isn't smart enough to tell. */
2144 if (domain_prot
== 3) {
2145 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2147 if (pxn
&& !is_user
) {
2150 if (xn
&& access_type
== 2)
2153 /* The simplified model uses AP[0] as an access control bit. */
2154 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2155 /* Access flag fault. */
2156 code
= (code
== 15) ? 6 : 3;
2159 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2161 /* Access permission fault. */
2168 *phys_ptr
= phys_addr
;
2171 return code
| (domain
<< 4);
2174 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
2175 int access_type
, int is_user
,
2176 target_phys_addr_t
*phys_ptr
, int *prot
)
2182 *phys_ptr
= address
;
2183 for (n
= 7; n
>= 0; n
--) {
2184 base
= env
->cp15
.c6_region
[n
];
2185 if ((base
& 1) == 0)
2187 mask
= 1 << ((base
>> 1) & 0x1f);
2188 /* Keep this shift separate from the above to avoid an
2189 (undefined) << 32. */
2190 mask
= (mask
<< 1) - 1;
2191 if (((base
^ address
) & ~mask
) == 0)
2197 if (access_type
== 2) {
2198 mask
= env
->cp15
.c5_insn
;
2200 mask
= env
->cp15
.c5_data
;
2202 mask
= (mask
>> (n
* 4)) & 0xf;
2209 *prot
= PAGE_READ
| PAGE_WRITE
;
2214 *prot
|= PAGE_WRITE
;
2217 *prot
= PAGE_READ
| PAGE_WRITE
;
2228 /* Bad permission. */
2235 /* get_phys_addr - get the physical address for this virtual address
2237 * Find the physical address corresponding to the given virtual address,
2238 * by doing a translation table walk on MMU based systems or using the
2239 * MPU state on MPU based systems.
2241 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2242 * prot and page_size are not filled in, and the return value provides
2243 * information on why the translation aborted, in the format of a
2244 * DFSR/IFSR fault register, with the following caveats:
2245 * * we honour the short vs long DFSR format differences.
2246 * * the WnR bit is never set (the caller must do this).
2247 * * for MPU based systems we don't bother to return a full FSR format
2251 * @address: virtual address to get physical address for
2252 * @access_type: 0 for read, 1 for write, 2 for execute
2253 * @is_user: 0 for privileged access, 1 for user
2254 * @phys_ptr: set to the physical address corresponding to the virtual address
2255 * @prot: set to the permissions for the page containing phys_ptr
2256 * @page_size: set to the size of the page containing phys_ptr
2258 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2259 int access_type
, int is_user
,
2260 target_phys_addr_t
*phys_ptr
, int *prot
,
2261 target_ulong
*page_size
)
2263 /* Fast Context Switch Extension. */
2264 if (address
< 0x02000000)
2265 address
+= env
->cp15
.c13_fcse
;
2267 if ((env
->cp15
.c1_sys
& 1) == 0) {
2268 /* MMU/MPU disabled. */
2269 *phys_ptr
= address
;
2270 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2271 *page_size
= TARGET_PAGE_SIZE
;
2273 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2274 *page_size
= TARGET_PAGE_SIZE
;
2275 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2277 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2278 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2281 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2286 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2287 int access_type
, int mmu_idx
)
2289 target_phys_addr_t phys_addr
;
2290 target_ulong page_size
;
2294 is_user
= mmu_idx
== MMU_USER_IDX
;
2295 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2298 /* Map a single [sub]page. */
2299 phys_addr
&= ~(target_phys_addr_t
)0x3ff;
2300 address
&= ~(uint32_t)0x3ff;
2301 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2305 if (access_type
== 2) {
2306 env
->cp15
.c5_insn
= ret
;
2307 env
->cp15
.c6_insn
= address
;
2308 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2310 env
->cp15
.c5_data
= ret
;
2311 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2312 env
->cp15
.c5_data
|= (1 << 11);
2313 env
->cp15
.c6_data
= address
;
2314 env
->exception_index
= EXCP_DATA_ABORT
;
2319 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2321 target_phys_addr_t phys_addr
;
2322 target_ulong page_size
;
2326 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2334 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2336 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2337 env
->regs
[13] = val
;
2339 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2343 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2345 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2346 return env
->regs
[13];
2348 return env
->banked_r13
[bank_number(env
, mode
)];
2352 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2356 return xpsr_read(env
) & 0xf8000000;
2358 return xpsr_read(env
) & 0xf80001ff;
2360 return xpsr_read(env
) & 0xff00fc00;
2362 return xpsr_read(env
) & 0xff00fdff;
2364 return xpsr_read(env
) & 0x000001ff;
2366 return xpsr_read(env
) & 0x0700fc00;
2368 return xpsr_read(env
) & 0x0700edff;
2370 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2372 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2373 case 16: /* PRIMASK */
2374 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2375 case 17: /* BASEPRI */
2376 case 18: /* BASEPRI_MAX */
2377 return env
->v7m
.basepri
;
2378 case 19: /* FAULTMASK */
2379 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2380 case 20: /* CONTROL */
2381 return env
->v7m
.control
;
2383 /* ??? For debugging only. */
2384 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2389 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2393 xpsr_write(env
, val
, 0xf8000000);
2396 xpsr_write(env
, val
, 0xf8000000);
2399 xpsr_write(env
, val
, 0xfe00fc00);
2402 xpsr_write(env
, val
, 0xfe00fc00);
2405 /* IPSR bits are readonly. */
2408 xpsr_write(env
, val
, 0x0600fc00);
2411 xpsr_write(env
, val
, 0x0600fc00);
2414 if (env
->v7m
.current_sp
)
2415 env
->v7m
.other_sp
= val
;
2417 env
->regs
[13] = val
;
2420 if (env
->v7m
.current_sp
)
2421 env
->regs
[13] = val
;
2423 env
->v7m
.other_sp
= val
;
2425 case 16: /* PRIMASK */
2427 env
->uncached_cpsr
|= CPSR_I
;
2429 env
->uncached_cpsr
&= ~CPSR_I
;
2431 case 17: /* BASEPRI */
2432 env
->v7m
.basepri
= val
& 0xff;
2434 case 18: /* BASEPRI_MAX */
2436 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2437 env
->v7m
.basepri
= val
;
2439 case 19: /* FAULTMASK */
2441 env
->uncached_cpsr
|= CPSR_F
;
2443 env
->uncached_cpsr
&= ~CPSR_F
;
2445 case 20: /* CONTROL */
2446 env
->v7m
.control
= val
& 3;
2447 switch_v7m_sp(env
, (val
& 2) != 0);
2450 /* ??? For debugging only. */
2451 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2458 /* Note that signed overflow is undefined in C. The following routines are
2459 careful to use unsigned types where modulo arithmetic is required.
2460 Failure to do so _will_ break on newer gcc. */
2462 /* Signed saturating arithmetic. */
2464 /* Perform 16-bit signed saturating addition. */
2465 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2470 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2479 /* Perform 8-bit signed saturating addition. */
2480 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2485 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2494 /* Perform 16-bit signed saturating subtraction. */
2495 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2500 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2509 /* Perform 8-bit signed saturating subtraction. */
2510 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2515 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2524 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2525 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2526 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2527 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2530 #include "op_addsub.h"
2532 /* Unsigned saturating arithmetic. */
2533 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2542 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2550 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2559 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2567 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2568 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2569 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2570 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2573 #include "op_addsub.h"
2575 /* Signed modulo arithmetic. */
2576 #define SARITH16(a, b, n, op) do { \
2578 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2579 RESULT(sum, n, 16); \
2581 ge |= 3 << (n * 2); \
2584 #define SARITH8(a, b, n, op) do { \
2586 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2587 RESULT(sum, n, 8); \
2593 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2594 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2595 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2596 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2600 #include "op_addsub.h"
2602 /* Unsigned modulo arithmetic. */
2603 #define ADD16(a, b, n) do { \
2605 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2606 RESULT(sum, n, 16); \
2607 if ((sum >> 16) == 1) \
2608 ge |= 3 << (n * 2); \
2611 #define ADD8(a, b, n) do { \
2613 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2614 RESULT(sum, n, 8); \
2615 if ((sum >> 8) == 1) \
2619 #define SUB16(a, b, n) do { \
2621 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2622 RESULT(sum, n, 16); \
2623 if ((sum >> 16) == 0) \
2624 ge |= 3 << (n * 2); \
2627 #define SUB8(a, b, n) do { \
2629 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2630 RESULT(sum, n, 8); \
2631 if ((sum >> 8) == 0) \
2638 #include "op_addsub.h"
2640 /* Halved signed arithmetic. */
2641 #define ADD16(a, b, n) \
2642 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2643 #define SUB16(a, b, n) \
2644 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2645 #define ADD8(a, b, n) \
2646 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2647 #define SUB8(a, b, n) \
2648 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2651 #include "op_addsub.h"
2653 /* Halved unsigned arithmetic. */
2654 #define ADD16(a, b, n) \
2655 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2656 #define SUB16(a, b, n) \
2657 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2658 #define ADD8(a, b, n) \
2659 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2660 #define SUB8(a, b, n) \
2661 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2664 #include "op_addsub.h"
2666 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2674 /* Unsigned sum of absolute byte differences. */
2675 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2678 sum
= do_usad(a
, b
);
2679 sum
+= do_usad(a
>> 8, b
>> 8);
2680 sum
+= do_usad(a
>> 16, b
>>16);
2681 sum
+= do_usad(a
>> 24, b
>> 24);
2685 /* For ARMv6 SEL instruction. */
2686 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2699 return (a
& mask
) | (b
& ~mask
);
2702 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2704 return (val
>> 32) | (val
!= 0);
2707 /* VFP support. We follow the convention used for VFP instrunctions:
2708 Single precition routines have a "s" suffix, double precision a
2711 /* Convert host exception flags to vfp form. */
2712 static inline int vfp_exceptbits_from_host(int host_bits
)
2714 int target_bits
= 0;
2716 if (host_bits
& float_flag_invalid
)
2718 if (host_bits
& float_flag_divbyzero
)
2720 if (host_bits
& float_flag_overflow
)
2722 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2724 if (host_bits
& float_flag_inexact
)
2725 target_bits
|= 0x10;
2726 if (host_bits
& float_flag_input_denormal
)
2727 target_bits
|= 0x80;
2731 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2736 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2737 | (env
->vfp
.vec_len
<< 16)
2738 | (env
->vfp
.vec_stride
<< 20);
2739 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2740 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2741 fpscr
|= vfp_exceptbits_from_host(i
);
2745 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2747 return HELPER(vfp_get_fpscr
)(env
);
2750 /* Convert vfp exception flags to target form. */
2751 static inline int vfp_exceptbits_to_host(int target_bits
)
2755 if (target_bits
& 1)
2756 host_bits
|= float_flag_invalid
;
2757 if (target_bits
& 2)
2758 host_bits
|= float_flag_divbyzero
;
2759 if (target_bits
& 4)
2760 host_bits
|= float_flag_overflow
;
2761 if (target_bits
& 8)
2762 host_bits
|= float_flag_underflow
;
2763 if (target_bits
& 0x10)
2764 host_bits
|= float_flag_inexact
;
2765 if (target_bits
& 0x80)
2766 host_bits
|= float_flag_input_denormal
;
2770 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2775 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2776 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2777 env
->vfp
.vec_len
= (val
>> 16) & 7;
2778 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2781 if (changed
& (3 << 22)) {
2782 i
= (val
>> 22) & 3;
2785 i
= float_round_nearest_even
;
2791 i
= float_round_down
;
2794 i
= float_round_to_zero
;
2797 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2799 if (changed
& (1 << 24)) {
2800 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2801 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2803 if (changed
& (1 << 25))
2804 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2806 i
= vfp_exceptbits_to_host(val
);
2807 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2808 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2811 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2813 HELPER(vfp_set_fpscr
)(env
, val
);
2816 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2818 #define VFP_BINOP(name) \
2819 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2821 float_status *fpst = fpstp; \
2822 return float32_ ## name(a, b, fpst); \
2824 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2826 float_status *fpst = fpstp; \
2827 return float64_ ## name(a, b, fpst); \
2835 float32
VFP_HELPER(neg
, s
)(float32 a
)
2837 return float32_chs(a
);
2840 float64
VFP_HELPER(neg
, d
)(float64 a
)
2842 return float64_chs(a
);
2845 float32
VFP_HELPER(abs
, s
)(float32 a
)
2847 return float32_abs(a
);
2850 float64
VFP_HELPER(abs
, d
)(float64 a
)
2852 return float64_abs(a
);
2855 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2857 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2860 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2862 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2865 /* XXX: check quiet/signaling case */
2866 #define DO_VFP_cmp(p, type) \
2867 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2870 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2871 case 0: flags = 0x6; break; \
2872 case -1: flags = 0x8; break; \
2873 case 1: flags = 0x2; break; \
2874 default: case 2: flags = 0x3; break; \
2876 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2877 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2879 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2882 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2883 case 0: flags = 0x6; break; \
2884 case -1: flags = 0x8; break; \
2885 case 1: flags = 0x2; break; \
2886 default: case 2: flags = 0x3; break; \
2888 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2889 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2891 DO_VFP_cmp(s
, float32
)
2892 DO_VFP_cmp(d
, float64
)
2895 /* Integer to float and float to integer conversions */
2897 #define CONV_ITOF(name, fsz, sign) \
2898 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2900 float_status *fpst = fpstp; \
2901 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2904 #define CONV_FTOI(name, fsz, sign, round) \
2905 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2907 float_status *fpst = fpstp; \
2908 if (float##fsz##_is_any_nan(x)) { \
2909 float_raise(float_flag_invalid, fpst); \
2912 return float##fsz##_to_##sign##int32##round(x, fpst); \
2915 #define FLOAT_CONVS(name, p, fsz, sign) \
2916 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2917 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2918 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2920 FLOAT_CONVS(si
, s
, 32, )
2921 FLOAT_CONVS(si
, d
, 64, )
2922 FLOAT_CONVS(ui
, s
, 32, u
)
2923 FLOAT_CONVS(ui
, d
, 64, u
)
2929 /* floating point conversion */
2930 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2932 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2933 /* ARM requires that S<->D conversion of any kind of NaN generates
2934 * a quiet NaN by forcing the most significant frac bit to 1.
2936 return float64_maybe_silence_nan(r
);
2939 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2941 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2942 /* ARM requires that S<->D conversion of any kind of NaN generates
2943 * a quiet NaN by forcing the most significant frac bit to 1.
2945 return float32_maybe_silence_nan(r
);
2948 /* VFP3 fixed point conversion. */
2949 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2950 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2953 float_status *fpst = fpstp; \
2955 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2956 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2958 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2961 float_status *fpst = fpstp; \
2963 if (float##fsz##_is_any_nan(x)) { \
2964 float_raise(float_flag_invalid, fpst); \
2967 tmp = float##fsz##_scalbn(x, shift, fpst); \
2968 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2971 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2972 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2973 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2974 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2975 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2976 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2977 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2978 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2981 /* Half precision conversions. */
2982 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2984 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2985 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2987 return float32_maybe_silence_nan(r
);
2992 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2994 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2995 float16 r
= float32_to_float16(a
, ieee
, s
);
2997 r
= float16_maybe_silence_nan(r
);
2999 return float16_val(r
);
3002 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3004 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
3007 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3009 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
3012 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3014 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
3017 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3019 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
3022 #define float32_two make_float32(0x40000000)
3023 #define float32_three make_float32(0x40400000)
3024 #define float32_one_point_five make_float32(0x3fc00000)
3026 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3028 float_status
*s
= &env
->vfp
.standard_fp_status
;
3029 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3030 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3031 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3032 float_raise(float_flag_input_denormal
, s
);
3036 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
3039 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3041 float_status
*s
= &env
->vfp
.standard_fp_status
;
3043 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3044 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3045 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3046 float_raise(float_flag_input_denormal
, s
);
3048 return float32_one_point_five
;
3050 product
= float32_mul(a
, b
, s
);
3051 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3056 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3057 * int->float conversions at run-time. */
3058 #define float64_256 make_float64(0x4070000000000000LL)
3059 #define float64_512 make_float64(0x4080000000000000LL)
3061 /* The algorithm that must be used to calculate the estimate
3062 * is specified by the ARM ARM.
3064 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
3066 /* These calculations mustn't set any fp exception flags,
3067 * so we use a local copy of the fp_status.
3069 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3070 float_status
*s
= &dummy_status
;
3071 /* q = (int)(a * 512.0) */
3072 float64 q
= float64_mul(float64_512
, a
, s
);
3073 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3075 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3076 q
= int64_to_float64(q_int
, s
);
3077 q
= float64_add(q
, float64_half
, s
);
3078 q
= float64_div(q
, float64_512
, s
);
3079 q
= float64_div(float64_one
, q
, s
);
3081 /* s = (int)(256.0 * r + 0.5) */
3082 q
= float64_mul(q
, float64_256
, s
);
3083 q
= float64_add(q
, float64_half
, s
);
3084 q_int
= float64_to_int64_round_to_zero(q
, s
);
3086 /* return (double)s / 256.0 */
3087 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3090 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
3092 float_status
*s
= &env
->vfp
.standard_fp_status
;
3094 uint32_t val32
= float32_val(a
);
3097 int a_exp
= (val32
& 0x7f800000) >> 23;
3098 int sign
= val32
& 0x80000000;
3100 if (float32_is_any_nan(a
)) {
3101 if (float32_is_signaling_nan(a
)) {
3102 float_raise(float_flag_invalid
, s
);
3104 return float32_default_nan
;
3105 } else if (float32_is_infinity(a
)) {
3106 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3107 } else if (float32_is_zero_or_denormal(a
)) {
3108 if (!float32_is_zero(a
)) {
3109 float_raise(float_flag_input_denormal
, s
);
3111 float_raise(float_flag_divbyzero
, s
);
3112 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3113 } else if (a_exp
>= 253) {
3114 float_raise(float_flag_underflow
, s
);
3115 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3118 f64
= make_float64((0x3feULL
<< 52)
3119 | ((int64_t)(val32
& 0x7fffff) << 29));
3121 result_exp
= 253 - a_exp
;
3123 f64
= recip_estimate(f64
, env
);
3126 | ((result_exp
& 0xff) << 23)
3127 | ((float64_val(f64
) >> 29) & 0x7fffff);
3128 return make_float32(val32
);
3131 /* The algorithm that must be used to calculate the estimate
3132 * is specified by the ARM ARM.
3134 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
3136 /* These calculations mustn't set any fp exception flags,
3137 * so we use a local copy of the fp_status.
3139 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3140 float_status
*s
= &dummy_status
;
3144 if (float64_lt(a
, float64_half
, s
)) {
3145 /* range 0.25 <= a < 0.5 */
3147 /* a in units of 1/512 rounded down */
3148 /* q0 = (int)(a * 512.0); */
3149 q
= float64_mul(float64_512
, a
, s
);
3150 q_int
= float64_to_int64_round_to_zero(q
, s
);
3152 /* reciprocal root r */
3153 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3154 q
= int64_to_float64(q_int
, s
);
3155 q
= float64_add(q
, float64_half
, s
);
3156 q
= float64_div(q
, float64_512
, s
);
3157 q
= float64_sqrt(q
, s
);
3158 q
= float64_div(float64_one
, q
, s
);
3160 /* range 0.5 <= a < 1.0 */
3162 /* a in units of 1/256 rounded down */
3163 /* q1 = (int)(a * 256.0); */
3164 q
= float64_mul(float64_256
, a
, s
);
3165 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3167 /* reciprocal root r */
3168 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3169 q
= int64_to_float64(q_int
, s
);
3170 q
= float64_add(q
, float64_half
, s
);
3171 q
= float64_div(q
, float64_256
, s
);
3172 q
= float64_sqrt(q
, s
);
3173 q
= float64_div(float64_one
, q
, s
);
3175 /* r in units of 1/256 rounded to nearest */
3176 /* s = (int)(256.0 * r + 0.5); */
3178 q
= float64_mul(q
, float64_256
,s
);
3179 q
= float64_add(q
, float64_half
, s
);
3180 q_int
= float64_to_int64_round_to_zero(q
, s
);
3182 /* return (double)s / 256.0;*/
3183 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3186 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3188 float_status
*s
= &env
->vfp
.standard_fp_status
;
3194 val
= float32_val(a
);
3196 if (float32_is_any_nan(a
)) {
3197 if (float32_is_signaling_nan(a
)) {
3198 float_raise(float_flag_invalid
, s
);
3200 return float32_default_nan
;
3201 } else if (float32_is_zero_or_denormal(a
)) {
3202 if (!float32_is_zero(a
)) {
3203 float_raise(float_flag_input_denormal
, s
);
3205 float_raise(float_flag_divbyzero
, s
);
3206 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3207 } else if (float32_is_neg(a
)) {
3208 float_raise(float_flag_invalid
, s
);
3209 return float32_default_nan
;
3210 } else if (float32_is_infinity(a
)) {
3211 return float32_zero
;
3214 /* Normalize to a double-precision value between 0.25 and 1.0,
3215 * preserving the parity of the exponent. */
3216 if ((val
& 0x800000) == 0) {
3217 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3219 | ((uint64_t)(val
& 0x7fffff) << 29));
3221 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3223 | ((uint64_t)(val
& 0x7fffff) << 29));
3226 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3228 f64
= recip_sqrt_estimate(f64
, env
);
3230 val64
= float64_val(f64
);
3232 val
= ((result_exp
& 0xff) << 23)
3233 | ((val64
>> 29) & 0x7fffff);
3234 return make_float32(val
);
3237 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3241 if ((a
& 0x80000000) == 0) {
3245 f64
= make_float64((0x3feULL
<< 52)
3246 | ((int64_t)(a
& 0x7fffffff) << 21));
3248 f64
= recip_estimate (f64
, env
);
3250 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3253 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3257 if ((a
& 0xc0000000) == 0) {
3261 if (a
& 0x80000000) {
3262 f64
= make_float64((0x3feULL
<< 52)
3263 | ((uint64_t)(a
& 0x7fffffff) << 21));
3264 } else { /* bits 31-30 == '01' */
3265 f64
= make_float64((0x3fdULL
<< 52)
3266 | ((uint64_t)(a
& 0x3fffffff) << 22));
3269 f64
= recip_sqrt_estimate(f64
, env
);
3271 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3274 /* VFPv4 fused multiply-accumulate */
3275 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3277 float_status
*fpst
= fpstp
;
3278 return float32_muladd(a
, b
, c
, 0, fpst
);
3281 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3283 float_status
*fpst
= fpstp
;
3284 return float64_muladd(a
, b
, c
, 0, fpst
);