4 #include "host-utils.h"
5 #if !defined(CONFIG_USER_ONLY)
10 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
13 case ARM_CPUID_ARM926
:
15 case ARM_CPUID_ARM946
:
17 case ARM_CPUID_ARM1026
:
19 case ARM_CPUID_ARM1136
:
20 /* This is the 1136 r1, which is a v6K core */
21 case ARM_CPUID_ARM1136_R2
:
23 case ARM_CPUID_ARM1176
:
25 case ARM_CPUID_ARM11MPCORE
:
27 case ARM_CPUID_CORTEXA8
:
28 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
29 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
30 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
31 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
33 case ARM_CPUID_CORTEXA9
:
34 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
35 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
36 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
38 case ARM_CPUID_CORTEXA15
:
39 env
->cp15
.c0_clid
= 0x0a200023;
40 env
->cp15
.c0_ccsid
[0] = 0x701fe00a; /* 32K L1 dcache */
41 env
->cp15
.c0_ccsid
[1] = 0x201fe00a; /* 32K L1 icache */
42 env
->cp15
.c0_ccsid
[2] = 0x711fe07a; /* 4096K L2 unified cache */
44 case ARM_CPUID_CORTEXM3
:
46 case ARM_CPUID_ANY
: /* For userspace emulation. */
48 case ARM_CPUID_TI915T
:
49 case ARM_CPUID_TI925T
:
51 case ARM_CPUID_PXA250
:
52 case ARM_CPUID_PXA255
:
53 case ARM_CPUID_PXA260
:
54 case ARM_CPUID_PXA261
:
55 case ARM_CPUID_PXA262
:
57 case ARM_CPUID_PXA270_A0
:
58 case ARM_CPUID_PXA270_A1
:
59 case ARM_CPUID_PXA270_B0
:
60 case ARM_CPUID_PXA270_B1
:
61 case ARM_CPUID_PXA270_C0
:
62 case ARM_CPUID_PXA270_C5
:
64 case ARM_CPUID_SA1100
:
65 case ARM_CPUID_SA1110
:
68 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
74 /* TODO Move contents into arm_cpu_reset() in cpu.c,
75 * once cpu_reset_model_id() is eliminated,
76 * and then forward to cpu_reset() here.
78 void cpu_state_reset(CPUARMState
*env
)
82 ARMCPU
*cpu
= arm_env_get_cpu(env
);
84 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
85 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
86 log_cpu_state(env
, 0);
90 tmp
= env
->cp15
.c15_config_base_address
;
91 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
93 cpu_reset_model_id(env
, id
);
94 env
->cp15
.c15_config_base_address
= tmp
;
95 env
->cp15
.c0_cpuid
= cpu
->midr
;
96 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
97 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
98 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
99 env
->cp15
.c0_cachetype
= cpu
->ctr
;
100 env
->cp15
.c1_sys
= cpu
->reset_sctlr
;
101 env
->cp15
.c0_c1
[0] = cpu
->id_pfr0
;
102 env
->cp15
.c0_c1
[1] = cpu
->id_pfr1
;
103 env
->cp15
.c0_c1
[2] = cpu
->id_dfr0
;
104 env
->cp15
.c0_c1
[3] = cpu
->id_afr0
;
105 env
->cp15
.c0_c1
[4] = cpu
->id_mmfr0
;
106 env
->cp15
.c0_c1
[5] = cpu
->id_mmfr1
;
107 env
->cp15
.c0_c1
[6] = cpu
->id_mmfr2
;
108 env
->cp15
.c0_c1
[7] = cpu
->id_mmfr3
;
109 env
->cp15
.c0_c2
[0] = cpu
->id_isar0
;
110 env
->cp15
.c0_c2
[1] = cpu
->id_isar1
;
111 env
->cp15
.c0_c2
[2] = cpu
->id_isar2
;
112 env
->cp15
.c0_c2
[3] = cpu
->id_isar3
;
113 env
->cp15
.c0_c2
[4] = cpu
->id_isar4
;
114 env
->cp15
.c0_c2
[5] = cpu
->id_isar5
;
115 env
->cp15
.c15_i_min
= 0xff0;
117 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
118 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
121 #if defined (CONFIG_USER_ONLY)
122 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
123 /* For user mode we must enable access to coprocessors */
124 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
125 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
126 env
->cp15
.c15_cpar
= 3;
127 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
128 env
->cp15
.c15_cpar
= 1;
131 /* SVC mode with interrupts disabled. */
132 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
133 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
134 clear at reset. Initial SP and PC are loaded from ROM. */
138 env
->uncached_cpsr
&= ~CPSR_I
;
141 /* We should really use ldl_phys here, in case the guest
142 modified flash and reset itself. However images
143 loaded via -kernel have not been copied yet, so load the
144 values directly from there. */
145 env
->regs
[13] = ldl_p(rom
);
148 env
->regs
[15] = pc
& ~1;
151 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
152 env
->cp15
.c2_base_mask
= 0xffffc000u
;
153 /* v7 performance monitor control register: same implementor
154 * field as main ID register, and we implement no event counters.
156 env
->cp15
.c9_pmcr
= (id
& 0xff000000);
158 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
159 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
160 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
161 set_float_detect_tininess(float_tininess_before_rounding
,
162 &env
->vfp
.fp_status
);
163 set_float_detect_tininess(float_tininess_before_rounding
,
164 &env
->vfp
.standard_fp_status
);
166 /* Reset is a state change for some CPUARMState fields which we
167 * bake assumptions about into translated code, so we need to
173 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
177 /* VFP data registers are always little-endian. */
178 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
180 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
183 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
184 /* Aliases for Q regs. */
187 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
188 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
192 switch (reg
- nregs
) {
193 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
194 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
195 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
200 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
204 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
206 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
209 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
212 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
213 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
217 switch (reg
- nregs
) {
218 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
219 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
220 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
225 CPUARMState
*cpu_arm_init(const char *cpu_model
)
229 static int inited
= 0;
231 if (!object_class_by_name(cpu_model
)) {
234 cpu
= ARM_CPU(object_new(cpu_model
));
236 env
->cpu_model_str
= cpu_model
;
237 arm_cpu_realize(cpu
);
239 if (tcg_enabled() && !inited
) {
241 arm_translate_init();
244 cpu_state_reset(env
);
245 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
246 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
247 51, "arm-neon.xml", 0);
248 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
249 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
250 35, "arm-vfp3.xml", 0);
251 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
252 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
253 19, "arm-vfp.xml", 0);
259 typedef struct ARMCPUListState
{
260 fprintf_function cpu_fprintf
;
264 /* Sort alphabetically by type name, except for "any". */
265 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
267 ObjectClass
*class_a
= (ObjectClass
*)a
;
268 ObjectClass
*class_b
= (ObjectClass
*)b
;
269 const char *name_a
, *name_b
;
271 name_a
= object_class_get_name(class_a
);
272 name_b
= object_class_get_name(class_b
);
273 if (strcmp(name_a
, "any") == 0) {
275 } else if (strcmp(name_b
, "any") == 0) {
278 return strcmp(name_a
, name_b
);
282 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
284 ObjectClass
*oc
= data
;
285 ARMCPUListState
*s
= user_data
;
287 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
288 object_class_get_name(oc
));
291 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
293 ARMCPUListState s
= {
295 .cpu_fprintf
= cpu_fprintf
,
299 list
= object_class_get_list(TYPE_ARM_CPU
, false);
300 list
= g_slist_sort(list
, arm_cpu_list_compare
);
301 (*cpu_fprintf
)(f
, "Available CPUs:\n");
302 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
306 static int bad_mode_switch(CPUARMState
*env
, int mode
)
308 /* Return true if it is not valid for us to switch to
309 * this CPU mode (ie all the UNPREDICTABLE cases in
310 * the ARM ARM CPSRWriteByInstr pseudocode).
313 case ARM_CPU_MODE_USR
:
314 case ARM_CPU_MODE_SYS
:
315 case ARM_CPU_MODE_SVC
:
316 case ARM_CPU_MODE_ABT
:
317 case ARM_CPU_MODE_UND
:
318 case ARM_CPU_MODE_IRQ
:
319 case ARM_CPU_MODE_FIQ
:
326 uint32_t cpsr_read(CPUARMState
*env
)
330 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
331 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
332 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
333 | ((env
->condexec_bits
& 0xfc) << 8)
337 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
339 if (mask
& CPSR_NZCV
) {
340 env
->ZF
= (~val
) & CPSR_Z
;
342 env
->CF
= (val
>> 29) & 1;
343 env
->VF
= (val
<< 3) & 0x80000000;
346 env
->QF
= ((val
& CPSR_Q
) != 0);
348 env
->thumb
= ((val
& CPSR_T
) != 0);
349 if (mask
& CPSR_IT_0_1
) {
350 env
->condexec_bits
&= ~3;
351 env
->condexec_bits
|= (val
>> 25) & 3;
353 if (mask
& CPSR_IT_2_7
) {
354 env
->condexec_bits
&= 3;
355 env
->condexec_bits
|= (val
>> 8) & 0xfc;
357 if (mask
& CPSR_GE
) {
358 env
->GE
= (val
>> 16) & 0xf;
361 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
362 if (bad_mode_switch(env
, val
& CPSR_M
)) {
363 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
364 * We choose to ignore the attempt and leave the CPSR M field
369 switch_mode(env
, val
& CPSR_M
);
372 mask
&= ~CACHED_CPSR_BITS
;
373 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
376 /* Sign/zero extend */
377 uint32_t HELPER(sxtb16
)(uint32_t x
)
380 res
= (uint16_t)(int8_t)x
;
381 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
385 uint32_t HELPER(uxtb16
)(uint32_t x
)
388 res
= (uint16_t)(uint8_t)x
;
389 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
393 uint32_t HELPER(clz
)(uint32_t x
)
398 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
402 if (num
== INT_MIN
&& den
== -1)
407 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
414 uint32_t HELPER(rbit
)(uint32_t x
)
416 x
= ((x
& 0xff000000) >> 24)
417 | ((x
& 0x00ff0000) >> 8)
418 | ((x
& 0x0000ff00) << 8)
419 | ((x
& 0x000000ff) << 24);
420 x
= ((x
& 0xf0f0f0f0) >> 4)
421 | ((x
& 0x0f0f0f0f) << 4);
422 x
= ((x
& 0x88888888) >> 3)
423 | ((x
& 0x44444444) >> 1)
424 | ((x
& 0x22222222) << 1)
425 | ((x
& 0x11111111) << 3);
429 uint32_t HELPER(abs
)(uint32_t x
)
431 return ((int32_t)x
< 0) ? -x
: x
;
434 #if defined(CONFIG_USER_ONLY)
436 void do_interrupt (CPUARMState
*env
)
438 env
->exception_index
= -1;
441 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
445 env
->exception_index
= EXCP_PREFETCH_ABORT
;
446 env
->cp15
.c6_insn
= address
;
448 env
->exception_index
= EXCP_DATA_ABORT
;
449 env
->cp15
.c6_data
= address
;
454 /* These should probably raise undefined insn exceptions. */
455 void HELPER(set_cp
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
457 int op1
= (insn
>> 8) & 0xf;
458 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
462 uint32_t HELPER(get_cp
)(CPUARMState
*env
, uint32_t insn
)
464 int op1
= (insn
>> 8) & 0xf;
465 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
469 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
471 cpu_abort(env
, "cp15 insn %08x\n", insn
);
474 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
476 cpu_abort(env
, "cp15 insn %08x\n", insn
);
479 /* These should probably raise undefined insn exceptions. */
480 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
482 cpu_abort(env
, "v7m_mrs %d\n", reg
);
485 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
487 cpu_abort(env
, "v7m_mrs %d\n", reg
);
491 void switch_mode(CPUARMState
*env
, int mode
)
493 if (mode
!= ARM_CPU_MODE_USR
)
494 cpu_abort(env
, "Tried to switch out of user mode\n");
497 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
499 cpu_abort(env
, "banked r13 write\n");
502 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
504 cpu_abort(env
, "banked r13 read\n");
510 /* Map CPU modes onto saved register banks. */
511 static inline int bank_number(CPUARMState
*env
, int mode
)
514 case ARM_CPU_MODE_USR
:
515 case ARM_CPU_MODE_SYS
:
517 case ARM_CPU_MODE_SVC
:
519 case ARM_CPU_MODE_ABT
:
521 case ARM_CPU_MODE_UND
:
523 case ARM_CPU_MODE_IRQ
:
525 case ARM_CPU_MODE_FIQ
:
528 cpu_abort(env
, "Bad mode %x\n", mode
);
532 void switch_mode(CPUARMState
*env
, int mode
)
537 old_mode
= env
->uncached_cpsr
& CPSR_M
;
538 if (mode
== old_mode
)
541 if (old_mode
== ARM_CPU_MODE_FIQ
) {
542 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
543 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
544 } else if (mode
== ARM_CPU_MODE_FIQ
) {
545 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
546 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
549 i
= bank_number(env
, old_mode
);
550 env
->banked_r13
[i
] = env
->regs
[13];
551 env
->banked_r14
[i
] = env
->regs
[14];
552 env
->banked_spsr
[i
] = env
->spsr
;
554 i
= bank_number(env
, mode
);
555 env
->regs
[13] = env
->banked_r13
[i
];
556 env
->regs
[14] = env
->banked_r14
[i
];
557 env
->spsr
= env
->banked_spsr
[i
];
560 static void v7m_push(CPUARMState
*env
, uint32_t val
)
563 stl_phys(env
->regs
[13], val
);
566 static uint32_t v7m_pop(CPUARMState
*env
)
569 val
= ldl_phys(env
->regs
[13]);
574 /* Switch to V7M main or process stack pointer. */
575 static void switch_v7m_sp(CPUARMState
*env
, int process
)
578 if (env
->v7m
.current_sp
!= process
) {
579 tmp
= env
->v7m
.other_sp
;
580 env
->v7m
.other_sp
= env
->regs
[13];
582 env
->v7m
.current_sp
= process
;
586 static void do_v7m_exception_exit(CPUARMState
*env
)
591 type
= env
->regs
[15];
592 if (env
->v7m
.exception
!= 0)
593 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
595 /* Switch to the target stack. */
596 switch_v7m_sp(env
, (type
& 4) != 0);
598 env
->regs
[0] = v7m_pop(env
);
599 env
->regs
[1] = v7m_pop(env
);
600 env
->regs
[2] = v7m_pop(env
);
601 env
->regs
[3] = v7m_pop(env
);
602 env
->regs
[12] = v7m_pop(env
);
603 env
->regs
[14] = v7m_pop(env
);
604 env
->regs
[15] = v7m_pop(env
);
606 xpsr_write(env
, xpsr
, 0xfffffdff);
607 /* Undo stack alignment. */
610 /* ??? The exception return type specifies Thread/Handler mode. However
611 this is also implied by the xPSR value. Not sure what to do
612 if there is a mismatch. */
613 /* ??? Likewise for mismatches between the CONTROL register and the stack
617 static void do_interrupt_v7m(CPUARMState
*env
)
619 uint32_t xpsr
= xpsr_read(env
);
624 if (env
->v7m
.current_sp
)
626 if (env
->v7m
.exception
== 0)
629 /* For exceptions we just mark as pending on the NVIC, and let that
631 /* TODO: Need to escalate if the current priority is higher than the
632 one we're raising. */
633 switch (env
->exception_index
) {
635 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
639 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
641 case EXCP_PREFETCH_ABORT
:
642 case EXCP_DATA_ABORT
:
643 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
646 if (semihosting_enabled
) {
648 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
651 env
->regs
[0] = do_arm_semihosting(env
);
655 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
658 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
660 case EXCP_EXCEPTION_EXIT
:
661 do_v7m_exception_exit(env
);
664 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
665 return; /* Never happens. Keep compiler happy. */
668 /* Align stack pointer. */
669 /* ??? Should only do this if Configuration Control Register
670 STACKALIGN bit is set. */
671 if (env
->regs
[13] & 4) {
675 /* Switch to the handler mode. */
677 v7m_push(env
, env
->regs
[15]);
678 v7m_push(env
, env
->regs
[14]);
679 v7m_push(env
, env
->regs
[12]);
680 v7m_push(env
, env
->regs
[3]);
681 v7m_push(env
, env
->regs
[2]);
682 v7m_push(env
, env
->regs
[1]);
683 v7m_push(env
, env
->regs
[0]);
684 switch_v7m_sp(env
, 0);
686 env
->condexec_bits
= 0;
688 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
689 env
->regs
[15] = addr
& 0xfffffffe;
690 env
->thumb
= addr
& 1;
693 /* Handle a CPU exception. */
694 void do_interrupt(CPUARMState
*env
)
702 do_interrupt_v7m(env
);
705 /* TODO: Vectored interrupt controller. */
706 switch (env
->exception_index
) {
708 new_mode
= ARM_CPU_MODE_UND
;
717 if (semihosting_enabled
) {
718 /* Check for semihosting interrupt. */
720 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
722 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
725 /* Only intercept calls from privileged modes, to provide some
726 semblance of security. */
727 if (((mask
== 0x123456 && !env
->thumb
)
728 || (mask
== 0xab && env
->thumb
))
729 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
730 env
->regs
[0] = do_arm_semihosting(env
);
734 new_mode
= ARM_CPU_MODE_SVC
;
737 /* The PC already points to the next instruction. */
741 /* See if this is a semihosting syscall. */
742 if (env
->thumb
&& semihosting_enabled
) {
743 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
745 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
747 env
->regs
[0] = do_arm_semihosting(env
);
751 env
->cp15
.c5_insn
= 2;
752 /* Fall through to prefetch abort. */
753 case EXCP_PREFETCH_ABORT
:
754 new_mode
= ARM_CPU_MODE_ABT
;
756 mask
= CPSR_A
| CPSR_I
;
759 case EXCP_DATA_ABORT
:
760 new_mode
= ARM_CPU_MODE_ABT
;
762 mask
= CPSR_A
| CPSR_I
;
766 new_mode
= ARM_CPU_MODE_IRQ
;
768 /* Disable IRQ and imprecise data aborts. */
769 mask
= CPSR_A
| CPSR_I
;
773 new_mode
= ARM_CPU_MODE_FIQ
;
775 /* Disable FIQ, IRQ and imprecise data aborts. */
776 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
780 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
781 return; /* Never happens. Keep compiler happy. */
784 if (env
->cp15
.c1_sys
& (1 << 13)) {
787 switch_mode (env
, new_mode
);
788 env
->spsr
= cpsr_read(env
);
790 env
->condexec_bits
= 0;
791 /* Switch to the new mode, and to the correct instruction set. */
792 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
793 env
->uncached_cpsr
|= mask
;
794 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
795 * and we should just guard the thumb mode on V4 */
796 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
797 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
799 env
->regs
[14] = env
->regs
[15] + offset
;
800 env
->regs
[15] = addr
;
801 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
804 /* Check section/page access permissions.
805 Returns the page protection flags, or zero if the access is not
807 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
808 int access_type
, int is_user
)
812 if (domain_prot
== 3) {
813 return PAGE_READ
| PAGE_WRITE
;
816 if (access_type
== 1)
823 if (access_type
== 1)
825 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
827 return is_user
? 0 : PAGE_READ
;
834 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
839 return PAGE_READ
| PAGE_WRITE
;
841 return PAGE_READ
| PAGE_WRITE
;
842 case 4: /* Reserved. */
845 return is_user
? 0 : prot_ro
;
849 if (!arm_feature (env
, ARM_FEATURE_V6K
))
857 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
861 if (address
& env
->cp15
.c2_mask
)
862 table
= env
->cp15
.c2_base1
& 0xffffc000;
864 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
866 table
|= (address
>> 18) & 0x3ffc;
870 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
871 int is_user
, uint32_t *phys_ptr
, int *prot
,
872 target_ulong
*page_size
)
883 /* Pagetable walk. */
884 /* Lookup l1 descriptor. */
885 table
= get_level1_table_address(env
, address
);
886 desc
= ldl_phys(table
);
888 domain
= (desc
>> 5) & 0x0f;
889 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
891 /* Section translation fault. */
895 if (domain_prot
== 0 || domain_prot
== 2) {
897 code
= 9; /* Section domain fault. */
899 code
= 11; /* Page domain fault. */
904 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
905 ap
= (desc
>> 10) & 3;
907 *page_size
= 1024 * 1024;
909 /* Lookup l2 entry. */
911 /* Coarse pagetable. */
912 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
914 /* Fine pagetable. */
915 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
917 desc
= ldl_phys(table
);
919 case 0: /* Page translation fault. */
922 case 1: /* 64k page. */
923 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
924 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
925 *page_size
= 0x10000;
927 case 2: /* 4k page. */
928 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
929 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
932 case 3: /* 1k page. */
934 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
935 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
937 /* Page translation fault. */
942 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
944 ap
= (desc
>> 4) & 3;
948 /* Never happens, but compiler isn't smart enough to tell. */
953 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
955 /* Access permission fault. */
959 *phys_ptr
= phys_addr
;
962 return code
| (domain
<< 4);
965 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
966 int is_user
, uint32_t *phys_ptr
, int *prot
,
967 target_ulong
*page_size
)
979 /* Pagetable walk. */
980 /* Lookup l1 descriptor. */
981 table
= get_level1_table_address(env
, address
);
982 desc
= ldl_phys(table
);
985 /* Section translation fault. */
989 } else if (type
== 2 && (desc
& (1 << 18))) {
993 /* Section or page. */
994 domain
= (desc
>> 5) & 0x0f;
996 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
997 if (domain_prot
== 0 || domain_prot
== 2) {
999 code
= 9; /* Section domain fault. */
1001 code
= 11; /* Page domain fault. */
1005 if (desc
& (1 << 18)) {
1007 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1008 *page_size
= 0x1000000;
1011 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1012 *page_size
= 0x100000;
1014 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1015 xn
= desc
& (1 << 4);
1018 /* Lookup l2 entry. */
1019 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1020 desc
= ldl_phys(table
);
1021 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1023 case 0: /* Page translation fault. */
1026 case 1: /* 64k page. */
1027 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1028 xn
= desc
& (1 << 15);
1029 *page_size
= 0x10000;
1031 case 2: case 3: /* 4k page. */
1032 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1034 *page_size
= 0x1000;
1037 /* Never happens, but compiler isn't smart enough to tell. */
1042 if (domain_prot
== 3) {
1043 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1045 if (xn
&& access_type
== 2)
1048 /* The simplified model uses AP[0] as an access control bit. */
1049 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1050 /* Access flag fault. */
1051 code
= (code
== 15) ? 6 : 3;
1054 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1056 /* Access permission fault. */
1063 *phys_ptr
= phys_addr
;
1066 return code
| (domain
<< 4);
1069 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1070 int is_user
, uint32_t *phys_ptr
, int *prot
)
1076 *phys_ptr
= address
;
1077 for (n
= 7; n
>= 0; n
--) {
1078 base
= env
->cp15
.c6_region
[n
];
1079 if ((base
& 1) == 0)
1081 mask
= 1 << ((base
>> 1) & 0x1f);
1082 /* Keep this shift separate from the above to avoid an
1083 (undefined) << 32. */
1084 mask
= (mask
<< 1) - 1;
1085 if (((base
^ address
) & ~mask
) == 0)
1091 if (access_type
== 2) {
1092 mask
= env
->cp15
.c5_insn
;
1094 mask
= env
->cp15
.c5_data
;
1096 mask
= (mask
>> (n
* 4)) & 0xf;
1103 *prot
= PAGE_READ
| PAGE_WRITE
;
1108 *prot
|= PAGE_WRITE
;
1111 *prot
= PAGE_READ
| PAGE_WRITE
;
1122 /* Bad permission. */
1129 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1130 int access_type
, int is_user
,
1131 uint32_t *phys_ptr
, int *prot
,
1132 target_ulong
*page_size
)
1134 /* Fast Context Switch Extension. */
1135 if (address
< 0x02000000)
1136 address
+= env
->cp15
.c13_fcse
;
1138 if ((env
->cp15
.c1_sys
& 1) == 0) {
1139 /* MMU/MPU disabled. */
1140 *phys_ptr
= address
;
1141 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1142 *page_size
= TARGET_PAGE_SIZE
;
1144 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1145 *page_size
= TARGET_PAGE_SIZE
;
1146 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1148 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1149 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1152 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1157 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1158 int access_type
, int mmu_idx
)
1161 target_ulong page_size
;
1165 is_user
= mmu_idx
== MMU_USER_IDX
;
1166 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1169 /* Map a single [sub]page. */
1170 phys_addr
&= ~(uint32_t)0x3ff;
1171 address
&= ~(uint32_t)0x3ff;
1172 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1176 if (access_type
== 2) {
1177 env
->cp15
.c5_insn
= ret
;
1178 env
->cp15
.c6_insn
= address
;
1179 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1181 env
->cp15
.c5_data
= ret
;
1182 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1183 env
->cp15
.c5_data
|= (1 << 11);
1184 env
->cp15
.c6_data
= address
;
1185 env
->exception_index
= EXCP_DATA_ABORT
;
1190 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1193 target_ulong page_size
;
1197 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1205 void HELPER(set_cp
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1207 int cp_num
= (insn
>> 8) & 0xf;
1208 int cp_info
= (insn
>> 5) & 7;
1209 int src
= (insn
>> 16) & 0xf;
1210 int operand
= insn
& 0xf;
1212 if (env
->cp
[cp_num
].cp_write
)
1213 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1214 cp_info
, src
, operand
, val
);
1217 uint32_t HELPER(get_cp
)(CPUARMState
*env
, uint32_t insn
)
1219 int cp_num
= (insn
>> 8) & 0xf;
1220 int cp_info
= (insn
>> 5) & 7;
1221 int dest
= (insn
>> 16) & 0xf;
1222 int operand
= insn
& 0xf;
1224 if (env
->cp
[cp_num
].cp_read
)
1225 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1226 cp_info
, dest
, operand
);
1230 /* Return basic MPU access permission bits. */
1231 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1238 for (i
= 0; i
< 16; i
+= 2) {
1239 ret
|= (val
>> i
) & mask
;
1245 /* Pad basic MPU access permission bits to extended format. */
1246 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1253 for (i
= 0; i
< 16; i
+= 2) {
1254 ret
|= (val
& mask
) << i
;
1260 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1266 op1
= (insn
>> 21) & 7;
1267 op2
= (insn
>> 5) & 7;
1269 switch ((insn
>> 16) & 0xf) {
1272 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1274 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1276 if (arm_feature(env
, ARM_FEATURE_V7
)
1277 && op1
== 2 && crm
== 0 && op2
== 0) {
1278 env
->cp15
.c0_cssel
= val
& 0xf;
1282 case 1: /* System configuration. */
1283 if (arm_feature(env
, ARM_FEATURE_V7
)
1284 && op1
== 0 && crm
== 1 && op2
== 0) {
1285 env
->cp15
.c1_scr
= val
;
1288 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1292 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1293 env
->cp15
.c1_sys
= val
;
1294 /* ??? Lots of these bits are not implemented. */
1295 /* This may enable/disable the MMU, so do a TLB flush. */
1298 case 1: /* Auxiliary control register. */
1299 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1300 env
->cp15
.c1_xscaleauxcr
= val
;
1303 /* Not implemented. */
1306 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1308 if (env
->cp15
.c1_coproc
!= val
) {
1309 env
->cp15
.c1_coproc
= val
;
1310 /* ??? Is this safe when called from within a TB? */
1318 case 2: /* MMU Page table control / MPU cache control. */
1319 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1322 env
->cp15
.c2_data
= val
;
1325 env
->cp15
.c2_insn
= val
;
1333 env
->cp15
.c2_base0
= val
;
1336 env
->cp15
.c2_base1
= val
;
1340 env
->cp15
.c2_control
= val
;
1341 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1342 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1349 case 3: /* MMU Domain access control / MPU write buffer control. */
1351 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1353 case 4: /* Reserved. */
1355 case 5: /* MMU Fault status / MPU access permission. */
1356 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1360 if (arm_feature(env
, ARM_FEATURE_MPU
))
1361 val
= extended_mpu_ap_bits(val
);
1362 env
->cp15
.c5_data
= val
;
1365 if (arm_feature(env
, ARM_FEATURE_MPU
))
1366 val
= extended_mpu_ap_bits(val
);
1367 env
->cp15
.c5_insn
= val
;
1370 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1372 env
->cp15
.c5_data
= val
;
1375 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1377 env
->cp15
.c5_insn
= val
;
1383 case 6: /* MMU Fault address / MPU base/size. */
1384 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1387 env
->cp15
.c6_region
[crm
] = val
;
1389 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1393 env
->cp15
.c6_data
= val
;
1395 case 1: /* ??? This is WFAR on armv6 */
1397 env
->cp15
.c6_insn
= val
;
1404 case 7: /* Cache control. */
1405 env
->cp15
.c15_i_max
= 0x000;
1406 env
->cp15
.c15_i_min
= 0xff0;
1410 /* No cache, so nothing to do except VA->PA translations. */
1411 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1414 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1415 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1417 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1422 target_ulong page_size
;
1424 int ret
, is_user
= op2
& 2;
1425 int access_type
= op2
& 1;
1428 /* Other states are only available with TrustZone */
1431 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1432 &phys_addr
, &prot
, &page_size
);
1434 /* We do not set any attribute bits in the PAR */
1435 if (page_size
== (1 << 24)
1436 && arm_feature(env
, ARM_FEATURE_V7
)) {
1437 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1439 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1442 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1443 ((ret
& (12 << 1)) >> 6) |
1444 ((ret
& 0xf) << 1) | 1;
1451 case 8: /* MMU TLB control. */
1453 case 0: /* Invalidate all (TLBIALL) */
1456 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
1457 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1459 case 2: /* Invalidate by ASID (TLBIASID) */
1460 tlb_flush(env
, val
== 0);
1462 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1463 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1470 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1472 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1473 break; /* Ignore ReadBuffer access */
1475 case 0: /* Cache lockdown. */
1477 case 0: /* L1 cache. */
1480 env
->cp15
.c9_data
= val
;
1483 env
->cp15
.c9_insn
= val
;
1489 case 1: /* L2 cache. */
1490 /* Ignore writes to L2 lockdown/auxiliary registers. */
1496 case 1: /* TCM memory region registers. */
1497 /* Not implemented. */
1499 case 12: /* Performance monitor control */
1500 /* Performance monitors are implementation defined in v7,
1501 * but with an ARM recommended set of registers, which we
1502 * follow (although we don't actually implement any counters)
1504 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1508 case 0: /* performance monitor control register */
1509 /* only the DP, X, D and E bits are writable */
1510 env
->cp15
.c9_pmcr
&= ~0x39;
1511 env
->cp15
.c9_pmcr
|= (val
& 0x39);
1513 case 1: /* Count enable set register */
1515 env
->cp15
.c9_pmcnten
|= val
;
1517 case 2: /* Count enable clear */
1519 env
->cp15
.c9_pmcnten
&= ~val
;
1521 case 3: /* Overflow flag status */
1522 env
->cp15
.c9_pmovsr
&= ~val
;
1524 case 4: /* Software increment */
1525 /* RAZ/WI since we don't implement the software-count event */
1527 case 5: /* Event counter selection register */
1528 /* Since we don't implement any events, writing to this register
1529 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1536 case 13: /* Performance counters */
1537 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1541 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1543 case 1: /* Event type select */
1544 env
->cp15
.c9_pmxevtyper
= val
& 0xff;
1546 case 2: /* Event count register */
1547 /* Unimplemented (we have no events), RAZ/WI */
1553 case 14: /* Performance monitor control */
1554 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1558 case 0: /* user enable */
1559 env
->cp15
.c9_pmuserenr
= val
& 1;
1560 /* changes access rights for cp registers, so flush tbs */
1563 case 1: /* interrupt enable set */
1564 /* We have no event counters so only the C bit can be changed */
1566 env
->cp15
.c9_pminten
|= val
;
1568 case 2: /* interrupt enable clear */
1570 env
->cp15
.c9_pminten
&= ~val
;
1578 case 10: /* MMU TLB lockdown. */
1579 /* ??? TLB lockdown not implemented. */
1581 case 12: /* Reserved. */
1583 case 13: /* Process ID. */
1586 /* Unlike real hardware the qemu TLB uses virtual addresses,
1587 not modified virtual addresses, so this causes a TLB flush.
1589 if (env
->cp15
.c13_fcse
!= val
)
1591 env
->cp15
.c13_fcse
= val
;
1594 /* This changes the ASID, so do a TLB flush. */
1595 if (env
->cp15
.c13_context
!= val
1596 && !arm_feature(env
, ARM_FEATURE_MPU
))
1598 env
->cp15
.c13_context
= val
;
1604 case 14: /* Generic timer */
1605 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1606 /* Dummy implementation: RAZ/WI for all */
1610 case 15: /* Implementation specific. */
1611 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1612 if (op2
== 0 && crm
== 1) {
1613 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1614 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1616 env
->cp15
.c15_cpar
= val
& 0x3fff;
1622 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1626 case 1: /* Set TI925T configuration. */
1627 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1628 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1629 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1631 case 2: /* Set I_max. */
1632 env
->cp15
.c15_i_max
= val
;
1634 case 3: /* Set I_min. */
1635 env
->cp15
.c15_i_min
= val
;
1637 case 4: /* Set thread-ID. */
1638 env
->cp15
.c15_threadid
= val
& 0xffff;
1640 case 8: /* Wait-for-interrupt (deprecated). */
1641 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1647 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1650 if ((op1
== 0) && (op2
== 0)) {
1651 env
->cp15
.c15_power_control
= val
;
1652 } else if ((op1
== 0) && (op2
== 1)) {
1653 env
->cp15
.c15_diagnostic
= val
;
1654 } else if ((op1
== 0) && (op2
== 2)) {
1655 env
->cp15
.c15_power_diagnostic
= val
;
1665 /* ??? For debugging only. Should raise illegal instruction exception. */
1666 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1667 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1670 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1676 op1
= (insn
>> 21) & 7;
1677 op2
= (insn
>> 5) & 7;
1679 switch ((insn
>> 16) & 0xf) {
1680 case 0: /* ID codes. */
1686 case 0: /* Device ID. */
1687 return env
->cp15
.c0_cpuid
;
1688 case 1: /* Cache Type. */
1689 return env
->cp15
.c0_cachetype
;
1690 case 2: /* TCM status. */
1692 case 3: /* TLB type register. */
1693 return 0; /* No lockable TLB entries. */
1695 /* The MPIDR was standardised in v7; prior to
1696 * this it was implemented only in the 11MPCore.
1697 * For all other pre-v7 cores it does not exist.
1699 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1700 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1701 int mpidr
= env
->cpu_index
;
1702 /* We don't support setting cluster ID ([8..11])
1703 * so these bits always RAZ.
1705 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1707 /* Cores which are uniprocessor (non-coherent)
1708 * but still implement the MP extensions set
1709 * bit 30. (For instance, A9UP.) However we do
1710 * not currently model any of those cores.
1715 /* otherwise fall through to the unimplemented-reg case */
1720 if (!arm_feature(env
, ARM_FEATURE_V6
))
1722 return env
->cp15
.c0_c1
[op2
];
1724 if (!arm_feature(env
, ARM_FEATURE_V6
))
1726 return env
->cp15
.c0_c2
[op2
];
1727 case 3: case 4: case 5: case 6: case 7:
1733 /* These registers aren't documented on arm11 cores. However
1734 Linux looks at them anyway. */
1735 if (!arm_feature(env
, ARM_FEATURE_V6
))
1739 if (!arm_feature(env
, ARM_FEATURE_V7
))
1744 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1746 return env
->cp15
.c0_clid
;
1752 if (op2
!= 0 || crm
!= 0)
1754 return env
->cp15
.c0_cssel
;
1758 case 1: /* System configuration. */
1759 if (arm_feature(env
, ARM_FEATURE_V7
)
1760 && op1
== 0 && crm
== 1 && op2
== 0) {
1761 return env
->cp15
.c1_scr
;
1763 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1766 case 0: /* Control register. */
1767 return env
->cp15
.c1_sys
;
1768 case 1: /* Auxiliary control register. */
1769 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1770 return env
->cp15
.c1_xscaleauxcr
;
1771 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1773 switch (ARM_CPUID(env
)) {
1774 case ARM_CPUID_ARM1026
:
1776 case ARM_CPUID_ARM1136
:
1777 case ARM_CPUID_ARM1136_R2
:
1778 case ARM_CPUID_ARM1176
:
1780 case ARM_CPUID_ARM11MPCORE
:
1782 case ARM_CPUID_CORTEXA8
:
1784 case ARM_CPUID_CORTEXA9
:
1785 case ARM_CPUID_CORTEXA15
:
1790 case 2: /* Coprocessor access register. */
1791 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1793 return env
->cp15
.c1_coproc
;
1797 case 2: /* MMU Page table control / MPU cache control. */
1798 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1801 return env
->cp15
.c2_data
;
1804 return env
->cp15
.c2_insn
;
1812 return env
->cp15
.c2_base0
;
1814 return env
->cp15
.c2_base1
;
1816 return env
->cp15
.c2_control
;
1821 case 3: /* MMU Domain access control / MPU write buffer control. */
1822 return env
->cp15
.c3
;
1823 case 4: /* Reserved. */
1825 case 5: /* MMU Fault status / MPU access permission. */
1826 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1830 if (arm_feature(env
, ARM_FEATURE_MPU
))
1831 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1832 return env
->cp15
.c5_data
;
1834 if (arm_feature(env
, ARM_FEATURE_MPU
))
1835 return simple_mpu_ap_bits(env
->cp15
.c5_insn
);
1836 return env
->cp15
.c5_insn
;
1838 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1840 return env
->cp15
.c5_data
;
1842 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1844 return env
->cp15
.c5_insn
;
1848 case 6: /* MMU Fault address. */
1849 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1852 return env
->cp15
.c6_region
[crm
];
1854 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1858 return env
->cp15
.c6_data
;
1860 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1861 /* Watchpoint Fault Adrress. */
1862 return 0; /* Not implemented. */
1864 /* Instruction Fault Adrress. */
1865 /* Arm9 doesn't have an IFAR, but implementing it anyway
1866 shouldn't do any harm. */
1867 return env
->cp15
.c6_insn
;
1870 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1871 /* Instruction Fault Adrress. */
1872 return env
->cp15
.c6_insn
;
1880 case 7: /* Cache control. */
1881 if (crm
== 4 && op1
== 0 && op2
== 0) {
1882 return env
->cp15
.c7_par
;
1884 /* FIXME: Should only clear Z flag if destination is r15. */
1887 case 8: /* MMU TLB control. */
1891 case 0: /* Cache lockdown */
1893 case 0: /* L1 cache. */
1894 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1899 return env
->cp15
.c9_data
;
1901 return env
->cp15
.c9_insn
;
1905 case 1: /* L2 cache */
1906 /* L2 Lockdown and Auxiliary control. */
1909 /* L2 cache lockdown (A8 only) */
1912 /* L2 cache auxiliary control (A8) or control (A15) */
1913 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
1914 /* Linux wants the number of processors from here.
1915 * Might as well set the interrupt-controller bit too.
1917 return ((smp_cpus
- 1) << 24) | (1 << 23);
1921 /* L2 cache extended control (A15) */
1930 case 12: /* Performance monitor control */
1931 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1935 case 0: /* performance monitor control register */
1936 return env
->cp15
.c9_pmcr
;
1937 case 1: /* count enable set */
1938 case 2: /* count enable clear */
1939 return env
->cp15
.c9_pmcnten
;
1940 case 3: /* overflow flag status */
1941 return env
->cp15
.c9_pmovsr
;
1942 case 4: /* software increment */
1943 case 5: /* event counter selection register */
1944 return 0; /* Unimplemented, RAZ/WI */
1948 case 13: /* Performance counters */
1949 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1953 case 1: /* Event type select */
1954 return env
->cp15
.c9_pmxevtyper
;
1955 case 0: /* Cycle count register */
1956 case 2: /* Event count register */
1957 /* Unimplemented, so RAZ/WI */
1962 case 14: /* Performance monitor control */
1963 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1967 case 0: /* user enable */
1968 return env
->cp15
.c9_pmuserenr
;
1969 case 1: /* interrupt enable set */
1970 case 2: /* interrupt enable clear */
1971 return env
->cp15
.c9_pminten
;
1979 case 10: /* MMU TLB lockdown. */
1980 /* ??? TLB lockdown not implemented. */
1982 case 11: /* TCM DMA control. */
1983 case 12: /* Reserved. */
1985 case 13: /* Process ID. */
1988 return env
->cp15
.c13_fcse
;
1990 return env
->cp15
.c13_context
;
1994 case 14: /* Generic timer */
1995 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1996 /* Dummy implementation: RAZ/WI for all */
2000 case 15: /* Implementation specific. */
2001 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2002 if (op2
== 0 && crm
== 1)
2003 return env
->cp15
.c15_cpar
;
2007 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2011 case 1: /* Read TI925T configuration. */
2012 return env
->cp15
.c15_ticonfig
;
2013 case 2: /* Read I_max. */
2014 return env
->cp15
.c15_i_max
;
2015 case 3: /* Read I_min. */
2016 return env
->cp15
.c15_i_min
;
2017 case 4: /* Read thread-ID. */
2018 return env
->cp15
.c15_threadid
;
2019 case 8: /* TI925T_status */
2022 /* TODO: Peripheral port remap register:
2023 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2024 * controller base address at $rn & ~0xfff and map size of
2025 * 0x200 << ($rn & 0xfff), when MMU is off. */
2028 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
2031 if ((op1
== 4) && (op2
== 0)) {
2032 /* The config_base_address should hold the value of
2033 * the peripheral base. ARM should get this from a CPU
2034 * object property, but that support isn't available in
2035 * December 2011. Default to 0 for now and board models
2036 * that care can set it by a private hook */
2037 return env
->cp15
.c15_config_base_address
;
2038 } else if ((op1
== 0) && (op2
== 0)) {
2039 /* power_control should be set to maximum latency. Again,
2040 default to 0 and set by private hook */
2041 return env
->cp15
.c15_power_control
;
2042 } else if ((op1
== 0) && (op2
== 1)) {
2043 return env
->cp15
.c15_diagnostic
;
2044 } else if ((op1
== 0) && (op2
== 2)) {
2045 return env
->cp15
.c15_power_diagnostic
;
2048 case 1: /* NEON Busy */
2050 case 5: /* tlb lockdown */
2053 if ((op1
== 5) && (op2
== 2)) {
2065 /* ??? For debugging only. Should raise illegal instruction exception. */
2066 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2067 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2071 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2073 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2074 env
->regs
[13] = val
;
2076 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2080 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2082 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2083 return env
->regs
[13];
2085 return env
->banked_r13
[bank_number(env
, mode
)];
2089 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2093 return xpsr_read(env
) & 0xf8000000;
2095 return xpsr_read(env
) & 0xf80001ff;
2097 return xpsr_read(env
) & 0xff00fc00;
2099 return xpsr_read(env
) & 0xff00fdff;
2101 return xpsr_read(env
) & 0x000001ff;
2103 return xpsr_read(env
) & 0x0700fc00;
2105 return xpsr_read(env
) & 0x0700edff;
2107 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2109 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2110 case 16: /* PRIMASK */
2111 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2112 case 17: /* BASEPRI */
2113 case 18: /* BASEPRI_MAX */
2114 return env
->v7m
.basepri
;
2115 case 19: /* FAULTMASK */
2116 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2117 case 20: /* CONTROL */
2118 return env
->v7m
.control
;
2120 /* ??? For debugging only. */
2121 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2126 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2130 xpsr_write(env
, val
, 0xf8000000);
2133 xpsr_write(env
, val
, 0xf8000000);
2136 xpsr_write(env
, val
, 0xfe00fc00);
2139 xpsr_write(env
, val
, 0xfe00fc00);
2142 /* IPSR bits are readonly. */
2145 xpsr_write(env
, val
, 0x0600fc00);
2148 xpsr_write(env
, val
, 0x0600fc00);
2151 if (env
->v7m
.current_sp
)
2152 env
->v7m
.other_sp
= val
;
2154 env
->regs
[13] = val
;
2157 if (env
->v7m
.current_sp
)
2158 env
->regs
[13] = val
;
2160 env
->v7m
.other_sp
= val
;
2162 case 16: /* PRIMASK */
2164 env
->uncached_cpsr
|= CPSR_I
;
2166 env
->uncached_cpsr
&= ~CPSR_I
;
2168 case 17: /* BASEPRI */
2169 env
->v7m
.basepri
= val
& 0xff;
2171 case 18: /* BASEPRI_MAX */
2173 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2174 env
->v7m
.basepri
= val
;
2176 case 19: /* FAULTMASK */
2178 env
->uncached_cpsr
|= CPSR_F
;
2180 env
->uncached_cpsr
&= ~CPSR_F
;
2182 case 20: /* CONTROL */
2183 env
->v7m
.control
= val
& 3;
2184 switch_v7m_sp(env
, (val
& 2) != 0);
2187 /* ??? For debugging only. */
2188 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2193 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
2194 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
2197 if (cpnum
< 0 || cpnum
> 14) {
2198 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2202 env
->cp
[cpnum
].cp_read
= cp_read
;
2203 env
->cp
[cpnum
].cp_write
= cp_write
;
2204 env
->cp
[cpnum
].opaque
= opaque
;
2209 /* Note that signed overflow is undefined in C. The following routines are
2210 careful to use unsigned types where modulo arithmetic is required.
2211 Failure to do so _will_ break on newer gcc. */
2213 /* Signed saturating arithmetic. */
2215 /* Perform 16-bit signed saturating addition. */
2216 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2221 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2230 /* Perform 8-bit signed saturating addition. */
2231 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2236 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2245 /* Perform 16-bit signed saturating subtraction. */
2246 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2251 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2260 /* Perform 8-bit signed saturating subtraction. */
2261 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2266 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2275 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2276 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2277 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2278 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2281 #include "op_addsub.h"
2283 /* Unsigned saturating arithmetic. */
2284 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2293 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2301 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2310 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2318 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2319 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2320 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2321 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2324 #include "op_addsub.h"
2326 /* Signed modulo arithmetic. */
2327 #define SARITH16(a, b, n, op) do { \
2329 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2330 RESULT(sum, n, 16); \
2332 ge |= 3 << (n * 2); \
2335 #define SARITH8(a, b, n, op) do { \
2337 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2338 RESULT(sum, n, 8); \
2344 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2345 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2346 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2347 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2351 #include "op_addsub.h"
2353 /* Unsigned modulo arithmetic. */
2354 #define ADD16(a, b, n) do { \
2356 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2357 RESULT(sum, n, 16); \
2358 if ((sum >> 16) == 1) \
2359 ge |= 3 << (n * 2); \
2362 #define ADD8(a, b, n) do { \
2364 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2365 RESULT(sum, n, 8); \
2366 if ((sum >> 8) == 1) \
2370 #define SUB16(a, b, n) do { \
2372 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2373 RESULT(sum, n, 16); \
2374 if ((sum >> 16) == 0) \
2375 ge |= 3 << (n * 2); \
2378 #define SUB8(a, b, n) do { \
2380 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2381 RESULT(sum, n, 8); \
2382 if ((sum >> 8) == 0) \
2389 #include "op_addsub.h"
2391 /* Halved signed arithmetic. */
2392 #define ADD16(a, b, n) \
2393 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2394 #define SUB16(a, b, n) \
2395 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2396 #define ADD8(a, b, n) \
2397 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2398 #define SUB8(a, b, n) \
2399 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2402 #include "op_addsub.h"
2404 /* Halved unsigned arithmetic. */
2405 #define ADD16(a, b, n) \
2406 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2407 #define SUB16(a, b, n) \
2408 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2409 #define ADD8(a, b, n) \
2410 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2411 #define SUB8(a, b, n) \
2412 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2415 #include "op_addsub.h"
2417 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2425 /* Unsigned sum of absolute byte differences. */
2426 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2429 sum
= do_usad(a
, b
);
2430 sum
+= do_usad(a
>> 8, b
>> 8);
2431 sum
+= do_usad(a
>> 16, b
>>16);
2432 sum
+= do_usad(a
>> 24, b
>> 24);
2436 /* For ARMv6 SEL instruction. */
2437 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2450 return (a
& mask
) | (b
& ~mask
);
2453 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2455 return (val
>> 32) | (val
!= 0);
2458 /* VFP support. We follow the convention used for VFP instrunctions:
2459 Single precition routines have a "s" suffix, double precision a
2462 /* Convert host exception flags to vfp form. */
2463 static inline int vfp_exceptbits_from_host(int host_bits
)
2465 int target_bits
= 0;
2467 if (host_bits
& float_flag_invalid
)
2469 if (host_bits
& float_flag_divbyzero
)
2471 if (host_bits
& float_flag_overflow
)
2473 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2475 if (host_bits
& float_flag_inexact
)
2476 target_bits
|= 0x10;
2477 if (host_bits
& float_flag_input_denormal
)
2478 target_bits
|= 0x80;
2482 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2487 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2488 | (env
->vfp
.vec_len
<< 16)
2489 | (env
->vfp
.vec_stride
<< 20);
2490 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2491 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2492 fpscr
|= vfp_exceptbits_from_host(i
);
2496 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2498 return HELPER(vfp_get_fpscr
)(env
);
2501 /* Convert vfp exception flags to target form. */
2502 static inline int vfp_exceptbits_to_host(int target_bits
)
2506 if (target_bits
& 1)
2507 host_bits
|= float_flag_invalid
;
2508 if (target_bits
& 2)
2509 host_bits
|= float_flag_divbyzero
;
2510 if (target_bits
& 4)
2511 host_bits
|= float_flag_overflow
;
2512 if (target_bits
& 8)
2513 host_bits
|= float_flag_underflow
;
2514 if (target_bits
& 0x10)
2515 host_bits
|= float_flag_inexact
;
2516 if (target_bits
& 0x80)
2517 host_bits
|= float_flag_input_denormal
;
2521 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2526 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2527 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2528 env
->vfp
.vec_len
= (val
>> 16) & 7;
2529 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2532 if (changed
& (3 << 22)) {
2533 i
= (val
>> 22) & 3;
2536 i
= float_round_nearest_even
;
2542 i
= float_round_down
;
2545 i
= float_round_to_zero
;
2548 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2550 if (changed
& (1 << 24)) {
2551 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2552 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2554 if (changed
& (1 << 25))
2555 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2557 i
= vfp_exceptbits_to_host(val
);
2558 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2559 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2562 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2564 HELPER(vfp_set_fpscr
)(env
, val
);
2567 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2569 #define VFP_BINOP(name) \
2570 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2572 float_status *fpst = fpstp; \
2573 return float32_ ## name(a, b, fpst); \
2575 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2577 float_status *fpst = fpstp; \
2578 return float64_ ## name(a, b, fpst); \
2586 float32
VFP_HELPER(neg
, s
)(float32 a
)
2588 return float32_chs(a
);
2591 float64
VFP_HELPER(neg
, d
)(float64 a
)
2593 return float64_chs(a
);
2596 float32
VFP_HELPER(abs
, s
)(float32 a
)
2598 return float32_abs(a
);
2601 float64
VFP_HELPER(abs
, d
)(float64 a
)
2603 return float64_abs(a
);
2606 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2608 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2611 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2613 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2616 /* XXX: check quiet/signaling case */
2617 #define DO_VFP_cmp(p, type) \
2618 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2621 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2622 case 0: flags = 0x6; break; \
2623 case -1: flags = 0x8; break; \
2624 case 1: flags = 0x2; break; \
2625 default: case 2: flags = 0x3; break; \
2627 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2628 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2630 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2633 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2634 case 0: flags = 0x6; break; \
2635 case -1: flags = 0x8; break; \
2636 case 1: flags = 0x2; break; \
2637 default: case 2: flags = 0x3; break; \
2639 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2640 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2642 DO_VFP_cmp(s
, float32
)
2643 DO_VFP_cmp(d
, float64
)
2646 /* Integer to float and float to integer conversions */
2648 #define CONV_ITOF(name, fsz, sign) \
2649 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2651 float_status *fpst = fpstp; \
2652 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2655 #define CONV_FTOI(name, fsz, sign, round) \
2656 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2658 float_status *fpst = fpstp; \
2659 if (float##fsz##_is_any_nan(x)) { \
2660 float_raise(float_flag_invalid, fpst); \
2663 return float##fsz##_to_##sign##int32##round(x, fpst); \
2666 #define FLOAT_CONVS(name, p, fsz, sign) \
2667 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2668 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2669 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2671 FLOAT_CONVS(si
, s
, 32, )
2672 FLOAT_CONVS(si
, d
, 64, )
2673 FLOAT_CONVS(ui
, s
, 32, u
)
2674 FLOAT_CONVS(ui
, d
, 64, u
)
2680 /* floating point conversion */
2681 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2683 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2684 /* ARM requires that S<->D conversion of any kind of NaN generates
2685 * a quiet NaN by forcing the most significant frac bit to 1.
2687 return float64_maybe_silence_nan(r
);
2690 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2692 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2693 /* ARM requires that S<->D conversion of any kind of NaN generates
2694 * a quiet NaN by forcing the most significant frac bit to 1.
2696 return float32_maybe_silence_nan(r
);
2699 /* VFP3 fixed point conversion. */
2700 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2701 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2704 float_status *fpst = fpstp; \
2706 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2707 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2709 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2712 float_status *fpst = fpstp; \
2714 if (float##fsz##_is_any_nan(x)) { \
2715 float_raise(float_flag_invalid, fpst); \
2718 tmp = float##fsz##_scalbn(x, shift, fpst); \
2719 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2722 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2723 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2724 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2725 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2726 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2727 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2728 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2729 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2732 /* Half precision conversions. */
2733 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2735 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2736 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2738 return float32_maybe_silence_nan(r
);
2743 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2745 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2746 float16 r
= float32_to_float16(a
, ieee
, s
);
2748 r
= float16_maybe_silence_nan(r
);
2750 return float16_val(r
);
2753 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2755 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2758 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2760 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2763 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2765 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2768 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2770 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2773 #define float32_two make_float32(0x40000000)
2774 #define float32_three make_float32(0x40400000)
2775 #define float32_one_point_five make_float32(0x3fc00000)
2777 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2779 float_status
*s
= &env
->vfp
.standard_fp_status
;
2780 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2781 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2782 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2783 float_raise(float_flag_input_denormal
, s
);
2787 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2790 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2792 float_status
*s
= &env
->vfp
.standard_fp_status
;
2794 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2795 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2796 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2797 float_raise(float_flag_input_denormal
, s
);
2799 return float32_one_point_five
;
2801 product
= float32_mul(a
, b
, s
);
2802 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2807 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2808 * int->float conversions at run-time. */
2809 #define float64_256 make_float64(0x4070000000000000LL)
2810 #define float64_512 make_float64(0x4080000000000000LL)
2812 /* The algorithm that must be used to calculate the estimate
2813 * is specified by the ARM ARM.
2815 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2817 /* These calculations mustn't set any fp exception flags,
2818 * so we use a local copy of the fp_status.
2820 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2821 float_status
*s
= &dummy_status
;
2822 /* q = (int)(a * 512.0) */
2823 float64 q
= float64_mul(float64_512
, a
, s
);
2824 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2826 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2827 q
= int64_to_float64(q_int
, s
);
2828 q
= float64_add(q
, float64_half
, s
);
2829 q
= float64_div(q
, float64_512
, s
);
2830 q
= float64_div(float64_one
, q
, s
);
2832 /* s = (int)(256.0 * r + 0.5) */
2833 q
= float64_mul(q
, float64_256
, s
);
2834 q
= float64_add(q
, float64_half
, s
);
2835 q_int
= float64_to_int64_round_to_zero(q
, s
);
2837 /* return (double)s / 256.0 */
2838 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2841 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2843 float_status
*s
= &env
->vfp
.standard_fp_status
;
2845 uint32_t val32
= float32_val(a
);
2848 int a_exp
= (val32
& 0x7f800000) >> 23;
2849 int sign
= val32
& 0x80000000;
2851 if (float32_is_any_nan(a
)) {
2852 if (float32_is_signaling_nan(a
)) {
2853 float_raise(float_flag_invalid
, s
);
2855 return float32_default_nan
;
2856 } else if (float32_is_infinity(a
)) {
2857 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2858 } else if (float32_is_zero_or_denormal(a
)) {
2859 if (!float32_is_zero(a
)) {
2860 float_raise(float_flag_input_denormal
, s
);
2862 float_raise(float_flag_divbyzero
, s
);
2863 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2864 } else if (a_exp
>= 253) {
2865 float_raise(float_flag_underflow
, s
);
2866 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2869 f64
= make_float64((0x3feULL
<< 52)
2870 | ((int64_t)(val32
& 0x7fffff) << 29));
2872 result_exp
= 253 - a_exp
;
2874 f64
= recip_estimate(f64
, env
);
2877 | ((result_exp
& 0xff) << 23)
2878 | ((float64_val(f64
) >> 29) & 0x7fffff);
2879 return make_float32(val32
);
2882 /* The algorithm that must be used to calculate the estimate
2883 * is specified by the ARM ARM.
2885 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2887 /* These calculations mustn't set any fp exception flags,
2888 * so we use a local copy of the fp_status.
2890 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2891 float_status
*s
= &dummy_status
;
2895 if (float64_lt(a
, float64_half
, s
)) {
2896 /* range 0.25 <= a < 0.5 */
2898 /* a in units of 1/512 rounded down */
2899 /* q0 = (int)(a * 512.0); */
2900 q
= float64_mul(float64_512
, a
, s
);
2901 q_int
= float64_to_int64_round_to_zero(q
, s
);
2903 /* reciprocal root r */
2904 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2905 q
= int64_to_float64(q_int
, s
);
2906 q
= float64_add(q
, float64_half
, s
);
2907 q
= float64_div(q
, float64_512
, s
);
2908 q
= float64_sqrt(q
, s
);
2909 q
= float64_div(float64_one
, q
, s
);
2911 /* range 0.5 <= a < 1.0 */
2913 /* a in units of 1/256 rounded down */
2914 /* q1 = (int)(a * 256.0); */
2915 q
= float64_mul(float64_256
, a
, s
);
2916 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2918 /* reciprocal root r */
2919 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2920 q
= int64_to_float64(q_int
, s
);
2921 q
= float64_add(q
, float64_half
, s
);
2922 q
= float64_div(q
, float64_256
, s
);
2923 q
= float64_sqrt(q
, s
);
2924 q
= float64_div(float64_one
, q
, s
);
2926 /* r in units of 1/256 rounded to nearest */
2927 /* s = (int)(256.0 * r + 0.5); */
2929 q
= float64_mul(q
, float64_256
,s
);
2930 q
= float64_add(q
, float64_half
, s
);
2931 q_int
= float64_to_int64_round_to_zero(q
, s
);
2933 /* return (double)s / 256.0;*/
2934 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2937 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
2939 float_status
*s
= &env
->vfp
.standard_fp_status
;
2945 val
= float32_val(a
);
2947 if (float32_is_any_nan(a
)) {
2948 if (float32_is_signaling_nan(a
)) {
2949 float_raise(float_flag_invalid
, s
);
2951 return float32_default_nan
;
2952 } else if (float32_is_zero_or_denormal(a
)) {
2953 if (!float32_is_zero(a
)) {
2954 float_raise(float_flag_input_denormal
, s
);
2956 float_raise(float_flag_divbyzero
, s
);
2957 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2958 } else if (float32_is_neg(a
)) {
2959 float_raise(float_flag_invalid
, s
);
2960 return float32_default_nan
;
2961 } else if (float32_is_infinity(a
)) {
2962 return float32_zero
;
2965 /* Normalize to a double-precision value between 0.25 and 1.0,
2966 * preserving the parity of the exponent. */
2967 if ((val
& 0x800000) == 0) {
2968 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
2970 | ((uint64_t)(val
& 0x7fffff) << 29));
2972 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
2974 | ((uint64_t)(val
& 0x7fffff) << 29));
2977 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
2979 f64
= recip_sqrt_estimate(f64
, env
);
2981 val64
= float64_val(f64
);
2983 val
= ((result_exp
& 0xff) << 23)
2984 | ((val64
>> 29) & 0x7fffff);
2985 return make_float32(val
);
2988 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
2992 if ((a
& 0x80000000) == 0) {
2996 f64
= make_float64((0x3feULL
<< 52)
2997 | ((int64_t)(a
& 0x7fffffff) << 21));
2999 f64
= recip_estimate (f64
, env
);
3001 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3004 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3008 if ((a
& 0xc0000000) == 0) {
3012 if (a
& 0x80000000) {
3013 f64
= make_float64((0x3feULL
<< 52)
3014 | ((uint64_t)(a
& 0x7fffffff) << 21));
3015 } else { /* bits 31-30 == '01' */
3016 f64
= make_float64((0x3fdULL
<< 52)
3017 | ((uint64_t)(a
& 0x3fffffff) << 22));
3020 f64
= recip_sqrt_estimate(f64
, env
);
3022 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3025 /* VFPv4 fused multiply-accumulate */
3026 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3028 float_status
*fpst
= fpstp
;
3029 return float32_muladd(a
, b
, c
, 0, fpst
);
3032 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3034 float_status
*fpst
= fpstp
;
3035 return float64_muladd(a
, b
, c
, 0, fpst
);
3038 void HELPER(set_teecr
)(CPUARMState
*env
, uint32_t val
)
3041 if (env
->teecr
!= val
) {