4 #include "host-utils.h"
7 #ifndef CONFIG_USER_ONLY
8 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
9 int access_type
, int is_user
,
10 uint32_t *phys_ptr
, int *prot
,
11 target_ulong
*page_size
);
14 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
18 /* VFP data registers are always little-endian. */
19 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
21 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
24 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
25 /* Aliases for Q regs. */
28 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
29 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
33 switch (reg
- nregs
) {
34 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
35 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
36 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
41 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
53 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
54 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
58 switch (reg
- nregs
) {
59 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
60 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
61 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
66 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
69 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
73 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
75 if (env
->cp15
.c13_fcse
!= value
) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
80 env
->cp15
.c13_fcse
= value
;
84 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
94 env
->cp15
.c13_context
= value
;
98 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Invalidate all (TLBIALL) */
106 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
114 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env
, value
== 0);
122 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
130 static const ARMCPRegInfo cp_reginfo
[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
135 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
136 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
137 /* MMU Domain access control / MPU write buffer control */
138 { .name
= "DACR", .cp
= 15,
139 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
140 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
141 .resetvalue
= 0, .writefn
= dacr_write
},
142 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
143 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
144 .resetvalue
= 0, .writefn
= fcse_write
},
145 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
147 .resetvalue
= 0, .writefn
= contextidr_write
},
148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
152 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
157 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
158 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
159 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
160 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
161 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
162 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
163 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
166 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
167 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
171 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
175 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
176 .access
= PL1_W
, .type
= ARM_CP_WFI
},
180 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
185 .access
= PL1_W
, .type
= ARM_CP_WFI
},
186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
190 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
191 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
193 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
194 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
198 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
202 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
204 if (env
->cp15
.c1_coproc
!= value
) {
205 env
->cp15
.c1_coproc
= value
;
206 /* ??? Is this safe when called from within a TB? */
212 static const ARMCPRegInfo v6_cp_reginfo
[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name
= "MVA_prefetch",
215 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
216 .access
= PL1_W
, .type
= ARM_CP_NOP
},
217 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
218 .access
= PL0_W
, .type
= ARM_CP_NOP
},
219 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
220 .access
= PL0_W
, .type
= ARM_CP_NOP
},
221 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
222 .access
= PL0_W
, .type
= ARM_CP_NOP
},
223 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
224 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
229 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
230 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
231 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
232 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
233 .resetvalue
= 0, .writefn
= cpacr_write
},
237 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
243 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
246 *value
= CPREG_FIELD32(env
, ri
);
250 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
253 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
256 /* only the DP, X, D and E bits are writable */
257 env
->cp15
.c9_pmcr
&= ~0x39;
258 env
->cp15
.c9_pmcr
|= (value
& 0x39);
262 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
265 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
269 env
->cp15
.c9_pmcnten
|= value
;
273 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
276 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
280 env
->cp15
.c9_pmcnten
&= ~value
;
284 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
287 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
290 env
->cp15
.c9_pmovsr
&= ~value
;
294 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
297 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
300 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
304 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
307 env
->cp15
.c9_pmuserenr
= value
& 1;
311 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
314 /* We have no event counters so only the C bit can be changed */
316 env
->cp15
.c9_pminten
|= value
;
320 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
324 env
->cp15
.c9_pminten
&= ~value
;
328 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
331 ARMCPU
*cpu
= arm_env_get_cpu(env
);
332 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
336 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 env
->cp15
.c0_cssel
= value
& 0xf;
343 static const ARMCPRegInfo v7_cp_reginfo
[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
347 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
348 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
350 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
353 .access
= PL1_W
, .type
= ARM_CP_NOP
},
354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
366 .access
= PL0_RW
, .resetvalue
= 0,
367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
368 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
369 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
370 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
371 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
372 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
373 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
374 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
378 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
379 .access
= PL0_W
, .type
= ARM_CP_NOP
},
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
384 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
387 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
388 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
390 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
391 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
394 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
395 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
396 .access
= PL0_R
| PL1_RW
,
397 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
399 .writefn
= pmuserenr_write
},
400 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
402 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
404 .writefn
= pmintenset_write
},
405 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
409 .writefn
= pmintenclr_write
},
410 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
411 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
413 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
414 .access
= PL1_R
, .readfn
= ccsidr_read
},
415 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
416 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
417 .writefn
= csselr_write
, .resetvalue
= 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
421 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
422 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
426 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
433 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
439 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
442 *value
= env
->teehbr
;
446 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
449 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
456 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
457 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
458 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
460 .writefn
= teecr_write
},
461 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
462 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
464 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
468 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
469 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
471 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
473 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
474 .access
= PL0_R
|PL1_W
,
475 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
477 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
479 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
484 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
487 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
488 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
492 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
494 if (arm_feature(env
, ARM_FEATURE_V7
)) {
495 env
->cp15
.c7_par
= value
& 0xfffff6ff;
497 env
->cp15
.c7_par
= value
& 0xfffff1ff;
502 #ifndef CONFIG_USER_ONLY
503 /* get_phys_addr() isn't present for user-mode-only targets */
504 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
507 target_ulong page_size
;
509 int ret
, is_user
= ri
->opc2
& 2;
510 int access_type
= ri
->opc2
& 1;
513 /* Other states are only available with TrustZone */
516 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
517 &phys_addr
, &prot
, &page_size
);
519 /* We do not set any attribute bits in the PAR */
520 if (page_size
== (1 << 24)
521 && arm_feature(env
, ARM_FEATURE_V7
)) {
522 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
524 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
527 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
528 ((ret
& (12 << 1)) >> 6) |
529 ((ret
& 0xf) << 1) | 1;
535 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
536 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
537 .access
= PL1_RW
, .resetvalue
= 0,
538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
539 .writefn
= par_write
},
540 #ifndef CONFIG_USER_ONLY
541 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
542 .access
= PL1_W
, .writefn
= ats_write
},
547 /* Return basic MPU access permission bits. */
548 static uint32_t simple_mpu_ap_bits(uint32_t val
)
555 for (i
= 0; i
< 16; i
+= 2) {
556 ret
|= (val
>> i
) & mask
;
562 /* Pad basic MPU access permission bits to extended format. */
563 static uint32_t extended_mpu_ap_bits(uint32_t val
)
570 for (i
= 0; i
< 16; i
+= 2) {
571 ret
|= (val
& mask
) << i
;
577 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
580 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
584 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
587 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
591 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
594 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
598 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
601 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
605 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
611 *value
= env
->cp15
.c6_region
[ri
->crm
];
615 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
621 env
->cp15
.c6_region
[ri
->crm
] = value
;
625 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
626 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
628 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
629 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
630 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
633 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
634 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
636 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
637 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
640 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
643 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
646 /* Protection region base and size registers */
647 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
648 .opc2
= CP_ANY
, .access
= PL1_RW
,
649 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
653 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
657 env
->cp15
.c2_control
= value
;
658 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
659 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
663 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
665 env
->cp15
.c2_base_mask
= 0xffffc000u
;
666 env
->cp15
.c2_control
= 0;
667 env
->cp15
.c2_mask
= 0;
670 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
671 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
673 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
674 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
676 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
677 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
679 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
680 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
682 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
683 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
684 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
685 .resetfn
= vmsa_ttbcr_reset
,
686 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
687 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
688 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
693 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 env
->cp15
.c15_ticonfig
= value
& 0xe7;
697 /* The OS_TYPE bit in this register changes the reported CPUID! */
698 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
699 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
703 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
706 env
->cp15
.c15_threadid
= value
& 0xffff;
710 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
713 /* Wait-for-interrupt (deprecated) */
714 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
718 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
721 /* On OMAP there are registers indicating the max/min index of dcache lines
722 * containing a dirty line; cache flush operations have to reset these.
724 env
->cp15
.c15_i_max
= 0x000;
725 env
->cp15
.c15_i_min
= 0xff0;
729 static const ARMCPRegInfo omap_cp_reginfo
[] = {
730 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
731 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
732 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
733 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
734 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
735 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
738 .writefn
= omap_ticonfig_write
},
739 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
741 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
742 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
743 .access
= PL1_RW
, .resetvalue
= 0xff0,
744 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
745 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
747 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
748 .writefn
= omap_threadid_write
},
749 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
750 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
751 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
752 /* TODO: Peripheral port remap register:
753 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
754 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
757 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
758 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
759 .writefn
= omap_cachemaint_write
},
760 { .name
= "C9", .cp
= 15, .crn
= 9,
761 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
762 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
766 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
770 if (env
->cp15
.c15_cpar
!= value
) {
771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
773 env
->cp15
.c15_cpar
= value
;
778 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
779 { .name
= "XSCALE_CPAR",
780 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
781 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
782 .writefn
= xscale_cpar_write
, },
783 { .name
= "XSCALE_AUXCR",
784 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
785 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
790 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
791 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
792 * implementation of this implementation-defined space.
793 * Ideally this should eventually disappear in favour of actually
794 * implementing the correct behaviour for all cores.
796 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
797 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
798 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
802 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
803 /* Cache status: RAZ because we have no cache so it's always clean */
804 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
805 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
809 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
810 /* We never have a a block transfer operation in progress */
811 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
812 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
816 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
817 /* The cache test-and-clean instructions always return (1 << 30)
818 * to indicate that there are no dirty cache lines.
820 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
821 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
822 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
823 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
827 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
828 /* Ignore ReadBuffer accesses */
829 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
830 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
831 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
836 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 uint32_t mpidr
= env
->cpu_index
;
840 /* We don't support setting cluster ID ([8..11])
841 * so these bits always RAZ.
843 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
845 /* Cores which are uniprocessor (non-coherent)
846 * but still implement the MP extensions set
847 * bit 30. (For instance, A9UP.) However we do
848 * not currently model any of those cores.
855 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
856 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
857 .access
= PL1_R
, .readfn
= mpidr_read
},
861 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
863 env
->cp15
.c1_sys
= value
;
864 /* ??? Lots of these bits are not implemented. */
865 /* This may enable/disable the MMU, so do a TLB flush. */
870 void register_cp_regs_for_features(ARMCPU
*cpu
)
872 /* Register all the coprocessor registers based on feature bits */
873 CPUARMState
*env
= &cpu
->env
;
874 if (arm_feature(env
, ARM_FEATURE_M
)) {
875 /* M profile has no coprocessor registers */
879 define_arm_cp_regs(cpu
, cp_reginfo
);
880 if (arm_feature(env
, ARM_FEATURE_V6
)) {
881 /* The ID registers all have impdef reset values */
882 ARMCPRegInfo v6_idregs
[] = {
883 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
884 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
885 .resetvalue
= cpu
->id_pfr0
},
886 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
887 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
888 .resetvalue
= cpu
->id_pfr1
},
889 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
890 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
891 .resetvalue
= cpu
->id_dfr0
},
892 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
893 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
894 .resetvalue
= cpu
->id_afr0
},
895 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
896 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
897 .resetvalue
= cpu
->id_mmfr0
},
898 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
899 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
900 .resetvalue
= cpu
->id_mmfr1
},
901 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
902 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
903 .resetvalue
= cpu
->id_mmfr2
},
904 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
905 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
906 .resetvalue
= cpu
->id_mmfr3
},
907 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
908 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
909 .resetvalue
= cpu
->id_isar0
},
910 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
911 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
912 .resetvalue
= cpu
->id_isar1
},
913 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
914 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
915 .resetvalue
= cpu
->id_isar2
},
916 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
917 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
918 .resetvalue
= cpu
->id_isar3
},
919 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
920 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
921 .resetvalue
= cpu
->id_isar4
},
922 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
923 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
924 .resetvalue
= cpu
->id_isar5
},
925 /* 6..7 are as yet unallocated and must RAZ */
926 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
927 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
929 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
930 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
934 define_arm_cp_regs(cpu
, v6_idregs
);
935 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
937 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
939 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
940 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
942 if (arm_feature(env
, ARM_FEATURE_V7
)) {
943 /* v7 performance monitor control register: same implementor
944 * field as main ID register, and we implement no event counters.
946 ARMCPRegInfo pmcr
= {
947 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
948 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
949 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
950 .readfn
= pmreg_read
, .writefn
= pmcr_write
952 ARMCPRegInfo clidr
= {
953 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
954 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
956 define_one_arm_cp_reg(cpu
, &pmcr
);
957 define_one_arm_cp_reg(cpu
, &clidr
);
958 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
960 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
962 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
963 /* These are the MPU registers prior to PMSAv6. Any new
964 * PMSA core later than the ARM946 will require that we
965 * implement the PMSAv6 or PMSAv7 registers, which are
966 * completely different.
968 assert(!arm_feature(env
, ARM_FEATURE_V6
));
969 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
971 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
973 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
974 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
976 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
977 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
979 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
980 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
982 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
983 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
985 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
986 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
988 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
989 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
991 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
992 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
994 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
995 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
997 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
998 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1000 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1001 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1003 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1004 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1006 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1007 ARMCPRegInfo auxcr
= {
1008 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1009 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1010 .resetvalue
= cpu
->reset_auxcr
1012 define_one_arm_cp_reg(cpu
, &auxcr
);
1015 /* Generic registers whose values depend on the implementation */
1017 ARMCPRegInfo sctlr
= {
1018 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1019 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1020 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
1022 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1023 /* Normally we would always end the TB on an SCTLR write, but Linux
1024 * arch/arm/mach-pxa/sleep.S expects two instructions following
1025 * an MMU enable to execute from cache. Imitate this behaviour.
1027 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1029 define_one_arm_cp_reg(cpu
, &sctlr
);
1033 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1037 static int inited
= 0;
1039 if (!object_class_by_name(cpu_model
)) {
1042 cpu
= ARM_CPU(object_new(cpu_model
));
1044 env
->cpu_model_str
= cpu_model
;
1045 arm_cpu_realize(cpu
);
1047 if (tcg_enabled() && !inited
) {
1049 arm_translate_init();
1052 cpu_reset(CPU(cpu
));
1053 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1054 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1055 51, "arm-neon.xml", 0);
1056 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1057 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1058 35, "arm-vfp3.xml", 0);
1059 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1060 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1061 19, "arm-vfp.xml", 0);
1063 qemu_init_vcpu(env
);
1067 typedef struct ARMCPUListState
{
1068 fprintf_function cpu_fprintf
;
1072 /* Sort alphabetically by type name, except for "any". */
1073 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1075 ObjectClass
*class_a
= (ObjectClass
*)a
;
1076 ObjectClass
*class_b
= (ObjectClass
*)b
;
1077 const char *name_a
, *name_b
;
1079 name_a
= object_class_get_name(class_a
);
1080 name_b
= object_class_get_name(class_b
);
1081 if (strcmp(name_a
, "any") == 0) {
1083 } else if (strcmp(name_b
, "any") == 0) {
1086 return strcmp(name_a
, name_b
);
1090 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1092 ObjectClass
*oc
= data
;
1093 ARMCPUListState
*s
= user_data
;
1095 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1096 object_class_get_name(oc
));
1099 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1101 ARMCPUListState s
= {
1103 .cpu_fprintf
= cpu_fprintf
,
1107 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1108 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1109 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1110 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1114 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1115 const ARMCPRegInfo
*r
, void *opaque
)
1117 /* Define implementations of coprocessor registers.
1118 * We store these in a hashtable because typically
1119 * there are less than 150 registers in a space which
1120 * is 16*16*16*8*8 = 262144 in size.
1121 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1122 * If a register is defined twice then the second definition is
1123 * used, so this can be used to define some generic registers and
1124 * then override them with implementation specific variations.
1125 * At least one of the original and the second definition should
1126 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1127 * against accidental use.
1129 int crm
, opc1
, opc2
;
1130 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1131 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1132 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1133 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1134 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1135 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1136 /* 64 bit registers have only CRm and Opc1 fields */
1137 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1138 /* Check that the register definition has enough info to handle
1139 * reads and writes if they are permitted.
1141 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1142 if (r
->access
& PL3_R
) {
1143 assert(r
->fieldoffset
|| r
->readfn
);
1145 if (r
->access
& PL3_W
) {
1146 assert(r
->fieldoffset
|| r
->writefn
);
1149 /* Bad type field probably means missing sentinel at end of reg list */
1150 assert(cptype_valid(r
->type
));
1151 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1152 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1153 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1154 uint32_t *key
= g_new(uint32_t, 1);
1155 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1156 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1157 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1158 r2
->opaque
= opaque
;
1159 /* Make sure reginfo passed to helpers for wildcarded regs
1160 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1165 /* Overriding of an existing definition must be explicitly
1168 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1169 ARMCPRegInfo
*oldreg
;
1170 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1171 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1172 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1173 "crn=%d crm=%d opc1=%d opc2=%d, "
1174 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1175 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1176 oldreg
->name
, r2
->name
);
1180 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1186 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1187 const ARMCPRegInfo
*regs
, void *opaque
)
1189 /* Define a whole list of registers */
1190 const ARMCPRegInfo
*r
;
1191 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1192 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1196 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1198 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1201 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1204 /* Helper coprocessor write function for write-ignore registers */
1208 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1210 /* Helper coprocessor write function for read-as-zero registers */
1215 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1217 /* Return true if it is not valid for us to switch to
1218 * this CPU mode (ie all the UNPREDICTABLE cases in
1219 * the ARM ARM CPSRWriteByInstr pseudocode).
1222 case ARM_CPU_MODE_USR
:
1223 case ARM_CPU_MODE_SYS
:
1224 case ARM_CPU_MODE_SVC
:
1225 case ARM_CPU_MODE_ABT
:
1226 case ARM_CPU_MODE_UND
:
1227 case ARM_CPU_MODE_IRQ
:
1228 case ARM_CPU_MODE_FIQ
:
1235 uint32_t cpsr_read(CPUARMState
*env
)
1238 ZF
= (env
->ZF
== 0);
1239 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1240 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1241 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1242 | ((env
->condexec_bits
& 0xfc) << 8)
1246 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1248 if (mask
& CPSR_NZCV
) {
1249 env
->ZF
= (~val
) & CPSR_Z
;
1251 env
->CF
= (val
>> 29) & 1;
1252 env
->VF
= (val
<< 3) & 0x80000000;
1255 env
->QF
= ((val
& CPSR_Q
) != 0);
1257 env
->thumb
= ((val
& CPSR_T
) != 0);
1258 if (mask
& CPSR_IT_0_1
) {
1259 env
->condexec_bits
&= ~3;
1260 env
->condexec_bits
|= (val
>> 25) & 3;
1262 if (mask
& CPSR_IT_2_7
) {
1263 env
->condexec_bits
&= 3;
1264 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1266 if (mask
& CPSR_GE
) {
1267 env
->GE
= (val
>> 16) & 0xf;
1270 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1271 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1272 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1273 * We choose to ignore the attempt and leave the CPSR M field
1278 switch_mode(env
, val
& CPSR_M
);
1281 mask
&= ~CACHED_CPSR_BITS
;
1282 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1285 /* Sign/zero extend */
1286 uint32_t HELPER(sxtb16
)(uint32_t x
)
1289 res
= (uint16_t)(int8_t)x
;
1290 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1294 uint32_t HELPER(uxtb16
)(uint32_t x
)
1297 res
= (uint16_t)(uint8_t)x
;
1298 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1302 uint32_t HELPER(clz
)(uint32_t x
)
1307 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1311 if (num
== INT_MIN
&& den
== -1)
1316 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1323 uint32_t HELPER(rbit
)(uint32_t x
)
1325 x
= ((x
& 0xff000000) >> 24)
1326 | ((x
& 0x00ff0000) >> 8)
1327 | ((x
& 0x0000ff00) << 8)
1328 | ((x
& 0x000000ff) << 24);
1329 x
= ((x
& 0xf0f0f0f0) >> 4)
1330 | ((x
& 0x0f0f0f0f) << 4);
1331 x
= ((x
& 0x88888888) >> 3)
1332 | ((x
& 0x44444444) >> 1)
1333 | ((x
& 0x22222222) << 1)
1334 | ((x
& 0x11111111) << 3);
1338 uint32_t HELPER(abs
)(uint32_t x
)
1340 return ((int32_t)x
< 0) ? -x
: x
;
1343 #if defined(CONFIG_USER_ONLY)
1345 void do_interrupt (CPUARMState
*env
)
1347 env
->exception_index
= -1;
1350 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1354 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1355 env
->cp15
.c6_insn
= address
;
1357 env
->exception_index
= EXCP_DATA_ABORT
;
1358 env
->cp15
.c6_data
= address
;
1363 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1365 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1368 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1370 cpu_abort(env
, "cp15 insn %08x\n", insn
);
1373 /* These should probably raise undefined insn exceptions. */
1374 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1376 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1379 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1381 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1385 void switch_mode(CPUARMState
*env
, int mode
)
1387 if (mode
!= ARM_CPU_MODE_USR
)
1388 cpu_abort(env
, "Tried to switch out of user mode\n");
1391 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1393 cpu_abort(env
, "banked r13 write\n");
1396 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1398 cpu_abort(env
, "banked r13 read\n");
1404 /* Map CPU modes onto saved register banks. */
1405 static inline int bank_number(CPUARMState
*env
, int mode
)
1408 case ARM_CPU_MODE_USR
:
1409 case ARM_CPU_MODE_SYS
:
1411 case ARM_CPU_MODE_SVC
:
1413 case ARM_CPU_MODE_ABT
:
1415 case ARM_CPU_MODE_UND
:
1417 case ARM_CPU_MODE_IRQ
:
1419 case ARM_CPU_MODE_FIQ
:
1422 cpu_abort(env
, "Bad mode %x\n", mode
);
1426 void switch_mode(CPUARMState
*env
, int mode
)
1431 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1432 if (mode
== old_mode
)
1435 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1436 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1437 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1438 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1439 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1440 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1443 i
= bank_number(env
, old_mode
);
1444 env
->banked_r13
[i
] = env
->regs
[13];
1445 env
->banked_r14
[i
] = env
->regs
[14];
1446 env
->banked_spsr
[i
] = env
->spsr
;
1448 i
= bank_number(env
, mode
);
1449 env
->regs
[13] = env
->banked_r13
[i
];
1450 env
->regs
[14] = env
->banked_r14
[i
];
1451 env
->spsr
= env
->banked_spsr
[i
];
1454 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1457 stl_phys(env
->regs
[13], val
);
1460 static uint32_t v7m_pop(CPUARMState
*env
)
1463 val
= ldl_phys(env
->regs
[13]);
1468 /* Switch to V7M main or process stack pointer. */
1469 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1472 if (env
->v7m
.current_sp
!= process
) {
1473 tmp
= env
->v7m
.other_sp
;
1474 env
->v7m
.other_sp
= env
->regs
[13];
1475 env
->regs
[13] = tmp
;
1476 env
->v7m
.current_sp
= process
;
1480 static void do_v7m_exception_exit(CPUARMState
*env
)
1485 type
= env
->regs
[15];
1486 if (env
->v7m
.exception
!= 0)
1487 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1489 /* Switch to the target stack. */
1490 switch_v7m_sp(env
, (type
& 4) != 0);
1491 /* Pop registers. */
1492 env
->regs
[0] = v7m_pop(env
);
1493 env
->regs
[1] = v7m_pop(env
);
1494 env
->regs
[2] = v7m_pop(env
);
1495 env
->regs
[3] = v7m_pop(env
);
1496 env
->regs
[12] = v7m_pop(env
);
1497 env
->regs
[14] = v7m_pop(env
);
1498 env
->regs
[15] = v7m_pop(env
);
1499 xpsr
= v7m_pop(env
);
1500 xpsr_write(env
, xpsr
, 0xfffffdff);
1501 /* Undo stack alignment. */
1504 /* ??? The exception return type specifies Thread/Handler mode. However
1505 this is also implied by the xPSR value. Not sure what to do
1506 if there is a mismatch. */
1507 /* ??? Likewise for mismatches between the CONTROL register and the stack
1511 static void do_interrupt_v7m(CPUARMState
*env
)
1513 uint32_t xpsr
= xpsr_read(env
);
1518 if (env
->v7m
.current_sp
)
1520 if (env
->v7m
.exception
== 0)
1523 /* For exceptions we just mark as pending on the NVIC, and let that
1525 /* TODO: Need to escalate if the current priority is higher than the
1526 one we're raising. */
1527 switch (env
->exception_index
) {
1529 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1533 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1535 case EXCP_PREFETCH_ABORT
:
1536 case EXCP_DATA_ABORT
:
1537 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1540 if (semihosting_enabled
) {
1542 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1545 env
->regs
[0] = do_arm_semihosting(env
);
1549 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1552 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1554 case EXCP_EXCEPTION_EXIT
:
1555 do_v7m_exception_exit(env
);
1558 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1559 return; /* Never happens. Keep compiler happy. */
1562 /* Align stack pointer. */
1563 /* ??? Should only do this if Configuration Control Register
1564 STACKALIGN bit is set. */
1565 if (env
->regs
[13] & 4) {
1569 /* Switch to the handler mode. */
1570 v7m_push(env
, xpsr
);
1571 v7m_push(env
, env
->regs
[15]);
1572 v7m_push(env
, env
->regs
[14]);
1573 v7m_push(env
, env
->regs
[12]);
1574 v7m_push(env
, env
->regs
[3]);
1575 v7m_push(env
, env
->regs
[2]);
1576 v7m_push(env
, env
->regs
[1]);
1577 v7m_push(env
, env
->regs
[0]);
1578 switch_v7m_sp(env
, 0);
1580 env
->condexec_bits
= 0;
1582 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1583 env
->regs
[15] = addr
& 0xfffffffe;
1584 env
->thumb
= addr
& 1;
1587 /* Handle a CPU exception. */
1588 void do_interrupt(CPUARMState
*env
)
1596 do_interrupt_v7m(env
);
1599 /* TODO: Vectored interrupt controller. */
1600 switch (env
->exception_index
) {
1602 new_mode
= ARM_CPU_MODE_UND
;
1611 if (semihosting_enabled
) {
1612 /* Check for semihosting interrupt. */
1614 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1616 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1619 /* Only intercept calls from privileged modes, to provide some
1620 semblance of security. */
1621 if (((mask
== 0x123456 && !env
->thumb
)
1622 || (mask
== 0xab && env
->thumb
))
1623 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1624 env
->regs
[0] = do_arm_semihosting(env
);
1628 new_mode
= ARM_CPU_MODE_SVC
;
1631 /* The PC already points to the next instruction. */
1635 /* See if this is a semihosting syscall. */
1636 if (env
->thumb
&& semihosting_enabled
) {
1637 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1639 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1641 env
->regs
[0] = do_arm_semihosting(env
);
1645 env
->cp15
.c5_insn
= 2;
1646 /* Fall through to prefetch abort. */
1647 case EXCP_PREFETCH_ABORT
:
1648 new_mode
= ARM_CPU_MODE_ABT
;
1650 mask
= CPSR_A
| CPSR_I
;
1653 case EXCP_DATA_ABORT
:
1654 new_mode
= ARM_CPU_MODE_ABT
;
1656 mask
= CPSR_A
| CPSR_I
;
1660 new_mode
= ARM_CPU_MODE_IRQ
;
1662 /* Disable IRQ and imprecise data aborts. */
1663 mask
= CPSR_A
| CPSR_I
;
1667 new_mode
= ARM_CPU_MODE_FIQ
;
1669 /* Disable FIQ, IRQ and imprecise data aborts. */
1670 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1674 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1675 return; /* Never happens. Keep compiler happy. */
1678 if (env
->cp15
.c1_sys
& (1 << 13)) {
1681 switch_mode (env
, new_mode
);
1682 env
->spsr
= cpsr_read(env
);
1683 /* Clear IT bits. */
1684 env
->condexec_bits
= 0;
1685 /* Switch to the new mode, and to the correct instruction set. */
1686 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1687 env
->uncached_cpsr
|= mask
;
1688 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1689 * and we should just guard the thumb mode on V4 */
1690 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1691 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1693 env
->regs
[14] = env
->regs
[15] + offset
;
1694 env
->regs
[15] = addr
;
1695 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1698 /* Check section/page access permissions.
1699 Returns the page protection flags, or zero if the access is not
1701 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1702 int access_type
, int is_user
)
1706 if (domain_prot
== 3) {
1707 return PAGE_READ
| PAGE_WRITE
;
1710 if (access_type
== 1)
1713 prot_ro
= PAGE_READ
;
1717 if (access_type
== 1)
1719 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1721 return is_user
? 0 : PAGE_READ
;
1728 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1733 return PAGE_READ
| PAGE_WRITE
;
1735 return PAGE_READ
| PAGE_WRITE
;
1736 case 4: /* Reserved. */
1739 return is_user
? 0 : prot_ro
;
1743 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1751 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1755 if (address
& env
->cp15
.c2_mask
)
1756 table
= env
->cp15
.c2_base1
& 0xffffc000;
1758 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1760 table
|= (address
>> 18) & 0x3ffc;
1764 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1765 int is_user
, uint32_t *phys_ptr
, int *prot
,
1766 target_ulong
*page_size
)
1777 /* Pagetable walk. */
1778 /* Lookup l1 descriptor. */
1779 table
= get_level1_table_address(env
, address
);
1780 desc
= ldl_phys(table
);
1782 domain
= (desc
>> 5) & 0x0f;
1783 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1785 /* Section translation fault. */
1789 if (domain_prot
== 0 || domain_prot
== 2) {
1791 code
= 9; /* Section domain fault. */
1793 code
= 11; /* Page domain fault. */
1798 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1799 ap
= (desc
>> 10) & 3;
1801 *page_size
= 1024 * 1024;
1803 /* Lookup l2 entry. */
1805 /* Coarse pagetable. */
1806 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1808 /* Fine pagetable. */
1809 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1811 desc
= ldl_phys(table
);
1813 case 0: /* Page translation fault. */
1816 case 1: /* 64k page. */
1817 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1818 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1819 *page_size
= 0x10000;
1821 case 2: /* 4k page. */
1822 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1823 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1824 *page_size
= 0x1000;
1826 case 3: /* 1k page. */
1828 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1829 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1831 /* Page translation fault. */
1836 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1838 ap
= (desc
>> 4) & 3;
1842 /* Never happens, but compiler isn't smart enough to tell. */
1847 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1849 /* Access permission fault. */
1853 *phys_ptr
= phys_addr
;
1856 return code
| (domain
<< 4);
1859 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1860 int is_user
, uint32_t *phys_ptr
, int *prot
,
1861 target_ulong
*page_size
)
1873 /* Pagetable walk. */
1874 /* Lookup l1 descriptor. */
1875 table
= get_level1_table_address(env
, address
);
1876 desc
= ldl_phys(table
);
1879 /* Section translation fault. */
1883 } else if (type
== 2 && (desc
& (1 << 18))) {
1887 /* Section or page. */
1888 domain
= (desc
>> 5) & 0x0f;
1890 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1891 if (domain_prot
== 0 || domain_prot
== 2) {
1893 code
= 9; /* Section domain fault. */
1895 code
= 11; /* Page domain fault. */
1899 if (desc
& (1 << 18)) {
1901 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1902 *page_size
= 0x1000000;
1905 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1906 *page_size
= 0x100000;
1908 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1909 xn
= desc
& (1 << 4);
1912 /* Lookup l2 entry. */
1913 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1914 desc
= ldl_phys(table
);
1915 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1917 case 0: /* Page translation fault. */
1920 case 1: /* 64k page. */
1921 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1922 xn
= desc
& (1 << 15);
1923 *page_size
= 0x10000;
1925 case 2: case 3: /* 4k page. */
1926 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1928 *page_size
= 0x1000;
1931 /* Never happens, but compiler isn't smart enough to tell. */
1936 if (domain_prot
== 3) {
1937 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1939 if (xn
&& access_type
== 2)
1942 /* The simplified model uses AP[0] as an access control bit. */
1943 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1944 /* Access flag fault. */
1945 code
= (code
== 15) ? 6 : 3;
1948 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1950 /* Access permission fault. */
1957 *phys_ptr
= phys_addr
;
1960 return code
| (domain
<< 4);
1963 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1964 int is_user
, uint32_t *phys_ptr
, int *prot
)
1970 *phys_ptr
= address
;
1971 for (n
= 7; n
>= 0; n
--) {
1972 base
= env
->cp15
.c6_region
[n
];
1973 if ((base
& 1) == 0)
1975 mask
= 1 << ((base
>> 1) & 0x1f);
1976 /* Keep this shift separate from the above to avoid an
1977 (undefined) << 32. */
1978 mask
= (mask
<< 1) - 1;
1979 if (((base
^ address
) & ~mask
) == 0)
1985 if (access_type
== 2) {
1986 mask
= env
->cp15
.c5_insn
;
1988 mask
= env
->cp15
.c5_data
;
1990 mask
= (mask
>> (n
* 4)) & 0xf;
1997 *prot
= PAGE_READ
| PAGE_WRITE
;
2002 *prot
|= PAGE_WRITE
;
2005 *prot
= PAGE_READ
| PAGE_WRITE
;
2016 /* Bad permission. */
2023 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2024 int access_type
, int is_user
,
2025 uint32_t *phys_ptr
, int *prot
,
2026 target_ulong
*page_size
)
2028 /* Fast Context Switch Extension. */
2029 if (address
< 0x02000000)
2030 address
+= env
->cp15
.c13_fcse
;
2032 if ((env
->cp15
.c1_sys
& 1) == 0) {
2033 /* MMU/MPU disabled. */
2034 *phys_ptr
= address
;
2035 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2036 *page_size
= TARGET_PAGE_SIZE
;
2038 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2039 *page_size
= TARGET_PAGE_SIZE
;
2040 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2042 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2043 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2046 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2051 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2052 int access_type
, int mmu_idx
)
2055 target_ulong page_size
;
2059 is_user
= mmu_idx
== MMU_USER_IDX
;
2060 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2063 /* Map a single [sub]page. */
2064 phys_addr
&= ~(uint32_t)0x3ff;
2065 address
&= ~(uint32_t)0x3ff;
2066 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2070 if (access_type
== 2) {
2071 env
->cp15
.c5_insn
= ret
;
2072 env
->cp15
.c6_insn
= address
;
2073 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2075 env
->cp15
.c5_data
= ret
;
2076 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2077 env
->cp15
.c5_data
|= (1 << 11);
2078 env
->cp15
.c6_data
= address
;
2079 env
->exception_index
= EXCP_DATA_ABORT
;
2084 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2087 target_ulong page_size
;
2091 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2099 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
2105 op1
= (insn
>> 21) & 7;
2106 op2
= (insn
>> 5) & 7;
2108 switch ((insn
>> 16) & 0xf) {
2111 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
2113 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2116 case 4: /* Reserved. */
2118 case 12: /* Reserved. */
2123 /* ??? For debugging only. Should raise illegal instruction exception. */
2124 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
2125 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2128 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
2134 op1
= (insn
>> 21) & 7;
2135 op2
= (insn
>> 5) & 7;
2137 switch ((insn
>> 16) & 0xf) {
2138 case 0: /* ID codes. */
2144 case 0: /* Device ID. */
2145 return env
->cp15
.c0_cpuid
;
2146 case 1: /* Cache Type. */
2147 return env
->cp15
.c0_cachetype
;
2148 case 2: /* TCM status. */
2150 case 3: /* TLB type register. */
2151 return 0; /* No lockable TLB entries. */
2155 case 3: case 4: case 5: case 6: case 7:
2163 case 4: /* Reserved. */
2165 case 11: /* TCM DMA control. */
2166 case 12: /* Reserved. */
2170 /* ??? For debugging only. Should raise illegal instruction exception. */
2171 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2172 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2176 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2178 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2179 env
->regs
[13] = val
;
2181 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2185 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2187 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2188 return env
->regs
[13];
2190 return env
->banked_r13
[bank_number(env
, mode
)];
2194 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2198 return xpsr_read(env
) & 0xf8000000;
2200 return xpsr_read(env
) & 0xf80001ff;
2202 return xpsr_read(env
) & 0xff00fc00;
2204 return xpsr_read(env
) & 0xff00fdff;
2206 return xpsr_read(env
) & 0x000001ff;
2208 return xpsr_read(env
) & 0x0700fc00;
2210 return xpsr_read(env
) & 0x0700edff;
2212 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2214 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2215 case 16: /* PRIMASK */
2216 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2217 case 17: /* BASEPRI */
2218 case 18: /* BASEPRI_MAX */
2219 return env
->v7m
.basepri
;
2220 case 19: /* FAULTMASK */
2221 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2222 case 20: /* CONTROL */
2223 return env
->v7m
.control
;
2225 /* ??? For debugging only. */
2226 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2231 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2235 xpsr_write(env
, val
, 0xf8000000);
2238 xpsr_write(env
, val
, 0xf8000000);
2241 xpsr_write(env
, val
, 0xfe00fc00);
2244 xpsr_write(env
, val
, 0xfe00fc00);
2247 /* IPSR bits are readonly. */
2250 xpsr_write(env
, val
, 0x0600fc00);
2253 xpsr_write(env
, val
, 0x0600fc00);
2256 if (env
->v7m
.current_sp
)
2257 env
->v7m
.other_sp
= val
;
2259 env
->regs
[13] = val
;
2262 if (env
->v7m
.current_sp
)
2263 env
->regs
[13] = val
;
2265 env
->v7m
.other_sp
= val
;
2267 case 16: /* PRIMASK */
2269 env
->uncached_cpsr
|= CPSR_I
;
2271 env
->uncached_cpsr
&= ~CPSR_I
;
2273 case 17: /* BASEPRI */
2274 env
->v7m
.basepri
= val
& 0xff;
2276 case 18: /* BASEPRI_MAX */
2278 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2279 env
->v7m
.basepri
= val
;
2281 case 19: /* FAULTMASK */
2283 env
->uncached_cpsr
|= CPSR_F
;
2285 env
->uncached_cpsr
&= ~CPSR_F
;
2287 case 20: /* CONTROL */
2288 env
->v7m
.control
= val
& 3;
2289 switch_v7m_sp(env
, (val
& 2) != 0);
2292 /* ??? For debugging only. */
2293 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2300 /* Note that signed overflow is undefined in C. The following routines are
2301 careful to use unsigned types where modulo arithmetic is required.
2302 Failure to do so _will_ break on newer gcc. */
2304 /* Signed saturating arithmetic. */
2306 /* Perform 16-bit signed saturating addition. */
2307 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2312 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2321 /* Perform 8-bit signed saturating addition. */
2322 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2327 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2336 /* Perform 16-bit signed saturating subtraction. */
2337 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2342 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2351 /* Perform 8-bit signed saturating subtraction. */
2352 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2357 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2366 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2367 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2368 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2369 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2372 #include "op_addsub.h"
2374 /* Unsigned saturating arithmetic. */
2375 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2384 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2392 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2401 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2409 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2410 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2411 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2412 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2415 #include "op_addsub.h"
2417 /* Signed modulo arithmetic. */
2418 #define SARITH16(a, b, n, op) do { \
2420 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2421 RESULT(sum, n, 16); \
2423 ge |= 3 << (n * 2); \
2426 #define SARITH8(a, b, n, op) do { \
2428 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2429 RESULT(sum, n, 8); \
2435 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2436 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2437 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2438 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2442 #include "op_addsub.h"
2444 /* Unsigned modulo arithmetic. */
2445 #define ADD16(a, b, n) do { \
2447 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2448 RESULT(sum, n, 16); \
2449 if ((sum >> 16) == 1) \
2450 ge |= 3 << (n * 2); \
2453 #define ADD8(a, b, n) do { \
2455 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2456 RESULT(sum, n, 8); \
2457 if ((sum >> 8) == 1) \
2461 #define SUB16(a, b, n) do { \
2463 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2464 RESULT(sum, n, 16); \
2465 if ((sum >> 16) == 0) \
2466 ge |= 3 << (n * 2); \
2469 #define SUB8(a, b, n) do { \
2471 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2472 RESULT(sum, n, 8); \
2473 if ((sum >> 8) == 0) \
2480 #include "op_addsub.h"
2482 /* Halved signed arithmetic. */
2483 #define ADD16(a, b, n) \
2484 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2485 #define SUB16(a, b, n) \
2486 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2487 #define ADD8(a, b, n) \
2488 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2489 #define SUB8(a, b, n) \
2490 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2493 #include "op_addsub.h"
2495 /* Halved unsigned arithmetic. */
2496 #define ADD16(a, b, n) \
2497 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2498 #define SUB16(a, b, n) \
2499 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2500 #define ADD8(a, b, n) \
2501 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2502 #define SUB8(a, b, n) \
2503 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2506 #include "op_addsub.h"
2508 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2516 /* Unsigned sum of absolute byte differences. */
2517 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2520 sum
= do_usad(a
, b
);
2521 sum
+= do_usad(a
>> 8, b
>> 8);
2522 sum
+= do_usad(a
>> 16, b
>>16);
2523 sum
+= do_usad(a
>> 24, b
>> 24);
2527 /* For ARMv6 SEL instruction. */
2528 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2541 return (a
& mask
) | (b
& ~mask
);
2544 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2546 return (val
>> 32) | (val
!= 0);
2549 /* VFP support. We follow the convention used for VFP instrunctions:
2550 Single precition routines have a "s" suffix, double precision a
2553 /* Convert host exception flags to vfp form. */
2554 static inline int vfp_exceptbits_from_host(int host_bits
)
2556 int target_bits
= 0;
2558 if (host_bits
& float_flag_invalid
)
2560 if (host_bits
& float_flag_divbyzero
)
2562 if (host_bits
& float_flag_overflow
)
2564 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2566 if (host_bits
& float_flag_inexact
)
2567 target_bits
|= 0x10;
2568 if (host_bits
& float_flag_input_denormal
)
2569 target_bits
|= 0x80;
2573 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2578 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2579 | (env
->vfp
.vec_len
<< 16)
2580 | (env
->vfp
.vec_stride
<< 20);
2581 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2582 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2583 fpscr
|= vfp_exceptbits_from_host(i
);
2587 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2589 return HELPER(vfp_get_fpscr
)(env
);
2592 /* Convert vfp exception flags to target form. */
2593 static inline int vfp_exceptbits_to_host(int target_bits
)
2597 if (target_bits
& 1)
2598 host_bits
|= float_flag_invalid
;
2599 if (target_bits
& 2)
2600 host_bits
|= float_flag_divbyzero
;
2601 if (target_bits
& 4)
2602 host_bits
|= float_flag_overflow
;
2603 if (target_bits
& 8)
2604 host_bits
|= float_flag_underflow
;
2605 if (target_bits
& 0x10)
2606 host_bits
|= float_flag_inexact
;
2607 if (target_bits
& 0x80)
2608 host_bits
|= float_flag_input_denormal
;
2612 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2617 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2618 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2619 env
->vfp
.vec_len
= (val
>> 16) & 7;
2620 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2623 if (changed
& (3 << 22)) {
2624 i
= (val
>> 22) & 3;
2627 i
= float_round_nearest_even
;
2633 i
= float_round_down
;
2636 i
= float_round_to_zero
;
2639 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2641 if (changed
& (1 << 24)) {
2642 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2643 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2645 if (changed
& (1 << 25))
2646 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2648 i
= vfp_exceptbits_to_host(val
);
2649 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2650 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2653 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2655 HELPER(vfp_set_fpscr
)(env
, val
);
2658 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2660 #define VFP_BINOP(name) \
2661 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2663 float_status *fpst = fpstp; \
2664 return float32_ ## name(a, b, fpst); \
2666 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2668 float_status *fpst = fpstp; \
2669 return float64_ ## name(a, b, fpst); \
2677 float32
VFP_HELPER(neg
, s
)(float32 a
)
2679 return float32_chs(a
);
2682 float64
VFP_HELPER(neg
, d
)(float64 a
)
2684 return float64_chs(a
);
2687 float32
VFP_HELPER(abs
, s
)(float32 a
)
2689 return float32_abs(a
);
2692 float64
VFP_HELPER(abs
, d
)(float64 a
)
2694 return float64_abs(a
);
2697 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2699 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2702 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2704 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2707 /* XXX: check quiet/signaling case */
2708 #define DO_VFP_cmp(p, type) \
2709 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2712 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2713 case 0: flags = 0x6; break; \
2714 case -1: flags = 0x8; break; \
2715 case 1: flags = 0x2; break; \
2716 default: case 2: flags = 0x3; break; \
2718 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2719 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2721 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2724 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2725 case 0: flags = 0x6; break; \
2726 case -1: flags = 0x8; break; \
2727 case 1: flags = 0x2; break; \
2728 default: case 2: flags = 0x3; break; \
2730 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2731 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2733 DO_VFP_cmp(s
, float32
)
2734 DO_VFP_cmp(d
, float64
)
2737 /* Integer to float and float to integer conversions */
2739 #define CONV_ITOF(name, fsz, sign) \
2740 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2742 float_status *fpst = fpstp; \
2743 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2746 #define CONV_FTOI(name, fsz, sign, round) \
2747 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2749 float_status *fpst = fpstp; \
2750 if (float##fsz##_is_any_nan(x)) { \
2751 float_raise(float_flag_invalid, fpst); \
2754 return float##fsz##_to_##sign##int32##round(x, fpst); \
2757 #define FLOAT_CONVS(name, p, fsz, sign) \
2758 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2759 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2760 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2762 FLOAT_CONVS(si
, s
, 32, )
2763 FLOAT_CONVS(si
, d
, 64, )
2764 FLOAT_CONVS(ui
, s
, 32, u
)
2765 FLOAT_CONVS(ui
, d
, 64, u
)
2771 /* floating point conversion */
2772 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2774 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2775 /* ARM requires that S<->D conversion of any kind of NaN generates
2776 * a quiet NaN by forcing the most significant frac bit to 1.
2778 return float64_maybe_silence_nan(r
);
2781 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2783 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2784 /* ARM requires that S<->D conversion of any kind of NaN generates
2785 * a quiet NaN by forcing the most significant frac bit to 1.
2787 return float32_maybe_silence_nan(r
);
2790 /* VFP3 fixed point conversion. */
2791 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2792 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2795 float_status *fpst = fpstp; \
2797 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2798 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2800 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2803 float_status *fpst = fpstp; \
2805 if (float##fsz##_is_any_nan(x)) { \
2806 float_raise(float_flag_invalid, fpst); \
2809 tmp = float##fsz##_scalbn(x, shift, fpst); \
2810 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2813 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2814 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2815 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2816 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2817 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2818 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2819 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2820 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2823 /* Half precision conversions. */
2824 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2826 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2827 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2829 return float32_maybe_silence_nan(r
);
2834 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2836 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2837 float16 r
= float32_to_float16(a
, ieee
, s
);
2839 r
= float16_maybe_silence_nan(r
);
2841 return float16_val(r
);
2844 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2846 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2849 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2851 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2854 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2856 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2859 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2861 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2864 #define float32_two make_float32(0x40000000)
2865 #define float32_three make_float32(0x40400000)
2866 #define float32_one_point_five make_float32(0x3fc00000)
2868 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2870 float_status
*s
= &env
->vfp
.standard_fp_status
;
2871 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2872 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2873 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2874 float_raise(float_flag_input_denormal
, s
);
2878 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2881 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2883 float_status
*s
= &env
->vfp
.standard_fp_status
;
2885 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2886 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2887 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2888 float_raise(float_flag_input_denormal
, s
);
2890 return float32_one_point_five
;
2892 product
= float32_mul(a
, b
, s
);
2893 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2898 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2899 * int->float conversions at run-time. */
2900 #define float64_256 make_float64(0x4070000000000000LL)
2901 #define float64_512 make_float64(0x4080000000000000LL)
2903 /* The algorithm that must be used to calculate the estimate
2904 * is specified by the ARM ARM.
2906 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2908 /* These calculations mustn't set any fp exception flags,
2909 * so we use a local copy of the fp_status.
2911 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2912 float_status
*s
= &dummy_status
;
2913 /* q = (int)(a * 512.0) */
2914 float64 q
= float64_mul(float64_512
, a
, s
);
2915 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2917 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2918 q
= int64_to_float64(q_int
, s
);
2919 q
= float64_add(q
, float64_half
, s
);
2920 q
= float64_div(q
, float64_512
, s
);
2921 q
= float64_div(float64_one
, q
, s
);
2923 /* s = (int)(256.0 * r + 0.5) */
2924 q
= float64_mul(q
, float64_256
, s
);
2925 q
= float64_add(q
, float64_half
, s
);
2926 q_int
= float64_to_int64_round_to_zero(q
, s
);
2928 /* return (double)s / 256.0 */
2929 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2932 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2934 float_status
*s
= &env
->vfp
.standard_fp_status
;
2936 uint32_t val32
= float32_val(a
);
2939 int a_exp
= (val32
& 0x7f800000) >> 23;
2940 int sign
= val32
& 0x80000000;
2942 if (float32_is_any_nan(a
)) {
2943 if (float32_is_signaling_nan(a
)) {
2944 float_raise(float_flag_invalid
, s
);
2946 return float32_default_nan
;
2947 } else if (float32_is_infinity(a
)) {
2948 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2949 } else if (float32_is_zero_or_denormal(a
)) {
2950 if (!float32_is_zero(a
)) {
2951 float_raise(float_flag_input_denormal
, s
);
2953 float_raise(float_flag_divbyzero
, s
);
2954 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2955 } else if (a_exp
>= 253) {
2956 float_raise(float_flag_underflow
, s
);
2957 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2960 f64
= make_float64((0x3feULL
<< 52)
2961 | ((int64_t)(val32
& 0x7fffff) << 29));
2963 result_exp
= 253 - a_exp
;
2965 f64
= recip_estimate(f64
, env
);
2968 | ((result_exp
& 0xff) << 23)
2969 | ((float64_val(f64
) >> 29) & 0x7fffff);
2970 return make_float32(val32
);
2973 /* The algorithm that must be used to calculate the estimate
2974 * is specified by the ARM ARM.
2976 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2978 /* These calculations mustn't set any fp exception flags,
2979 * so we use a local copy of the fp_status.
2981 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2982 float_status
*s
= &dummy_status
;
2986 if (float64_lt(a
, float64_half
, s
)) {
2987 /* range 0.25 <= a < 0.5 */
2989 /* a in units of 1/512 rounded down */
2990 /* q0 = (int)(a * 512.0); */
2991 q
= float64_mul(float64_512
, a
, s
);
2992 q_int
= float64_to_int64_round_to_zero(q
, s
);
2994 /* reciprocal root r */
2995 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2996 q
= int64_to_float64(q_int
, s
);
2997 q
= float64_add(q
, float64_half
, s
);
2998 q
= float64_div(q
, float64_512
, s
);
2999 q
= float64_sqrt(q
, s
);
3000 q
= float64_div(float64_one
, q
, s
);
3002 /* range 0.5 <= a < 1.0 */
3004 /* a in units of 1/256 rounded down */
3005 /* q1 = (int)(a * 256.0); */
3006 q
= float64_mul(float64_256
, a
, s
);
3007 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3009 /* reciprocal root r */
3010 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3011 q
= int64_to_float64(q_int
, s
);
3012 q
= float64_add(q
, float64_half
, s
);
3013 q
= float64_div(q
, float64_256
, s
);
3014 q
= float64_sqrt(q
, s
);
3015 q
= float64_div(float64_one
, q
, s
);
3017 /* r in units of 1/256 rounded to nearest */
3018 /* s = (int)(256.0 * r + 0.5); */
3020 q
= float64_mul(q
, float64_256
,s
);
3021 q
= float64_add(q
, float64_half
, s
);
3022 q_int
= float64_to_int64_round_to_zero(q
, s
);
3024 /* return (double)s / 256.0;*/
3025 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3028 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3030 float_status
*s
= &env
->vfp
.standard_fp_status
;
3036 val
= float32_val(a
);
3038 if (float32_is_any_nan(a
)) {
3039 if (float32_is_signaling_nan(a
)) {
3040 float_raise(float_flag_invalid
, s
);
3042 return float32_default_nan
;
3043 } else if (float32_is_zero_or_denormal(a
)) {
3044 if (!float32_is_zero(a
)) {
3045 float_raise(float_flag_input_denormal
, s
);
3047 float_raise(float_flag_divbyzero
, s
);
3048 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3049 } else if (float32_is_neg(a
)) {
3050 float_raise(float_flag_invalid
, s
);
3051 return float32_default_nan
;
3052 } else if (float32_is_infinity(a
)) {
3053 return float32_zero
;
3056 /* Normalize to a double-precision value between 0.25 and 1.0,
3057 * preserving the parity of the exponent. */
3058 if ((val
& 0x800000) == 0) {
3059 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3061 | ((uint64_t)(val
& 0x7fffff) << 29));
3063 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3065 | ((uint64_t)(val
& 0x7fffff) << 29));
3068 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3070 f64
= recip_sqrt_estimate(f64
, env
);
3072 val64
= float64_val(f64
);
3074 val
= ((result_exp
& 0xff) << 23)
3075 | ((val64
>> 29) & 0x7fffff);
3076 return make_float32(val
);
3079 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3083 if ((a
& 0x80000000) == 0) {
3087 f64
= make_float64((0x3feULL
<< 52)
3088 | ((int64_t)(a
& 0x7fffffff) << 21));
3090 f64
= recip_estimate (f64
, env
);
3092 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3095 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3099 if ((a
& 0xc0000000) == 0) {
3103 if (a
& 0x80000000) {
3104 f64
= make_float64((0x3feULL
<< 52)
3105 | ((uint64_t)(a
& 0x7fffffff) << 21));
3106 } else { /* bits 31-30 == '01' */
3107 f64
= make_float64((0x3fdULL
<< 52)
3108 | ((uint64_t)(a
& 0x3fffffff) << 22));
3111 f64
= recip_sqrt_estimate(f64
, env
);
3113 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3116 /* VFPv4 fused multiply-accumulate */
3117 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3119 float_status
*fpst
= fpstp
;
3120 return float32_muladd(a
, b
, c
, 0, fpst
);
3123 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3125 float_status
*fpst
= fpstp
;
3126 return float64_muladd(a
, b
, c
, 0, fpst
);