target-arm/kvm.c

   1 /*
   2  * ARM implementation of KVM hooks
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "hw/arm/arm.h"
  25
  26 /* Check that cpu.h's idea of coprocessor fields matches KVM's */
  27 #if (CP_REG_SIZE_SHIFT != KVM_REG_SIZE_SHIFT) || \
  28     (CP_REG_SIZE_MASK != KVM_REG_SIZE_MASK) ||   \
  29     (CP_REG_SIZE_U32 != KVM_REG_SIZE_U32) || \
  30     (CP_REG_SIZE_U64 != KVM_REG_SIZE_U64) || \
  31     (CP_REG_ARM != KVM_REG_ARM)
  32 #error mismatch between cpu.h and KVM header definitions
  33 #endif
  34
  35 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  36     KVM_CAP_LAST_INFO
  37 };
  38
  39 int kvm_arch_init(KVMState *s)
  40 {
  41     /* For ARM interrupt delivery is always asynchronous,
  42      * whether we are using an in-kernel VGIC or not.
  43      */
  44     kvm_async_interrupts_allowed = true;
  45     return 0;
  46 }
  47
  48 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
  49 {
  50     return cpu->cpu_index;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     struct kvm_vcpu_init init;
  56     int ret;
  57     uint64_t v;
  58     struct kvm_one_reg r;
  59
  60     init.target = KVM_ARM_TARGET_CORTEX_A15;
  61     memset(init.features, 0, sizeof(init.features));
  62     ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
  63     if (ret) {
  64         return ret;
  65     }
  66     /* Query the kernel to make sure it supports 32 VFP
  67      * registers: QEMU's "cortex-a15" CPU is always a
  68      * VFP-D32 core. The simplest way to do this is just
  69      * to attempt to read register d31.
  70      */
  71     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
  72     r.addr = (uintptr_t)(&v);
  73     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
  74     if (ret == -ENOENT) {
  75         return -EINVAL;
  76     }
  77     return ret;
  78 }
  79
  80 /* We track all the KVM devices which need their memory addresses
  81  * passing to the kernel in a list of these structures.
  82  * When board init is complete we run through the list and
  83  * tell the kernel the base addresses of the memory regions.
  84  * We use a MemoryListener to track mapping and unmapping of
  85  * the regions during board creation, so the board models don't
  86  * need to do anything special for the KVM case.
  87  */
  88 typedef struct KVMDevice {
  89     struct kvm_arm_device_addr kda;
  90     MemoryRegion *mr;
  91     QSLIST_ENTRY(KVMDevice) entries;
  92 } KVMDevice;
  93
  94 static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
  95
  96 static void kvm_arm_devlistener_add(MemoryListener *listener,
  97                                     MemoryRegionSection *section)
  98 {
  99     KVMDevice *kd;
 100
 101     QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
 102         if (section->mr == kd->mr) {
 103             kd->kda.addr = section->offset_within_address_space;
 104         }
 105     }
 106 }
 107
 108 static void kvm_arm_devlistener_del(MemoryListener *listener,
 109                                     MemoryRegionSection *section)
 110 {
 111     KVMDevice *kd;
 112
 113     QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
 114         if (section->mr == kd->mr) {
 115             kd->kda.addr = -1;
 116         }
 117     }
 118 }
 119
 120 static MemoryListener devlistener = {
 121     .region_add = kvm_arm_devlistener_add,
 122     .region_del = kvm_arm_devlistener_del,
 123 };
 124
 125 static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
 126 {
 127     KVMDevice *kd, *tkd;
 128
 129     memory_listener_unregister(&devlistener);
 130     QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
 131         if (kd->kda.addr != -1) {
 132             if (kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR,
 133                              &kd->kda) < 0) {
 134                 fprintf(stderr, "KVM_ARM_SET_DEVICE_ADDRESS failed: %s\n",
 135                         strerror(errno));
 136                 abort();
 137             }
 138         }
 139         g_free(kd);
 140     }
 141 }
 142
 143 static Notifier notify = {
 144     .notify = kvm_arm_machine_init_done,
 145 };
 146
 147 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid)
 148 {
 149     KVMDevice *kd;
 150
 151     if (!kvm_irqchip_in_kernel()) {
 152         return;
 153     }
 154
 155     if (QSLIST_EMPTY(&kvm_devices_head)) {
 156         memory_listener_register(&devlistener, NULL);
 157         qemu_add_machine_init_done_notifier(&notify);
 158     }
 159     kd = g_new0(KVMDevice, 1);
 160     kd->mr = mr;
 161     kd->kda.id = devid;
 162     kd->kda.addr = -1;
 163     QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
 164 }
 165
 166 typedef struct Reg {
 167     uint64_t id;
 168     int offset;
 169 } Reg;
 170
 171 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 172     {                                                        \
 173         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 174         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 175         offsetof(CPUARMState, QEMUFIELD)                     \
 176     }
 177
 178 #define CP15REG(CRN, CRM, OPC1, OPC2, QEMUFIELD) \
 179     {                                            \
 180         KVM_REG_ARM | KVM_REG_SIZE_U32 |         \
 181         (15 << KVM_REG_ARM_COPROC_SHIFT) |       \
 182         ((CRN) << KVM_REG_ARM_32_CRN_SHIFT) |    \
 183         ((CRM) << KVM_REG_ARM_CRM_SHIFT) |       \
 184         ((OPC1) << KVM_REG_ARM_OPC1_SHIFT) |     \
 185         ((OPC2) << KVM_REG_ARM_32_OPC2_SHIFT),   \
 186         offsetof(CPUARMState, QEMUFIELD)         \
 187     }
 188
 189 #define VFPSYSREG(R)                                       \
 190     {                                                      \
 191         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 192         KVM_REG_ARM_VFP_##R,                               \
 193         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 194     }
 195
 196 static const Reg regs[] = {
 197     /* R0_usr .. R14_usr */
 198     COREREG(usr_regs.uregs[0], regs[0]),
 199     COREREG(usr_regs.uregs[1], regs[1]),
 200     COREREG(usr_regs.uregs[2], regs[2]),
 201     COREREG(usr_regs.uregs[3], regs[3]),
 202     COREREG(usr_regs.uregs[4], regs[4]),
 203     COREREG(usr_regs.uregs[5], regs[5]),
 204     COREREG(usr_regs.uregs[6], regs[6]),
 205     COREREG(usr_regs.uregs[7], regs[7]),
 206     COREREG(usr_regs.uregs[8], usr_regs[0]),
 207     COREREG(usr_regs.uregs[9], usr_regs[1]),
 208     COREREG(usr_regs.uregs[10], usr_regs[2]),
 209     COREREG(usr_regs.uregs[11], usr_regs[3]),
 210     COREREG(usr_regs.uregs[12], usr_regs[4]),
 211     COREREG(usr_regs.uregs[13], banked_r13[0]),
 212     COREREG(usr_regs.uregs[14], banked_r14[0]),
 213     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 214     COREREG(svc_regs[0], banked_r13[1]),
 215     COREREG(svc_regs[1], banked_r14[1]),
 216     COREREG(svc_regs[2], banked_spsr[1]),
 217     COREREG(abt_regs[0], banked_r13[2]),
 218     COREREG(abt_regs[1], banked_r14[2]),
 219     COREREG(abt_regs[2], banked_spsr[2]),
 220     COREREG(und_regs[0], banked_r13[3]),
 221     COREREG(und_regs[1], banked_r14[3]),
 222     COREREG(und_regs[2], banked_spsr[3]),
 223     COREREG(irq_regs[0], banked_r13[4]),
 224     COREREG(irq_regs[1], banked_r14[4]),
 225     COREREG(irq_regs[2], banked_spsr[4]),
 226     /* R8_fiq .. R14_fiq and SPSR_fiq */
 227     COREREG(fiq_regs[0], fiq_regs[0]),
 228     COREREG(fiq_regs[1], fiq_regs[1]),
 229     COREREG(fiq_regs[2], fiq_regs[2]),
 230     COREREG(fiq_regs[3], fiq_regs[3]),
 231     COREREG(fiq_regs[4], fiq_regs[4]),
 232     COREREG(fiq_regs[5], banked_r13[5]),
 233     COREREG(fiq_regs[6], banked_r14[5]),
 234     COREREG(fiq_regs[7], banked_spsr[5]),
 235     /* R15 */
 236     COREREG(usr_regs.uregs[15], regs[15]),
 237     /* A non-comprehensive set of cp15 registers.
 238      * TODO: drive this from the cp_regs hashtable instead.
 239      */
 240     CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */
 241     CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */
 242     CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */
 243     /* VFP system registers */
 244     VFPSYSREG(FPSID),
 245     VFPSYSREG(MVFR1),
 246     VFPSYSREG(MVFR0),
 247     VFPSYSREG(FPEXC),
 248     VFPSYSREG(FPINST),
 249     VFPSYSREG(FPINST2),
 250 };
 251
 252 int kvm_arch_put_registers(CPUState *cs, int level)
 253 {
 254     ARMCPU *cpu = ARM_CPU(cs);
 255     CPUARMState *env = &cpu->env;
 256     struct kvm_one_reg r;
 257     int mode, bn;
 258     int ret, i;
 259     uint32_t cpsr, fpscr;
 260     uint64_t ttbr;
 261
 262     /* Make sure the banked regs are properly set */
 263     mode = env->uncached_cpsr & CPSR_M;
 264     bn = bank_number(mode);
 265     if (mode == ARM_CPU_MODE_FIQ) {
 266         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 267     } else {
 268         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 269     }
 270     env->banked_r13[bn] = env->regs[13];
 271     env->banked_r14[bn] = env->regs[14];
 272     env->banked_spsr[bn] = env->spsr;
 273
 274     /* Now we can safely copy stuff down to the kernel */
 275     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 276         r.id = regs[i].id;
 277         r.addr = (uintptr_t)(env) + regs[i].offset;
 278         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 279         if (ret) {
 280             return ret;
 281         }
 282     }
 283
 284     /* Special cases which aren't a single CPUARMState field */
 285     cpsr = cpsr_read(env);
 286     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 287         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 288     r.addr = (uintptr_t)(&cpsr);
 289     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 290     if (ret) {
 291         return ret;
 292     }
 293
 294     /* TTBR0: cp15 crm=2 opc1=0 */
 295     ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
 296     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
 297         (2 << KVM_REG_ARM_CRM_SHIFT) | (0 << KVM_REG_ARM_OPC1_SHIFT);
 298     r.addr = (uintptr_t)(&ttbr);
 299     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 300     if (ret) {
 301         return ret;
 302     }
 303
 304     /* TTBR1: cp15 crm=2 opc1=1 */
 305     ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
 306     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
 307         (2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT);
 308     r.addr = (uintptr_t)(&ttbr);
 309     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 310     if (ret) {
 311         return ret;
 312     }
 313
 314     /* VFP registers */
 315     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 316     for (i = 0; i < 32; i++) {
 317         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 318         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 319         if (ret) {
 320             return ret;
 321         }
 322         r.id++;
 323     }
 324
 325     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 326         KVM_REG_ARM_VFP_FPSCR;
 327     fpscr = vfp_get_fpscr(env);
 328     r.addr = (uintptr_t)&fpscr;
 329     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 330
 331     return ret;
 332 }
 333
 334 int kvm_arch_get_registers(CPUState *cs)
 335 {
 336     ARMCPU *cpu = ARM_CPU(cs);
 337     CPUARMState *env = &cpu->env;
 338     struct kvm_one_reg r;
 339     int mode, bn;
 340     int ret, i;
 341     uint32_t cpsr, fpscr;
 342     uint64_t ttbr;
 343
 344     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 345         r.id = regs[i].id;
 346         r.addr = (uintptr_t)(env) + regs[i].offset;
 347         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 348         if (ret) {
 349             return ret;
 350         }
 351     }
 352
 353     /* Special cases which aren't a single CPUARMState field */
 354     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 355         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 356     r.addr = (uintptr_t)(&cpsr);
 357     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 358     if (ret) {
 359         return ret;
 360     }
 361     cpsr_write(env, cpsr, 0xffffffff);
 362
 363     /* TTBR0: cp15 crm=2 opc1=0 */
 364     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
 365         (2 << KVM_REG_ARM_CRM_SHIFT) | (0 << KVM_REG_ARM_OPC1_SHIFT);
 366     r.addr = (uintptr_t)(&ttbr);
 367     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 368     if (ret) {
 369         return ret;
 370     }
 371     env->cp15.c2_base0_hi = ttbr >> 32;
 372     env->cp15.c2_base0 = ttbr;
 373
 374     /* TTBR1: cp15 crm=2 opc1=1 */
 375     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | (15 << KVM_REG_ARM_COPROC_SHIFT) |
 376         (2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT);
 377     r.addr = (uintptr_t)(&ttbr);
 378     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 379     if (ret) {
 380         return ret;
 381     }
 382     env->cp15.c2_base1_hi = ttbr >> 32;
 383     env->cp15.c2_base1 = ttbr;
 384
 385     /* Make sure the current mode regs are properly set */
 386     mode = env->uncached_cpsr & CPSR_M;
 387     bn = bank_number(mode);
 388     if (mode == ARM_CPU_MODE_FIQ) {
 389         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 390     } else {
 391         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 392     }
 393     env->regs[13] = env->banked_r13[bn];
 394     env->regs[14] = env->banked_r14[bn];
 395     env->spsr = env->banked_spsr[bn];
 396
 397     /* The main GET_ONE_REG loop above set c2_control, but we need to
 398      * update some extra cached precomputed values too.
 399      * When this is driven from the cp_regs hashtable then this ugliness
 400      * can disappear because we'll use the access function which sets
 401      * these values automatically.
 402      */
 403     env->cp15.c2_mask = ~(0xffffffffu >> env->cp15.c2_control);
 404     env->cp15.c2_base_mask = ~(0x3fffu >> env->cp15.c2_control);
 405
 406     /* VFP registers */
 407     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 408     for (i = 0; i < 32; i++) {
 409         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 410         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 411         if (ret) {
 412             return ret;
 413         }
 414         r.id++;
 415     }
 416
 417     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 418         KVM_REG_ARM_VFP_FPSCR;
 419     r.addr = (uintptr_t)&fpscr;
 420     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 421     if (ret) {
 422         return ret;
 423     }
 424     vfp_set_fpscr(env, fpscr);
 425
 426     return 0;
 427 }
 428
 429 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 430 {
 431 }
 432
 433 void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 434 {
 435 }
 436
 437 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 438 {
 439     return 0;
 440 }
 441
 442 void kvm_arch_reset_vcpu(CPUState *cs)
 443 {
 444 }
 445
 446 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 447 {
 448     return true;
 449 }
 450
 451 int kvm_arch_process_async_events(CPUState *cs)
 452 {
 453     return 0;
 454 }
 455
 456 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 457 {
 458     return 1;
 459 }
 460
 461 int kvm_arch_on_sigbus(int code, void *addr)
 462 {
 463     return 1;
 464 }
 465
 466 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
 467 {
 468     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 469 }
 470
 471 int kvm_arch_insert_sw_breakpoint(CPUState *cs,
 472                                   struct kvm_sw_breakpoint *bp)
 473 {
 474     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 475     return -EINVAL;
 476 }
 477
 478 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 479                                   target_ulong len, int type)
 480 {
 481     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 482     return -EINVAL;
 483 }
 484
 485 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 486                                   target_ulong len, int type)
 487 {
 488     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 489     return -EINVAL;
 490 }
 491
 492 int kvm_arch_remove_sw_breakpoint(CPUState *cs,
 493                                   struct kvm_sw_breakpoint *bp)
 494 {
 495     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 496     return -EINVAL;
 497 }
 498
 499 void kvm_arch_remove_all_hw_breakpoints(void)
 500 {
 501     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 502 }
 503
 504 void kvm_arch_init_irq_routing(KVMState *s)
 505 {
 506 }