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target-arm: Convert TCG to using (index,value) list for cp migration
[qemu.git] / target-arm / machine.c
1 #include "hw/hw.h"
2 #include "hw/boards.h"
3
4 static bool vfp_needed(void *opaque)
5 {
6 ARMCPU *cpu = opaque;
7 CPUARMState *env = &cpu->env;
8
9 return arm_feature(env, ARM_FEATURE_VFP);
10 }
11
12 static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
13 {
14 ARMCPU *cpu = opaque;
15 CPUARMState *env = &cpu->env;
16 uint32_t val = qemu_get_be32(f);
17
18 vfp_set_fpscr(env, val);
19 return 0;
20 }
21
22 static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
23 {
24 ARMCPU *cpu = opaque;
25 CPUARMState *env = &cpu->env;
26
27 qemu_put_be32(f, vfp_get_fpscr(env));
28 }
29
30 static const VMStateInfo vmstate_fpscr = {
31 .name = "fpscr",
32 .get = get_fpscr,
33 .put = put_fpscr,
34 };
35
36 static const VMStateDescription vmstate_vfp = {
37 .name = "cpu/vfp",
38 .version_id = 2,
39 .minimum_version_id = 2,
40 .minimum_version_id_old = 2,
41 .fields = (VMStateField[]) {
42 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
43 /* The xregs array is a little awkward because element 1 (FPSCR)
44 * requires a specific accessor, so we have to split it up in
45 * the vmstate:
46 */
47 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
48 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
49 {
50 .name = "fpscr",
51 .version_id = 0,
52 .size = sizeof(uint32_t),
53 .info = &vmstate_fpscr,
54 .flags = VMS_SINGLE,
55 .offset = 0,
56 },
57 VMSTATE_END_OF_LIST()
58 }
59 };
60
61 static bool iwmmxt_needed(void *opaque)
62 {
63 ARMCPU *cpu = opaque;
64 CPUARMState *env = &cpu->env;
65
66 return arm_feature(env, ARM_FEATURE_IWMMXT);
67 }
68
69 static const VMStateDescription vmstate_iwmmxt = {
70 .name = "cpu/iwmmxt",
71 .version_id = 1,
72 .minimum_version_id = 1,
73 .minimum_version_id_old = 1,
74 .fields = (VMStateField[]) {
75 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
76 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
77 VMSTATE_END_OF_LIST()
78 }
79 };
80
81 static bool m_needed(void *opaque)
82 {
83 ARMCPU *cpu = opaque;
84 CPUARMState *env = &cpu->env;
85
86 return arm_feature(env, ARM_FEATURE_M);
87 }
88
89 const VMStateDescription vmstate_m = {
90 .name = "cpu/m",
91 .version_id = 1,
92 .minimum_version_id = 1,
93 .minimum_version_id_old = 1,
94 .fields = (VMStateField[]) {
95 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
96 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
97 VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
98 VMSTATE_UINT32(env.v7m.control, ARMCPU),
99 VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
100 VMSTATE_INT32(env.v7m.exception, ARMCPU),
101 VMSTATE_END_OF_LIST()
102 }
103 };
104
105 static bool thumb2ee_needed(void *opaque)
106 {
107 ARMCPU *cpu = opaque;
108 CPUARMState *env = &cpu->env;
109
110 return arm_feature(env, ARM_FEATURE_THUMB2EE);
111 }
112
113 static const VMStateDescription vmstate_thumb2ee = {
114 .name = "cpu/thumb2ee",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .minimum_version_id_old = 1,
118 .fields = (VMStateField[]) {
119 VMSTATE_UINT32(env.teecr, ARMCPU),
120 VMSTATE_UINT32(env.teehbr, ARMCPU),
121 VMSTATE_END_OF_LIST()
122 }
123 };
124
125 static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
126 {
127 ARMCPU *cpu = opaque;
128 CPUARMState *env = &cpu->env;
129 uint32_t val = qemu_get_be32(f);
130
131 /* Avoid mode switch when restoring CPSR */
132 env->uncached_cpsr = val & CPSR_M;
133 cpsr_write(env, val, 0xffffffff);
134 return 0;
135 }
136
137 static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
138 {
139 ARMCPU *cpu = opaque;
140 CPUARMState *env = &cpu->env;
141
142 qemu_put_be32(f, cpsr_read(env));
143 }
144
145 static const VMStateInfo vmstate_cpsr = {
146 .name = "cpsr",
147 .get = get_cpsr,
148 .put = put_cpsr,
149 };
150
151 static void cpu_pre_save(void *opaque)
152 {
153 ARMCPU *cpu = opaque;
154
155 if (!write_cpustate_to_list(cpu)) {
156 /* This should never fail. */
157 abort();
158 }
159
160 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
161 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
162 cpu->cpreg_array_len * sizeof(uint64_t));
163 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
164 cpu->cpreg_array_len * sizeof(uint64_t));
165 }
166
167 static int cpu_post_load(void *opaque, int version_id)
168 {
169 ARMCPU *cpu = opaque;
170 int i, v;
171
172 /* Update the values list from the incoming migration data.
173 * Anything in the incoming data which we don't know about is
174 * a migration failure; anything we know about but the incoming
175 * data doesn't specify retains its current (reset) value.
176 * The indexes list remains untouched -- we only inspect the
177 * incoming migration index list so we can match the values array
178 * entries with the right slots in our own values array.
179 */
180
181 for (i = 0, v = 0; i < cpu->cpreg_array_len
182 && v < cpu->cpreg_vmstate_array_len; i++) {
183 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
184 /* register in our list but not incoming : skip it */
185 continue;
186 }
187 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
188 /* register in their list but not ours: fail migration */
189 return -1;
190 }
191 /* matching register, copy the value over */
192 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
193 v++;
194 }
195
196 if (!write_list_to_cpustate(cpu)) {
197 return -1;
198 }
199
200 return 0;
201 }
202
203 const VMStateDescription vmstate_arm_cpu = {
204 .name = "cpu",
205 .version_id = 12,
206 .minimum_version_id = 12,
207 .minimum_version_id_old = 12,
208 .pre_save = cpu_pre_save,
209 .post_load = cpu_post_load,
210 .fields = (VMStateField[]) {
211 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
212 {
213 .name = "cpsr",
214 .version_id = 0,
215 .size = sizeof(uint32_t),
216 .info = &vmstate_cpsr,
217 .flags = VMS_SINGLE,
218 .offset = 0,
219 },
220 VMSTATE_UINT32(env.spsr, ARMCPU),
221 VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
222 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
223 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
224 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
225 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
226 /* The length-check must come before the arrays to avoid
227 * incoming data possibly overflowing the array.
228 */
229 VMSTATE_INT32_LE(cpreg_vmstate_array_len, ARMCPU),
230 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
231 cpreg_vmstate_array_len,
232 0, vmstate_info_uint64, uint64_t),
233 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
234 cpreg_vmstate_array_len,
235 0, vmstate_info_uint64, uint64_t),
236 VMSTATE_UINT32(env.exclusive_addr, ARMCPU),
237 VMSTATE_UINT32(env.exclusive_val, ARMCPU),
238 VMSTATE_UINT32(env.exclusive_high, ARMCPU),
239 VMSTATE_UINT64(env.features, ARMCPU),
240 VMSTATE_END_OF_LIST()
241 },
242 .subsections = (VMStateSubsection[]) {
243 {
244 .vmsd = &vmstate_vfp,
245 .needed = vfp_needed,
246 } , {
247 .vmsd = &vmstate_iwmmxt,
248 .needed = iwmmxt_needed,
249 } , {
250 .vmsd = &vmstate_m,
251 .needed = m_needed,
252 } , {
253 .vmsd = &vmstate_thumb2ee,
254 .needed = thumb2ee_needed,
255 } , {
256 /* empty */
257 }
258 }
259 };