4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
47 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
49 /* internal defines */
50 typedef struct DisasContext
{
53 /* Nonzero if this instruction has been conditionally skipped. */
55 /* The label that will be jumped to when the instruction is skipped. */
57 /* Thumb-2 condtional execution bits. */
60 struct TranslationBlock
*tb
;
61 int singlestep_enabled
;
63 #if !defined(CONFIG_USER_ONLY)
71 static uint32_t gen_opc_condexec_bits
[OPC_BUF_SIZE
];
73 #if defined(CONFIG_USER_ONLY)
76 #define IS_USER(s) (s->user)
79 /* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
84 static TCGv_ptr cpu_env
;
85 /* We reuse the same 64-bit temporaries for efficiency. */
86 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
87 static TCGv_i32 cpu_R
[16];
88 static TCGv_i32 cpu_exclusive_addr
;
89 static TCGv_i32 cpu_exclusive_val
;
90 static TCGv_i32 cpu_exclusive_high
;
91 #ifdef CONFIG_USER_ONLY
92 static TCGv_i32 cpu_exclusive_test
;
93 static TCGv_i32 cpu_exclusive_info
;
96 /* FIXME: These should be removed. */
97 static TCGv cpu_F0s
, cpu_F1s
;
98 static TCGv_i64 cpu_F0d
, cpu_F1d
;
100 #include "gen-icount.h"
102 static const char *regnames
[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
106 /* initialize TCG globals. */
107 void arm_translate_init(void)
111 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
113 for (i
= 0; i
< 16; i
++) {
114 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
115 offsetof(CPUState
, regs
[i
]),
118 cpu_exclusive_addr
= tcg_global_mem_new_i32(TCG_AREG0
,
119 offsetof(CPUState
, exclusive_addr
), "exclusive_addr");
120 cpu_exclusive_val
= tcg_global_mem_new_i32(TCG_AREG0
,
121 offsetof(CPUState
, exclusive_val
), "exclusive_val");
122 cpu_exclusive_high
= tcg_global_mem_new_i32(TCG_AREG0
,
123 offsetof(CPUState
, exclusive_high
), "exclusive_high");
124 #ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test
= tcg_global_mem_new_i32(TCG_AREG0
,
126 offsetof(CPUState
, exclusive_test
), "exclusive_test");
127 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
128 offsetof(CPUState
, exclusive_info
), "exclusive_info");
135 static inline TCGv
load_cpu_offset(int offset
)
137 TCGv tmp
= tcg_temp_new_i32();
138 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
142 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
144 static inline void store_cpu_offset(TCGv var
, int offset
)
146 tcg_gen_st_i32(var
, cpu_env
, offset
);
147 tcg_temp_free_i32(var
);
150 #define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
153 /* Set a variable to the value of a CPU register. */
154 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
158 /* normaly, since we updated PC, we need only to add one insn */
160 addr
= (long)s
->pc
+ 2;
162 addr
= (long)s
->pc
+ 4;
163 tcg_gen_movi_i32(var
, addr
);
165 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
169 /* Create a new temporary and set it to the value of a CPU register. */
170 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
172 TCGv tmp
= tcg_temp_new_i32();
173 load_reg_var(s
, tmp
, reg
);
177 /* Set a CPU register. The source must be a temporary and will be
179 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
182 tcg_gen_andi_i32(var
, var
, ~1);
183 s
->is_jmp
= DISAS_JUMP
;
185 tcg_gen_mov_i32(cpu_R
[reg
], var
);
186 tcg_temp_free_i32(var
);
189 /* Value extensions. */
190 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
192 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
195 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
199 static inline void gen_set_cpsr(TCGv var
, uint32_t mask
)
201 TCGv tmp_mask
= tcg_const_i32(mask
);
202 gen_helper_cpsr_write(var
, tmp_mask
);
203 tcg_temp_free_i32(tmp_mask
);
205 /* Set NZCV flags from the high 4 bits of var. */
206 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
208 static void gen_exception(int excp
)
210 TCGv tmp
= tcg_temp_new_i32();
211 tcg_gen_movi_i32(tmp
, excp
);
212 gen_helper_exception(tmp
);
213 tcg_temp_free_i32(tmp
);
216 static void gen_smul_dual(TCGv a
, TCGv b
)
218 TCGv tmp1
= tcg_temp_new_i32();
219 TCGv tmp2
= tcg_temp_new_i32();
220 tcg_gen_ext16s_i32(tmp1
, a
);
221 tcg_gen_ext16s_i32(tmp2
, b
);
222 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
223 tcg_temp_free_i32(tmp2
);
224 tcg_gen_sari_i32(a
, a
, 16);
225 tcg_gen_sari_i32(b
, b
, 16);
226 tcg_gen_mul_i32(b
, b
, a
);
227 tcg_gen_mov_i32(a
, tmp1
);
228 tcg_temp_free_i32(tmp1
);
231 /* Byteswap each halfword. */
232 static void gen_rev16(TCGv var
)
234 TCGv tmp
= tcg_temp_new_i32();
235 tcg_gen_shri_i32(tmp
, var
, 8);
236 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
237 tcg_gen_shli_i32(var
, var
, 8);
238 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
239 tcg_gen_or_i32(var
, var
, tmp
);
240 tcg_temp_free_i32(tmp
);
243 /* Byteswap low halfword and sign extend. */
244 static void gen_revsh(TCGv var
)
246 tcg_gen_ext16u_i32(var
, var
);
247 tcg_gen_bswap16_i32(var
, var
);
248 tcg_gen_ext16s_i32(var
, var
);
251 /* Unsigned bitfield extract. */
252 static void gen_ubfx(TCGv var
, int shift
, uint32_t mask
)
255 tcg_gen_shri_i32(var
, var
, shift
);
256 tcg_gen_andi_i32(var
, var
, mask
);
259 /* Signed bitfield extract. */
260 static void gen_sbfx(TCGv var
, int shift
, int width
)
265 tcg_gen_sari_i32(var
, var
, shift
);
266 if (shift
+ width
< 32) {
267 signbit
= 1u << (width
- 1);
268 tcg_gen_andi_i32(var
, var
, (1u << width
) - 1);
269 tcg_gen_xori_i32(var
, var
, signbit
);
270 tcg_gen_subi_i32(var
, var
, signbit
);
274 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
275 static void gen_bfi(TCGv dest
, TCGv base
, TCGv val
, int shift
, uint32_t mask
)
277 tcg_gen_andi_i32(val
, val
, mask
);
278 tcg_gen_shli_i32(val
, val
, shift
);
279 tcg_gen_andi_i32(base
, base
, ~(mask
<< shift
));
280 tcg_gen_or_i32(dest
, base
, val
);
283 /* Return (b << 32) + a. Mark inputs as dead */
284 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv b
)
286 TCGv_i64 tmp64
= tcg_temp_new_i64();
288 tcg_gen_extu_i32_i64(tmp64
, b
);
289 tcg_temp_free_i32(b
);
290 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
291 tcg_gen_add_i64(a
, tmp64
, a
);
293 tcg_temp_free_i64(tmp64
);
297 /* Return (b << 32) - a. Mark inputs as dead. */
298 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv b
)
300 TCGv_i64 tmp64
= tcg_temp_new_i64();
302 tcg_gen_extu_i32_i64(tmp64
, b
);
303 tcg_temp_free_i32(b
);
304 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
305 tcg_gen_sub_i64(a
, tmp64
, a
);
307 tcg_temp_free_i64(tmp64
);
311 /* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
313 /* 32x32->64 multiply. Marks inputs as dead. */
314 static TCGv_i64
gen_mulu_i64_i32(TCGv a
, TCGv b
)
316 TCGv_i64 tmp1
= tcg_temp_new_i64();
317 TCGv_i64 tmp2
= tcg_temp_new_i64();
319 tcg_gen_extu_i32_i64(tmp1
, a
);
320 tcg_temp_free_i32(a
);
321 tcg_gen_extu_i32_i64(tmp2
, b
);
322 tcg_temp_free_i32(b
);
323 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
324 tcg_temp_free_i64(tmp2
);
328 static TCGv_i64
gen_muls_i64_i32(TCGv a
, TCGv b
)
330 TCGv_i64 tmp1
= tcg_temp_new_i64();
331 TCGv_i64 tmp2
= tcg_temp_new_i64();
333 tcg_gen_ext_i32_i64(tmp1
, a
);
334 tcg_temp_free_i32(a
);
335 tcg_gen_ext_i32_i64(tmp2
, b
);
336 tcg_temp_free_i32(b
);
337 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
338 tcg_temp_free_i64(tmp2
);
342 /* Swap low and high halfwords. */
343 static void gen_swap_half(TCGv var
)
345 TCGv tmp
= tcg_temp_new_i32();
346 tcg_gen_shri_i32(tmp
, var
, 16);
347 tcg_gen_shli_i32(var
, var
, 16);
348 tcg_gen_or_i32(var
, var
, tmp
);
349 tcg_temp_free_i32(tmp
);
352 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
356 t0 = (t0 + t1) ^ tmp;
359 static void gen_add16(TCGv t0
, TCGv t1
)
361 TCGv tmp
= tcg_temp_new_i32();
362 tcg_gen_xor_i32(tmp
, t0
, t1
);
363 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
364 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
365 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
366 tcg_gen_add_i32(t0
, t0
, t1
);
367 tcg_gen_xor_i32(t0
, t0
, tmp
);
368 tcg_temp_free_i32(tmp
);
369 tcg_temp_free_i32(t1
);
372 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
374 /* Set CF to the top bit of var. */
375 static void gen_set_CF_bit31(TCGv var
)
377 TCGv tmp
= tcg_temp_new_i32();
378 tcg_gen_shri_i32(tmp
, var
, 31);
380 tcg_temp_free_i32(tmp
);
383 /* Set N and Z flags from var. */
384 static inline void gen_logic_CC(TCGv var
)
386 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, NF
));
387 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, ZF
));
391 static void gen_adc(TCGv t0
, TCGv t1
)
394 tcg_gen_add_i32(t0
, t0
, t1
);
395 tmp
= load_cpu_field(CF
);
396 tcg_gen_add_i32(t0
, t0
, tmp
);
397 tcg_temp_free_i32(tmp
);
400 /* dest = T0 + T1 + CF. */
401 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
404 tcg_gen_add_i32(dest
, t0
, t1
);
405 tmp
= load_cpu_field(CF
);
406 tcg_gen_add_i32(dest
, dest
, tmp
);
407 tcg_temp_free_i32(tmp
);
410 /* dest = T0 - T1 + CF - 1. */
411 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
414 tcg_gen_sub_i32(dest
, t0
, t1
);
415 tmp
= load_cpu_field(CF
);
416 tcg_gen_add_i32(dest
, dest
, tmp
);
417 tcg_gen_subi_i32(dest
, dest
, 1);
418 tcg_temp_free_i32(tmp
);
421 /* FIXME: Implement this natively. */
422 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
424 static void shifter_out_im(TCGv var
, int shift
)
426 TCGv tmp
= tcg_temp_new_i32();
428 tcg_gen_andi_i32(tmp
, var
, 1);
430 tcg_gen_shri_i32(tmp
, var
, shift
);
432 tcg_gen_andi_i32(tmp
, tmp
, 1);
435 tcg_temp_free_i32(tmp
);
438 /* Shift by immediate. Includes special handling for shift == 0. */
439 static inline void gen_arm_shift_im(TCGv var
, int shiftop
, int shift
, int flags
)
445 shifter_out_im(var
, 32 - shift
);
446 tcg_gen_shli_i32(var
, var
, shift
);
452 tcg_gen_shri_i32(var
, var
, 31);
455 tcg_gen_movi_i32(var
, 0);
458 shifter_out_im(var
, shift
- 1);
459 tcg_gen_shri_i32(var
, var
, shift
);
466 shifter_out_im(var
, shift
- 1);
469 tcg_gen_sari_i32(var
, var
, shift
);
471 case 3: /* ROR/RRX */
474 shifter_out_im(var
, shift
- 1);
475 tcg_gen_rotri_i32(var
, var
, shift
); break;
477 TCGv tmp
= load_cpu_field(CF
);
479 shifter_out_im(var
, 0);
480 tcg_gen_shri_i32(var
, var
, 1);
481 tcg_gen_shli_i32(tmp
, tmp
, 31);
482 tcg_gen_or_i32(var
, var
, tmp
);
483 tcg_temp_free_i32(tmp
);
488 static inline void gen_arm_shift_reg(TCGv var
, int shiftop
,
489 TCGv shift
, int flags
)
493 case 0: gen_helper_shl_cc(var
, var
, shift
); break;
494 case 1: gen_helper_shr_cc(var
, var
, shift
); break;
495 case 2: gen_helper_sar_cc(var
, var
, shift
); break;
496 case 3: gen_helper_ror_cc(var
, var
, shift
); break;
500 case 0: gen_helper_shl(var
, var
, shift
); break;
501 case 1: gen_helper_shr(var
, var
, shift
); break;
502 case 2: gen_helper_sar(var
, var
, shift
); break;
503 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
504 tcg_gen_rotr_i32(var
, var
, shift
); break;
507 tcg_temp_free_i32(shift
);
510 #define PAS_OP(pfx) \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
519 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
524 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
526 tmp
= tcg_temp_new_ptr();
527 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
529 tcg_temp_free_ptr(tmp
);
532 tmp
= tcg_temp_new_ptr();
533 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
535 tcg_temp_free_ptr(tmp
);
537 #undef gen_pas_helper
538 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 #undef gen_pas_helper
556 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557 #define PAS_OP(pfx) \
559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
566 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
571 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
573 tmp
= tcg_temp_new_ptr();
574 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
576 tcg_temp_free_ptr(tmp
);
579 tmp
= tcg_temp_new_ptr();
580 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
582 tcg_temp_free_ptr(tmp
);
584 #undef gen_pas_helper
585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 #undef gen_pas_helper
603 static void gen_test_cc(int cc
, int label
)
611 tmp
= load_cpu_field(ZF
);
612 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
615 tmp
= load_cpu_field(ZF
);
616 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
619 tmp
= load_cpu_field(CF
);
620 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
623 tmp
= load_cpu_field(CF
);
624 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
627 tmp
= load_cpu_field(NF
);
628 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
631 tmp
= load_cpu_field(NF
);
632 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
635 tmp
= load_cpu_field(VF
);
636 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
639 tmp
= load_cpu_field(VF
);
640 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
642 case 8: /* hi: C && !Z */
643 inv
= gen_new_label();
644 tmp
= load_cpu_field(CF
);
645 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
646 tcg_temp_free_i32(tmp
);
647 tmp
= load_cpu_field(ZF
);
648 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
651 case 9: /* ls: !C || Z */
652 tmp
= load_cpu_field(CF
);
653 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
654 tcg_temp_free_i32(tmp
);
655 tmp
= load_cpu_field(ZF
);
656 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp
= load_cpu_field(VF
);
660 tmp2
= load_cpu_field(NF
);
661 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
662 tcg_temp_free_i32(tmp2
);
663 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp
= load_cpu_field(VF
);
667 tmp2
= load_cpu_field(NF
);
668 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
669 tcg_temp_free_i32(tmp2
);
670 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
672 case 12: /* gt: !Z && N == V */
673 inv
= gen_new_label();
674 tmp
= load_cpu_field(ZF
);
675 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
676 tcg_temp_free_i32(tmp
);
677 tmp
= load_cpu_field(VF
);
678 tmp2
= load_cpu_field(NF
);
679 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
680 tcg_temp_free_i32(tmp2
);
681 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
684 case 13: /* le: Z || N != V */
685 tmp
= load_cpu_field(ZF
);
686 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
687 tcg_temp_free_i32(tmp
);
688 tmp
= load_cpu_field(VF
);
689 tmp2
= load_cpu_field(NF
);
690 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
691 tcg_temp_free_i32(tmp2
);
692 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
695 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
698 tcg_temp_free_i32(tmp
);
701 static const uint8_t table_logic_cc
[16] = {
720 /* Set PC and Thumb state from an immediate address. */
721 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
725 s
->is_jmp
= DISAS_UPDATE
;
726 if (s
->thumb
!= (addr
& 1)) {
727 tmp
= tcg_temp_new_i32();
728 tcg_gen_movi_i32(tmp
, addr
& 1);
729 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, thumb
));
730 tcg_temp_free_i32(tmp
);
732 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
735 /* Set PC and Thumb state from var. var is marked as dead. */
736 static inline void gen_bx(DisasContext
*s
, TCGv var
)
738 s
->is_jmp
= DISAS_UPDATE
;
739 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
740 tcg_gen_andi_i32(var
, var
, 1);
741 store_cpu_field(var
, thumb
);
744 /* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747 static inline void store_reg_bx(CPUState
*env
, DisasContext
*s
,
750 if (reg
== 15 && ENABLE_ARCH_7
) {
753 store_reg(s
, reg
, var
);
757 /* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761 static inline void store_reg_from_load(CPUState
*env
, DisasContext
*s
,
764 if (reg
== 15 && ENABLE_ARCH_5
) {
767 store_reg(s
, reg
, var
);
771 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
773 TCGv tmp
= tcg_temp_new_i32();
774 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
777 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
779 TCGv tmp
= tcg_temp_new_i32();
780 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
783 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
785 TCGv tmp
= tcg_temp_new_i32();
786 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
789 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
791 TCGv tmp
= tcg_temp_new_i32();
792 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
795 static inline TCGv
gen_ld32(TCGv addr
, int index
)
797 TCGv tmp
= tcg_temp_new_i32();
798 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
801 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
803 TCGv_i64 tmp
= tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp
, addr
, index
);
807 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
809 tcg_gen_qemu_st8(val
, addr
, index
);
810 tcg_temp_free_i32(val
);
812 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
814 tcg_gen_qemu_st16(val
, addr
, index
);
815 tcg_temp_free_i32(val
);
817 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
819 tcg_gen_qemu_st32(val
, addr
, index
);
820 tcg_temp_free_i32(val
);
822 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
824 tcg_gen_qemu_st64(val
, addr
, index
);
825 tcg_temp_free_i64(val
);
828 static inline void gen_set_pc_im(uint32_t val
)
830 tcg_gen_movi_i32(cpu_R
[15], val
);
833 /* Force a TB lookup after an instruction that changes the CPU state. */
834 static inline void gen_lookup_tb(DisasContext
*s
)
836 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
837 s
->is_jmp
= DISAS_UPDATE
;
840 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
843 int val
, rm
, shift
, shiftop
;
846 if (!(insn
& (1 << 25))) {
849 if (!(insn
& (1 << 23)))
852 tcg_gen_addi_i32(var
, var
, val
);
856 shift
= (insn
>> 7) & 0x1f;
857 shiftop
= (insn
>> 5) & 3;
858 offset
= load_reg(s
, rm
);
859 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
860 if (!(insn
& (1 << 23)))
861 tcg_gen_sub_i32(var
, var
, offset
);
863 tcg_gen_add_i32(var
, var
, offset
);
864 tcg_temp_free_i32(offset
);
868 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
874 if (insn
& (1 << 22)) {
876 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
877 if (!(insn
& (1 << 23)))
881 tcg_gen_addi_i32(var
, var
, val
);
885 tcg_gen_addi_i32(var
, var
, extra
);
887 offset
= load_reg(s
, rm
);
888 if (!(insn
& (1 << 23)))
889 tcg_gen_sub_i32(var
, var
, offset
);
891 tcg_gen_add_i32(var
, var
, offset
);
892 tcg_temp_free_i32(offset
);
896 #define VFP_OP2(name) \
897 static inline void gen_vfp_##name(int dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
912 static inline void gen_vfp_abs(int dp
)
915 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
917 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
920 static inline void gen_vfp_neg(int dp
)
923 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
925 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
928 static inline void gen_vfp_sqrt(int dp
)
931 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
933 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
936 static inline void gen_vfp_cmp(int dp
)
939 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
941 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
944 static inline void gen_vfp_cmpe(int dp
)
947 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
949 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
952 static inline void gen_vfp_F1_ld0(int dp
)
955 tcg_gen_movi_i64(cpu_F1d
, 0);
957 tcg_gen_movi_i32(cpu_F1s
, 0);
960 static inline void gen_vfp_uito(int dp
)
963 gen_helper_vfp_uitod(cpu_F0d
, cpu_F0s
, cpu_env
);
965 gen_helper_vfp_uitos(cpu_F0s
, cpu_F0s
, cpu_env
);
968 static inline void gen_vfp_sito(int dp
)
971 gen_helper_vfp_sitod(cpu_F0d
, cpu_F0s
, cpu_env
);
973 gen_helper_vfp_sitos(cpu_F0s
, cpu_F0s
, cpu_env
);
976 static inline void gen_vfp_toui(int dp
)
979 gen_helper_vfp_touid(cpu_F0s
, cpu_F0d
, cpu_env
);
981 gen_helper_vfp_touis(cpu_F0s
, cpu_F0s
, cpu_env
);
984 static inline void gen_vfp_touiz(int dp
)
987 gen_helper_vfp_touizd(cpu_F0s
, cpu_F0d
, cpu_env
);
989 gen_helper_vfp_touizs(cpu_F0s
, cpu_F0s
, cpu_env
);
992 static inline void gen_vfp_tosi(int dp
)
995 gen_helper_vfp_tosid(cpu_F0s
, cpu_F0d
, cpu_env
);
997 gen_helper_vfp_tosis(cpu_F0s
, cpu_F0s
, cpu_env
);
1000 static inline void gen_vfp_tosiz(int dp
)
1003 gen_helper_vfp_tosizd(cpu_F0s
, cpu_F0d
, cpu_env
);
1005 gen_helper_vfp_tosizs(cpu_F0s
, cpu_F0s
, cpu_env
);
1008 #define VFP_GEN_FIX(name) \
1009 static inline void gen_vfp_##name(int dp, int shift) \
1011 TCGv tmp_shift = tcg_const_i32(shift); \
1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
1028 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv addr
)
1031 tcg_gen_qemu_ld64(cpu_F0d
, addr
, IS_USER(s
));
1033 tcg_gen_qemu_ld32u(cpu_F0s
, addr
, IS_USER(s
));
1036 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv addr
)
1039 tcg_gen_qemu_st64(cpu_F0d
, addr
, IS_USER(s
));
1041 tcg_gen_qemu_st32(cpu_F0s
, addr
, IS_USER(s
));
1045 vfp_reg_offset (int dp
, int reg
)
1048 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1050 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1051 + offsetof(CPU_DoubleU
, l
.upper
);
1053 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1054 + offsetof(CPU_DoubleU
, l
.lower
);
1058 /* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1061 neon_reg_offset (int reg
, int n
)
1065 return vfp_reg_offset(0, sreg
);
1068 static TCGv
neon_load_reg(int reg
, int pass
)
1070 TCGv tmp
= tcg_temp_new_i32();
1071 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1075 static void neon_store_reg(int reg
, int pass
, TCGv var
)
1077 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1078 tcg_temp_free_i32(var
);
1081 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1083 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1086 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1088 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1091 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1092 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1093 #define tcg_gen_st_f32 tcg_gen_st_i32
1094 #define tcg_gen_st_f64 tcg_gen_st_i64
1096 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1099 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1101 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1104 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1107 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1109 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1112 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1115 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1117 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1120 #define ARM_CP_RW_BIT (1 << 20)
1122 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1124 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1127 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1129 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1132 static inline TCGv
iwmmxt_load_creg(int reg
)
1134 TCGv var
= tcg_temp_new_i32();
1135 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1139 static inline void iwmmxt_store_creg(int reg
, TCGv var
)
1141 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1142 tcg_temp_free_i32(var
);
1145 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1147 iwmmxt_store_reg(cpu_M0
, rn
);
1150 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1152 iwmmxt_load_reg(cpu_M0
, rn
);
1155 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1157 iwmmxt_load_reg(cpu_V1
, rn
);
1158 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1161 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1163 iwmmxt_load_reg(cpu_V1
, rn
);
1164 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1167 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1169 iwmmxt_load_reg(cpu_V1
, rn
);
1170 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1173 #define IWMMXT_OP(name) \
1174 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1180 #define IWMMXT_OP_SIZE(name) \
1181 IWMMXT_OP(name##b) \
1182 IWMMXT_OP(name##w) \
1185 #define IWMMXT_OP_1(name) \
1186 static inline void gen_op_iwmmxt_##name##_M0(void) \
1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
1202 IWMMXT_OP_SIZE(unpackl
)
1203 IWMMXT_OP_SIZE(unpackh
)
1205 IWMMXT_OP_1(unpacklub
)
1206 IWMMXT_OP_1(unpackluw
)
1207 IWMMXT_OP_1(unpacklul
)
1208 IWMMXT_OP_1(unpackhub
)
1209 IWMMXT_OP_1(unpackhuw
)
1210 IWMMXT_OP_1(unpackhul
)
1211 IWMMXT_OP_1(unpacklsb
)
1212 IWMMXT_OP_1(unpacklsw
)
1213 IWMMXT_OP_1(unpacklsl
)
1214 IWMMXT_OP_1(unpackhsb
)
1215 IWMMXT_OP_1(unpackhsw
)
1216 IWMMXT_OP_1(unpackhsl
)
1218 IWMMXT_OP_SIZE(cmpeq
)
1219 IWMMXT_OP_SIZE(cmpgtu
)
1220 IWMMXT_OP_SIZE(cmpgts
)
1222 IWMMXT_OP_SIZE(mins
)
1223 IWMMXT_OP_SIZE(minu
)
1224 IWMMXT_OP_SIZE(maxs
)
1225 IWMMXT_OP_SIZE(maxu
)
1227 IWMMXT_OP_SIZE(subn
)
1228 IWMMXT_OP_SIZE(addn
)
1229 IWMMXT_OP_SIZE(subu
)
1230 IWMMXT_OP_SIZE(addu
)
1231 IWMMXT_OP_SIZE(subs
)
1232 IWMMXT_OP_SIZE(adds
)
1248 static void gen_op_iwmmxt_set_mup(void)
1251 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1252 tcg_gen_ori_i32(tmp
, tmp
, 2);
1253 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1256 static void gen_op_iwmmxt_set_cup(void)
1259 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1260 tcg_gen_ori_i32(tmp
, tmp
, 1);
1261 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1264 static void gen_op_iwmmxt_setpsr_nz(void)
1266 TCGv tmp
= tcg_temp_new_i32();
1267 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1268 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1271 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1273 iwmmxt_load_reg(cpu_V1
, rn
);
1274 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1275 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1278 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
, TCGv dest
)
1284 rd
= (insn
>> 16) & 0xf;
1285 tmp
= load_reg(s
, rd
);
1287 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1288 if (insn
& (1 << 24)) {
1290 if (insn
& (1 << 23))
1291 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1293 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1294 tcg_gen_mov_i32(dest
, tmp
);
1295 if (insn
& (1 << 21))
1296 store_reg(s
, rd
, tmp
);
1298 tcg_temp_free_i32(tmp
);
1299 } else if (insn
& (1 << 21)) {
1301 tcg_gen_mov_i32(dest
, tmp
);
1302 if (insn
& (1 << 23))
1303 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1305 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1306 store_reg(s
, rd
, tmp
);
1307 } else if (!(insn
& (1 << 23)))
1312 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv dest
)
1314 int rd
= (insn
>> 0) & 0xf;
1317 if (insn
& (1 << 8)) {
1318 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1321 tmp
= iwmmxt_load_creg(rd
);
1324 tmp
= tcg_temp_new_i32();
1325 iwmmxt_load_reg(cpu_V0
, rd
);
1326 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
1328 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1329 tcg_gen_mov_i32(dest
, tmp
);
1330 tcg_temp_free_i32(tmp
);
1334 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336 static int disas_iwmmxt_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
1339 int rdhi
, rdlo
, rd0
, rd1
, i
;
1341 TCGv tmp
, tmp2
, tmp3
;
1343 if ((insn
& 0x0e000e00) == 0x0c000000) {
1344 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1346 rdlo
= (insn
>> 12) & 0xf;
1347 rdhi
= (insn
>> 16) & 0xf;
1348 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1349 iwmmxt_load_reg(cpu_V0
, wrd
);
1350 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1351 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1353 } else { /* TMCRR */
1354 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1355 iwmmxt_store_reg(cpu_V0
, wrd
);
1356 gen_op_iwmmxt_set_mup();
1361 wrd
= (insn
>> 12) & 0xf;
1362 addr
= tcg_temp_new_i32();
1363 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1364 tcg_temp_free_i32(addr
);
1367 if (insn
& ARM_CP_RW_BIT
) {
1368 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1369 tmp
= tcg_temp_new_i32();
1370 tcg_gen_qemu_ld32u(tmp
, addr
, IS_USER(s
));
1371 iwmmxt_store_creg(wrd
, tmp
);
1374 if (insn
& (1 << 8)) {
1375 if (insn
& (1 << 22)) { /* WLDRD */
1376 tcg_gen_qemu_ld64(cpu_M0
, addr
, IS_USER(s
));
1378 } else { /* WLDRW wRd */
1379 tmp
= gen_ld32(addr
, IS_USER(s
));
1382 if (insn
& (1 << 22)) { /* WLDRH */
1383 tmp
= gen_ld16u(addr
, IS_USER(s
));
1384 } else { /* WLDRB */
1385 tmp
= gen_ld8u(addr
, IS_USER(s
));
1389 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1390 tcg_temp_free_i32(tmp
);
1392 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1395 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1396 tmp
= iwmmxt_load_creg(wrd
);
1397 gen_st32(tmp
, addr
, IS_USER(s
));
1399 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1400 tmp
= tcg_temp_new_i32();
1401 if (insn
& (1 << 8)) {
1402 if (insn
& (1 << 22)) { /* WSTRD */
1403 tcg_temp_free_i32(tmp
);
1404 tcg_gen_qemu_st64(cpu_M0
, addr
, IS_USER(s
));
1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1407 gen_st32(tmp
, addr
, IS_USER(s
));
1410 if (insn
& (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1412 gen_st16(tmp
, addr
, IS_USER(s
));
1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1415 gen_st8(tmp
, addr
, IS_USER(s
));
1420 tcg_temp_free_i32(addr
);
1424 if ((insn
& 0x0f000000) != 0x0e000000)
1427 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd
= (insn
>> 12) & 0xf;
1430 rd0
= (insn
>> 0) & 0xf;
1431 rd1
= (insn
>> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1439 case 0x011: /* TMCR */
1442 rd
= (insn
>> 12) & 0xf;
1443 wrd
= (insn
>> 16) & 0xf;
1445 case ARM_IWMMXT_wCID
:
1446 case ARM_IWMMXT_wCASF
:
1448 case ARM_IWMMXT_wCon
:
1449 gen_op_iwmmxt_set_cup();
1451 case ARM_IWMMXT_wCSSF
:
1452 tmp
= iwmmxt_load_creg(wrd
);
1453 tmp2
= load_reg(s
, rd
);
1454 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1455 tcg_temp_free_i32(tmp2
);
1456 iwmmxt_store_creg(wrd
, tmp
);
1458 case ARM_IWMMXT_wCGR0
:
1459 case ARM_IWMMXT_wCGR1
:
1460 case ARM_IWMMXT_wCGR2
:
1461 case ARM_IWMMXT_wCGR3
:
1462 gen_op_iwmmxt_set_cup();
1463 tmp
= load_reg(s
, rd
);
1464 iwmmxt_store_creg(wrd
, tmp
);
1470 case 0x100: /* WXOR */
1471 wrd
= (insn
>> 12) & 0xf;
1472 rd0
= (insn
>> 0) & 0xf;
1473 rd1
= (insn
>> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1481 case 0x111: /* TMRC */
1484 rd
= (insn
>> 12) & 0xf;
1485 wrd
= (insn
>> 16) & 0xf;
1486 tmp
= iwmmxt_load_creg(wrd
);
1487 store_reg(s
, rd
, tmp
);
1489 case 0x300: /* WANDN */
1490 wrd
= (insn
>> 12) & 0xf;
1491 rd0
= (insn
>> 0) & 0xf;
1492 rd1
= (insn
>> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1494 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1501 case 0x200: /* WAND */
1502 wrd
= (insn
>> 12) & 0xf;
1503 rd0
= (insn
>> 0) & 0xf;
1504 rd1
= (insn
>> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd
= (insn
>> 12) & 0xf;
1514 rd0
= (insn
>> 0) & 0xf;
1515 rd1
= (insn
>> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1517 if (insn
& (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1522 gen_op_iwmmxt_set_mup();
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd
= (insn
>> 12) & 0xf;
1526 rd0
= (insn
>> 16) & 0xf;
1527 rd1
= (insn
>> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1529 switch ((insn
>> 22) & 3) {
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1542 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd
= (insn
>> 12) & 0xf;
1548 rd0
= (insn
>> 16) & 0xf;
1549 rd1
= (insn
>> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1551 switch ((insn
>> 22) & 3) {
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1564 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd
= (insn
>> 12) & 0xf;
1570 rd0
= (insn
>> 16) & 0xf;
1571 rd1
= (insn
>> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1573 if (insn
& (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1577 if (!(insn
& (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1580 gen_op_iwmmxt_set_mup();
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd
= (insn
>> 12) & 0xf;
1584 rd0
= (insn
>> 16) & 0xf;
1585 rd1
= (insn
>> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1587 if (insn
& (1 << 21)) {
1588 if (insn
& (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1593 if (insn
& (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1598 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1599 gen_op_iwmmxt_set_mup();
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd
= (insn
>> 12) & 0xf;
1603 rd0
= (insn
>> 16) & 0xf;
1604 rd1
= (insn
>> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1606 if (insn
& (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1610 if (!(insn
& (1 << 20))) {
1611 iwmmxt_load_reg(cpu_V1
, wrd
);
1612 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1614 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1615 gen_op_iwmmxt_set_mup();
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd
= (insn
>> 12) & 0xf;
1619 rd0
= (insn
>> 16) & 0xf;
1620 rd1
= (insn
>> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1622 switch ((insn
>> 22) & 3) {
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1635 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd
= (insn
>> 12) & 0xf;
1641 rd0
= (insn
>> 16) & 0xf;
1642 rd1
= (insn
>> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1644 if (insn
& (1 << 22)) {
1645 if (insn
& (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1650 if (insn
& (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1655 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd
= (insn
>> 12) & 0xf;
1661 rd0
= (insn
>> 16) & 0xf;
1662 rd1
= (insn
>> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1664 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1665 tcg_gen_andi_i32(tmp
, tmp
, 7);
1666 iwmmxt_load_reg(cpu_V1
, rd1
);
1667 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1668 tcg_temp_free_i32(tmp
);
1669 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1670 gen_op_iwmmxt_set_mup();
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1673 if (((insn
>> 6) & 3) == 3)
1675 rd
= (insn
>> 12) & 0xf;
1676 wrd
= (insn
>> 16) & 0xf;
1677 tmp
= load_reg(s
, rd
);
1678 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1679 switch ((insn
>> 6) & 3) {
1681 tmp2
= tcg_const_i32(0xff);
1682 tmp3
= tcg_const_i32((insn
& 7) << 3);
1685 tmp2
= tcg_const_i32(0xffff);
1686 tmp3
= tcg_const_i32((insn
& 3) << 4);
1689 tmp2
= tcg_const_i32(0xffffffff);
1690 tmp3
= tcg_const_i32((insn
& 1) << 5);
1696 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1697 tcg_temp_free(tmp3
);
1698 tcg_temp_free(tmp2
);
1699 tcg_temp_free_i32(tmp
);
1700 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1701 gen_op_iwmmxt_set_mup();
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd
= (insn
>> 12) & 0xf;
1705 wrd
= (insn
>> 16) & 0xf;
1706 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1708 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1709 tmp
= tcg_temp_new_i32();
1710 switch ((insn
>> 22) & 3) {
1712 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1715 tcg_gen_ext8s_i32(tmp
, tmp
);
1717 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1721 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1724 tcg_gen_ext16s_i32(tmp
, tmp
);
1726 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1730 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1734 store_reg(s
, rd
, tmp
);
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1737 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1739 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1740 switch ((insn
>> 22) & 3) {
1742 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1745 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1748 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1751 tcg_gen_shli_i32(tmp
, tmp
, 28);
1753 tcg_temp_free_i32(tmp
);
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1756 if (((insn
>> 6) & 3) == 3)
1758 rd
= (insn
>> 12) & 0xf;
1759 wrd
= (insn
>> 16) & 0xf;
1760 tmp
= load_reg(s
, rd
);
1761 switch ((insn
>> 6) & 3) {
1763 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1766 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1769 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1772 tcg_temp_free_i32(tmp
);
1773 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1774 gen_op_iwmmxt_set_mup();
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1777 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1779 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1780 tmp2
= tcg_temp_new_i32();
1781 tcg_gen_mov_i32(tmp2
, tmp
);
1782 switch ((insn
>> 22) & 3) {
1784 for (i
= 0; i
< 7; i
++) {
1785 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1786 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1790 for (i
= 0; i
< 3; i
++) {
1791 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1792 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1796 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1797 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1801 tcg_temp_free_i32(tmp2
);
1802 tcg_temp_free_i32(tmp
);
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd
= (insn
>> 12) & 0xf;
1806 rd0
= (insn
>> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1808 switch ((insn
>> 22) & 3) {
1810 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
1813 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
1816 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
1821 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1822 gen_op_iwmmxt_set_mup();
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1825 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1827 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1828 tmp2
= tcg_temp_new_i32();
1829 tcg_gen_mov_i32(tmp2
, tmp
);
1830 switch ((insn
>> 22) & 3) {
1832 for (i
= 0; i
< 7; i
++) {
1833 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1834 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1838 for (i
= 0; i
< 3; i
++) {
1839 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1840 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1844 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1845 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1849 tcg_temp_free_i32(tmp2
);
1850 tcg_temp_free_i32(tmp
);
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd
= (insn
>> 12) & 0xf;
1854 rd0
= (insn
>> 16) & 0xf;
1855 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
1857 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1858 tmp
= tcg_temp_new_i32();
1859 switch ((insn
>> 22) & 3) {
1861 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
1864 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
1867 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
1870 store_reg(s
, rd
, tmp
);
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd
= (insn
>> 12) & 0xf;
1875 rd0
= (insn
>> 16) & 0xf;
1876 rd1
= (insn
>> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1878 switch ((insn
>> 22) & 3) {
1880 if (insn
& (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
1886 if (insn
& (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
1892 if (insn
& (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
1900 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd
= (insn
>> 12) & 0xf;
1907 rd0
= (insn
>> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1909 switch ((insn
>> 22) & 3) {
1911 if (insn
& (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1914 gen_op_iwmmxt_unpacklub_M0();
1917 if (insn
& (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1920 gen_op_iwmmxt_unpackluw_M0();
1923 if (insn
& (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1926 gen_op_iwmmxt_unpacklul_M0();
1931 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd
= (insn
>> 12) & 0xf;
1938 rd0
= (insn
>> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1940 switch ((insn
>> 22) & 3) {
1942 if (insn
& (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1945 gen_op_iwmmxt_unpackhub_M0();
1948 if (insn
& (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1951 gen_op_iwmmxt_unpackhuw_M0();
1954 if (insn
& (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1957 gen_op_iwmmxt_unpackhul_M0();
1962 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
1968 if (((insn
>> 22) & 3) == 0)
1970 wrd
= (insn
>> 12) & 0xf;
1971 rd0
= (insn
>> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1973 tmp
= tcg_temp_new_i32();
1974 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
1975 tcg_temp_free_i32(tmp
);
1978 switch ((insn
>> 22) & 3) {
1980 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_M0
, tmp
);
1983 gen_helper_iwmmxt_srll(cpu_M0
, cpu_M0
, tmp
);
1986 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_M0
, tmp
);
1989 tcg_temp_free_i32(tmp
);
1990 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
1996 if (((insn
>> 22) & 3) == 0)
1998 wrd
= (insn
>> 12) & 0xf;
1999 rd0
= (insn
>> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2001 tmp
= tcg_temp_new_i32();
2002 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2003 tcg_temp_free_i32(tmp
);
2006 switch ((insn
>> 22) & 3) {
2008 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_M0
, tmp
);
2011 gen_helper_iwmmxt_sral(cpu_M0
, cpu_M0
, tmp
);
2014 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_M0
, tmp
);
2017 tcg_temp_free_i32(tmp
);
2018 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
2024 if (((insn
>> 22) & 3) == 0)
2026 wrd
= (insn
>> 12) & 0xf;
2027 rd0
= (insn
>> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2029 tmp
= tcg_temp_new_i32();
2030 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2031 tcg_temp_free_i32(tmp
);
2034 switch ((insn
>> 22) & 3) {
2036 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_M0
, tmp
);
2039 gen_helper_iwmmxt_slll(cpu_M0
, cpu_M0
, tmp
);
2042 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_M0
, tmp
);
2045 tcg_temp_free_i32(tmp
);
2046 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
2052 if (((insn
>> 22) & 3) == 0)
2054 wrd
= (insn
>> 12) & 0xf;
2055 rd0
= (insn
>> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2057 tmp
= tcg_temp_new_i32();
2058 switch ((insn
>> 22) & 3) {
2060 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2061 tcg_temp_free_i32(tmp
);
2064 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_M0
, tmp
);
2067 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2068 tcg_temp_free_i32(tmp
);
2071 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_M0
, tmp
);
2074 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2075 tcg_temp_free_i32(tmp
);
2078 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_M0
, tmp
);
2081 tcg_temp_free_i32(tmp
);
2082 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd
= (insn
>> 12) & 0xf;
2089 rd0
= (insn
>> 16) & 0xf;
2090 rd1
= (insn
>> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2092 switch ((insn
>> 22) & 3) {
2094 if (insn
& (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2097 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2100 if (insn
& (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2106 if (insn
& (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2109 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2114 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2115 gen_op_iwmmxt_set_mup();
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd
= (insn
>> 12) & 0xf;
2120 rd0
= (insn
>> 16) & 0xf;
2121 rd1
= (insn
>> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2123 switch ((insn
>> 22) & 3) {
2125 if (insn
& (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2131 if (insn
& (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2137 if (insn
& (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2145 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2146 gen_op_iwmmxt_set_mup();
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd
= (insn
>> 12) & 0xf;
2151 rd0
= (insn
>> 16) & 0xf;
2152 rd1
= (insn
>> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2154 tmp
= tcg_const_i32((insn
>> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1
, rd1
);
2156 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2158 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2159 gen_op_iwmmxt_set_mup();
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd
= (insn
>> 12) & 0xf;
2166 rd0
= (insn
>> 16) & 0xf;
2167 rd1
= (insn
>> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2169 switch ((insn
>> 20) & 0xf) {
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2174 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2192 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2200 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd
= (insn
>> 12) & 0xf;
2209 rd0
= (insn
>> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2211 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2212 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_M0
, tmp
);
2214 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd
= (insn
>> 12) & 0xf;
2223 rd0
= (insn
>> 16) & 0xf;
2224 rd1
= (insn
>> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2226 switch ((insn
>> 20) & 0xf) {
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2231 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2249 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2257 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2265 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2267 wrd
= (insn
>> 12) & 0xf;
2268 rd0
= (insn
>> 16) & 0xf;
2269 rd1
= (insn
>> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2271 switch ((insn
>> 22) & 3) {
2273 if (insn
& (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2279 if (insn
& (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2282 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2285 if (insn
& (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2291 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd
= (insn
>> 5) & 0xf;
2300 rd0
= (insn
>> 12) & 0xf;
2301 rd1
= (insn
>> 0) & 0xf;
2302 if (rd0
== 0xf || rd1
== 0xf)
2304 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2305 tmp
= load_reg(s
, rd0
);
2306 tmp2
= load_reg(s
, rd1
);
2307 switch ((insn
>> 16) & 0xf) {
2308 case 0x0: /* TMIA */
2309 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2311 case 0x8: /* TMIAPH */
2312 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2315 if (insn
& (1 << 16))
2316 tcg_gen_shri_i32(tmp
, tmp
, 16);
2317 if (insn
& (1 << 17))
2318 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2322 tcg_temp_free_i32(tmp2
);
2323 tcg_temp_free_i32(tmp
);
2326 tcg_temp_free_i32(tmp2
);
2327 tcg_temp_free_i32(tmp
);
2328 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2329 gen_op_iwmmxt_set_mup();
2338 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340 static int disas_dsp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2342 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2345 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0
= (insn
>> 12) & 0xf;
2349 acc
= (insn
>> 5) & 7;
2354 tmp
= load_reg(s
, rd0
);
2355 tmp2
= load_reg(s
, rd1
);
2356 switch ((insn
>> 16) & 0xf) {
2358 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2360 case 0x8: /* MIAPH */
2361 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
2367 if (insn
& (1 << 16))
2368 tcg_gen_shri_i32(tmp
, tmp
, 16);
2369 if (insn
& (1 << 17))
2370 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2376 tcg_temp_free_i32(tmp2
);
2377 tcg_temp_free_i32(tmp
);
2379 gen_op_iwmmxt_movq_wRn_M0(acc
);
2383 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi
= (insn
>> 16) & 0xf;
2386 rdlo
= (insn
>> 12) & 0xf;
2392 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2393 iwmmxt_load_reg(cpu_V0
, acc
);
2394 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2395 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2397 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2399 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2400 iwmmxt_store_reg(cpu_V0
, acc
);
2408 /* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410 static int disas_cp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2413 uint32_t rd
= (insn
>> 12) & 0xf;
2414 uint32_t cp
= (insn
>> 8) & 0xf;
2419 if (insn
& ARM_CP_RW_BIT
) {
2420 if (!env
->cp
[cp
].cp_read
)
2422 gen_set_pc_im(s
->pc
);
2423 tmp
= tcg_temp_new_i32();
2424 tmp2
= tcg_const_i32(insn
);
2425 gen_helper_get_cp(tmp
, cpu_env
, tmp2
);
2426 tcg_temp_free(tmp2
);
2427 store_reg(s
, rd
, tmp
);
2429 if (!env
->cp
[cp
].cp_write
)
2431 gen_set_pc_im(s
->pc
);
2432 tmp
= load_reg(s
, rd
);
2433 tmp2
= tcg_const_i32(insn
);
2434 gen_helper_set_cp(cpu_env
, tmp2
, tmp
);
2435 tcg_temp_free(tmp2
);
2436 tcg_temp_free_i32(tmp
);
2441 static int cp15_user_ok(uint32_t insn
)
2443 int cpn
= (insn
>> 16) & 0xf;
2444 int cpm
= insn
& 0xf;
2445 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2447 if (cpn
== 13 && cpm
== 0) {
2449 if (op
== 2 || (op
== 3 && (insn
& ARM_CP_RW_BIT
)))
2453 /* ISB, DSB, DMB. */
2454 if ((cpm
== 5 && op
== 4)
2455 || (cpm
== 10 && (op
== 4 || op
== 5)))
2461 static int cp15_tls_load_store(CPUState
*env
, DisasContext
*s
, uint32_t insn
, uint32_t rd
)
2464 int cpn
= (insn
>> 16) & 0xf;
2465 int cpm
= insn
& 0xf;
2466 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2468 if (!arm_feature(env
, ARM_FEATURE_V6K
))
2471 if (!(cpn
== 13 && cpm
== 0))
2474 if (insn
& ARM_CP_RW_BIT
) {
2477 tmp
= load_cpu_field(cp15
.c13_tls1
);
2480 tmp
= load_cpu_field(cp15
.c13_tls2
);
2483 tmp
= load_cpu_field(cp15
.c13_tls3
);
2488 store_reg(s
, rd
, tmp
);
2491 tmp
= load_reg(s
, rd
);
2494 store_cpu_field(tmp
, cp15
.c13_tls1
);
2497 store_cpu_field(tmp
, cp15
.c13_tls2
);
2500 store_cpu_field(tmp
, cp15
.c13_tls3
);
2503 tcg_temp_free_i32(tmp
);
2510 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
2512 static int disas_cp15_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env
, ARM_FEATURE_M
))
2521 if ((insn
& (1 << 25)) == 0) {
2522 if (insn
& (1 << 20)) {
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2529 if ((insn
& (1 << 4)) == 0) {
2533 if (IS_USER(s
) && !cp15_user_ok(insn
)) {
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2540 if ((insn
& 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2544 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s
->pc
);
2547 s
->is_jmp
= DISAS_WFI
;
2552 if ((insn
& 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2556 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s
->pc
);
2559 s
->is_jmp
= DISAS_WFI
;
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2568 rd
= (insn
>> 12) & 0xf;
2570 if (cp15_tls_load_store(env
, s
, insn
, rd
))
2573 tmp2
= tcg_const_i32(insn
);
2574 if (insn
& ARM_CP_RW_BIT
) {
2575 tmp
= tcg_temp_new_i32();
2576 gen_helper_get_cp15(tmp
, cpu_env
, tmp2
);
2577 /* If the destination register is r15 then sets condition codes. */
2579 store_reg(s
, rd
, tmp
);
2581 tcg_temp_free_i32(tmp
);
2583 tmp
= load_reg(s
, rd
);
2584 gen_helper_set_cp15(cpu_env
, tmp2
, tmp
);
2585 tcg_temp_free_i32(tmp
);
2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) ||
2590 (insn
& 0x0fff0fff) != 0x0e010f10)
2593 tcg_temp_free_i32(tmp2
);
2597 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598 #define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2605 if (insn & (1 << (smallbit))) \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2610 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2617 /* Move between integer and VFP cores. */
2618 static TCGv
gen_vfp_mrs(void)
2620 TCGv tmp
= tcg_temp_new_i32();
2621 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2625 static void gen_vfp_msr(TCGv tmp
)
2627 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2628 tcg_temp_free_i32(tmp
);
2631 static void gen_neon_dup_u8(TCGv var
, int shift
)
2633 TCGv tmp
= tcg_temp_new_i32();
2635 tcg_gen_shri_i32(var
, var
, shift
);
2636 tcg_gen_ext8u_i32(var
, var
);
2637 tcg_gen_shli_i32(tmp
, var
, 8);
2638 tcg_gen_or_i32(var
, var
, tmp
);
2639 tcg_gen_shli_i32(tmp
, var
, 16);
2640 tcg_gen_or_i32(var
, var
, tmp
);
2641 tcg_temp_free_i32(tmp
);
2644 static void gen_neon_dup_low16(TCGv var
)
2646 TCGv tmp
= tcg_temp_new_i32();
2647 tcg_gen_ext16u_i32(var
, var
);
2648 tcg_gen_shli_i32(tmp
, var
, 16);
2649 tcg_gen_or_i32(var
, var
, tmp
);
2650 tcg_temp_free_i32(tmp
);
2653 static void gen_neon_dup_high16(TCGv var
)
2655 TCGv tmp
= tcg_temp_new_i32();
2656 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2657 tcg_gen_shri_i32(tmp
, var
, 16);
2658 tcg_gen_or_i32(var
, var
, tmp
);
2659 tcg_temp_free_i32(tmp
);
2662 static TCGv
gen_load_and_replicate(DisasContext
*s
, TCGv addr
, int size
)
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2668 tmp
= gen_ld8u(addr
, IS_USER(s
));
2669 gen_neon_dup_u8(tmp
, 0);
2672 tmp
= gen_ld16u(addr
, IS_USER(s
));
2673 gen_neon_dup_low16(tmp
);
2676 tmp
= gen_ld32(addr
, IS_USER(s
));
2678 default: /* Avoid compiler warnings. */
2684 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686 static int disas_vfp_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
2688 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
2694 if (!arm_feature(env
, ARM_FEATURE_VFP
))
2697 if (!s
->vfp_enabled
) {
2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2699 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
2701 rn
= (insn
>> 16) & 0xf;
2702 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
2703 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
)
2706 dp
= ((insn
& 0xf00) == 0xb00);
2707 switch ((insn
>> 24) & 0xf) {
2709 if (insn
& (1 << 4)) {
2710 /* single register transfer */
2711 rd
= (insn
>> 12) & 0xf;
2716 VFP_DREG_N(rn
, insn
);
2719 if (insn
& 0x00c00060
2720 && !arm_feature(env
, ARM_FEATURE_NEON
))
2723 pass
= (insn
>> 21) & 1;
2724 if (insn
& (1 << 22)) {
2726 offset
= ((insn
>> 5) & 3) * 8;
2727 } else if (insn
& (1 << 5)) {
2729 offset
= (insn
& (1 << 6)) ? 16 : 0;
2734 if (insn
& ARM_CP_RW_BIT
) {
2736 tmp
= neon_load_reg(rn
, pass
);
2740 tcg_gen_shri_i32(tmp
, tmp
, offset
);
2741 if (insn
& (1 << 23))
2747 if (insn
& (1 << 23)) {
2749 tcg_gen_shri_i32(tmp
, tmp
, 16);
2755 tcg_gen_sari_i32(tmp
, tmp
, 16);
2764 store_reg(s
, rd
, tmp
);
2767 tmp
= load_reg(s
, rd
);
2768 if (insn
& (1 << 23)) {
2771 gen_neon_dup_u8(tmp
, 0);
2772 } else if (size
== 1) {
2773 gen_neon_dup_low16(tmp
);
2775 for (n
= 0; n
<= pass
* 2; n
++) {
2776 tmp2
= tcg_temp_new_i32();
2777 tcg_gen_mov_i32(tmp2
, tmp
);
2778 neon_store_reg(rn
, n
, tmp2
);
2780 neon_store_reg(rn
, n
, tmp
);
2785 tmp2
= neon_load_reg(rn
, pass
);
2786 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xff);
2787 tcg_temp_free_i32(tmp2
);
2790 tmp2
= neon_load_reg(rn
, pass
);
2791 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xffff);
2792 tcg_temp_free_i32(tmp2
);
2797 neon_store_reg(rn
, pass
, tmp
);
2801 if ((insn
& 0x6f) != 0x00)
2803 rn
= VFP_SREG_N(insn
);
2804 if (insn
& ARM_CP_RW_BIT
) {
2806 if (insn
& (1 << 21)) {
2807 /* system register */
2812 /* VFP2 allows access to FSID from userspace.
2813 VFP3 restricts all id registers to privileged
2816 && arm_feature(env
, ARM_FEATURE_VFP3
))
2818 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2823 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2825 case ARM_VFP_FPINST
:
2826 case ARM_VFP_FPINST2
:
2827 /* Not present in VFP3. */
2829 || arm_feature(env
, ARM_FEATURE_VFP3
))
2831 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2835 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
2836 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
2838 tmp
= tcg_temp_new_i32();
2839 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
2845 || !arm_feature(env
, ARM_FEATURE_VFP3
))
2847 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2853 gen_mov_F0_vreg(0, rn
);
2854 tmp
= gen_vfp_mrs();
2857 /* Set the 4 flag bits in the CPSR. */
2859 tcg_temp_free_i32(tmp
);
2861 store_reg(s
, rd
, tmp
);
2865 tmp
= load_reg(s
, rd
);
2866 if (insn
& (1 << 21)) {
2868 /* system register */
2873 /* Writes are ignored. */
2876 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
2877 tcg_temp_free_i32(tmp
);
2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
2886 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2889 case ARM_VFP_FPINST
:
2890 case ARM_VFP_FPINST2
:
2891 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2898 gen_mov_vreg_F0(0, rn
);
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
2909 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
2911 /* rn is register number */
2912 VFP_DREG_N(rn
, insn
);
2915 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18))) {
2916 /* Integer or single precision destination. */
2917 rd
= VFP_SREG_D(insn
);
2919 VFP_DREG_D(rd
, insn
);
2922 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2926 rm
= VFP_SREG_M(insn
);
2928 VFP_DREG_M(rm
, insn
);
2931 rn
= VFP_SREG_N(insn
);
2932 if (op
== 15 && rn
== 15) {
2933 /* Double precision destination. */
2934 VFP_DREG_D(rd
, insn
);
2936 rd
= VFP_SREG_D(insn
);
2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2941 rm
= VFP_SREG_M(insn
);
2944 veclen
= s
->vec_len
;
2945 if (op
== 15 && rn
> 3)
2948 /* Shut up compiler warnings. */
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd
& bank_mask
) == 0) {
2965 delta_d
= (s
->vec_stride
>> 1) + 1;
2967 delta_d
= s
->vec_stride
+ 1;
2969 if ((rm
& bank_mask
) == 0) {
2970 /* mixed scalar/vector */
2979 /* Load the initial operands. */
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm
);
2990 gen_mov_F0_vreg(dp
, rd
);
2991 gen_mov_F1_vreg(dp
, rm
);
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp
, rd
);
3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp
, rd
);
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp
, rm
);
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp
, rn
);
3018 gen_mov_F1_vreg(dp
, rm
);
3022 /* Perform the calculation. */
3024 case 0: /* mac: fd + (fn * fm) */
3026 gen_mov_F1_vreg(dp
, rd
);
3029 case 1: /* nmac: fd - (fn * fm) */
3032 gen_mov_F1_vreg(dp
, rd
);
3035 case 2: /* msc: -fd + (fn * fm) */
3037 gen_mov_F1_vreg(dp
, rd
);
3040 case 3: /* nmsc: -fd - (fn * fm) */
3043 gen_mov_F1_vreg(dp
, rd
);
3046 case 4: /* mul: fn * fm */
3049 case 5: /* nmul: -(fn * fm) */
3053 case 6: /* add: fn + fm */
3056 case 7: /* sub: fn - fm */
3059 case 8: /* div: fn / fm */
3062 case 14: /* fconst */
3063 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3066 n
= (insn
<< 12) & 0x80000000;
3067 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3074 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3081 tcg_gen_movi_i32(cpu_F0s
, n
);
3084 case 15: /* extension space */
3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3101 tmp
= gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp
, tmp
);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3104 tcg_temp_free_i32(tmp
);
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3109 tmp
= gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp
, tmp
, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3112 tcg_temp_free_i32(tmp
);
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3117 tmp
= tcg_temp_new_i32();
3118 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3119 gen_mov_F0_vreg(0, rd
);
3120 tmp2
= gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3122 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3123 tcg_temp_free_i32(tmp2
);
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3129 tmp
= tcg_temp_new_i32();
3130 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3131 tcg_gen_shli_i32(tmp
, tmp
, 16);
3132 gen_mov_F0_vreg(0, rd
);
3133 tmp2
= gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3135 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3136 tcg_temp_free_i32(tmp2
);
3148 case 11: /* cmpez */
3152 case 15: /* single<->double conversion */
3154 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3156 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3158 case 16: /* fuito */
3161 case 17: /* fsito */
3164 case 20: /* fshto */
3165 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3167 gen_vfp_shto(dp
, 16 - rm
);
3169 case 21: /* fslto */
3170 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3172 gen_vfp_slto(dp
, 32 - rm
);
3174 case 22: /* fuhto */
3175 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3177 gen_vfp_uhto(dp
, 16 - rm
);
3179 case 23: /* fulto */
3180 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3182 gen_vfp_ulto(dp
, 32 - rm
);
3184 case 24: /* ftoui */
3187 case 25: /* ftouiz */
3190 case 26: /* ftosi */
3193 case 27: /* ftosiz */
3196 case 28: /* ftosh */
3197 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3199 gen_vfp_tosh(dp
, 16 - rm
);
3201 case 29: /* ftosl */
3202 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3204 gen_vfp_tosl(dp
, 32 - rm
);
3206 case 30: /* ftouh */
3207 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3209 gen_vfp_touh(dp
, 16 - rm
);
3211 case 31: /* ftoul */
3212 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3214 gen_vfp_toul(dp
, 32 - rm
);
3216 default: /* undefined */
3217 printf ("rn:%d\n", rn
);
3221 default: /* undefined */
3222 printf ("op:%d\n", op
);
3226 /* Write back the result. */
3227 if (op
== 15 && (rn
>= 8 && rn
<= 11))
3228 ; /* Comparison, do nothing. */
3229 else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
3231 gen_mov_vreg_F0(0, rd
);
3232 else if (op
== 15 && rn
== 15)
3234 gen_mov_vreg_F0(!dp
, rd
);
3236 gen_mov_vreg_F0(dp
, rd
);
3238 /* break out of the loop if we have finished */
3242 if (op
== 15 && delta_m
== 0) {
3243 /* single source one-many */
3245 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3247 gen_mov_vreg_F0(dp
, rd
);
3251 /* Setup the next operands. */
3253 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3257 /* One source operand. */
3258 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3260 gen_mov_F0_vreg(dp
, rm
);
3262 /* Two source operands. */
3263 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3265 gen_mov_F0_vreg(dp
, rn
);
3267 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3269 gen_mov_F1_vreg(dp
, rm
);
3277 if ((insn
& 0x03e00000) == 0x00400000) {
3278 /* two-register transfer */
3279 rn
= (insn
>> 16) & 0xf;
3280 rd
= (insn
>> 12) & 0xf;
3282 VFP_DREG_M(rm
, insn
);
3284 rm
= VFP_SREG_M(insn
);
3287 if (insn
& ARM_CP_RW_BIT
) {
3290 gen_mov_F0_vreg(0, rm
* 2);
3291 tmp
= gen_vfp_mrs();
3292 store_reg(s
, rd
, tmp
);
3293 gen_mov_F0_vreg(0, rm
* 2 + 1);
3294 tmp
= gen_vfp_mrs();
3295 store_reg(s
, rn
, tmp
);
3297 gen_mov_F0_vreg(0, rm
);
3298 tmp
= gen_vfp_mrs();
3299 store_reg(s
, rd
, tmp
);
3300 gen_mov_F0_vreg(0, rm
+ 1);
3301 tmp
= gen_vfp_mrs();
3302 store_reg(s
, rn
, tmp
);
3307 tmp
= load_reg(s
, rd
);
3309 gen_mov_vreg_F0(0, rm
* 2);
3310 tmp
= load_reg(s
, rn
);
3312 gen_mov_vreg_F0(0, rm
* 2 + 1);
3314 tmp
= load_reg(s
, rd
);
3316 gen_mov_vreg_F0(0, rm
);
3317 tmp
= load_reg(s
, rn
);
3319 gen_mov_vreg_F0(0, rm
+ 1);
3324 rn
= (insn
>> 16) & 0xf;
3326 VFP_DREG_D(rd
, insn
);
3328 rd
= VFP_SREG_D(insn
);
3329 if (s
->thumb
&& rn
== 15) {
3330 addr
= tcg_temp_new_i32();
3331 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3333 addr
= load_reg(s
, rn
);
3335 if ((insn
& 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset
= (insn
& 0xff) << 2;
3338 if ((insn
& (1 << 23)) == 0)
3340 tcg_gen_addi_i32(addr
, addr
, offset
);
3341 if (insn
& (1 << 20)) {
3342 gen_vfp_ld(s
, dp
, addr
);
3343 gen_mov_vreg_F0(dp
, rd
);
3345 gen_mov_F0_vreg(dp
, rd
);
3346 gen_vfp_st(s
, dp
, addr
);
3348 tcg_temp_free_i32(addr
);
3350 /* load/store multiple */
3352 n
= (insn
>> 1) & 0x7f;
3356 if (insn
& (1 << 24)) /* pre-decrement */
3357 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
3363 for (i
= 0; i
< n
; i
++) {
3364 if (insn
& ARM_CP_RW_BIT
) {
3366 gen_vfp_ld(s
, dp
, addr
);
3367 gen_mov_vreg_F0(dp
, rd
+ i
);
3370 gen_mov_F0_vreg(dp
, rd
+ i
);
3371 gen_vfp_st(s
, dp
, addr
);
3373 tcg_gen_addi_i32(addr
, addr
, offset
);
3375 if (insn
& (1 << 21)) {
3377 if (insn
& (1 << 24))
3378 offset
= -offset
* n
;
3379 else if (dp
&& (insn
& 1))
3385 tcg_gen_addi_i32(addr
, addr
, offset
);
3386 store_reg(s
, rn
, addr
);
3388 tcg_temp_free_i32(addr
);
3394 /* Should never happen. */
3400 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
3402 TranslationBlock
*tb
;
3405 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3407 gen_set_pc_im(dest
);
3408 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3410 gen_set_pc_im(dest
);
3415 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
3417 if (unlikely(s
->singlestep_enabled
)) {
3418 /* An indirect jump so that we still trigger the debug exception. */
3423 gen_goto_tb(s
, 0, dest
);
3424 s
->is_jmp
= DISAS_TB_JUMP
;
3428 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
3431 tcg_gen_sari_i32(t0
, t0
, 16);
3435 tcg_gen_sari_i32(t1
, t1
, 16);
3438 tcg_gen_mul_i32(t0
, t0
, t1
);
3441 /* Return the mask of PSR bits set by a MSR instruction. */
3442 static uint32_t msr_mask(CPUState
*env
, DisasContext
*s
, int flags
, int spsr
) {
3446 if (flags
& (1 << 0))
3448 if (flags
& (1 << 1))
3450 if (flags
& (1 << 2))
3452 if (flags
& (1 << 3))
3455 /* Mask out undefined bits. */
3456 mask
&= ~CPSR_RESERVED
;
3457 if (!arm_feature(env
, ARM_FEATURE_V4T
))
3459 if (!arm_feature(env
, ARM_FEATURE_V5
))
3460 mask
&= ~CPSR_Q
; /* V5TE in reality*/
3461 if (!arm_feature(env
, ARM_FEATURE_V6
))
3462 mask
&= ~(CPSR_E
| CPSR_GE
);
3463 if (!arm_feature(env
, ARM_FEATURE_THUMB2
))
3465 /* Mask out execution state bits. */
3468 /* Mask out privileged bits. */
3474 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv t0
)
3479 /* ??? This is also undefined in system mode. */
3483 tmp
= load_cpu_field(spsr
);
3484 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
3485 tcg_gen_andi_i32(t0
, t0
, mask
);
3486 tcg_gen_or_i32(tmp
, tmp
, t0
);
3487 store_cpu_field(tmp
, spsr
);
3489 gen_set_cpsr(t0
, mask
);
3491 tcg_temp_free_i32(t0
);
3496 /* Returns nonzero if access to the PSR is not permitted. */
3497 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3500 tmp
= tcg_temp_new_i32();
3501 tcg_gen_movi_i32(tmp
, val
);
3502 return gen_set_psr(s
, mask
, spsr
, tmp
);
3505 /* Generate an old-style exception return. Marks pc as dead. */
3506 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
3509 store_reg(s
, 15, pc
);
3510 tmp
= load_cpu_field(spsr
);
3511 gen_set_cpsr(tmp
, 0xffffffff);
3512 tcg_temp_free_i32(tmp
);
3513 s
->is_jmp
= DISAS_UPDATE
;
3516 /* Generate a v6 exception return. Marks both values as dead. */
3517 static void gen_rfe(DisasContext
*s
, TCGv pc
, TCGv cpsr
)
3519 gen_set_cpsr(cpsr
, 0xffffffff);
3520 tcg_temp_free_i32(cpsr
);
3521 store_reg(s
, 15, pc
);
3522 s
->is_jmp
= DISAS_UPDATE
;
3526 gen_set_condexec (DisasContext
*s
)
3528 if (s
->condexec_mask
) {
3529 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
3530 TCGv tmp
= tcg_temp_new_i32();
3531 tcg_gen_movi_i32(tmp
, val
);
3532 store_cpu_field(tmp
, condexec_bits
);
3536 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
3538 gen_set_condexec(s
);
3539 gen_set_pc_im(s
->pc
- offset
);
3540 gen_exception(excp
);
3541 s
->is_jmp
= DISAS_JUMP
;
3544 static void gen_nop_hint(DisasContext
*s
, int val
)
3548 gen_set_pc_im(s
->pc
);
3549 s
->is_jmp
= DISAS_WFI
;
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3559 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3561 static inline int gen_neon_add(int size
, TCGv t0
, TCGv t1
)
3564 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3565 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3566 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3572 static inline void gen_neon_rsb(int size
, TCGv t0
, TCGv t1
)
3575 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3576 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3577 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3582 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3583 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3584 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3585 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3586 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3588 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3589 switch ((size << 1) | u) { \
3591 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3594 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3597 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3600 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3603 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3606 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3608 default: return 1; \
3611 #define GEN_NEON_INTEGER_OP(name) do { \
3612 switch ((size << 1) | u) { \
3614 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3617 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3620 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3623 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3626 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3629 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3631 default: return 1; \
3634 static TCGv
neon_load_scratch(int scratch
)
3636 TCGv tmp
= tcg_temp_new_i32();
3637 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3641 static void neon_store_scratch(int scratch
, TCGv var
)
3643 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3644 tcg_temp_free_i32(var
);
3647 static inline TCGv
neon_get_scalar(int size
, int reg
)
3651 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3653 gen_neon_dup_high16(tmp
);
3655 gen_neon_dup_low16(tmp
);
3658 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3663 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3666 if (size
== 3 || (!q
&& size
== 2)) {
3669 tmp
= tcg_const_i32(rd
);
3670 tmp2
= tcg_const_i32(rm
);
3674 gen_helper_neon_qunzip8(tmp
, tmp2
);
3677 gen_helper_neon_qunzip16(tmp
, tmp2
);
3680 gen_helper_neon_qunzip32(tmp
, tmp2
);
3688 gen_helper_neon_unzip8(tmp
, tmp2
);
3691 gen_helper_neon_unzip16(tmp
, tmp2
);
3697 tcg_temp_free_i32(tmp
);
3698 tcg_temp_free_i32(tmp2
);
3702 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3705 if (size
== 3 || (!q
&& size
== 2)) {
3708 tmp
= tcg_const_i32(rd
);
3709 tmp2
= tcg_const_i32(rm
);
3713 gen_helper_neon_qzip8(tmp
, tmp2
);
3716 gen_helper_neon_qzip16(tmp
, tmp2
);
3719 gen_helper_neon_qzip32(tmp
, tmp2
);
3727 gen_helper_neon_zip8(tmp
, tmp2
);
3730 gen_helper_neon_zip16(tmp
, tmp2
);
3736 tcg_temp_free_i32(tmp
);
3737 tcg_temp_free_i32(tmp2
);
3741 static void gen_neon_trn_u8(TCGv t0
, TCGv t1
)
3745 rd
= tcg_temp_new_i32();
3746 tmp
= tcg_temp_new_i32();
3748 tcg_gen_shli_i32(rd
, t0
, 8);
3749 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3750 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3751 tcg_gen_or_i32(rd
, rd
, tmp
);
3753 tcg_gen_shri_i32(t1
, t1
, 8);
3754 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3755 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3756 tcg_gen_or_i32(t1
, t1
, tmp
);
3757 tcg_gen_mov_i32(t0
, rd
);
3759 tcg_temp_free_i32(tmp
);
3760 tcg_temp_free_i32(rd
);
3763 static void gen_neon_trn_u16(TCGv t0
, TCGv t1
)
3767 rd
= tcg_temp_new_i32();
3768 tmp
= tcg_temp_new_i32();
3770 tcg_gen_shli_i32(rd
, t0
, 16);
3771 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3772 tcg_gen_or_i32(rd
, rd
, tmp
);
3773 tcg_gen_shri_i32(t1
, t1
, 16);
3774 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3775 tcg_gen_or_i32(t1
, t1
, tmp
);
3776 tcg_gen_mov_i32(t0
, rd
);
3778 tcg_temp_free_i32(tmp
);
3779 tcg_temp_free_i32(rd
);
3787 } neon_ls_element_type
[11] = {
3801 /* Translate a NEON load/store element instruction. Return nonzero if the
3802 instruction is invalid. */
3803 static int disas_neon_ls_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
3822 if (!s
->vfp_enabled
)
3824 VFP_DREG_D(rd
, insn
);
3825 rn
= (insn
>> 16) & 0xf;
3827 load
= (insn
& (1 << 21)) != 0;
3828 if ((insn
& (1 << 23)) == 0) {
3829 /* Load store all elements. */
3830 op
= (insn
>> 8) & 0xf;
3831 size
= (insn
>> 6) & 3;
3834 nregs
= neon_ls_element_type
[op
].nregs
;
3835 interleave
= neon_ls_element_type
[op
].interleave
;
3836 spacing
= neon_ls_element_type
[op
].spacing
;
3837 if (size
== 3 && (interleave
| spacing
) != 1)
3839 addr
= tcg_temp_new_i32();
3840 load_reg_var(s
, addr
, rn
);
3841 stride
= (1 << size
) * interleave
;
3842 for (reg
= 0; reg
< nregs
; reg
++) {
3843 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
3844 load_reg_var(s
, addr
, rn
);
3845 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
3846 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
3847 load_reg_var(s
, addr
, rn
);
3848 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3852 tmp64
= gen_ld64(addr
, IS_USER(s
));
3853 neon_store_reg64(tmp64
, rd
);
3854 tcg_temp_free_i64(tmp64
);
3856 tmp64
= tcg_temp_new_i64();
3857 neon_load_reg64(tmp64
, rd
);
3858 gen_st64(tmp64
, addr
, IS_USER(s
));
3860 tcg_gen_addi_i32(addr
, addr
, stride
);
3862 for (pass
= 0; pass
< 2; pass
++) {
3865 tmp
= gen_ld32(addr
, IS_USER(s
));
3866 neon_store_reg(rd
, pass
, tmp
);
3868 tmp
= neon_load_reg(rd
, pass
);
3869 gen_st32(tmp
, addr
, IS_USER(s
));
3871 tcg_gen_addi_i32(addr
, addr
, stride
);
3872 } else if (size
== 1) {
3874 tmp
= gen_ld16u(addr
, IS_USER(s
));
3875 tcg_gen_addi_i32(addr
, addr
, stride
);
3876 tmp2
= gen_ld16u(addr
, IS_USER(s
));
3877 tcg_gen_addi_i32(addr
, addr
, stride
);
3878 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
3879 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3880 tcg_temp_free_i32(tmp2
);
3881 neon_store_reg(rd
, pass
, tmp
);
3883 tmp
= neon_load_reg(rd
, pass
);
3884 tmp2
= tcg_temp_new_i32();
3885 tcg_gen_shri_i32(tmp2
, tmp
, 16);
3886 gen_st16(tmp
, addr
, IS_USER(s
));
3887 tcg_gen_addi_i32(addr
, addr
, stride
);
3888 gen_st16(tmp2
, addr
, IS_USER(s
));
3889 tcg_gen_addi_i32(addr
, addr
, stride
);
3891 } else /* size == 0 */ {
3894 for (n
= 0; n
< 4; n
++) {
3895 tmp
= gen_ld8u(addr
, IS_USER(s
));
3896 tcg_gen_addi_i32(addr
, addr
, stride
);
3900 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
3901 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
3902 tcg_temp_free_i32(tmp
);
3905 neon_store_reg(rd
, pass
, tmp2
);
3907 tmp2
= neon_load_reg(rd
, pass
);
3908 for (n
= 0; n
< 4; n
++) {
3909 tmp
= tcg_temp_new_i32();
3911 tcg_gen_mov_i32(tmp
, tmp2
);
3913 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
3915 gen_st8(tmp
, addr
, IS_USER(s
));
3916 tcg_gen_addi_i32(addr
, addr
, stride
);
3918 tcg_temp_free_i32(tmp2
);
3925 tcg_temp_free_i32(addr
);
3928 size
= (insn
>> 10) & 3;
3930 /* Load single element to all lanes. */
3931 int a
= (insn
>> 4) & 1;
3935 size
= (insn
>> 6) & 3;
3936 nregs
= ((insn
>> 8) & 3) + 1;
3939 if (nregs
!= 4 || a
== 0) {
3942 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3945 if (nregs
== 1 && a
== 1 && size
== 0) {
3948 if (nregs
== 3 && a
== 1) {
3951 addr
= tcg_temp_new_i32();
3952 load_reg_var(s
, addr
, rn
);
3954 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3955 tmp
= gen_load_and_replicate(s
, addr
, size
);
3956 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
3957 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
3958 if (insn
& (1 << 5)) {
3959 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 0));
3960 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 1));
3962 tcg_temp_free_i32(tmp
);
3964 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3965 stride
= (insn
& (1 << 5)) ? 2 : 1;
3966 for (reg
= 0; reg
< nregs
; reg
++) {
3967 tmp
= gen_load_and_replicate(s
, addr
, size
);
3968 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
3969 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
3970 tcg_temp_free_i32(tmp
);
3971 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3975 tcg_temp_free_i32(addr
);
3976 stride
= (1 << size
) * nregs
;
3978 /* Single element. */
3979 pass
= (insn
>> 7) & 1;
3982 shift
= ((insn
>> 5) & 3) * 8;
3986 shift
= ((insn
>> 6) & 1) * 16;
3987 stride
= (insn
& (1 << 5)) ? 2 : 1;
3991 stride
= (insn
& (1 << 6)) ? 2 : 1;
3996 nregs
= ((insn
>> 8) & 3) + 1;
3997 addr
= tcg_temp_new_i32();
3998 load_reg_var(s
, addr
, rn
);
3999 for (reg
= 0; reg
< nregs
; reg
++) {
4003 tmp
= gen_ld8u(addr
, IS_USER(s
));
4006 tmp
= gen_ld16u(addr
, IS_USER(s
));
4009 tmp
= gen_ld32(addr
, IS_USER(s
));
4011 default: /* Avoid compiler warnings. */
4015 tmp2
= neon_load_reg(rd
, pass
);
4016 gen_bfi(tmp
, tmp2
, tmp
, shift
, size
? 0xffff : 0xff);
4017 tcg_temp_free_i32(tmp2
);
4019 neon_store_reg(rd
, pass
, tmp
);
4020 } else { /* Store */
4021 tmp
= neon_load_reg(rd
, pass
);
4023 tcg_gen_shri_i32(tmp
, tmp
, shift
);
4026 gen_st8(tmp
, addr
, IS_USER(s
));
4029 gen_st16(tmp
, addr
, IS_USER(s
));
4032 gen_st32(tmp
, addr
, IS_USER(s
));
4037 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4039 tcg_temp_free_i32(addr
);
4040 stride
= nregs
* (1 << size
);
4046 base
= load_reg(s
, rn
);
4048 tcg_gen_addi_i32(base
, base
, stride
);
4051 index
= load_reg(s
, rm
);
4052 tcg_gen_add_i32(base
, base
, index
);
4053 tcg_temp_free_i32(index
);
4055 store_reg(s
, rn
, base
);
4060 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4061 static void gen_neon_bsl(TCGv dest
, TCGv t
, TCGv f
, TCGv c
)
4063 tcg_gen_and_i32(t
, t
, c
);
4064 tcg_gen_andc_i32(f
, f
, c
);
4065 tcg_gen_or_i32(dest
, t
, f
);
4068 static inline void gen_neon_narrow(int size
, TCGv dest
, TCGv_i64 src
)
4071 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
4072 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
4073 case 2: tcg_gen_trunc_i64_i32(dest
, src
); break;
4078 static inline void gen_neon_narrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4081 case 0: gen_helper_neon_narrow_sat_s8(dest
, src
); break;
4082 case 1: gen_helper_neon_narrow_sat_s16(dest
, src
); break;
4083 case 2: gen_helper_neon_narrow_sat_s32(dest
, src
); break;
4088 static inline void gen_neon_narrow_satu(int size
, TCGv dest
, TCGv_i64 src
)
4091 case 0: gen_helper_neon_narrow_sat_u8(dest
, src
); break;
4092 case 1: gen_helper_neon_narrow_sat_u16(dest
, src
); break;
4093 case 2: gen_helper_neon_narrow_sat_u32(dest
, src
); break;
4098 static inline void gen_neon_unarrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4101 case 0: gen_helper_neon_unarrow_sat8(dest
, src
); break;
4102 case 1: gen_helper_neon_unarrow_sat16(dest
, src
); break;
4103 case 2: gen_helper_neon_unarrow_sat32(dest
, src
); break;
4108 static inline void gen_neon_shift_narrow(int size
, TCGv var
, TCGv shift
,
4114 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
4115 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
4120 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
4121 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
4128 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
4129 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
4134 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
4135 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
4142 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv src
, int size
, int u
)
4146 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
4147 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
4148 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
4153 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
4154 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
4155 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
4159 tcg_temp_free_i32(src
);
4162 static inline void gen_neon_addl(int size
)
4165 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
4166 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
4167 case 2: tcg_gen_add_i64(CPU_V001
); break;
4172 static inline void gen_neon_subl(int size
)
4175 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
4176 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
4177 case 2: tcg_gen_sub_i64(CPU_V001
); break;
4182 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
4185 case 0: gen_helper_neon_negl_u16(var
, var
); break;
4186 case 1: gen_helper_neon_negl_u32(var
, var
); break;
4187 case 2: gen_helper_neon_negl_u64(var
, var
); break;
4192 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
4195 case 1: gen_helper_neon_addl_saturate_s32(op0
, op0
, op1
); break;
4196 case 2: gen_helper_neon_addl_saturate_s64(op0
, op0
, op1
); break;
4201 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv a
, TCGv b
, int size
, int u
)
4205 switch ((size
<< 1) | u
) {
4206 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
4207 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
4208 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
4209 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
4211 tmp
= gen_muls_i64_i32(a
, b
);
4212 tcg_gen_mov_i64(dest
, tmp
);
4213 tcg_temp_free_i64(tmp
);
4216 tmp
= gen_mulu_i64_i32(a
, b
);
4217 tcg_gen_mov_i64(dest
, tmp
);
4218 tcg_temp_free_i64(tmp
);
4223 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4224 Don't forget to clean them now. */
4226 tcg_temp_free_i32(a
);
4227 tcg_temp_free_i32(b
);
4231 static void gen_neon_narrow_op(int op
, int u
, int size
, TCGv dest
, TCGv_i64 src
)
4235 gen_neon_unarrow_sats(size
, dest
, src
);
4237 gen_neon_narrow(size
, dest
, src
);
4241 gen_neon_narrow_satu(size
, dest
, src
);
4243 gen_neon_narrow_sats(size
, dest
, src
);
4248 /* Translate a NEON data processing instruction. Return nonzero if the
4249 instruction is invalid.
4250 We process data in a mixture of 32-bit and 64-bit chunks.
4251 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4253 static int disas_neon_data_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
4266 TCGv tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4269 if (!s
->vfp_enabled
)
4271 q
= (insn
& (1 << 6)) != 0;
4272 u
= (insn
>> 24) & 1;
4273 VFP_DREG_D(rd
, insn
);
4274 VFP_DREG_N(rn
, insn
);
4275 VFP_DREG_M(rm
, insn
);
4276 size
= (insn
>> 20) & 3;
4277 if ((insn
& (1 << 23)) == 0) {
4278 /* Three register same length. */
4279 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4280 if (size
== 3 && (op
== 1 || op
== 5 || op
== 8 || op
== 9
4281 || op
== 10 || op
== 11 || op
== 16)) {
4282 /* 64-bit element instructions. */
4283 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
4284 neon_load_reg64(cpu_V0
, rn
+ pass
);
4285 neon_load_reg64(cpu_V1
, rm
+ pass
);
4289 gen_helper_neon_qadd_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4291 gen_helper_neon_qadd_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4296 gen_helper_neon_qsub_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4298 gen_helper_neon_qsub_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4303 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4305 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4310 gen_helper_neon_qshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4312 gen_helper_neon_qshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4315 case 10: /* VRSHL */
4317 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4319 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4322 case 11: /* VQRSHL */
4324 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4326 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4331 tcg_gen_sub_i64(CPU_V001
);
4333 tcg_gen_add_i64(CPU_V001
);
4339 neon_store_reg64(cpu_V0
, rd
+ pass
);
4346 case 10: /* VRSHL */
4347 case 11: /* VQRSHL */
4350 /* Shift instruction operands are reversed. */
4357 case 20: /* VPMAX */
4358 case 21: /* VPMIN */
4359 case 23: /* VPADD */
4362 case 26: /* VPADD (float) */
4363 pairwise
= (u
&& size
< 2);
4365 case 30: /* VPMIN/VPMAX (float) */
4373 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4382 tmp
= neon_load_reg(rn
, n
);
4383 tmp2
= neon_load_reg(rn
, n
+ 1);
4385 tmp
= neon_load_reg(rm
, n
);
4386 tmp2
= neon_load_reg(rm
, n
+ 1);
4390 tmp
= neon_load_reg(rn
, pass
);
4391 tmp2
= neon_load_reg(rm
, pass
);
4395 GEN_NEON_INTEGER_OP(hadd
);
4398 GEN_NEON_INTEGER_OP(qadd
);
4400 case 2: /* VRHADD */
4401 GEN_NEON_INTEGER_OP(rhadd
);
4403 case 3: /* Logic ops. */
4404 switch ((u
<< 2) | size
) {
4406 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
4409 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
4412 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4415 tcg_gen_orc_i32(tmp
, tmp
, tmp2
);
4418 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
4421 tmp3
= neon_load_reg(rd
, pass
);
4422 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
4423 tcg_temp_free_i32(tmp3
);
4426 tmp3
= neon_load_reg(rd
, pass
);
4427 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
4428 tcg_temp_free_i32(tmp3
);
4431 tmp3
= neon_load_reg(rd
, pass
);
4432 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
4433 tcg_temp_free_i32(tmp3
);
4438 GEN_NEON_INTEGER_OP(hsub
);
4441 GEN_NEON_INTEGER_OP(qsub
);
4444 GEN_NEON_INTEGER_OP(cgt
);
4447 GEN_NEON_INTEGER_OP(cge
);
4450 GEN_NEON_INTEGER_OP(shl
);
4453 GEN_NEON_INTEGER_OP(qshl
);
4455 case 10: /* VRSHL */
4456 GEN_NEON_INTEGER_OP(rshl
);
4458 case 11: /* VQRSHL */
4459 GEN_NEON_INTEGER_OP(qrshl
);
4462 GEN_NEON_INTEGER_OP(max
);
4465 GEN_NEON_INTEGER_OP(min
);
4468 GEN_NEON_INTEGER_OP(abd
);
4471 GEN_NEON_INTEGER_OP(abd
);
4472 tcg_temp_free_i32(tmp2
);
4473 tmp2
= neon_load_reg(rd
, pass
);
4474 gen_neon_add(size
, tmp
, tmp2
);
4477 if (!u
) { /* VADD */
4478 if (gen_neon_add(size
, tmp
, tmp2
))
4482 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
4483 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
4484 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
4490 if (!u
) { /* VTST */
4492 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
4493 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
4494 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
4499 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
4500 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
4501 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
4506 case 18: /* Multiply. */
4508 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4509 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4510 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4513 tcg_temp_free_i32(tmp2
);
4514 tmp2
= neon_load_reg(rd
, pass
);
4516 gen_neon_rsb(size
, tmp
, tmp2
);
4518 gen_neon_add(size
, tmp
, tmp2
);
4522 if (u
) { /* polynomial */
4523 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
4524 } else { /* Integer */
4526 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4527 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4528 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4533 case 20: /* VPMAX */
4534 GEN_NEON_INTEGER_OP(pmax
);
4536 case 21: /* VPMIN */
4537 GEN_NEON_INTEGER_OP(pmin
);
4539 case 22: /* Hultiply high. */
4540 if (!u
) { /* VQDMULH */
4542 case 1: gen_helper_neon_qdmulh_s16(tmp
, tmp
, tmp2
); break;
4543 case 2: gen_helper_neon_qdmulh_s32(tmp
, tmp
, tmp2
); break;
4546 } else { /* VQRDHMUL */
4548 case 1: gen_helper_neon_qrdmulh_s16(tmp
, tmp
, tmp2
); break;
4549 case 2: gen_helper_neon_qrdmulh_s32(tmp
, tmp
, tmp2
); break;
4554 case 23: /* VPADD */
4558 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
4559 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
4560 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
4564 case 26: /* Floating point arithnetic. */
4565 switch ((u
<< 2) | size
) {
4567 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4570 gen_helper_neon_sub_f32(tmp
, tmp
, tmp2
);
4573 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4576 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
);
4582 case 27: /* Float multiply. */
4583 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
4585 tcg_temp_free_i32(tmp2
);
4586 tmp2
= neon_load_reg(rd
, pass
);
4588 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4590 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
4594 case 28: /* Float compare. */
4596 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
4599 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
4601 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
4604 case 29: /* Float compare absolute. */
4608 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
);
4610 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
);
4612 case 30: /* Float min/max. */
4614 gen_helper_neon_max_f32(tmp
, tmp
, tmp2
);
4616 gen_helper_neon_min_f32(tmp
, tmp
, tmp2
);
4620 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
4622 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
4627 tcg_temp_free_i32(tmp2
);
4629 /* Save the result. For elementwise operations we can put it
4630 straight into the destination register. For pairwise operations
4631 we have to be careful to avoid clobbering the source operands. */
4632 if (pairwise
&& rd
== rm
) {
4633 neon_store_scratch(pass
, tmp
);
4635 neon_store_reg(rd
, pass
, tmp
);
4639 if (pairwise
&& rd
== rm
) {
4640 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4641 tmp
= neon_load_scratch(pass
);
4642 neon_store_reg(rd
, pass
, tmp
);
4645 /* End of 3 register same size operations. */
4646 } else if (insn
& (1 << 4)) {
4647 if ((insn
& 0x00380080) != 0) {
4648 /* Two registers and shift. */
4649 op
= (insn
>> 8) & 0xf;
4650 if (insn
& (1 << 7)) {
4655 while ((insn
& (1 << (size
+ 19))) == 0)
4658 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
4659 /* To avoid excessive dumplication of ops we implement shift
4660 by immediate using the variable shift operations. */
4662 /* Shift by immediate:
4663 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4664 /* Right shifts are encoded as N - shift, where N is the
4665 element size in bits. */
4667 shift
= shift
- (1 << (size
+ 3));
4675 imm
= (uint8_t) shift
;
4680 imm
= (uint16_t) shift
;
4691 for (pass
= 0; pass
< count
; pass
++) {
4693 neon_load_reg64(cpu_V0
, rm
+ pass
);
4694 tcg_gen_movi_i64(cpu_V1
, imm
);
4699 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4701 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4706 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4708 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4713 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4715 case 5: /* VSHL, VSLI */
4716 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4718 case 6: /* VQSHLU */
4720 gen_helper_neon_qshlu_s64(cpu_V0
,
4728 gen_helper_neon_qshl_u64(cpu_V0
,
4731 gen_helper_neon_qshl_s64(cpu_V0
,
4736 if (op
== 1 || op
== 3) {
4738 neon_load_reg64(cpu_V1
, rd
+ pass
);
4739 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4740 } else if (op
== 4 || (op
== 5 && u
)) {
4742 neon_load_reg64(cpu_V1
, rd
+ pass
);
4744 if (shift
< -63 || shift
> 63) {
4748 mask
= 0xffffffffffffffffull
>> -shift
;
4750 mask
= 0xffffffffffffffffull
<< shift
;
4753 tcg_gen_andi_i64(cpu_V1
, cpu_V1
, ~mask
);
4754 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4756 neon_store_reg64(cpu_V0
, rd
+ pass
);
4757 } else { /* size < 3 */
4758 /* Operands in T0 and T1. */
4759 tmp
= neon_load_reg(rm
, pass
);
4760 tmp2
= tcg_temp_new_i32();
4761 tcg_gen_movi_i32(tmp2
, imm
);
4765 GEN_NEON_INTEGER_OP(shl
);
4769 GEN_NEON_INTEGER_OP(rshl
);
4774 GEN_NEON_INTEGER_OP(shl
);
4776 case 5: /* VSHL, VSLI */
4778 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
4779 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
4780 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
4784 case 6: /* VQSHLU */
4790 gen_helper_neon_qshlu_s8(tmp
, tmp
, tmp2
);
4793 gen_helper_neon_qshlu_s16(tmp
, tmp
, tmp2
);
4796 gen_helper_neon_qshlu_s32(tmp
, tmp
, tmp2
);
4803 GEN_NEON_INTEGER_OP(qshl
);
4806 tcg_temp_free_i32(tmp2
);
4808 if (op
== 1 || op
== 3) {
4810 tmp2
= neon_load_reg(rd
, pass
);
4811 gen_neon_add(size
, tmp
, tmp2
);
4812 tcg_temp_free_i32(tmp2
);
4813 } else if (op
== 4 || (op
== 5 && u
)) {
4818 mask
= 0xff >> -shift
;
4820 mask
= (uint8_t)(0xff << shift
);
4826 mask
= 0xffff >> -shift
;
4828 mask
= (uint16_t)(0xffff << shift
);
4832 if (shift
< -31 || shift
> 31) {
4836 mask
= 0xffffffffu
>> -shift
;
4838 mask
= 0xffffffffu
<< shift
;
4844 tmp2
= neon_load_reg(rd
, pass
);
4845 tcg_gen_andi_i32(tmp
, tmp
, mask
);
4846 tcg_gen_andi_i32(tmp2
, tmp2
, ~mask
);
4847 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4848 tcg_temp_free_i32(tmp2
);
4850 neon_store_reg(rd
, pass
, tmp
);
4853 } else if (op
< 10) {
4854 /* Shift by immediate and narrow:
4855 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4856 int input_unsigned
= (op
== 8) ? !u
: u
;
4858 shift
= shift
- (1 << (size
+ 3));
4861 tmp64
= tcg_const_i64(shift
);
4862 neon_load_reg64(cpu_V0
, rm
);
4863 neon_load_reg64(cpu_V1
, rm
+ 1);
4864 for (pass
= 0; pass
< 2; pass
++) {
4872 if (input_unsigned
) {
4873 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
4875 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
4878 if (input_unsigned
) {
4879 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
4881 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
4884 tmp
= tcg_temp_new_i32();
4885 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
4886 neon_store_reg(rd
, pass
, tmp
);
4888 tcg_temp_free_i64(tmp64
);
4891 imm
= (uint16_t)shift
;
4895 imm
= (uint32_t)shift
;
4897 tmp2
= tcg_const_i32(imm
);
4898 tmp4
= neon_load_reg(rm
+ 1, 0);
4899 tmp5
= neon_load_reg(rm
+ 1, 1);
4900 for (pass
= 0; pass
< 2; pass
++) {
4902 tmp
= neon_load_reg(rm
, 0);
4906 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
4909 tmp3
= neon_load_reg(rm
, 1);
4913 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
4915 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
4916 tcg_temp_free_i32(tmp
);
4917 tcg_temp_free_i32(tmp3
);
4918 tmp
= tcg_temp_new_i32();
4919 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
4920 neon_store_reg(rd
, pass
, tmp
);
4922 tcg_temp_free_i32(tmp2
);
4924 } else if (op
== 10) {
4928 tmp
= neon_load_reg(rm
, 0);
4929 tmp2
= neon_load_reg(rm
, 1);
4930 for (pass
= 0; pass
< 2; pass
++) {
4934 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
4937 /* The shift is less than the width of the source
4938 type, so we can just shift the whole register. */
4939 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
4940 /* Widen the result of shift: we need to clear
4941 * the potential overflow bits resulting from
4942 * left bits of the narrow input appearing as
4943 * right bits of left the neighbour narrow
4945 if (size
< 2 || !u
) {
4948 imm
= (0xffu
>> (8 - shift
));
4950 } else if (size
== 1) {
4951 imm
= 0xffff >> (16 - shift
);
4954 imm
= 0xffffffff >> (32 - shift
);
4957 imm64
= imm
| (((uint64_t)imm
) << 32);
4961 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
4964 neon_store_reg64(cpu_V0
, rd
+ pass
);
4966 } else if (op
>= 14) {
4967 /* VCVT fixed-point. */
4968 /* We have already masked out the must-be-1 top bit of imm6,
4969 * hence this 32-shift where the ARM ARM has 64-imm6.
4972 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4973 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
4976 gen_vfp_ulto(0, shift
);
4978 gen_vfp_slto(0, shift
);
4981 gen_vfp_toul(0, shift
);
4983 gen_vfp_tosl(0, shift
);
4985 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
4990 } else { /* (insn & 0x00380080) == 0 */
4993 op
= (insn
>> 8) & 0xf;
4994 /* One register and immediate. */
4995 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
4996 invert
= (insn
& (1 << 5)) != 0;
5014 imm
= (imm
<< 8) | (imm
<< 24);
5017 imm
= (imm
<< 8) | 0xff;
5020 imm
= (imm
<< 16) | 0xffff;
5023 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
5028 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
5029 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
5035 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5036 if (op
& 1 && op
< 12) {
5037 tmp
= neon_load_reg(rd
, pass
);
5039 /* The immediate value has already been inverted, so
5041 tcg_gen_andi_i32(tmp
, tmp
, imm
);
5043 tcg_gen_ori_i32(tmp
, tmp
, imm
);
5047 tmp
= tcg_temp_new_i32();
5048 if (op
== 14 && invert
) {
5051 for (n
= 0; n
< 4; n
++) {
5052 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
5053 val
|= 0xff << (n
* 8);
5055 tcg_gen_movi_i32(tmp
, val
);
5057 tcg_gen_movi_i32(tmp
, imm
);
5060 neon_store_reg(rd
, pass
, tmp
);
5063 } else { /* (insn & 0x00800010 == 0x00800000) */
5065 op
= (insn
>> 8) & 0xf;
5066 if ((insn
& (1 << 6)) == 0) {
5067 /* Three registers of different lengths. */
5071 /* prewiden, src1_wide, src2_wide */
5072 static const int neon_3reg_wide
[16][3] = {
5073 {1, 0, 0}, /* VADDL */
5074 {1, 1, 0}, /* VADDW */
5075 {1, 0, 0}, /* VSUBL */
5076 {1, 1, 0}, /* VSUBW */
5077 {0, 1, 1}, /* VADDHN */
5078 {0, 0, 0}, /* VABAL */
5079 {0, 1, 1}, /* VSUBHN */
5080 {0, 0, 0}, /* VABDL */
5081 {0, 0, 0}, /* VMLAL */
5082 {0, 0, 0}, /* VQDMLAL */
5083 {0, 0, 0}, /* VMLSL */
5084 {0, 0, 0}, /* VQDMLSL */
5085 {0, 0, 0}, /* Integer VMULL */
5086 {0, 0, 0}, /* VQDMULL */
5087 {0, 0, 0} /* Polynomial VMULL */
5090 prewiden
= neon_3reg_wide
[op
][0];
5091 src1_wide
= neon_3reg_wide
[op
][1];
5092 src2_wide
= neon_3reg_wide
[op
][2];
5094 if (size
== 0 && (op
== 9 || op
== 11 || op
== 13))
5097 /* Avoid overlapping operands. Wide source operands are
5098 always aligned so will never overlap with wide
5099 destinations in problematic ways. */
5100 if (rd
== rm
&& !src2_wide
) {
5101 tmp
= neon_load_reg(rm
, 1);
5102 neon_store_scratch(2, tmp
);
5103 } else if (rd
== rn
&& !src1_wide
) {
5104 tmp
= neon_load_reg(rn
, 1);
5105 neon_store_scratch(2, tmp
);
5108 for (pass
= 0; pass
< 2; pass
++) {
5110 neon_load_reg64(cpu_V0
, rn
+ pass
);
5113 if (pass
== 1 && rd
== rn
) {
5114 tmp
= neon_load_scratch(2);
5116 tmp
= neon_load_reg(rn
, pass
);
5119 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5123 neon_load_reg64(cpu_V1
, rm
+ pass
);
5126 if (pass
== 1 && rd
== rm
) {
5127 tmp2
= neon_load_scratch(2);
5129 tmp2
= neon_load_reg(rm
, pass
);
5132 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
5136 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5137 gen_neon_addl(size
);
5139 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5140 gen_neon_subl(size
);
5142 case 5: case 7: /* VABAL, VABDL */
5143 switch ((size
<< 1) | u
) {
5145 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
5148 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
5151 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
5154 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
5157 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
5160 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
5164 tcg_temp_free_i32(tmp2
);
5165 tcg_temp_free_i32(tmp
);
5167 case 8: case 9: case 10: case 11: case 12: case 13:
5168 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5169 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5171 case 14: /* Polynomial VMULL */
5172 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
5173 tcg_temp_free_i32(tmp2
);
5174 tcg_temp_free_i32(tmp
);
5176 default: /* 15 is RESERVED. */
5181 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5182 neon_store_reg64(cpu_V0
, rd
+ pass
);
5183 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
5185 neon_load_reg64(cpu_V1
, rd
+ pass
);
5187 case 10: /* VMLSL */
5188 gen_neon_negl(cpu_V0
, size
);
5190 case 5: case 8: /* VABAL, VMLAL */
5191 gen_neon_addl(size
);
5193 case 9: case 11: /* VQDMLAL, VQDMLSL */
5194 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5196 gen_neon_negl(cpu_V0
, size
);
5198 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5203 neon_store_reg64(cpu_V0
, rd
+ pass
);
5204 } else if (op
== 4 || op
== 6) {
5205 /* Narrowing operation. */
5206 tmp
= tcg_temp_new_i32();
5210 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
5213 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
5216 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5217 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5224 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
5227 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
5230 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
5231 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5232 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5240 neon_store_reg(rd
, 0, tmp3
);
5241 neon_store_reg(rd
, 1, tmp
);
5244 /* Write back the result. */
5245 neon_store_reg64(cpu_V0
, rd
+ pass
);
5249 /* Two registers and a scalar. */
5251 case 0: /* Integer VMLA scalar */
5252 case 1: /* Float VMLA scalar */
5253 case 4: /* Integer VMLS scalar */
5254 case 5: /* Floating point VMLS scalar */
5255 case 8: /* Integer VMUL scalar */
5256 case 9: /* Floating point VMUL scalar */
5257 case 12: /* VQDMULH scalar */
5258 case 13: /* VQRDMULH scalar */
5259 tmp
= neon_get_scalar(size
, rm
);
5260 neon_store_scratch(0, tmp
);
5261 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5262 tmp
= neon_load_scratch(0);
5263 tmp2
= neon_load_reg(rn
, pass
);
5266 gen_helper_neon_qdmulh_s16(tmp
, tmp
, tmp2
);
5268 gen_helper_neon_qdmulh_s32(tmp
, tmp
, tmp2
);
5270 } else if (op
== 13) {
5272 gen_helper_neon_qrdmulh_s16(tmp
, tmp
, tmp2
);
5274 gen_helper_neon_qrdmulh_s32(tmp
, tmp
, tmp2
);
5276 } else if (op
& 1) {
5277 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
5280 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5281 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5282 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5286 tcg_temp_free_i32(tmp2
);
5289 tmp2
= neon_load_reg(rd
, pass
);
5292 gen_neon_add(size
, tmp
, tmp2
);
5295 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
5298 gen_neon_rsb(size
, tmp
, tmp2
);
5301 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
5306 tcg_temp_free_i32(tmp2
);
5308 neon_store_reg(rd
, pass
, tmp
);
5311 case 2: /* VMLAL sclar */
5312 case 3: /* VQDMLAL scalar */
5313 case 6: /* VMLSL scalar */
5314 case 7: /* VQDMLSL scalar */
5315 case 10: /* VMULL scalar */
5316 case 11: /* VQDMULL scalar */
5317 if (size
== 0 && (op
== 3 || op
== 7 || op
== 11))
5320 tmp2
= neon_get_scalar(size
, rm
);
5321 /* We need a copy of tmp2 because gen_neon_mull
5322 * deletes it during pass 0. */
5323 tmp4
= tcg_temp_new_i32();
5324 tcg_gen_mov_i32(tmp4
, tmp2
);
5325 tmp3
= neon_load_reg(rn
, 1);
5327 for (pass
= 0; pass
< 2; pass
++) {
5329 tmp
= neon_load_reg(rn
, 0);
5334 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5336 neon_load_reg64(cpu_V1
, rd
+ pass
);
5340 gen_neon_negl(cpu_V0
, size
);
5343 gen_neon_addl(size
);
5346 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5348 gen_neon_negl(cpu_V0
, size
);
5350 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5356 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5361 neon_store_reg64(cpu_V0
, rd
+ pass
);
5366 default: /* 14 and 15 are RESERVED */
5370 } else { /* size == 3 */
5373 imm
= (insn
>> 8) & 0xf;
5379 neon_load_reg64(cpu_V0
, rn
);
5381 neon_load_reg64(cpu_V1
, rn
+ 1);
5383 } else if (imm
== 8) {
5384 neon_load_reg64(cpu_V0
, rn
+ 1);
5386 neon_load_reg64(cpu_V1
, rm
);
5389 tmp64
= tcg_temp_new_i64();
5391 neon_load_reg64(cpu_V0
, rn
);
5392 neon_load_reg64(tmp64
, rn
+ 1);
5394 neon_load_reg64(cpu_V0
, rn
+ 1);
5395 neon_load_reg64(tmp64
, rm
);
5397 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
5398 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
5399 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5401 neon_load_reg64(cpu_V1
, rm
);
5403 neon_load_reg64(cpu_V1
, rm
+ 1);
5406 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5407 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
5408 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
5409 tcg_temp_free_i64(tmp64
);
5412 neon_load_reg64(cpu_V0
, rn
);
5413 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
5414 neon_load_reg64(cpu_V1
, rm
);
5415 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5416 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5418 neon_store_reg64(cpu_V0
, rd
);
5420 neon_store_reg64(cpu_V1
, rd
+ 1);
5422 } else if ((insn
& (1 << 11)) == 0) {
5423 /* Two register misc. */
5424 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
5425 size
= (insn
>> 18) & 3;
5427 case 0: /* VREV64 */
5430 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5431 tmp
= neon_load_reg(rm
, pass
* 2);
5432 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
5434 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5435 case 1: gen_swap_half(tmp
); break;
5436 case 2: /* no-op */ break;
5439 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
5441 neon_store_reg(rd
, pass
* 2, tmp2
);
5444 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
5445 case 1: gen_swap_half(tmp2
); break;
5448 neon_store_reg(rd
, pass
* 2, tmp2
);
5452 case 4: case 5: /* VPADDL */
5453 case 12: case 13: /* VPADAL */
5456 for (pass
= 0; pass
< q
+ 1; pass
++) {
5457 tmp
= neon_load_reg(rm
, pass
* 2);
5458 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
5459 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
5460 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
5462 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
5463 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
5464 case 2: tcg_gen_add_i64(CPU_V001
); break;
5469 neon_load_reg64(cpu_V1
, rd
+ pass
);
5470 gen_neon_addl(size
);
5472 neon_store_reg64(cpu_V0
, rd
+ pass
);
5477 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
5478 tmp
= neon_load_reg(rm
, n
);
5479 tmp2
= neon_load_reg(rd
, n
+ 1);
5480 neon_store_reg(rm
, n
, tmp2
);
5481 neon_store_reg(rd
, n
+ 1, tmp
);
5488 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
5493 if (gen_neon_zip(rd
, rm
, size
, q
)) {
5497 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5501 for (pass
= 0; pass
< 2; pass
++) {
5502 neon_load_reg64(cpu_V0
, rm
+ pass
);
5503 tmp
= tcg_temp_new_i32();
5504 gen_neon_narrow_op(op
== 36, q
, size
, tmp
, cpu_V0
);
5508 neon_store_reg(rd
, 0, tmp2
);
5509 neon_store_reg(rd
, 1, tmp
);
5513 case 38: /* VSHLL */
5516 tmp
= neon_load_reg(rm
, 0);
5517 tmp2
= neon_load_reg(rm
, 1);
5518 for (pass
= 0; pass
< 2; pass
++) {
5521 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
5522 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
5523 neon_store_reg64(cpu_V0
, rd
+ pass
);
5526 case 44: /* VCVT.F16.F32 */
5527 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
5529 tmp
= tcg_temp_new_i32();
5530 tmp2
= tcg_temp_new_i32();
5531 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
5532 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5533 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
5534 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5535 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5536 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5537 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
5538 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5539 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
5540 neon_store_reg(rd
, 0, tmp2
);
5541 tmp2
= tcg_temp_new_i32();
5542 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5543 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5544 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5545 neon_store_reg(rd
, 1, tmp2
);
5546 tcg_temp_free_i32(tmp
);
5548 case 46: /* VCVT.F32.F16 */
5549 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
5551 tmp3
= tcg_temp_new_i32();
5552 tmp
= neon_load_reg(rm
, 0);
5553 tmp2
= neon_load_reg(rm
, 1);
5554 tcg_gen_ext16u_i32(tmp3
, tmp
);
5555 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5556 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
5557 tcg_gen_shri_i32(tmp3
, tmp
, 16);
5558 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5559 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
5560 tcg_temp_free_i32(tmp
);
5561 tcg_gen_ext16u_i32(tmp3
, tmp2
);
5562 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5563 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
5564 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
5565 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5566 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
5567 tcg_temp_free_i32(tmp2
);
5568 tcg_temp_free_i32(tmp3
);
5572 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5573 if (op
== 30 || op
== 31 || op
>= 58) {
5574 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
5575 neon_reg_offset(rm
, pass
));
5578 tmp
= neon_load_reg(rm
, pass
);
5581 case 1: /* VREV32 */
5583 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5584 case 1: gen_swap_half(tmp
); break;
5588 case 2: /* VREV16 */
5595 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
5596 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
5597 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
5603 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
5604 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
5605 case 2: gen_helper_clz(tmp
, tmp
); break;
5612 gen_helper_neon_cnt_u8(tmp
, tmp
);
5617 tcg_gen_not_i32(tmp
, tmp
);
5619 case 14: /* VQABS */
5621 case 0: gen_helper_neon_qabs_s8(tmp
, tmp
); break;
5622 case 1: gen_helper_neon_qabs_s16(tmp
, tmp
); break;
5623 case 2: gen_helper_neon_qabs_s32(tmp
, tmp
); break;
5627 case 15: /* VQNEG */
5629 case 0: gen_helper_neon_qneg_s8(tmp
, tmp
); break;
5630 case 1: gen_helper_neon_qneg_s16(tmp
, tmp
); break;
5631 case 2: gen_helper_neon_qneg_s32(tmp
, tmp
); break;
5635 case 16: case 19: /* VCGT #0, VCLE #0 */
5636 tmp2
= tcg_const_i32(0);
5638 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
5639 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
5640 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
5643 tcg_temp_free(tmp2
);
5645 tcg_gen_not_i32(tmp
, tmp
);
5647 case 17: case 20: /* VCGE #0, VCLT #0 */
5648 tmp2
= tcg_const_i32(0);
5650 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
5651 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
5652 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
5655 tcg_temp_free(tmp2
);
5657 tcg_gen_not_i32(tmp
, tmp
);
5659 case 18: /* VCEQ #0 */
5660 tmp2
= tcg_const_i32(0);
5662 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5663 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5664 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5667 tcg_temp_free(tmp2
);
5671 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
5672 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
5673 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
5680 tmp2
= tcg_const_i32(0);
5681 gen_neon_rsb(size
, tmp
, tmp2
);
5682 tcg_temp_free(tmp2
);
5684 case 24: /* Float VCGT #0 */
5685 tmp2
= tcg_const_i32(0);
5686 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
5687 tcg_temp_free(tmp2
);
5689 case 25: /* Float VCGE #0 */
5690 tmp2
= tcg_const_i32(0);
5691 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
5692 tcg_temp_free(tmp2
);
5694 case 26: /* Float VCEQ #0 */
5695 tmp2
= tcg_const_i32(0);
5696 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
5697 tcg_temp_free(tmp2
);
5699 case 27: /* Float VCLE #0 */
5700 tmp2
= tcg_const_i32(0);
5701 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
);
5702 tcg_temp_free(tmp2
);
5704 case 28: /* Float VCLT #0 */
5705 tmp2
= tcg_const_i32(0);
5706 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
);
5707 tcg_temp_free(tmp2
);
5709 case 30: /* Float VABS */
5712 case 31: /* Float VNEG */
5716 tmp2
= neon_load_reg(rd
, pass
);
5717 neon_store_reg(rm
, pass
, tmp2
);
5720 tmp2
= neon_load_reg(rd
, pass
);
5722 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
5723 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
5727 neon_store_reg(rm
, pass
, tmp2
);
5729 case 56: /* Integer VRECPE */
5730 gen_helper_recpe_u32(tmp
, tmp
, cpu_env
);
5732 case 57: /* Integer VRSQRTE */
5733 gen_helper_rsqrte_u32(tmp
, tmp
, cpu_env
);
5735 case 58: /* Float VRECPE */
5736 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5738 case 59: /* Float VRSQRTE */
5739 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5741 case 60: /* VCVT.F32.S32 */
5744 case 61: /* VCVT.F32.U32 */
5747 case 62: /* VCVT.S32.F32 */
5750 case 63: /* VCVT.U32.F32 */
5754 /* Reserved: 21, 29, 39-56 */
5757 if (op
== 30 || op
== 31 || op
>= 58) {
5758 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
5759 neon_reg_offset(rd
, pass
));
5761 neon_store_reg(rd
, pass
, tmp
);
5766 } else if ((insn
& (1 << 10)) == 0) {
5768 n
= ((insn
>> 5) & 0x18) + 8;
5769 if (insn
& (1 << 6)) {
5770 tmp
= neon_load_reg(rd
, 0);
5772 tmp
= tcg_temp_new_i32();
5773 tcg_gen_movi_i32(tmp
, 0);
5775 tmp2
= neon_load_reg(rm
, 0);
5776 tmp4
= tcg_const_i32(rn
);
5777 tmp5
= tcg_const_i32(n
);
5778 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, tmp4
, tmp5
);
5779 tcg_temp_free_i32(tmp
);
5780 if (insn
& (1 << 6)) {
5781 tmp
= neon_load_reg(rd
, 1);
5783 tmp
= tcg_temp_new_i32();
5784 tcg_gen_movi_i32(tmp
, 0);
5786 tmp3
= neon_load_reg(rm
, 1);
5787 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, tmp4
, tmp5
);
5788 tcg_temp_free_i32(tmp5
);
5789 tcg_temp_free_i32(tmp4
);
5790 neon_store_reg(rd
, 0, tmp2
);
5791 neon_store_reg(rd
, 1, tmp3
);
5792 tcg_temp_free_i32(tmp
);
5793 } else if ((insn
& 0x380) == 0) {
5795 if (insn
& (1 << 19)) {
5796 tmp
= neon_load_reg(rm
, 1);
5798 tmp
= neon_load_reg(rm
, 0);
5800 if (insn
& (1 << 16)) {
5801 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
5802 } else if (insn
& (1 << 17)) {
5803 if ((insn
>> 18) & 1)
5804 gen_neon_dup_high16(tmp
);
5806 gen_neon_dup_low16(tmp
);
5808 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5809 tmp2
= tcg_temp_new_i32();
5810 tcg_gen_mov_i32(tmp2
, tmp
);
5811 neon_store_reg(rd
, pass
, tmp2
);
5813 tcg_temp_free_i32(tmp
);
5822 static int disas_cp14_read(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5824 int crn
= (insn
>> 16) & 0xf;
5825 int crm
= insn
& 0xf;
5826 int op1
= (insn
>> 21) & 7;
5827 int op2
= (insn
>> 5) & 7;
5828 int rt
= (insn
>> 12) & 0xf;
5831 /* Minimal set of debug registers, since we don't support debug */
5832 if (op1
== 0 && crn
== 0 && op2
== 0) {
5835 /* DBGDIDR: just RAZ. In particular this means the
5836 * "debug architecture version" bits will read as
5837 * a reserved value, which should cause Linux to
5838 * not try to use the debug hardware.
5840 tmp
= tcg_const_i32(0);
5841 store_reg(s
, rt
, tmp
);
5845 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5846 * don't implement memory mapped debug components
5848 if (ENABLE_ARCH_7
) {
5849 tmp
= tcg_const_i32(0);
5850 store_reg(s
, rt
, tmp
);
5859 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5860 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5864 tmp
= load_cpu_field(teecr
);
5865 store_reg(s
, rt
, tmp
);
5868 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5870 if (IS_USER(s
) && (env
->teecr
& 1))
5872 tmp
= load_cpu_field(teehbr
);
5873 store_reg(s
, rt
, tmp
);
5877 fprintf(stderr
, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5878 op1
, crn
, crm
, op2
);
5882 static int disas_cp14_write(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5884 int crn
= (insn
>> 16) & 0xf;
5885 int crm
= insn
& 0xf;
5886 int op1
= (insn
>> 21) & 7;
5887 int op2
= (insn
>> 5) & 7;
5888 int rt
= (insn
>> 12) & 0xf;
5891 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5892 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5896 tmp
= load_reg(s
, rt
);
5897 gen_helper_set_teecr(cpu_env
, tmp
);
5898 tcg_temp_free_i32(tmp
);
5901 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5903 if (IS_USER(s
) && (env
->teecr
& 1))
5905 tmp
= load_reg(s
, rt
);
5906 store_cpu_field(tmp
, teehbr
);
5910 fprintf(stderr
, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5911 op1
, crn
, crm
, op2
);
5915 static int disas_coproc_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5919 cpnum
= (insn
>> 8) & 0xf;
5920 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
5921 && ((env
->cp15
.c15_cpar
^ 0x3fff) & (1 << cpnum
)))
5927 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
5928 return disas_iwmmxt_insn(env
, s
, insn
);
5929 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5930 return disas_dsp_insn(env
, s
, insn
);
5935 return disas_vfp_insn (env
, s
, insn
);
5937 /* Coprocessors 7-15 are architecturally reserved by ARM.
5938 Unfortunately Intel decided to ignore this. */
5939 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
5941 if (insn
& (1 << 20))
5942 return disas_cp14_read(env
, s
, insn
);
5944 return disas_cp14_write(env
, s
, insn
);
5946 return disas_cp15_insn (env
, s
, insn
);
5949 /* Unknown coprocessor. See if the board has hooked it. */
5950 return disas_cp_insn (env
, s
, insn
);
5955 /* Store a 64-bit value to a register pair. Clobbers val. */
5956 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
5959 tmp
= tcg_temp_new_i32();
5960 tcg_gen_trunc_i64_i32(tmp
, val
);
5961 store_reg(s
, rlow
, tmp
);
5962 tmp
= tcg_temp_new_i32();
5963 tcg_gen_shri_i64(val
, val
, 32);
5964 tcg_gen_trunc_i64_i32(tmp
, val
);
5965 store_reg(s
, rhigh
, tmp
);
5968 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5969 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
5974 /* Load value and extend to 64 bits. */
5975 tmp
= tcg_temp_new_i64();
5976 tmp2
= load_reg(s
, rlow
);
5977 tcg_gen_extu_i32_i64(tmp
, tmp2
);
5978 tcg_temp_free_i32(tmp2
);
5979 tcg_gen_add_i64(val
, val
, tmp
);
5980 tcg_temp_free_i64(tmp
);
5983 /* load and add a 64-bit value from a register pair. */
5984 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
5990 /* Load 64-bit value rd:rn. */
5991 tmpl
= load_reg(s
, rlow
);
5992 tmph
= load_reg(s
, rhigh
);
5993 tmp
= tcg_temp_new_i64();
5994 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
5995 tcg_temp_free_i32(tmpl
);
5996 tcg_temp_free_i32(tmph
);
5997 tcg_gen_add_i64(val
, val
, tmp
);
5998 tcg_temp_free_i64(tmp
);
6001 /* Set N and Z flags from a 64-bit value. */
6002 static void gen_logicq_cc(TCGv_i64 val
)
6004 TCGv tmp
= tcg_temp_new_i32();
6005 gen_helper_logicq_cc(tmp
, val
);
6007 tcg_temp_free_i32(tmp
);
6010 /* Load/Store exclusive instructions are implemented by remembering
6011 the value/address loaded, and seeing if these are the same
6012 when the store is performed. This should be is sufficient to implement
6013 the architecturally mandated semantics, and avoids having to monitor
6016 In system emulation mode only one CPU will be running at once, so
6017 this sequence is effectively atomic. In user emulation mode we
6018 throw an exception and handle the atomic operation elsewhere. */
6019 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
6020 TCGv addr
, int size
)
6026 tmp
= gen_ld8u(addr
, IS_USER(s
));
6029 tmp
= gen_ld16u(addr
, IS_USER(s
));
6033 tmp
= gen_ld32(addr
, IS_USER(s
));
6038 tcg_gen_mov_i32(cpu_exclusive_val
, tmp
);
6039 store_reg(s
, rt
, tmp
);
6041 TCGv tmp2
= tcg_temp_new_i32();
6042 tcg_gen_addi_i32(tmp2
, addr
, 4);
6043 tmp
= gen_ld32(tmp2
, IS_USER(s
));
6044 tcg_temp_free_i32(tmp2
);
6045 tcg_gen_mov_i32(cpu_exclusive_high
, tmp
);
6046 store_reg(s
, rt2
, tmp
);
6048 tcg_gen_mov_i32(cpu_exclusive_addr
, addr
);
6051 static void gen_clrex(DisasContext
*s
)
6053 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
6056 #ifdef CONFIG_USER_ONLY
6057 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
6058 TCGv addr
, int size
)
6060 tcg_gen_mov_i32(cpu_exclusive_test
, addr
);
6061 tcg_gen_movi_i32(cpu_exclusive_info
,
6062 size
| (rd
<< 4) | (rt
<< 8) | (rt2
<< 12));
6063 gen_exception_insn(s
, 4, EXCP_STREX
);
6066 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
6067 TCGv addr
, int size
)
6073 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6079 fail_label
= gen_new_label();
6080 done_label
= gen_new_label();
6081 tcg_gen_brcond_i32(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
6084 tmp
= gen_ld8u(addr
, IS_USER(s
));
6087 tmp
= gen_ld16u(addr
, IS_USER(s
));
6091 tmp
= gen_ld32(addr
, IS_USER(s
));
6096 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
6097 tcg_temp_free_i32(tmp
);
6099 TCGv tmp2
= tcg_temp_new_i32();
6100 tcg_gen_addi_i32(tmp2
, addr
, 4);
6101 tmp
= gen_ld32(tmp2
, IS_USER(s
));
6102 tcg_temp_free_i32(tmp2
);
6103 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_high
, fail_label
);
6104 tcg_temp_free_i32(tmp
);
6106 tmp
= load_reg(s
, rt
);
6109 gen_st8(tmp
, addr
, IS_USER(s
));
6112 gen_st16(tmp
, addr
, IS_USER(s
));
6116 gen_st32(tmp
, addr
, IS_USER(s
));
6122 tcg_gen_addi_i32(addr
, addr
, 4);
6123 tmp
= load_reg(s
, rt2
);
6124 gen_st32(tmp
, addr
, IS_USER(s
));
6126 tcg_gen_movi_i32(cpu_R
[rd
], 0);
6127 tcg_gen_br(done_label
);
6128 gen_set_label(fail_label
);
6129 tcg_gen_movi_i32(cpu_R
[rd
], 1);
6130 gen_set_label(done_label
);
6131 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
6135 static void disas_arm_insn(CPUState
* env
, DisasContext
*s
)
6137 unsigned int cond
, insn
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
6144 insn
= ldl_code(s
->pc
);
6147 /* M variants do not implement ARM mode. */
6152 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6153 * choose to UNDEF. In ARMv5 and above the space is used
6154 * for miscellaneous unconditional instructions.
6158 /* Unconditional instructions. */
6159 if (((insn
>> 25) & 7) == 1) {
6160 /* NEON Data processing. */
6161 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6164 if (disas_neon_data_insn(env
, s
, insn
))
6168 if ((insn
& 0x0f100000) == 0x04000000) {
6169 /* NEON load/store. */
6170 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6173 if (disas_neon_ls_insn(env
, s
, insn
))
6177 if (((insn
& 0x0f30f000) == 0x0510f000) ||
6178 ((insn
& 0x0f30f010) == 0x0710f000)) {
6179 if ((insn
& (1 << 22)) == 0) {
6181 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6185 /* Otherwise PLD; v5TE+ */
6189 if (((insn
& 0x0f70f000) == 0x0450f000) ||
6190 ((insn
& 0x0f70f010) == 0x0650f000)) {
6192 return; /* PLI; V7 */
6194 if (((insn
& 0x0f700000) == 0x04100000) ||
6195 ((insn
& 0x0f700010) == 0x06100000)) {
6196 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6199 return; /* v7MP: Unallocated memory hint: must NOP */
6202 if ((insn
& 0x0ffffdff) == 0x01010000) {
6205 if (insn
& (1 << 9)) {
6206 /* BE8 mode not implemented. */
6210 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
6211 switch ((insn
>> 4) & 0xf) {
6220 /* We don't emulate caches so these are a no-op. */
6225 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
6231 op1
= (insn
& 0x1f);
6232 addr
= tcg_temp_new_i32();
6233 tmp
= tcg_const_i32(op1
);
6234 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
6235 tcg_temp_free_i32(tmp
);
6236 i
= (insn
>> 23) & 3;
6238 case 0: offset
= -4; break; /* DA */
6239 case 1: offset
= 0; break; /* IA */
6240 case 2: offset
= -8; break; /* DB */
6241 case 3: offset
= 4; break; /* IB */
6245 tcg_gen_addi_i32(addr
, addr
, offset
);
6246 tmp
= load_reg(s
, 14);
6247 gen_st32(tmp
, addr
, 0);
6248 tmp
= load_cpu_field(spsr
);
6249 tcg_gen_addi_i32(addr
, addr
, 4);
6250 gen_st32(tmp
, addr
, 0);
6251 if (insn
& (1 << 21)) {
6252 /* Base writeback. */
6254 case 0: offset
= -8; break;
6255 case 1: offset
= 4; break;
6256 case 2: offset
= -4; break;
6257 case 3: offset
= 0; break;
6261 tcg_gen_addi_i32(addr
, addr
, offset
);
6262 tmp
= tcg_const_i32(op1
);
6263 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
6264 tcg_temp_free_i32(tmp
);
6265 tcg_temp_free_i32(addr
);
6267 tcg_temp_free_i32(addr
);
6270 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
6276 rn
= (insn
>> 16) & 0xf;
6277 addr
= load_reg(s
, rn
);
6278 i
= (insn
>> 23) & 3;
6280 case 0: offset
= -4; break; /* DA */
6281 case 1: offset
= 0; break; /* IA */
6282 case 2: offset
= -8; break; /* DB */
6283 case 3: offset
= 4; break; /* IB */
6287 tcg_gen_addi_i32(addr
, addr
, offset
);
6288 /* Load PC into tmp and CPSR into tmp2. */
6289 tmp
= gen_ld32(addr
, 0);
6290 tcg_gen_addi_i32(addr
, addr
, 4);
6291 tmp2
= gen_ld32(addr
, 0);
6292 if (insn
& (1 << 21)) {
6293 /* Base writeback. */
6295 case 0: offset
= -8; break;
6296 case 1: offset
= 4; break;
6297 case 2: offset
= -4; break;
6298 case 3: offset
= 0; break;
6302 tcg_gen_addi_i32(addr
, addr
, offset
);
6303 store_reg(s
, rn
, addr
);
6305 tcg_temp_free_i32(addr
);
6307 gen_rfe(s
, tmp
, tmp2
);
6309 } else if ((insn
& 0x0e000000) == 0x0a000000) {
6310 /* branch link and change to thumb (blx <offset>) */
6313 val
= (uint32_t)s
->pc
;
6314 tmp
= tcg_temp_new_i32();
6315 tcg_gen_movi_i32(tmp
, val
);
6316 store_reg(s
, 14, tmp
);
6317 /* Sign-extend the 24-bit offset */
6318 offset
= (((int32_t)insn
) << 8) >> 8;
6319 /* offset * 4 + bit24 * 2 + (thumb bit) */
6320 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
6321 /* pipeline offset */
6323 /* protected by ARCH(5); above, near the start of uncond block */
6326 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
6327 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
6328 /* iWMMXt register transfer. */
6329 if (env
->cp15
.c15_cpar
& (1 << 1))
6330 if (!disas_iwmmxt_insn(env
, s
, insn
))
6333 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
6334 /* Coprocessor double register transfer. */
6336 } else if ((insn
& 0x0f000010) == 0x0e000010) {
6337 /* Additional coprocessor register transfer. */
6338 } else if ((insn
& 0x0ff10020) == 0x01000000) {
6341 /* cps (privileged) */
6345 if (insn
& (1 << 19)) {
6346 if (insn
& (1 << 8))
6348 if (insn
& (1 << 7))
6350 if (insn
& (1 << 6))
6352 if (insn
& (1 << 18))
6355 if (insn
& (1 << 17)) {
6357 val
|= (insn
& 0x1f);
6360 gen_set_psr_im(s
, mask
, 0, val
);
6367 /* if not always execute, we generate a conditional jump to
6369 s
->condlabel
= gen_new_label();
6370 gen_test_cc(cond
^ 1, s
->condlabel
);
6373 if ((insn
& 0x0f900000) == 0x03000000) {
6374 if ((insn
& (1 << 21)) == 0) {
6376 rd
= (insn
>> 12) & 0xf;
6377 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
6378 if ((insn
& (1 << 22)) == 0) {
6380 tmp
= tcg_temp_new_i32();
6381 tcg_gen_movi_i32(tmp
, val
);
6384 tmp
= load_reg(s
, rd
);
6385 tcg_gen_ext16u_i32(tmp
, tmp
);
6386 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
6388 store_reg(s
, rd
, tmp
);
6390 if (((insn
>> 12) & 0xf) != 0xf)
6392 if (((insn
>> 16) & 0xf) == 0) {
6393 gen_nop_hint(s
, insn
& 0xff);
6395 /* CPSR = immediate */
6397 shift
= ((insn
>> 8) & 0xf) * 2;
6399 val
= (val
>> shift
) | (val
<< (32 - shift
));
6400 i
= ((insn
& (1 << 22)) != 0);
6401 if (gen_set_psr_im(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, val
))
6405 } else if ((insn
& 0x0f900000) == 0x01000000
6406 && (insn
& 0x00000090) != 0x00000090) {
6407 /* miscellaneous instructions */
6408 op1
= (insn
>> 21) & 3;
6409 sh
= (insn
>> 4) & 0xf;
6412 case 0x0: /* move program status register */
6415 tmp
= load_reg(s
, rm
);
6416 i
= ((op1
& 2) != 0);
6417 if (gen_set_psr(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
6421 rd
= (insn
>> 12) & 0xf;
6425 tmp
= load_cpu_field(spsr
);
6427 tmp
= tcg_temp_new_i32();
6428 gen_helper_cpsr_read(tmp
);
6430 store_reg(s
, rd
, tmp
);
6435 /* branch/exchange thumb (bx). */
6437 tmp
= load_reg(s
, rm
);
6439 } else if (op1
== 3) {
6442 rd
= (insn
>> 12) & 0xf;
6443 tmp
= load_reg(s
, rm
);
6444 gen_helper_clz(tmp
, tmp
);
6445 store_reg(s
, rd
, tmp
);
6453 /* Trivial implementation equivalent to bx. */
6454 tmp
= load_reg(s
, rm
);
6465 /* branch link/exchange thumb (blx) */
6466 tmp
= load_reg(s
, rm
);
6467 tmp2
= tcg_temp_new_i32();
6468 tcg_gen_movi_i32(tmp2
, s
->pc
);
6469 store_reg(s
, 14, tmp2
);
6472 case 0x5: /* saturating add/subtract */
6474 rd
= (insn
>> 12) & 0xf;
6475 rn
= (insn
>> 16) & 0xf;
6476 tmp
= load_reg(s
, rm
);
6477 tmp2
= load_reg(s
, rn
);
6479 gen_helper_double_saturate(tmp2
, tmp2
);
6481 gen_helper_sub_saturate(tmp
, tmp
, tmp2
);
6483 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
6484 tcg_temp_free_i32(tmp2
);
6485 store_reg(s
, rd
, tmp
);
6488 /* SMC instruction (op1 == 3)
6489 and undefined instructions (op1 == 0 || op1 == 2)
6496 gen_exception_insn(s
, 4, EXCP_BKPT
);
6498 case 0x8: /* signed multiply */
6503 rs
= (insn
>> 8) & 0xf;
6504 rn
= (insn
>> 12) & 0xf;
6505 rd
= (insn
>> 16) & 0xf;
6507 /* (32 * 16) >> 16 */
6508 tmp
= load_reg(s
, rm
);
6509 tmp2
= load_reg(s
, rs
);
6511 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
6514 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6515 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
6516 tmp
= tcg_temp_new_i32();
6517 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6518 tcg_temp_free_i64(tmp64
);
6519 if ((sh
& 2) == 0) {
6520 tmp2
= load_reg(s
, rn
);
6521 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6522 tcg_temp_free_i32(tmp2
);
6524 store_reg(s
, rd
, tmp
);
6527 tmp
= load_reg(s
, rm
);
6528 tmp2
= load_reg(s
, rs
);
6529 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
6530 tcg_temp_free_i32(tmp2
);
6532 tmp64
= tcg_temp_new_i64();
6533 tcg_gen_ext_i32_i64(tmp64
, tmp
);
6534 tcg_temp_free_i32(tmp
);
6535 gen_addq(s
, tmp64
, rn
, rd
);
6536 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6537 tcg_temp_free_i64(tmp64
);
6540 tmp2
= load_reg(s
, rn
);
6541 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6542 tcg_temp_free_i32(tmp2
);
6544 store_reg(s
, rd
, tmp
);
6551 } else if (((insn
& 0x0e000000) == 0 &&
6552 (insn
& 0x00000090) != 0x90) ||
6553 ((insn
& 0x0e000000) == (1 << 25))) {
6554 int set_cc
, logic_cc
, shiftop
;
6556 op1
= (insn
>> 21) & 0xf;
6557 set_cc
= (insn
>> 20) & 1;
6558 logic_cc
= table_logic_cc
[op1
] & set_cc
;
6560 /* data processing instruction */
6561 if (insn
& (1 << 25)) {
6562 /* immediate operand */
6564 shift
= ((insn
>> 8) & 0xf) * 2;
6566 val
= (val
>> shift
) | (val
<< (32 - shift
));
6568 tmp2
= tcg_temp_new_i32();
6569 tcg_gen_movi_i32(tmp2
, val
);
6570 if (logic_cc
&& shift
) {
6571 gen_set_CF_bit31(tmp2
);
6576 tmp2
= load_reg(s
, rm
);
6577 shiftop
= (insn
>> 5) & 3;
6578 if (!(insn
& (1 << 4))) {
6579 shift
= (insn
>> 7) & 0x1f;
6580 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
6582 rs
= (insn
>> 8) & 0xf;
6583 tmp
= load_reg(s
, rs
);
6584 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
6587 if (op1
!= 0x0f && op1
!= 0x0d) {
6588 rn
= (insn
>> 16) & 0xf;
6589 tmp
= load_reg(s
, rn
);
6593 rd
= (insn
>> 12) & 0xf;
6596 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6600 store_reg_bx(env
, s
, rd
, tmp
);
6603 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6607 store_reg_bx(env
, s
, rd
, tmp
);
6610 if (set_cc
&& rd
== 15) {
6611 /* SUBS r15, ... is used for exception return. */
6615 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6616 gen_exception_return(s
, tmp
);
6619 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6621 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6623 store_reg_bx(env
, s
, rd
, tmp
);
6628 gen_helper_sub_cc(tmp
, tmp2
, tmp
);
6630 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6632 store_reg_bx(env
, s
, rd
, tmp
);
6636 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6638 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6640 store_reg_bx(env
, s
, rd
, tmp
);
6644 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
6646 gen_add_carry(tmp
, tmp
, tmp2
);
6648 store_reg_bx(env
, s
, rd
, tmp
);
6652 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
6654 gen_sub_carry(tmp
, tmp
, tmp2
);
6656 store_reg_bx(env
, s
, rd
, tmp
);
6660 gen_helper_sbc_cc(tmp
, tmp2
, tmp
);
6662 gen_sub_carry(tmp
, tmp2
, tmp
);
6664 store_reg_bx(env
, s
, rd
, tmp
);
6668 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6671 tcg_temp_free_i32(tmp
);
6675 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6678 tcg_temp_free_i32(tmp
);
6682 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6684 tcg_temp_free_i32(tmp
);
6688 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6690 tcg_temp_free_i32(tmp
);
6693 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6697 store_reg_bx(env
, s
, rd
, tmp
);
6700 if (logic_cc
&& rd
== 15) {
6701 /* MOVS r15, ... is used for exception return. */
6705 gen_exception_return(s
, tmp2
);
6710 store_reg_bx(env
, s
, rd
, tmp2
);
6714 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
6718 store_reg_bx(env
, s
, rd
, tmp
);
6722 tcg_gen_not_i32(tmp2
, tmp2
);
6726 store_reg_bx(env
, s
, rd
, tmp2
);
6729 if (op1
!= 0x0f && op1
!= 0x0d) {
6730 tcg_temp_free_i32(tmp2
);
6733 /* other instructions */
6734 op1
= (insn
>> 24) & 0xf;
6738 /* multiplies, extra load/stores */
6739 sh
= (insn
>> 5) & 3;
6742 rd
= (insn
>> 16) & 0xf;
6743 rn
= (insn
>> 12) & 0xf;
6744 rs
= (insn
>> 8) & 0xf;
6746 op1
= (insn
>> 20) & 0xf;
6748 case 0: case 1: case 2: case 3: case 6:
6750 tmp
= load_reg(s
, rs
);
6751 tmp2
= load_reg(s
, rm
);
6752 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
6753 tcg_temp_free_i32(tmp2
);
6754 if (insn
& (1 << 22)) {
6755 /* Subtract (mls) */
6757 tmp2
= load_reg(s
, rn
);
6758 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6759 tcg_temp_free_i32(tmp2
);
6760 } else if (insn
& (1 << 21)) {
6762 tmp2
= load_reg(s
, rn
);
6763 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6764 tcg_temp_free_i32(tmp2
);
6766 if (insn
& (1 << 20))
6768 store_reg(s
, rd
, tmp
);
6771 /* 64 bit mul double accumulate (UMAAL) */
6773 tmp
= load_reg(s
, rs
);
6774 tmp2
= load_reg(s
, rm
);
6775 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
6776 gen_addq_lo(s
, tmp64
, rn
);
6777 gen_addq_lo(s
, tmp64
, rd
);
6778 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6779 tcg_temp_free_i64(tmp64
);
6781 case 8: case 9: case 10: case 11:
6782 case 12: case 13: case 14: case 15:
6783 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6784 tmp
= load_reg(s
, rs
);
6785 tmp2
= load_reg(s
, rm
);
6786 if (insn
& (1 << 22)) {
6787 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6789 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
6791 if (insn
& (1 << 21)) { /* mult accumulate */
6792 gen_addq(s
, tmp64
, rn
, rd
);
6794 if (insn
& (1 << 20)) {
6795 gen_logicq_cc(tmp64
);
6797 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6798 tcg_temp_free_i64(tmp64
);
6804 rn
= (insn
>> 16) & 0xf;
6805 rd
= (insn
>> 12) & 0xf;
6806 if (insn
& (1 << 23)) {
6807 /* load/store exclusive */
6808 op1
= (insn
>> 21) & 0x3;
6813 addr
= tcg_temp_local_new_i32();
6814 load_reg_var(s
, addr
, rn
);
6815 if (insn
& (1 << 20)) {
6818 gen_load_exclusive(s
, rd
, 15, addr
, 2);
6820 case 1: /* ldrexd */
6821 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
6823 case 2: /* ldrexb */
6824 gen_load_exclusive(s
, rd
, 15, addr
, 0);
6826 case 3: /* ldrexh */
6827 gen_load_exclusive(s
, rd
, 15, addr
, 1);
6836 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
6838 case 1: /* strexd */
6839 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
6841 case 2: /* strexb */
6842 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
6844 case 3: /* strexh */
6845 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
6851 tcg_temp_free(addr
);
6853 /* SWP instruction */
6856 /* ??? This is not really atomic. However we know
6857 we never have multiple CPUs running in parallel,
6858 so it is good enough. */
6859 addr
= load_reg(s
, rn
);
6860 tmp
= load_reg(s
, rm
);
6861 if (insn
& (1 << 22)) {
6862 tmp2
= gen_ld8u(addr
, IS_USER(s
));
6863 gen_st8(tmp
, addr
, IS_USER(s
));
6865 tmp2
= gen_ld32(addr
, IS_USER(s
));
6866 gen_st32(tmp
, addr
, IS_USER(s
));
6868 tcg_temp_free_i32(addr
);
6869 store_reg(s
, rd
, tmp2
);
6875 /* Misc load/store */
6876 rn
= (insn
>> 16) & 0xf;
6877 rd
= (insn
>> 12) & 0xf;
6878 addr
= load_reg(s
, rn
);
6879 if (insn
& (1 << 24))
6880 gen_add_datah_offset(s
, insn
, 0, addr
);
6882 if (insn
& (1 << 20)) {
6886 tmp
= gen_ld16u(addr
, IS_USER(s
));
6889 tmp
= gen_ld8s(addr
, IS_USER(s
));
6893 tmp
= gen_ld16s(addr
, IS_USER(s
));
6897 } else if (sh
& 2) {
6902 tmp
= load_reg(s
, rd
);
6903 gen_st32(tmp
, addr
, IS_USER(s
));
6904 tcg_gen_addi_i32(addr
, addr
, 4);
6905 tmp
= load_reg(s
, rd
+ 1);
6906 gen_st32(tmp
, addr
, IS_USER(s
));
6910 tmp
= gen_ld32(addr
, IS_USER(s
));
6911 store_reg(s
, rd
, tmp
);
6912 tcg_gen_addi_i32(addr
, addr
, 4);
6913 tmp
= gen_ld32(addr
, IS_USER(s
));
6917 address_offset
= -4;
6920 tmp
= load_reg(s
, rd
);
6921 gen_st16(tmp
, addr
, IS_USER(s
));
6924 /* Perform base writeback before the loaded value to
6925 ensure correct behavior with overlapping index registers.
6926 ldrd with base writeback is is undefined if the
6927 destination and index registers overlap. */
6928 if (!(insn
& (1 << 24))) {
6929 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
6930 store_reg(s
, rn
, addr
);
6931 } else if (insn
& (1 << 21)) {
6933 tcg_gen_addi_i32(addr
, addr
, address_offset
);
6934 store_reg(s
, rn
, addr
);
6936 tcg_temp_free_i32(addr
);
6939 /* Complete the load. */
6940 store_reg(s
, rd
, tmp
);
6949 if (insn
& (1 << 4)) {
6951 /* Armv6 Media instructions. */
6953 rn
= (insn
>> 16) & 0xf;
6954 rd
= (insn
>> 12) & 0xf;
6955 rs
= (insn
>> 8) & 0xf;
6956 switch ((insn
>> 23) & 3) {
6957 case 0: /* Parallel add/subtract. */
6958 op1
= (insn
>> 20) & 7;
6959 tmp
= load_reg(s
, rn
);
6960 tmp2
= load_reg(s
, rm
);
6961 sh
= (insn
>> 5) & 7;
6962 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
6964 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
6965 tcg_temp_free_i32(tmp2
);
6966 store_reg(s
, rd
, tmp
);
6969 if ((insn
& 0x00700020) == 0) {
6970 /* Halfword pack. */
6971 tmp
= load_reg(s
, rn
);
6972 tmp2
= load_reg(s
, rm
);
6973 shift
= (insn
>> 7) & 0x1f;
6974 if (insn
& (1 << 6)) {
6978 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
6979 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
6980 tcg_gen_ext16u_i32(tmp2
, tmp2
);
6984 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
6985 tcg_gen_ext16u_i32(tmp
, tmp
);
6986 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
6988 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6989 tcg_temp_free_i32(tmp2
);
6990 store_reg(s
, rd
, tmp
);
6991 } else if ((insn
& 0x00200020) == 0x00200000) {
6993 tmp
= load_reg(s
, rm
);
6994 shift
= (insn
>> 7) & 0x1f;
6995 if (insn
& (1 << 6)) {
6998 tcg_gen_sari_i32(tmp
, tmp
, shift
);
7000 tcg_gen_shli_i32(tmp
, tmp
, shift
);
7002 sh
= (insn
>> 16) & 0x1f;
7003 tmp2
= tcg_const_i32(sh
);
7004 if (insn
& (1 << 22))
7005 gen_helper_usat(tmp
, tmp
, tmp2
);
7007 gen_helper_ssat(tmp
, tmp
, tmp2
);
7008 tcg_temp_free_i32(tmp2
);
7009 store_reg(s
, rd
, tmp
);
7010 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
7012 tmp
= load_reg(s
, rm
);
7013 sh
= (insn
>> 16) & 0x1f;
7014 tmp2
= tcg_const_i32(sh
);
7015 if (insn
& (1 << 22))
7016 gen_helper_usat16(tmp
, tmp
, tmp2
);
7018 gen_helper_ssat16(tmp
, tmp
, tmp2
);
7019 tcg_temp_free_i32(tmp2
);
7020 store_reg(s
, rd
, tmp
);
7021 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
7023 tmp
= load_reg(s
, rn
);
7024 tmp2
= load_reg(s
, rm
);
7025 tmp3
= tcg_temp_new_i32();
7026 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
7027 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
7028 tcg_temp_free_i32(tmp3
);
7029 tcg_temp_free_i32(tmp2
);
7030 store_reg(s
, rd
, tmp
);
7031 } else if ((insn
& 0x000003e0) == 0x00000060) {
7032 tmp
= load_reg(s
, rm
);
7033 shift
= (insn
>> 10) & 3;
7034 /* ??? In many cases it's not neccessary to do a
7035 rotate, a shift is sufficient. */
7037 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
7038 op1
= (insn
>> 20) & 7;
7040 case 0: gen_sxtb16(tmp
); break;
7041 case 2: gen_sxtb(tmp
); break;
7042 case 3: gen_sxth(tmp
); break;
7043 case 4: gen_uxtb16(tmp
); break;
7044 case 6: gen_uxtb(tmp
); break;
7045 case 7: gen_uxth(tmp
); break;
7046 default: goto illegal_op
;
7049 tmp2
= load_reg(s
, rn
);
7050 if ((op1
& 3) == 0) {
7051 gen_add16(tmp
, tmp2
);
7053 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7054 tcg_temp_free_i32(tmp2
);
7057 store_reg(s
, rd
, tmp
);
7058 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
7060 tmp
= load_reg(s
, rm
);
7061 if (insn
& (1 << 22)) {
7062 if (insn
& (1 << 7)) {
7066 gen_helper_rbit(tmp
, tmp
);
7069 if (insn
& (1 << 7))
7072 tcg_gen_bswap32_i32(tmp
, tmp
);
7074 store_reg(s
, rd
, tmp
);
7079 case 2: /* Multiplies (Type 3). */
7080 tmp
= load_reg(s
, rm
);
7081 tmp2
= load_reg(s
, rs
);
7082 if (insn
& (1 << 20)) {
7083 /* Signed multiply most significant [accumulate].
7084 (SMMUL, SMMLA, SMMLS) */
7085 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7088 tmp
= load_reg(s
, rd
);
7089 if (insn
& (1 << 6)) {
7090 tmp64
= gen_subq_msw(tmp64
, tmp
);
7092 tmp64
= gen_addq_msw(tmp64
, tmp
);
7095 if (insn
& (1 << 5)) {
7096 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
7098 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7099 tmp
= tcg_temp_new_i32();
7100 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7101 tcg_temp_free_i64(tmp64
);
7102 store_reg(s
, rn
, tmp
);
7104 if (insn
& (1 << 5))
7105 gen_swap_half(tmp2
);
7106 gen_smul_dual(tmp
, tmp2
);
7107 if (insn
& (1 << 6)) {
7108 /* This subtraction cannot overflow. */
7109 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7111 /* This addition cannot overflow 32 bits;
7112 * however it may overflow considered as a signed
7113 * operation, in which case we must set the Q flag.
7115 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7117 tcg_temp_free_i32(tmp2
);
7118 if (insn
& (1 << 22)) {
7119 /* smlald, smlsld */
7120 tmp64
= tcg_temp_new_i64();
7121 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7122 tcg_temp_free_i32(tmp
);
7123 gen_addq(s
, tmp64
, rd
, rn
);
7124 gen_storeq_reg(s
, rd
, rn
, tmp64
);
7125 tcg_temp_free_i64(tmp64
);
7127 /* smuad, smusd, smlad, smlsd */
7130 tmp2
= load_reg(s
, rd
);
7131 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7132 tcg_temp_free_i32(tmp2
);
7134 store_reg(s
, rn
, tmp
);
7139 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
7141 case 0: /* Unsigned sum of absolute differences. */
7143 tmp
= load_reg(s
, rm
);
7144 tmp2
= load_reg(s
, rs
);
7145 gen_helper_usad8(tmp
, tmp
, tmp2
);
7146 tcg_temp_free_i32(tmp2
);
7148 tmp2
= load_reg(s
, rd
);
7149 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7150 tcg_temp_free_i32(tmp2
);
7152 store_reg(s
, rn
, tmp
);
7154 case 0x20: case 0x24: case 0x28: case 0x2c:
7155 /* Bitfield insert/clear. */
7157 shift
= (insn
>> 7) & 0x1f;
7158 i
= (insn
>> 16) & 0x1f;
7161 tmp
= tcg_temp_new_i32();
7162 tcg_gen_movi_i32(tmp
, 0);
7164 tmp
= load_reg(s
, rm
);
7167 tmp2
= load_reg(s
, rd
);
7168 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << i
) - 1);
7169 tcg_temp_free_i32(tmp2
);
7171 store_reg(s
, rd
, tmp
);
7173 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7174 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7176 tmp
= load_reg(s
, rm
);
7177 shift
= (insn
>> 7) & 0x1f;
7178 i
= ((insn
>> 16) & 0x1f) + 1;
7183 gen_ubfx(tmp
, shift
, (1u << i
) - 1);
7185 gen_sbfx(tmp
, shift
, i
);
7188 store_reg(s
, rd
, tmp
);
7198 /* Check for undefined extension instructions
7199 * per the ARM Bible IE:
7200 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7202 sh
= (0xf << 20) | (0xf << 4);
7203 if (op1
== 0x7 && ((insn
& sh
) == sh
))
7207 /* load/store byte/word */
7208 rn
= (insn
>> 16) & 0xf;
7209 rd
= (insn
>> 12) & 0xf;
7210 tmp2
= load_reg(s
, rn
);
7211 i
= (IS_USER(s
) || (insn
& 0x01200000) == 0x00200000);
7212 if (insn
& (1 << 24))
7213 gen_add_data_offset(s
, insn
, tmp2
);
7214 if (insn
& (1 << 20)) {
7216 if (insn
& (1 << 22)) {
7217 tmp
= gen_ld8u(tmp2
, i
);
7219 tmp
= gen_ld32(tmp2
, i
);
7223 tmp
= load_reg(s
, rd
);
7224 if (insn
& (1 << 22))
7225 gen_st8(tmp
, tmp2
, i
);
7227 gen_st32(tmp
, tmp2
, i
);
7229 if (!(insn
& (1 << 24))) {
7230 gen_add_data_offset(s
, insn
, tmp2
);
7231 store_reg(s
, rn
, tmp2
);
7232 } else if (insn
& (1 << 21)) {
7233 store_reg(s
, rn
, tmp2
);
7235 tcg_temp_free_i32(tmp2
);
7237 if (insn
& (1 << 20)) {
7238 /* Complete the load. */
7239 store_reg_from_load(env
, s
, rd
, tmp
);
7245 int j
, n
, user
, loaded_base
;
7247 /* load/store multiple words */
7248 /* XXX: store correct base if write back */
7250 if (insn
& (1 << 22)) {
7252 goto illegal_op
; /* only usable in supervisor mode */
7254 if ((insn
& (1 << 15)) == 0)
7257 rn
= (insn
>> 16) & 0xf;
7258 addr
= load_reg(s
, rn
);
7260 /* compute total size */
7262 TCGV_UNUSED(loaded_var
);
7265 if (insn
& (1 << i
))
7268 /* XXX: test invalid n == 0 case ? */
7269 if (insn
& (1 << 23)) {
7270 if (insn
& (1 << 24)) {
7272 tcg_gen_addi_i32(addr
, addr
, 4);
7274 /* post increment */
7277 if (insn
& (1 << 24)) {
7279 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7281 /* post decrement */
7283 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7288 if (insn
& (1 << i
)) {
7289 if (insn
& (1 << 20)) {
7291 tmp
= gen_ld32(addr
, IS_USER(s
));
7293 tmp2
= tcg_const_i32(i
);
7294 gen_helper_set_user_reg(tmp2
, tmp
);
7295 tcg_temp_free_i32(tmp2
);
7296 tcg_temp_free_i32(tmp
);
7297 } else if (i
== rn
) {
7301 store_reg_from_load(env
, s
, i
, tmp
);
7306 /* special case: r15 = PC + 8 */
7307 val
= (long)s
->pc
+ 4;
7308 tmp
= tcg_temp_new_i32();
7309 tcg_gen_movi_i32(tmp
, val
);
7311 tmp
= tcg_temp_new_i32();
7312 tmp2
= tcg_const_i32(i
);
7313 gen_helper_get_user_reg(tmp
, tmp2
);
7314 tcg_temp_free_i32(tmp2
);
7316 tmp
= load_reg(s
, i
);
7318 gen_st32(tmp
, addr
, IS_USER(s
));
7321 /* no need to add after the last transfer */
7323 tcg_gen_addi_i32(addr
, addr
, 4);
7326 if (insn
& (1 << 21)) {
7328 if (insn
& (1 << 23)) {
7329 if (insn
& (1 << 24)) {
7332 /* post increment */
7333 tcg_gen_addi_i32(addr
, addr
, 4);
7336 if (insn
& (1 << 24)) {
7339 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7341 /* post decrement */
7342 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7345 store_reg(s
, rn
, addr
);
7347 tcg_temp_free_i32(addr
);
7350 store_reg(s
, rn
, loaded_var
);
7352 if ((insn
& (1 << 22)) && !user
) {
7353 /* Restore CPSR from SPSR. */
7354 tmp
= load_cpu_field(spsr
);
7355 gen_set_cpsr(tmp
, 0xffffffff);
7356 tcg_temp_free_i32(tmp
);
7357 s
->is_jmp
= DISAS_UPDATE
;
7366 /* branch (and link) */
7367 val
= (int32_t)s
->pc
;
7368 if (insn
& (1 << 24)) {
7369 tmp
= tcg_temp_new_i32();
7370 tcg_gen_movi_i32(tmp
, val
);
7371 store_reg(s
, 14, tmp
);
7373 offset
= (((int32_t)insn
<< 8) >> 8);
7374 val
+= (offset
<< 2) + 4;
7382 if (disas_coproc_insn(env
, s
, insn
))
7387 gen_set_pc_im(s
->pc
);
7388 s
->is_jmp
= DISAS_SWI
;
7392 gen_exception_insn(s
, 4, EXCP_UDEF
);
7398 /* Return true if this is a Thumb-2 logical op. */
7400 thumb2_logic_op(int op
)
7405 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7406 then set condition code flags based on the result of the operation.
7407 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7408 to the high bit of T1.
7409 Returns zero if the opcode is valid. */
7412 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
, TCGv t0
, TCGv t1
)
7419 tcg_gen_and_i32(t0
, t0
, t1
);
7423 tcg_gen_andc_i32(t0
, t0
, t1
);
7427 tcg_gen_or_i32(t0
, t0
, t1
);
7431 tcg_gen_orc_i32(t0
, t0
, t1
);
7435 tcg_gen_xor_i32(t0
, t0
, t1
);
7440 gen_helper_add_cc(t0
, t0
, t1
);
7442 tcg_gen_add_i32(t0
, t0
, t1
);
7446 gen_helper_adc_cc(t0
, t0
, t1
);
7452 gen_helper_sbc_cc(t0
, t0
, t1
);
7454 gen_sub_carry(t0
, t0
, t1
);
7458 gen_helper_sub_cc(t0
, t0
, t1
);
7460 tcg_gen_sub_i32(t0
, t0
, t1
);
7464 gen_helper_sub_cc(t0
, t1
, t0
);
7466 tcg_gen_sub_i32(t0
, t1
, t0
);
7468 default: /* 5, 6, 7, 9, 12, 15. */
7474 gen_set_CF_bit31(t1
);
7479 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7481 static int disas_thumb2_insn(CPUState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
7483 uint32_t insn
, imm
, shift
, offset
;
7484 uint32_t rd
, rn
, rm
, rs
;
7495 if (!(arm_feature(env
, ARM_FEATURE_THUMB2
)
7496 || arm_feature (env
, ARM_FEATURE_M
))) {
7497 /* Thumb-1 cores may need to treat bl and blx as a pair of
7498 16-bit instructions to get correct prefetch abort behavior. */
7500 if ((insn
& (1 << 12)) == 0) {
7502 /* Second half of blx. */
7503 offset
= ((insn
& 0x7ff) << 1);
7504 tmp
= load_reg(s
, 14);
7505 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7506 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
7508 tmp2
= tcg_temp_new_i32();
7509 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7510 store_reg(s
, 14, tmp2
);
7514 if (insn
& (1 << 11)) {
7515 /* Second half of bl. */
7516 offset
= ((insn
& 0x7ff) << 1) | 1;
7517 tmp
= load_reg(s
, 14);
7518 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7520 tmp2
= tcg_temp_new_i32();
7521 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7522 store_reg(s
, 14, tmp2
);
7526 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
7527 /* Instruction spans a page boundary. Implement it as two
7528 16-bit instructions in case the second half causes an
7530 offset
= ((int32_t)insn
<< 21) >> 9;
7531 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
7534 /* Fall through to 32-bit decode. */
7537 insn
= lduw_code(s
->pc
);
7539 insn
|= (uint32_t)insn_hw1
<< 16;
7541 if ((insn
& 0xf800e800) != 0xf000e800) {
7545 rn
= (insn
>> 16) & 0xf;
7546 rs
= (insn
>> 12) & 0xf;
7547 rd
= (insn
>> 8) & 0xf;
7549 switch ((insn
>> 25) & 0xf) {
7550 case 0: case 1: case 2: case 3:
7551 /* 16-bit instructions. Should never happen. */
7554 if (insn
& (1 << 22)) {
7555 /* Other load/store, table branch. */
7556 if (insn
& 0x01200000) {
7557 /* Load/store doubleword. */
7559 addr
= tcg_temp_new_i32();
7560 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
7562 addr
= load_reg(s
, rn
);
7564 offset
= (insn
& 0xff) * 4;
7565 if ((insn
& (1 << 23)) == 0)
7567 if (insn
& (1 << 24)) {
7568 tcg_gen_addi_i32(addr
, addr
, offset
);
7571 if (insn
& (1 << 20)) {
7573 tmp
= gen_ld32(addr
, IS_USER(s
));
7574 store_reg(s
, rs
, tmp
);
7575 tcg_gen_addi_i32(addr
, addr
, 4);
7576 tmp
= gen_ld32(addr
, IS_USER(s
));
7577 store_reg(s
, rd
, tmp
);
7580 tmp
= load_reg(s
, rs
);
7581 gen_st32(tmp
, addr
, IS_USER(s
));
7582 tcg_gen_addi_i32(addr
, addr
, 4);
7583 tmp
= load_reg(s
, rd
);
7584 gen_st32(tmp
, addr
, IS_USER(s
));
7586 if (insn
& (1 << 21)) {
7587 /* Base writeback. */
7590 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
7591 store_reg(s
, rn
, addr
);
7593 tcg_temp_free_i32(addr
);
7595 } else if ((insn
& (1 << 23)) == 0) {
7596 /* Load/store exclusive word. */
7597 addr
= tcg_temp_local_new();
7598 load_reg_var(s
, addr
, rn
);
7599 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
7600 if (insn
& (1 << 20)) {
7601 gen_load_exclusive(s
, rs
, 15, addr
, 2);
7603 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
7605 tcg_temp_free(addr
);
7606 } else if ((insn
& (1 << 6)) == 0) {
7609 addr
= tcg_temp_new_i32();
7610 tcg_gen_movi_i32(addr
, s
->pc
);
7612 addr
= load_reg(s
, rn
);
7614 tmp
= load_reg(s
, rm
);
7615 tcg_gen_add_i32(addr
, addr
, tmp
);
7616 if (insn
& (1 << 4)) {
7618 tcg_gen_add_i32(addr
, addr
, tmp
);
7619 tcg_temp_free_i32(tmp
);
7620 tmp
= gen_ld16u(addr
, IS_USER(s
));
7622 tcg_temp_free_i32(tmp
);
7623 tmp
= gen_ld8u(addr
, IS_USER(s
));
7625 tcg_temp_free_i32(addr
);
7626 tcg_gen_shli_i32(tmp
, tmp
, 1);
7627 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
7628 store_reg(s
, 15, tmp
);
7630 /* Load/store exclusive byte/halfword/doubleword. */
7632 op
= (insn
>> 4) & 0x3;
7636 addr
= tcg_temp_local_new();
7637 load_reg_var(s
, addr
, rn
);
7638 if (insn
& (1 << 20)) {
7639 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
7641 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
7643 tcg_temp_free(addr
);
7646 /* Load/store multiple, RFE, SRS. */
7647 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
7648 /* Not available in user mode. */
7651 if (insn
& (1 << 20)) {
7653 addr
= load_reg(s
, rn
);
7654 if ((insn
& (1 << 24)) == 0)
7655 tcg_gen_addi_i32(addr
, addr
, -8);
7656 /* Load PC into tmp and CPSR into tmp2. */
7657 tmp
= gen_ld32(addr
, 0);
7658 tcg_gen_addi_i32(addr
, addr
, 4);
7659 tmp2
= gen_ld32(addr
, 0);
7660 if (insn
& (1 << 21)) {
7661 /* Base writeback. */
7662 if (insn
& (1 << 24)) {
7663 tcg_gen_addi_i32(addr
, addr
, 4);
7665 tcg_gen_addi_i32(addr
, addr
, -4);
7667 store_reg(s
, rn
, addr
);
7669 tcg_temp_free_i32(addr
);
7671 gen_rfe(s
, tmp
, tmp2
);
7675 addr
= tcg_temp_new_i32();
7676 tmp
= tcg_const_i32(op
);
7677 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7678 tcg_temp_free_i32(tmp
);
7679 if ((insn
& (1 << 24)) == 0) {
7680 tcg_gen_addi_i32(addr
, addr
, -8);
7682 tmp
= load_reg(s
, 14);
7683 gen_st32(tmp
, addr
, 0);
7684 tcg_gen_addi_i32(addr
, addr
, 4);
7685 tmp
= tcg_temp_new_i32();
7686 gen_helper_cpsr_read(tmp
);
7687 gen_st32(tmp
, addr
, 0);
7688 if (insn
& (1 << 21)) {
7689 if ((insn
& (1 << 24)) == 0) {
7690 tcg_gen_addi_i32(addr
, addr
, -4);
7692 tcg_gen_addi_i32(addr
, addr
, 4);
7694 tmp
= tcg_const_i32(op
);
7695 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7696 tcg_temp_free_i32(tmp
);
7698 tcg_temp_free_i32(addr
);
7703 /* Load/store multiple. */
7704 addr
= load_reg(s
, rn
);
7706 for (i
= 0; i
< 16; i
++) {
7707 if (insn
& (1 << i
))
7710 if (insn
& (1 << 24)) {
7711 tcg_gen_addi_i32(addr
, addr
, -offset
);
7714 for (i
= 0; i
< 16; i
++) {
7715 if ((insn
& (1 << i
)) == 0)
7717 if (insn
& (1 << 20)) {
7719 tmp
= gen_ld32(addr
, IS_USER(s
));
7723 store_reg(s
, i
, tmp
);
7727 tmp
= load_reg(s
, i
);
7728 gen_st32(tmp
, addr
, IS_USER(s
));
7730 tcg_gen_addi_i32(addr
, addr
, 4);
7732 if (insn
& (1 << 21)) {
7733 /* Base register writeback. */
7734 if (insn
& (1 << 24)) {
7735 tcg_gen_addi_i32(addr
, addr
, -offset
);
7737 /* Fault if writeback register is in register list. */
7738 if (insn
& (1 << rn
))
7740 store_reg(s
, rn
, addr
);
7742 tcg_temp_free_i32(addr
);
7749 op
= (insn
>> 21) & 0xf;
7751 /* Halfword pack. */
7752 tmp
= load_reg(s
, rn
);
7753 tmp2
= load_reg(s
, rm
);
7754 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
7755 if (insn
& (1 << 5)) {
7759 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
7760 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
7761 tcg_gen_ext16u_i32(tmp2
, tmp2
);
7765 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
7766 tcg_gen_ext16u_i32(tmp
, tmp
);
7767 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
7769 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
7770 tcg_temp_free_i32(tmp2
);
7771 store_reg(s
, rd
, tmp
);
7773 /* Data processing register constant shift. */
7775 tmp
= tcg_temp_new_i32();
7776 tcg_gen_movi_i32(tmp
, 0);
7778 tmp
= load_reg(s
, rn
);
7780 tmp2
= load_reg(s
, rm
);
7782 shiftop
= (insn
>> 4) & 3;
7783 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
7784 conds
= (insn
& (1 << 20)) != 0;
7785 logic_cc
= (conds
&& thumb2_logic_op(op
));
7786 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
7787 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
7789 tcg_temp_free_i32(tmp2
);
7791 store_reg(s
, rd
, tmp
);
7793 tcg_temp_free_i32(tmp
);
7797 case 13: /* Misc data processing. */
7798 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
7799 if (op
< 4 && (insn
& 0xf000) != 0xf000)
7802 case 0: /* Register controlled shift. */
7803 tmp
= load_reg(s
, rn
);
7804 tmp2
= load_reg(s
, rm
);
7805 if ((insn
& 0x70) != 0)
7807 op
= (insn
>> 21) & 3;
7808 logic_cc
= (insn
& (1 << 20)) != 0;
7809 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
7812 store_reg_bx(env
, s
, rd
, tmp
);
7814 case 1: /* Sign/zero extend. */
7815 tmp
= load_reg(s
, rm
);
7816 shift
= (insn
>> 4) & 3;
7817 /* ??? In many cases it's not neccessary to do a
7818 rotate, a shift is sufficient. */
7820 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
7821 op
= (insn
>> 20) & 7;
7823 case 0: gen_sxth(tmp
); break;
7824 case 1: gen_uxth(tmp
); break;
7825 case 2: gen_sxtb16(tmp
); break;
7826 case 3: gen_uxtb16(tmp
); break;
7827 case 4: gen_sxtb(tmp
); break;
7828 case 5: gen_uxtb(tmp
); break;
7829 default: goto illegal_op
;
7832 tmp2
= load_reg(s
, rn
);
7833 if ((op
>> 1) == 1) {
7834 gen_add16(tmp
, tmp2
);
7836 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7837 tcg_temp_free_i32(tmp2
);
7840 store_reg(s
, rd
, tmp
);
7842 case 2: /* SIMD add/subtract. */
7843 op
= (insn
>> 20) & 7;
7844 shift
= (insn
>> 4) & 7;
7845 if ((op
& 3) == 3 || (shift
& 3) == 3)
7847 tmp
= load_reg(s
, rn
);
7848 tmp2
= load_reg(s
, rm
);
7849 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
7850 tcg_temp_free_i32(tmp2
);
7851 store_reg(s
, rd
, tmp
);
7853 case 3: /* Other data processing. */
7854 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
7856 /* Saturating add/subtract. */
7857 tmp
= load_reg(s
, rn
);
7858 tmp2
= load_reg(s
, rm
);
7860 gen_helper_double_saturate(tmp
, tmp
);
7862 gen_helper_sub_saturate(tmp
, tmp2
, tmp
);
7864 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
7865 tcg_temp_free_i32(tmp2
);
7867 tmp
= load_reg(s
, rn
);
7869 case 0x0a: /* rbit */
7870 gen_helper_rbit(tmp
, tmp
);
7872 case 0x08: /* rev */
7873 tcg_gen_bswap32_i32(tmp
, tmp
);
7875 case 0x09: /* rev16 */
7878 case 0x0b: /* revsh */
7881 case 0x10: /* sel */
7882 tmp2
= load_reg(s
, rm
);
7883 tmp3
= tcg_temp_new_i32();
7884 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
7885 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
7886 tcg_temp_free_i32(tmp3
);
7887 tcg_temp_free_i32(tmp2
);
7889 case 0x18: /* clz */
7890 gen_helper_clz(tmp
, tmp
);
7896 store_reg(s
, rd
, tmp
);
7898 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7899 op
= (insn
>> 4) & 0xf;
7900 tmp
= load_reg(s
, rn
);
7901 tmp2
= load_reg(s
, rm
);
7902 switch ((insn
>> 20) & 7) {
7903 case 0: /* 32 x 32 -> 32 */
7904 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
7905 tcg_temp_free_i32(tmp2
);
7907 tmp2
= load_reg(s
, rs
);
7909 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7911 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7912 tcg_temp_free_i32(tmp2
);
7915 case 1: /* 16 x 16 -> 32 */
7916 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
7917 tcg_temp_free_i32(tmp2
);
7919 tmp2
= load_reg(s
, rs
);
7920 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7921 tcg_temp_free_i32(tmp2
);
7924 case 2: /* Dual multiply add. */
7925 case 4: /* Dual multiply subtract. */
7927 gen_swap_half(tmp2
);
7928 gen_smul_dual(tmp
, tmp2
);
7929 if (insn
& (1 << 22)) {
7930 /* This subtraction cannot overflow. */
7931 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7933 /* This addition cannot overflow 32 bits;
7934 * however it may overflow considered as a signed
7935 * operation, in which case we must set the Q flag.
7937 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7939 tcg_temp_free_i32(tmp2
);
7942 tmp2
= load_reg(s
, rs
);
7943 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7944 tcg_temp_free_i32(tmp2
);
7947 case 3: /* 32 * 16 -> 32msb */
7949 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
7952 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7953 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
7954 tmp
= tcg_temp_new_i32();
7955 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7956 tcg_temp_free_i64(tmp64
);
7959 tmp2
= load_reg(s
, rs
);
7960 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7961 tcg_temp_free_i32(tmp2
);
7964 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7965 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7967 tmp
= load_reg(s
, rs
);
7968 if (insn
& (1 << 20)) {
7969 tmp64
= gen_addq_msw(tmp64
, tmp
);
7971 tmp64
= gen_subq_msw(tmp64
, tmp
);
7974 if (insn
& (1 << 4)) {
7975 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
7977 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7978 tmp
= tcg_temp_new_i32();
7979 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7980 tcg_temp_free_i64(tmp64
);
7982 case 7: /* Unsigned sum of absolute differences. */
7983 gen_helper_usad8(tmp
, tmp
, tmp2
);
7984 tcg_temp_free_i32(tmp2
);
7986 tmp2
= load_reg(s
, rs
);
7987 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7988 tcg_temp_free_i32(tmp2
);
7992 store_reg(s
, rd
, tmp
);
7994 case 6: case 7: /* 64-bit multiply, Divide. */
7995 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
7996 tmp
= load_reg(s
, rn
);
7997 tmp2
= load_reg(s
, rm
);
7998 if ((op
& 0x50) == 0x10) {
8000 if (!arm_feature(env
, ARM_FEATURE_DIV
))
8003 gen_helper_udiv(tmp
, tmp
, tmp2
);
8005 gen_helper_sdiv(tmp
, tmp
, tmp2
);
8006 tcg_temp_free_i32(tmp2
);
8007 store_reg(s
, rd
, tmp
);
8008 } else if ((op
& 0xe) == 0xc) {
8009 /* Dual multiply accumulate long. */
8011 gen_swap_half(tmp2
);
8012 gen_smul_dual(tmp
, tmp2
);
8014 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8016 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8018 tcg_temp_free_i32(tmp2
);
8020 tmp64
= tcg_temp_new_i64();
8021 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8022 tcg_temp_free_i32(tmp
);
8023 gen_addq(s
, tmp64
, rs
, rd
);
8024 gen_storeq_reg(s
, rs
, rd
, tmp64
);
8025 tcg_temp_free_i64(tmp64
);
8028 /* Unsigned 64-bit multiply */
8029 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
8033 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
8034 tcg_temp_free_i32(tmp2
);
8035 tmp64
= tcg_temp_new_i64();
8036 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8037 tcg_temp_free_i32(tmp
);
8039 /* Signed 64-bit multiply */
8040 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8045 gen_addq_lo(s
, tmp64
, rs
);
8046 gen_addq_lo(s
, tmp64
, rd
);
8047 } else if (op
& 0x40) {
8048 /* 64-bit accumulate. */
8049 gen_addq(s
, tmp64
, rs
, rd
);
8051 gen_storeq_reg(s
, rs
, rd
, tmp64
);
8052 tcg_temp_free_i64(tmp64
);
8057 case 6: case 7: case 14: case 15:
8059 if (((insn
>> 24) & 3) == 3) {
8060 /* Translate into the equivalent ARM encoding. */
8061 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
8062 if (disas_neon_data_insn(env
, s
, insn
))
8065 if (insn
& (1 << 28))
8067 if (disas_coproc_insn (env
, s
, insn
))
8071 case 8: case 9: case 10: case 11:
8072 if (insn
& (1 << 15)) {
8073 /* Branches, misc control. */
8074 if (insn
& 0x5000) {
8075 /* Unconditional branch. */
8076 /* signextend(hw1[10:0]) -> offset[:12]. */
8077 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
8078 /* hw1[10:0] -> offset[11:1]. */
8079 offset
|= (insn
& 0x7ff) << 1;
8080 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8081 offset[24:22] already have the same value because of the
8082 sign extension above. */
8083 offset
^= ((~insn
) & (1 << 13)) << 10;
8084 offset
^= ((~insn
) & (1 << 11)) << 11;
8086 if (insn
& (1 << 14)) {
8087 /* Branch and link. */
8088 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
8092 if (insn
& (1 << 12)) {
8097 offset
&= ~(uint32_t)2;
8098 /* thumb2 bx, no need to check */
8099 gen_bx_im(s
, offset
);
8101 } else if (((insn
>> 23) & 7) == 7) {
8103 if (insn
& (1 << 13))
8106 if (insn
& (1 << 26)) {
8107 /* Secure monitor call (v6Z) */
8108 goto illegal_op
; /* not implemented. */
8110 op
= (insn
>> 20) & 7;
8112 case 0: /* msr cpsr. */
8114 tmp
= load_reg(s
, rn
);
8115 addr
= tcg_const_i32(insn
& 0xff);
8116 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8117 tcg_temp_free_i32(addr
);
8118 tcg_temp_free_i32(tmp
);
8123 case 1: /* msr spsr. */
8126 tmp
= load_reg(s
, rn
);
8128 msr_mask(env
, s
, (insn
>> 8) & 0xf, op
== 1),
8132 case 2: /* cps, nop-hint. */
8133 if (((insn
>> 8) & 7) == 0) {
8134 gen_nop_hint(s
, insn
& 0xff);
8136 /* Implemented as NOP in user mode. */
8141 if (insn
& (1 << 10)) {
8142 if (insn
& (1 << 7))
8144 if (insn
& (1 << 6))
8146 if (insn
& (1 << 5))
8148 if (insn
& (1 << 9))
8149 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
8151 if (insn
& (1 << 8)) {
8153 imm
|= (insn
& 0x1f);
8156 gen_set_psr_im(s
, offset
, 0, imm
);
8159 case 3: /* Special control operations. */
8161 op
= (insn
>> 4) & 0xf;
8169 /* These execute as NOPs. */
8176 /* Trivial implementation equivalent to bx. */
8177 tmp
= load_reg(s
, rn
);
8180 case 5: /* Exception return. */
8184 if (rn
!= 14 || rd
!= 15) {
8187 tmp
= load_reg(s
, rn
);
8188 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
8189 gen_exception_return(s
, tmp
);
8191 case 6: /* mrs cpsr. */
8192 tmp
= tcg_temp_new_i32();
8194 addr
= tcg_const_i32(insn
& 0xff);
8195 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
8196 tcg_temp_free_i32(addr
);
8198 gen_helper_cpsr_read(tmp
);
8200 store_reg(s
, rd
, tmp
);
8202 case 7: /* mrs spsr. */
8203 /* Not accessible in user mode. */
8204 if (IS_USER(s
) || IS_M(env
))
8206 tmp
= load_cpu_field(spsr
);
8207 store_reg(s
, rd
, tmp
);
8212 /* Conditional branch. */
8213 op
= (insn
>> 22) & 0xf;
8214 /* Generate a conditional jump to next instruction. */
8215 s
->condlabel
= gen_new_label();
8216 gen_test_cc(op
^ 1, s
->condlabel
);
8219 /* offset[11:1] = insn[10:0] */
8220 offset
= (insn
& 0x7ff) << 1;
8221 /* offset[17:12] = insn[21:16]. */
8222 offset
|= (insn
& 0x003f0000) >> 4;
8223 /* offset[31:20] = insn[26]. */
8224 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
8225 /* offset[18] = insn[13]. */
8226 offset
|= (insn
& (1 << 13)) << 5;
8227 /* offset[19] = insn[11]. */
8228 offset
|= (insn
& (1 << 11)) << 8;
8230 /* jump to the offset */
8231 gen_jmp(s
, s
->pc
+ offset
);
8234 /* Data processing immediate. */
8235 if (insn
& (1 << 25)) {
8236 if (insn
& (1 << 24)) {
8237 if (insn
& (1 << 20))
8239 /* Bitfield/Saturate. */
8240 op
= (insn
>> 21) & 7;
8242 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
8244 tmp
= tcg_temp_new_i32();
8245 tcg_gen_movi_i32(tmp
, 0);
8247 tmp
= load_reg(s
, rn
);
8250 case 2: /* Signed bitfield extract. */
8252 if (shift
+ imm
> 32)
8255 gen_sbfx(tmp
, shift
, imm
);
8257 case 6: /* Unsigned bitfield extract. */
8259 if (shift
+ imm
> 32)
8262 gen_ubfx(tmp
, shift
, (1u << imm
) - 1);
8264 case 3: /* Bitfield insert/clear. */
8267 imm
= imm
+ 1 - shift
;
8269 tmp2
= load_reg(s
, rd
);
8270 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << imm
) - 1);
8271 tcg_temp_free_i32(tmp2
);
8276 default: /* Saturate. */
8279 tcg_gen_sari_i32(tmp
, tmp
, shift
);
8281 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8283 tmp2
= tcg_const_i32(imm
);
8286 if ((op
& 1) && shift
== 0)
8287 gen_helper_usat16(tmp
, tmp
, tmp2
);
8289 gen_helper_usat(tmp
, tmp
, tmp2
);
8292 if ((op
& 1) && shift
== 0)
8293 gen_helper_ssat16(tmp
, tmp
, tmp2
);
8295 gen_helper_ssat(tmp
, tmp
, tmp2
);
8297 tcg_temp_free_i32(tmp2
);
8300 store_reg(s
, rd
, tmp
);
8302 imm
= ((insn
& 0x04000000) >> 15)
8303 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
8304 if (insn
& (1 << 22)) {
8305 /* 16-bit immediate. */
8306 imm
|= (insn
>> 4) & 0xf000;
8307 if (insn
& (1 << 23)) {
8309 tmp
= load_reg(s
, rd
);
8310 tcg_gen_ext16u_i32(tmp
, tmp
);
8311 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
8314 tmp
= tcg_temp_new_i32();
8315 tcg_gen_movi_i32(tmp
, imm
);
8318 /* Add/sub 12-bit immediate. */
8320 offset
= s
->pc
& ~(uint32_t)3;
8321 if (insn
& (1 << 23))
8325 tmp
= tcg_temp_new_i32();
8326 tcg_gen_movi_i32(tmp
, offset
);
8328 tmp
= load_reg(s
, rn
);
8329 if (insn
& (1 << 23))
8330 tcg_gen_subi_i32(tmp
, tmp
, imm
);
8332 tcg_gen_addi_i32(tmp
, tmp
, imm
);
8335 store_reg(s
, rd
, tmp
);
8338 int shifter_out
= 0;
8339 /* modified 12-bit immediate. */
8340 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
8341 imm
= (insn
& 0xff);
8344 /* Nothing to do. */
8346 case 1: /* 00XY00XY */
8349 case 2: /* XY00XY00 */
8353 case 3: /* XYXYXYXY */
8357 default: /* Rotated constant. */
8358 shift
= (shift
<< 1) | (imm
>> 7);
8360 imm
= imm
<< (32 - shift
);
8364 tmp2
= tcg_temp_new_i32();
8365 tcg_gen_movi_i32(tmp2
, imm
);
8366 rn
= (insn
>> 16) & 0xf;
8368 tmp
= tcg_temp_new_i32();
8369 tcg_gen_movi_i32(tmp
, 0);
8371 tmp
= load_reg(s
, rn
);
8373 op
= (insn
>> 21) & 0xf;
8374 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
8375 shifter_out
, tmp
, tmp2
))
8377 tcg_temp_free_i32(tmp2
);
8378 rd
= (insn
>> 8) & 0xf;
8380 store_reg(s
, rd
, tmp
);
8382 tcg_temp_free_i32(tmp
);
8387 case 12: /* Load/store single data item. */
8392 if ((insn
& 0x01100000) == 0x01000000) {
8393 if (disas_neon_ls_insn(env
, s
, insn
))
8397 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
8399 if (!(insn
& (1 << 20))) {
8403 /* Byte or halfword load space with dest == r15 : memory hints.
8404 * Catch them early so we don't emit pointless addressing code.
8405 * This space is a mix of:
8406 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8407 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8409 * unallocated hints, which must be treated as NOPs
8410 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8411 * which is easiest for the decoding logic
8412 * Some space which must UNDEF
8414 int op1
= (insn
>> 23) & 3;
8415 int op2
= (insn
>> 6) & 0x3f;
8420 /* UNPREDICTABLE or unallocated hint */
8424 return 0; /* PLD* or unallocated hint */
8426 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
8427 return 0; /* PLD* or unallocated hint */
8429 /* UNDEF space, or an UNPREDICTABLE */
8435 addr
= tcg_temp_new_i32();
8437 /* s->pc has already been incremented by 4. */
8438 imm
= s
->pc
& 0xfffffffc;
8439 if (insn
& (1 << 23))
8440 imm
+= insn
& 0xfff;
8442 imm
-= insn
& 0xfff;
8443 tcg_gen_movi_i32(addr
, imm
);
8445 addr
= load_reg(s
, rn
);
8446 if (insn
& (1 << 23)) {
8447 /* Positive offset. */
8449 tcg_gen_addi_i32(addr
, addr
, imm
);
8452 switch ((insn
>> 8) & 0xf) {
8453 case 0x0: /* Shifted Register. */
8454 shift
= (insn
>> 4) & 0xf;
8456 tcg_temp_free_i32(addr
);
8459 tmp
= load_reg(s
, rm
);
8461 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8462 tcg_gen_add_i32(addr
, addr
, tmp
);
8463 tcg_temp_free_i32(tmp
);
8465 case 0xc: /* Negative offset. */
8466 tcg_gen_addi_i32(addr
, addr
, -imm
);
8468 case 0xe: /* User privilege. */
8469 tcg_gen_addi_i32(addr
, addr
, imm
);
8472 case 0x9: /* Post-decrement. */
8475 case 0xb: /* Post-increment. */
8479 case 0xd: /* Pre-decrement. */
8482 case 0xf: /* Pre-increment. */
8483 tcg_gen_addi_i32(addr
, addr
, imm
);
8487 tcg_temp_free_i32(addr
);
8492 if (insn
& (1 << 20)) {
8495 case 0: tmp
= gen_ld8u(addr
, user
); break;
8496 case 4: tmp
= gen_ld8s(addr
, user
); break;
8497 case 1: tmp
= gen_ld16u(addr
, user
); break;
8498 case 5: tmp
= gen_ld16s(addr
, user
); break;
8499 case 2: tmp
= gen_ld32(addr
, user
); break;
8501 tcg_temp_free_i32(addr
);
8507 store_reg(s
, rs
, tmp
);
8511 tmp
= load_reg(s
, rs
);
8513 case 0: gen_st8(tmp
, addr
, user
); break;
8514 case 1: gen_st16(tmp
, addr
, user
); break;
8515 case 2: gen_st32(tmp
, addr
, user
); break;
8517 tcg_temp_free_i32(addr
);
8522 tcg_gen_addi_i32(addr
, addr
, imm
);
8524 store_reg(s
, rn
, addr
);
8526 tcg_temp_free_i32(addr
);
8538 static void disas_thumb_insn(CPUState
*env
, DisasContext
*s
)
8540 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
8547 if (s
->condexec_mask
) {
8548 cond
= s
->condexec_cond
;
8549 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
8550 s
->condlabel
= gen_new_label();
8551 gen_test_cc(cond
^ 1, s
->condlabel
);
8556 insn
= lduw_code(s
->pc
);
8559 switch (insn
>> 12) {
8563 op
= (insn
>> 11) & 3;
8566 rn
= (insn
>> 3) & 7;
8567 tmp
= load_reg(s
, rn
);
8568 if (insn
& (1 << 10)) {
8570 tmp2
= tcg_temp_new_i32();
8571 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
8574 rm
= (insn
>> 6) & 7;
8575 tmp2
= load_reg(s
, rm
);
8577 if (insn
& (1 << 9)) {
8578 if (s
->condexec_mask
)
8579 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8581 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8583 if (s
->condexec_mask
)
8584 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8586 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8588 tcg_temp_free_i32(tmp2
);
8589 store_reg(s
, rd
, tmp
);
8591 /* shift immediate */
8592 rm
= (insn
>> 3) & 7;
8593 shift
= (insn
>> 6) & 0x1f;
8594 tmp
= load_reg(s
, rm
);
8595 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
8596 if (!s
->condexec_mask
)
8598 store_reg(s
, rd
, tmp
);
8602 /* arithmetic large immediate */
8603 op
= (insn
>> 11) & 3;
8604 rd
= (insn
>> 8) & 0x7;
8605 if (op
== 0) { /* mov */
8606 tmp
= tcg_temp_new_i32();
8607 tcg_gen_movi_i32(tmp
, insn
& 0xff);
8608 if (!s
->condexec_mask
)
8610 store_reg(s
, rd
, tmp
);
8612 tmp
= load_reg(s
, rd
);
8613 tmp2
= tcg_temp_new_i32();
8614 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
8617 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8618 tcg_temp_free_i32(tmp
);
8619 tcg_temp_free_i32(tmp2
);
8622 if (s
->condexec_mask
)
8623 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8625 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8626 tcg_temp_free_i32(tmp2
);
8627 store_reg(s
, rd
, tmp
);
8630 if (s
->condexec_mask
)
8631 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8633 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8634 tcg_temp_free_i32(tmp2
);
8635 store_reg(s
, rd
, tmp
);
8641 if (insn
& (1 << 11)) {
8642 rd
= (insn
>> 8) & 7;
8643 /* load pc-relative. Bit 1 of PC is ignored. */
8644 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
8645 val
&= ~(uint32_t)2;
8646 addr
= tcg_temp_new_i32();
8647 tcg_gen_movi_i32(addr
, val
);
8648 tmp
= gen_ld32(addr
, IS_USER(s
));
8649 tcg_temp_free_i32(addr
);
8650 store_reg(s
, rd
, tmp
);
8653 if (insn
& (1 << 10)) {
8654 /* data processing extended or blx */
8655 rd
= (insn
& 7) | ((insn
>> 4) & 8);
8656 rm
= (insn
>> 3) & 0xf;
8657 op
= (insn
>> 8) & 3;
8660 tmp
= load_reg(s
, rd
);
8661 tmp2
= load_reg(s
, rm
);
8662 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8663 tcg_temp_free_i32(tmp2
);
8664 store_reg(s
, rd
, tmp
);
8667 tmp
= load_reg(s
, rd
);
8668 tmp2
= load_reg(s
, rm
);
8669 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8670 tcg_temp_free_i32(tmp2
);
8671 tcg_temp_free_i32(tmp
);
8673 case 2: /* mov/cpy */
8674 tmp
= load_reg(s
, rm
);
8675 store_reg(s
, rd
, tmp
);
8677 case 3:/* branch [and link] exchange thumb register */
8678 tmp
= load_reg(s
, rm
);
8679 if (insn
& (1 << 7)) {
8681 val
= (uint32_t)s
->pc
| 1;
8682 tmp2
= tcg_temp_new_i32();
8683 tcg_gen_movi_i32(tmp2
, val
);
8684 store_reg(s
, 14, tmp2
);
8686 /* already thumb, no need to check */
8693 /* data processing register */
8695 rm
= (insn
>> 3) & 7;
8696 op
= (insn
>> 6) & 0xf;
8697 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
8698 /* the shift/rotate ops want the operands backwards */
8707 if (op
== 9) { /* neg */
8708 tmp
= tcg_temp_new_i32();
8709 tcg_gen_movi_i32(tmp
, 0);
8710 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
8711 tmp
= load_reg(s
, rd
);
8716 tmp2
= load_reg(s
, rm
);
8719 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8720 if (!s
->condexec_mask
)
8724 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8725 if (!s
->condexec_mask
)
8729 if (s
->condexec_mask
) {
8730 gen_helper_shl(tmp2
, tmp2
, tmp
);
8732 gen_helper_shl_cc(tmp2
, tmp2
, tmp
);
8737 if (s
->condexec_mask
) {
8738 gen_helper_shr(tmp2
, tmp2
, tmp
);
8740 gen_helper_shr_cc(tmp2
, tmp2
, tmp
);
8745 if (s
->condexec_mask
) {
8746 gen_helper_sar(tmp2
, tmp2
, tmp
);
8748 gen_helper_sar_cc(tmp2
, tmp2
, tmp
);
8753 if (s
->condexec_mask
)
8756 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
8759 if (s
->condexec_mask
)
8760 gen_sub_carry(tmp
, tmp
, tmp2
);
8762 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
8765 if (s
->condexec_mask
) {
8766 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
8767 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
8769 gen_helper_ror_cc(tmp2
, tmp2
, tmp
);
8774 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8779 if (s
->condexec_mask
)
8780 tcg_gen_neg_i32(tmp
, tmp2
);
8782 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8785 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8789 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8793 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8794 if (!s
->condexec_mask
)
8798 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8799 if (!s
->condexec_mask
)
8803 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
8804 if (!s
->condexec_mask
)
8808 tcg_gen_not_i32(tmp2
, tmp2
);
8809 if (!s
->condexec_mask
)
8817 store_reg(s
, rm
, tmp2
);
8819 tcg_temp_free_i32(tmp
);
8821 store_reg(s
, rd
, tmp
);
8822 tcg_temp_free_i32(tmp2
);
8825 tcg_temp_free_i32(tmp
);
8826 tcg_temp_free_i32(tmp2
);
8831 /* load/store register offset. */
8833 rn
= (insn
>> 3) & 7;
8834 rm
= (insn
>> 6) & 7;
8835 op
= (insn
>> 9) & 7;
8836 addr
= load_reg(s
, rn
);
8837 tmp
= load_reg(s
, rm
);
8838 tcg_gen_add_i32(addr
, addr
, tmp
);
8839 tcg_temp_free_i32(tmp
);
8841 if (op
< 3) /* store */
8842 tmp
= load_reg(s
, rd
);
8846 gen_st32(tmp
, addr
, IS_USER(s
));
8849 gen_st16(tmp
, addr
, IS_USER(s
));
8852 gen_st8(tmp
, addr
, IS_USER(s
));
8855 tmp
= gen_ld8s(addr
, IS_USER(s
));
8858 tmp
= gen_ld32(addr
, IS_USER(s
));
8861 tmp
= gen_ld16u(addr
, IS_USER(s
));
8864 tmp
= gen_ld8u(addr
, IS_USER(s
));
8867 tmp
= gen_ld16s(addr
, IS_USER(s
));
8870 if (op
>= 3) /* load */
8871 store_reg(s
, rd
, tmp
);
8872 tcg_temp_free_i32(addr
);
8876 /* load/store word immediate offset */
8878 rn
= (insn
>> 3) & 7;
8879 addr
= load_reg(s
, rn
);
8880 val
= (insn
>> 4) & 0x7c;
8881 tcg_gen_addi_i32(addr
, addr
, val
);
8883 if (insn
& (1 << 11)) {
8885 tmp
= gen_ld32(addr
, IS_USER(s
));
8886 store_reg(s
, rd
, tmp
);
8889 tmp
= load_reg(s
, rd
);
8890 gen_st32(tmp
, addr
, IS_USER(s
));
8892 tcg_temp_free_i32(addr
);
8896 /* load/store byte immediate offset */
8898 rn
= (insn
>> 3) & 7;
8899 addr
= load_reg(s
, rn
);
8900 val
= (insn
>> 6) & 0x1f;
8901 tcg_gen_addi_i32(addr
, addr
, val
);
8903 if (insn
& (1 << 11)) {
8905 tmp
= gen_ld8u(addr
, IS_USER(s
));
8906 store_reg(s
, rd
, tmp
);
8909 tmp
= load_reg(s
, rd
);
8910 gen_st8(tmp
, addr
, IS_USER(s
));
8912 tcg_temp_free_i32(addr
);
8916 /* load/store halfword immediate offset */
8918 rn
= (insn
>> 3) & 7;
8919 addr
= load_reg(s
, rn
);
8920 val
= (insn
>> 5) & 0x3e;
8921 tcg_gen_addi_i32(addr
, addr
, val
);
8923 if (insn
& (1 << 11)) {
8925 tmp
= gen_ld16u(addr
, IS_USER(s
));
8926 store_reg(s
, rd
, tmp
);
8929 tmp
= load_reg(s
, rd
);
8930 gen_st16(tmp
, addr
, IS_USER(s
));
8932 tcg_temp_free_i32(addr
);
8936 /* load/store from stack */
8937 rd
= (insn
>> 8) & 7;
8938 addr
= load_reg(s
, 13);
8939 val
= (insn
& 0xff) * 4;
8940 tcg_gen_addi_i32(addr
, addr
, val
);
8942 if (insn
& (1 << 11)) {
8944 tmp
= gen_ld32(addr
, IS_USER(s
));
8945 store_reg(s
, rd
, tmp
);
8948 tmp
= load_reg(s
, rd
);
8949 gen_st32(tmp
, addr
, IS_USER(s
));
8951 tcg_temp_free_i32(addr
);
8955 /* add to high reg */
8956 rd
= (insn
>> 8) & 7;
8957 if (insn
& (1 << 11)) {
8959 tmp
= load_reg(s
, 13);
8961 /* PC. bit 1 is ignored. */
8962 tmp
= tcg_temp_new_i32();
8963 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
8965 val
= (insn
& 0xff) * 4;
8966 tcg_gen_addi_i32(tmp
, tmp
, val
);
8967 store_reg(s
, rd
, tmp
);
8972 op
= (insn
>> 8) & 0xf;
8975 /* adjust stack pointer */
8976 tmp
= load_reg(s
, 13);
8977 val
= (insn
& 0x7f) * 4;
8978 if (insn
& (1 << 7))
8979 val
= -(int32_t)val
;
8980 tcg_gen_addi_i32(tmp
, tmp
, val
);
8981 store_reg(s
, 13, tmp
);
8984 case 2: /* sign/zero extend. */
8987 rm
= (insn
>> 3) & 7;
8988 tmp
= load_reg(s
, rm
);
8989 switch ((insn
>> 6) & 3) {
8990 case 0: gen_sxth(tmp
); break;
8991 case 1: gen_sxtb(tmp
); break;
8992 case 2: gen_uxth(tmp
); break;
8993 case 3: gen_uxtb(tmp
); break;
8995 store_reg(s
, rd
, tmp
);
8997 case 4: case 5: case 0xc: case 0xd:
8999 addr
= load_reg(s
, 13);
9000 if (insn
& (1 << 8))
9004 for (i
= 0; i
< 8; i
++) {
9005 if (insn
& (1 << i
))
9008 if ((insn
& (1 << 11)) == 0) {
9009 tcg_gen_addi_i32(addr
, addr
, -offset
);
9011 for (i
= 0; i
< 8; i
++) {
9012 if (insn
& (1 << i
)) {
9013 if (insn
& (1 << 11)) {
9015 tmp
= gen_ld32(addr
, IS_USER(s
));
9016 store_reg(s
, i
, tmp
);
9019 tmp
= load_reg(s
, i
);
9020 gen_st32(tmp
, addr
, IS_USER(s
));
9022 /* advance to the next address. */
9023 tcg_gen_addi_i32(addr
, addr
, 4);
9027 if (insn
& (1 << 8)) {
9028 if (insn
& (1 << 11)) {
9030 tmp
= gen_ld32(addr
, IS_USER(s
));
9031 /* don't set the pc until the rest of the instruction
9035 tmp
= load_reg(s
, 14);
9036 gen_st32(tmp
, addr
, IS_USER(s
));
9038 tcg_gen_addi_i32(addr
, addr
, 4);
9040 if ((insn
& (1 << 11)) == 0) {
9041 tcg_gen_addi_i32(addr
, addr
, -offset
);
9043 /* write back the new stack pointer */
9044 store_reg(s
, 13, addr
);
9045 /* set the new PC value */
9046 if ((insn
& 0x0900) == 0x0900) {
9047 store_reg_from_load(env
, s
, 15, tmp
);
9051 case 1: case 3: case 9: case 11: /* czb */
9053 tmp
= load_reg(s
, rm
);
9054 s
->condlabel
= gen_new_label();
9056 if (insn
& (1 << 11))
9057 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
9059 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
9060 tcg_temp_free_i32(tmp
);
9061 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
9062 val
= (uint32_t)s
->pc
+ 2;
9067 case 15: /* IT, nop-hint. */
9068 if ((insn
& 0xf) == 0) {
9069 gen_nop_hint(s
, (insn
>> 4) & 0xf);
9073 s
->condexec_cond
= (insn
>> 4) & 0xe;
9074 s
->condexec_mask
= insn
& 0x1f;
9075 /* No actual code generated for this insn, just setup state. */
9078 case 0xe: /* bkpt */
9080 gen_exception_insn(s
, 2, EXCP_BKPT
);
9085 rn
= (insn
>> 3) & 0x7;
9087 tmp
= load_reg(s
, rn
);
9088 switch ((insn
>> 6) & 3) {
9089 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
9090 case 1: gen_rev16(tmp
); break;
9091 case 3: gen_revsh(tmp
); break;
9092 default: goto illegal_op
;
9094 store_reg(s
, rd
, tmp
);
9102 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
9105 addr
= tcg_const_i32(16);
9106 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9107 tcg_temp_free_i32(addr
);
9111 addr
= tcg_const_i32(17);
9112 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9113 tcg_temp_free_i32(addr
);
9115 tcg_temp_free_i32(tmp
);
9118 if (insn
& (1 << 4))
9119 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
9122 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
9132 /* load/store multiple */
9133 rn
= (insn
>> 8) & 0x7;
9134 addr
= load_reg(s
, rn
);
9135 for (i
= 0; i
< 8; i
++) {
9136 if (insn
& (1 << i
)) {
9137 if (insn
& (1 << 11)) {
9139 tmp
= gen_ld32(addr
, IS_USER(s
));
9140 store_reg(s
, i
, tmp
);
9143 tmp
= load_reg(s
, i
);
9144 gen_st32(tmp
, addr
, IS_USER(s
));
9146 /* advance to the next address */
9147 tcg_gen_addi_i32(addr
, addr
, 4);
9150 /* Base register writeback. */
9151 if ((insn
& (1 << rn
)) == 0) {
9152 store_reg(s
, rn
, addr
);
9154 tcg_temp_free_i32(addr
);
9159 /* conditional branch or swi */
9160 cond
= (insn
>> 8) & 0xf;
9166 gen_set_pc_im(s
->pc
);
9167 s
->is_jmp
= DISAS_SWI
;
9170 /* generate a conditional jump to next instruction */
9171 s
->condlabel
= gen_new_label();
9172 gen_test_cc(cond
^ 1, s
->condlabel
);
9175 /* jump to the offset */
9176 val
= (uint32_t)s
->pc
+ 2;
9177 offset
= ((int32_t)insn
<< 24) >> 24;
9183 if (insn
& (1 << 11)) {
9184 if (disas_thumb2_insn(env
, s
, insn
))
9188 /* unconditional branch */
9189 val
= (uint32_t)s
->pc
;
9190 offset
= ((int32_t)insn
<< 21) >> 21;
9191 val
+= (offset
<< 1) + 2;
9196 if (disas_thumb2_insn(env
, s
, insn
))
9202 gen_exception_insn(s
, 4, EXCP_UDEF
);
9206 gen_exception_insn(s
, 2, EXCP_UDEF
);
9209 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9210 basic block 'tb'. If search_pc is TRUE, also generate PC
9211 information for each intermediate instruction. */
9212 static inline void gen_intermediate_code_internal(CPUState
*env
,
9213 TranslationBlock
*tb
,
9216 DisasContext dc1
, *dc
= &dc1
;
9218 uint16_t *gen_opc_end
;
9220 target_ulong pc_start
;
9221 uint32_t next_page_start
;
9225 /* generate intermediate code */
9230 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9232 dc
->is_jmp
= DISAS_NEXT
;
9234 dc
->singlestep_enabled
= env
->singlestep_enabled
;
9236 dc
->thumb
= ARM_TBFLAG_THUMB(tb
->flags
);
9237 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(tb
->flags
) & 0xf) << 1;
9238 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(tb
->flags
) >> 4;
9239 #if !defined(CONFIG_USER_ONLY)
9240 dc
->user
= (ARM_TBFLAG_PRIV(tb
->flags
) == 0);
9242 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(tb
->flags
);
9243 dc
->vec_len
= ARM_TBFLAG_VECLEN(tb
->flags
);
9244 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(tb
->flags
);
9245 cpu_F0s
= tcg_temp_new_i32();
9246 cpu_F1s
= tcg_temp_new_i32();
9247 cpu_F0d
= tcg_temp_new_i64();
9248 cpu_F1d
= tcg_temp_new_i64();
9251 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9252 cpu_M0
= tcg_temp_new_i64();
9253 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
9256 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9258 max_insns
= CF_COUNT_MASK
;
9262 tcg_clear_temp_count();
9264 /* A note on handling of the condexec (IT) bits:
9266 * We want to avoid the overhead of having to write the updated condexec
9267 * bits back to the CPUState for every instruction in an IT block. So:
9268 * (1) if the condexec bits are not already zero then we write
9269 * zero back into the CPUState now. This avoids complications trying
9270 * to do it at the end of the block. (For example if we don't do this
9271 * it's hard to identify whether we can safely skip writing condexec
9272 * at the end of the TB, which we definitely want to do for the case
9273 * where a TB doesn't do anything with the IT state at all.)
9274 * (2) if we are going to leave the TB then we call gen_set_condexec()
9275 * which will write the correct value into CPUState if zero is wrong.
9276 * This is done both for leaving the TB at the end, and for leaving
9277 * it because of an exception we know will happen, which is done in
9278 * gen_exception_insn(). The latter is necessary because we need to
9279 * leave the TB with the PC/IT state just prior to execution of the
9280 * instruction which caused the exception.
9281 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9282 * then the CPUState will be wrong and we need to reset it.
9283 * This is handled in the same way as restoration of the
9284 * PC in these situations: we will be called again with search_pc=1
9285 * and generate a mapping of the condexec bits for each PC in
9286 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9287 * the condexec bits.
9289 * Note that there are no instructions which can read the condexec
9290 * bits, and none which can write non-static values to them, so
9291 * we don't need to care about whether CPUState is correct in the
9295 /* Reset the conditional execution bits immediately. This avoids
9296 complications trying to do it at the end of the block. */
9297 if (dc
->condexec_mask
|| dc
->condexec_cond
)
9299 TCGv tmp
= tcg_temp_new_i32();
9300 tcg_gen_movi_i32(tmp
, 0);
9301 store_cpu_field(tmp
, condexec_bits
);
9304 #ifdef CONFIG_USER_ONLY
9305 /* Intercept jump to the magic kernel page. */
9306 if (dc
->pc
>= 0xffff0000) {
9307 /* We always get here via a jump, so know we are not in a
9308 conditional execution block. */
9309 gen_exception(EXCP_KERNEL_TRAP
);
9310 dc
->is_jmp
= DISAS_UPDATE
;
9314 if (dc
->pc
>= 0xfffffff0 && IS_M(env
)) {
9315 /* We always get here via a jump, so know we are not in a
9316 conditional execution block. */
9317 gen_exception(EXCP_EXCEPTION_EXIT
);
9318 dc
->is_jmp
= DISAS_UPDATE
;
9323 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9324 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9325 if (bp
->pc
== dc
->pc
) {
9326 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
9327 /* Advance PC so that clearing the breakpoint will
9328 invalidate this TB. */
9330 goto done_generating
;
9336 j
= gen_opc_ptr
- gen_opc_buf
;
9340 gen_opc_instr_start
[lj
++] = 0;
9342 gen_opc_pc
[lj
] = dc
->pc
;
9343 gen_opc_condexec_bits
[lj
] = (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1);
9344 gen_opc_instr_start
[lj
] = 1;
9345 gen_opc_icount
[lj
] = num_insns
;
9348 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9351 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
9352 tcg_gen_debug_insn_start(dc
->pc
);
9356 disas_thumb_insn(env
, dc
);
9357 if (dc
->condexec_mask
) {
9358 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
9359 | ((dc
->condexec_mask
>> 4) & 1);
9360 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
9361 if (dc
->condexec_mask
== 0) {
9362 dc
->condexec_cond
= 0;
9366 disas_arm_insn(env
, dc
);
9369 if (dc
->condjmp
&& !dc
->is_jmp
) {
9370 gen_set_label(dc
->condlabel
);
9374 if (tcg_check_temp_count()) {
9375 fprintf(stderr
, "TCG temporary leak before %08x\n", dc
->pc
);
9378 /* Translation stops when a conditional branch is encountered.
9379 * Otherwise the subsequent code could get translated several times.
9380 * Also stop translation when a page boundary is reached. This
9381 * ensures prefetch aborts occur at the right place. */
9383 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
9384 !env
->singlestep_enabled
&&
9386 dc
->pc
< next_page_start
&&
9387 num_insns
< max_insns
);
9389 if (tb
->cflags
& CF_LAST_IO
) {
9391 /* FIXME: This can theoretically happen with self-modifying
9393 cpu_abort(env
, "IO on conditional branch instruction");
9398 /* At this stage dc->condjmp will only be set when the skipped
9399 instruction was a conditional branch or trap, and the PC has
9400 already been written. */
9401 if (unlikely(env
->singlestep_enabled
)) {
9402 /* Make sure the pc is updated, and raise a debug exception. */
9404 gen_set_condexec(dc
);
9405 if (dc
->is_jmp
== DISAS_SWI
) {
9406 gen_exception(EXCP_SWI
);
9408 gen_exception(EXCP_DEBUG
);
9410 gen_set_label(dc
->condlabel
);
9412 if (dc
->condjmp
|| !dc
->is_jmp
) {
9413 gen_set_pc_im(dc
->pc
);
9416 gen_set_condexec(dc
);
9417 if (dc
->is_jmp
== DISAS_SWI
&& !dc
->condjmp
) {
9418 gen_exception(EXCP_SWI
);
9420 /* FIXME: Single stepping a WFI insn will not halt
9422 gen_exception(EXCP_DEBUG
);
9425 /* While branches must always occur at the end of an IT block,
9426 there are a few other things that can cause us to terminate
9427 the TB in the middel of an IT block:
9428 - Exception generating instructions (bkpt, swi, undefined).
9430 - Hardware watchpoints.
9431 Hardware breakpoints have already been handled and skip this code.
9433 gen_set_condexec(dc
);
9434 switch(dc
->is_jmp
) {
9436 gen_goto_tb(dc
, 1, dc
->pc
);
9441 /* indicate that the hash table must be used to find the next TB */
9445 /* nothing more to generate */
9451 gen_exception(EXCP_SWI
);
9455 gen_set_label(dc
->condlabel
);
9456 gen_set_condexec(dc
);
9457 gen_goto_tb(dc
, 1, dc
->pc
);
9463 gen_icount_end(tb
, num_insns
);
9464 *gen_opc_ptr
= INDEX_op_end
;
9467 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9468 qemu_log("----------------\n");
9469 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9470 log_target_disas(pc_start
, dc
->pc
- pc_start
, dc
->thumb
);
9475 j
= gen_opc_ptr
- gen_opc_buf
;
9478 gen_opc_instr_start
[lj
++] = 0;
9480 tb
->size
= dc
->pc
- pc_start
;
9481 tb
->icount
= num_insns
;
9485 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
9487 gen_intermediate_code_internal(env
, tb
, 0);
9490 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
9492 gen_intermediate_code_internal(env
, tb
, 1);
9495 static const char *cpu_mode_names
[16] = {
9496 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9497 "???", "???", "???", "und", "???", "???", "???", "sys"
9500 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9510 /* ??? This assumes float64 and double have the same layout.
9511 Oh well, it's only debug dumps. */
9520 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
9522 cpu_fprintf(f
, "\n");
9524 cpu_fprintf(f
, " ");
9526 psr
= cpsr_read(env
);
9527 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%d\n",
9529 psr
& (1 << 31) ? 'N' : '-',
9530 psr
& (1 << 30) ? 'Z' : '-',
9531 psr
& (1 << 29) ? 'C' : '-',
9532 psr
& (1 << 28) ? 'V' : '-',
9533 psr
& CPSR_T
? 'T' : 'A',
9534 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
9537 for (i
= 0; i
< 16; i
++) {
9538 d
.d
= env
->vfp
.regs
[i
];
9542 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9543 i
* 2, (int)s0
.i
, s0
.s
,
9544 i
* 2 + 1, (int)s1
.i
, s1
.s
,
9545 i
, (int)(uint32_t)d
.l
.upper
, (int)(uint32_t)d
.l
.lower
,
9548 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
9552 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
9553 unsigned long searched_pc
, int pc_pos
, void *puc
)
9555 env
->regs
[15] = gen_opc_pc
[pc_pos
];
9556 env
->condexec_bits
= gen_opc_condexec_bits
[pc_pos
];