4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
45 /* internal defines */
46 typedef struct DisasContext
{
49 /* Nonzero if this instruction has been conditionally skipped. */
51 /* The label that will be jumped to when the instruction is skipped. */
53 /* Thumb-2 condtional execution bits. */
56 struct TranslationBlock
*tb
;
57 int singlestep_enabled
;
59 #if !defined(CONFIG_USER_ONLY)
67 static uint32_t gen_opc_condexec_bits
[OPC_BUF_SIZE
];
69 #if defined(CONFIG_USER_ONLY)
72 #define IS_USER(s) (s->user)
75 /* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
80 static TCGv_ptr cpu_env
;
81 /* We reuse the same 64-bit temporaries for efficiency. */
82 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
83 static TCGv_i32 cpu_R
[16];
84 static TCGv_i32 cpu_exclusive_addr
;
85 static TCGv_i32 cpu_exclusive_val
;
86 static TCGv_i32 cpu_exclusive_high
;
87 #ifdef CONFIG_USER_ONLY
88 static TCGv_i32 cpu_exclusive_test
;
89 static TCGv_i32 cpu_exclusive_info
;
92 /* FIXME: These should be removed. */
93 static TCGv cpu_F0s
, cpu_F1s
;
94 static TCGv_i64 cpu_F0d
, cpu_F1d
;
96 #include "gen-icount.h"
98 static const char *regnames
[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
102 /* initialize TCG globals. */
103 void arm_translate_init(void)
107 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
109 for (i
= 0; i
< 16; i
++) {
110 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
111 offsetof(CPUState
, regs
[i
]),
114 cpu_exclusive_addr
= tcg_global_mem_new_i32(TCG_AREG0
,
115 offsetof(CPUState
, exclusive_addr
), "exclusive_addr");
116 cpu_exclusive_val
= tcg_global_mem_new_i32(TCG_AREG0
,
117 offsetof(CPUState
, exclusive_val
), "exclusive_val");
118 cpu_exclusive_high
= tcg_global_mem_new_i32(TCG_AREG0
,
119 offsetof(CPUState
, exclusive_high
), "exclusive_high");
120 #ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test
= tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUState
, exclusive_test
), "exclusive_test");
123 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
124 offsetof(CPUState
, exclusive_info
), "exclusive_info");
131 static inline TCGv
load_cpu_offset(int offset
)
133 TCGv tmp
= tcg_temp_new_i32();
134 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
138 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
140 static inline void store_cpu_offset(TCGv var
, int offset
)
142 tcg_gen_st_i32(var
, cpu_env
, offset
);
143 tcg_temp_free_i32(var
);
146 #define store_cpu_field(var, name) \
147 store_cpu_offset(var, offsetof(CPUState, name))
149 /* Set a variable to the value of a CPU register. */
150 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
154 /* normaly, since we updated PC, we need only to add one insn */
156 addr
= (long)s
->pc
+ 2;
158 addr
= (long)s
->pc
+ 4;
159 tcg_gen_movi_i32(var
, addr
);
161 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
165 /* Create a new temporary and set it to the value of a CPU register. */
166 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
168 TCGv tmp
= tcg_temp_new_i32();
169 load_reg_var(s
, tmp
, reg
);
173 /* Set a CPU register. The source must be a temporary and will be
175 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
178 tcg_gen_andi_i32(var
, var
, ~1);
179 s
->is_jmp
= DISAS_JUMP
;
181 tcg_gen_mov_i32(cpu_R
[reg
], var
);
182 tcg_temp_free_i32(var
);
185 /* Value extensions. */
186 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
187 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
188 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
189 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
191 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
192 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
195 static inline void gen_set_cpsr(TCGv var
, uint32_t mask
)
197 TCGv tmp_mask
= tcg_const_i32(mask
);
198 gen_helper_cpsr_write(var
, tmp_mask
);
199 tcg_temp_free_i32(tmp_mask
);
201 /* Set NZCV flags from the high 4 bits of var. */
202 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
204 static void gen_exception(int excp
)
206 TCGv tmp
= tcg_temp_new_i32();
207 tcg_gen_movi_i32(tmp
, excp
);
208 gen_helper_exception(tmp
);
209 tcg_temp_free_i32(tmp
);
212 static void gen_smul_dual(TCGv a
, TCGv b
)
214 TCGv tmp1
= tcg_temp_new_i32();
215 TCGv tmp2
= tcg_temp_new_i32();
216 tcg_gen_ext16s_i32(tmp1
, a
);
217 tcg_gen_ext16s_i32(tmp2
, b
);
218 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
219 tcg_temp_free_i32(tmp2
);
220 tcg_gen_sari_i32(a
, a
, 16);
221 tcg_gen_sari_i32(b
, b
, 16);
222 tcg_gen_mul_i32(b
, b
, a
);
223 tcg_gen_mov_i32(a
, tmp1
);
224 tcg_temp_free_i32(tmp1
);
227 /* Byteswap each halfword. */
228 static void gen_rev16(TCGv var
)
230 TCGv tmp
= tcg_temp_new_i32();
231 tcg_gen_shri_i32(tmp
, var
, 8);
232 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
233 tcg_gen_shli_i32(var
, var
, 8);
234 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
235 tcg_gen_or_i32(var
, var
, tmp
);
236 tcg_temp_free_i32(tmp
);
239 /* Byteswap low halfword and sign extend. */
240 static void gen_revsh(TCGv var
)
242 tcg_gen_ext16u_i32(var
, var
);
243 tcg_gen_bswap16_i32(var
, var
);
244 tcg_gen_ext16s_i32(var
, var
);
247 /* Unsigned bitfield extract. */
248 static void gen_ubfx(TCGv var
, int shift
, uint32_t mask
)
251 tcg_gen_shri_i32(var
, var
, shift
);
252 tcg_gen_andi_i32(var
, var
, mask
);
255 /* Signed bitfield extract. */
256 static void gen_sbfx(TCGv var
, int shift
, int width
)
261 tcg_gen_sari_i32(var
, var
, shift
);
262 if (shift
+ width
< 32) {
263 signbit
= 1u << (width
- 1);
264 tcg_gen_andi_i32(var
, var
, (1u << width
) - 1);
265 tcg_gen_xori_i32(var
, var
, signbit
);
266 tcg_gen_subi_i32(var
, var
, signbit
);
270 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
271 static void gen_bfi(TCGv dest
, TCGv base
, TCGv val
, int shift
, uint32_t mask
)
273 tcg_gen_andi_i32(val
, val
, mask
);
274 tcg_gen_shli_i32(val
, val
, shift
);
275 tcg_gen_andi_i32(base
, base
, ~(mask
<< shift
));
276 tcg_gen_or_i32(dest
, base
, val
);
279 /* Return (b << 32) + a. Mark inputs as dead */
280 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv b
)
282 TCGv_i64 tmp64
= tcg_temp_new_i64();
284 tcg_gen_extu_i32_i64(tmp64
, b
);
285 tcg_temp_free_i32(b
);
286 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
287 tcg_gen_add_i64(a
, tmp64
, a
);
289 tcg_temp_free_i64(tmp64
);
293 /* Return (b << 32) - a. Mark inputs as dead. */
294 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv b
)
296 TCGv_i64 tmp64
= tcg_temp_new_i64();
298 tcg_gen_extu_i32_i64(tmp64
, b
);
299 tcg_temp_free_i32(b
);
300 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
301 tcg_gen_sub_i64(a
, tmp64
, a
);
303 tcg_temp_free_i64(tmp64
);
307 /* FIXME: Most targets have native widening multiplication.
308 It would be good to use that instead of a full wide multiply. */
309 /* 32x32->64 multiply. Marks inputs as dead. */
310 static TCGv_i64
gen_mulu_i64_i32(TCGv a
, TCGv b
)
312 TCGv_i64 tmp1
= tcg_temp_new_i64();
313 TCGv_i64 tmp2
= tcg_temp_new_i64();
315 tcg_gen_extu_i32_i64(tmp1
, a
);
316 tcg_temp_free_i32(a
);
317 tcg_gen_extu_i32_i64(tmp2
, b
);
318 tcg_temp_free_i32(b
);
319 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
320 tcg_temp_free_i64(tmp2
);
324 static TCGv_i64
gen_muls_i64_i32(TCGv a
, TCGv b
)
326 TCGv_i64 tmp1
= tcg_temp_new_i64();
327 TCGv_i64 tmp2
= tcg_temp_new_i64();
329 tcg_gen_ext_i32_i64(tmp1
, a
);
330 tcg_temp_free_i32(a
);
331 tcg_gen_ext_i32_i64(tmp2
, b
);
332 tcg_temp_free_i32(b
);
333 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
334 tcg_temp_free_i64(tmp2
);
338 /* Swap low and high halfwords. */
339 static void gen_swap_half(TCGv var
)
341 TCGv tmp
= tcg_temp_new_i32();
342 tcg_gen_shri_i32(tmp
, var
, 16);
343 tcg_gen_shli_i32(var
, var
, 16);
344 tcg_gen_or_i32(var
, var
, tmp
);
345 tcg_temp_free_i32(tmp
);
348 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
349 tmp = (t0 ^ t1) & 0x8000;
352 t0 = (t0 + t1) ^ tmp;
355 static void gen_add16(TCGv t0
, TCGv t1
)
357 TCGv tmp
= tcg_temp_new_i32();
358 tcg_gen_xor_i32(tmp
, t0
, t1
);
359 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
360 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
361 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
362 tcg_gen_add_i32(t0
, t0
, t1
);
363 tcg_gen_xor_i32(t0
, t0
, tmp
);
364 tcg_temp_free_i32(tmp
);
365 tcg_temp_free_i32(t1
);
368 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
370 /* Set CF to the top bit of var. */
371 static void gen_set_CF_bit31(TCGv var
)
373 TCGv tmp
= tcg_temp_new_i32();
374 tcg_gen_shri_i32(tmp
, var
, 31);
376 tcg_temp_free_i32(tmp
);
379 /* Set N and Z flags from var. */
380 static inline void gen_logic_CC(TCGv var
)
382 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, NF
));
383 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, ZF
));
387 static void gen_adc(TCGv t0
, TCGv t1
)
390 tcg_gen_add_i32(t0
, t0
, t1
);
391 tmp
= load_cpu_field(CF
);
392 tcg_gen_add_i32(t0
, t0
, tmp
);
393 tcg_temp_free_i32(tmp
);
396 /* dest = T0 + T1 + CF. */
397 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
400 tcg_gen_add_i32(dest
, t0
, t1
);
401 tmp
= load_cpu_field(CF
);
402 tcg_gen_add_i32(dest
, dest
, tmp
);
403 tcg_temp_free_i32(tmp
);
406 /* dest = T0 - T1 + CF - 1. */
407 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
410 tcg_gen_sub_i32(dest
, t0
, t1
);
411 tmp
= load_cpu_field(CF
);
412 tcg_gen_add_i32(dest
, dest
, tmp
);
413 tcg_gen_subi_i32(dest
, dest
, 1);
414 tcg_temp_free_i32(tmp
);
417 /* FIXME: Implement this natively. */
418 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
420 static void shifter_out_im(TCGv var
, int shift
)
422 TCGv tmp
= tcg_temp_new_i32();
424 tcg_gen_andi_i32(tmp
, var
, 1);
426 tcg_gen_shri_i32(tmp
, var
, shift
);
428 tcg_gen_andi_i32(tmp
, tmp
, 1);
431 tcg_temp_free_i32(tmp
);
434 /* Shift by immediate. Includes special handling for shift == 0. */
435 static inline void gen_arm_shift_im(TCGv var
, int shiftop
, int shift
, int flags
)
441 shifter_out_im(var
, 32 - shift
);
442 tcg_gen_shli_i32(var
, var
, shift
);
448 tcg_gen_shri_i32(var
, var
, 31);
451 tcg_gen_movi_i32(var
, 0);
454 shifter_out_im(var
, shift
- 1);
455 tcg_gen_shri_i32(var
, var
, shift
);
462 shifter_out_im(var
, shift
- 1);
465 tcg_gen_sari_i32(var
, var
, shift
);
467 case 3: /* ROR/RRX */
470 shifter_out_im(var
, shift
- 1);
471 tcg_gen_rotri_i32(var
, var
, shift
); break;
473 TCGv tmp
= load_cpu_field(CF
);
475 shifter_out_im(var
, 0);
476 tcg_gen_shri_i32(var
, var
, 1);
477 tcg_gen_shli_i32(tmp
, tmp
, 31);
478 tcg_gen_or_i32(var
, var
, tmp
);
479 tcg_temp_free_i32(tmp
);
484 static inline void gen_arm_shift_reg(TCGv var
, int shiftop
,
485 TCGv shift
, int flags
)
489 case 0: gen_helper_shl_cc(var
, var
, shift
); break;
490 case 1: gen_helper_shr_cc(var
, var
, shift
); break;
491 case 2: gen_helper_sar_cc(var
, var
, shift
); break;
492 case 3: gen_helper_ror_cc(var
, var
, shift
); break;
496 case 0: gen_helper_shl(var
, var
, shift
); break;
497 case 1: gen_helper_shr(var
, var
, shift
); break;
498 case 2: gen_helper_sar(var
, var
, shift
); break;
499 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
500 tcg_gen_rotr_i32(var
, var
, shift
); break;
503 tcg_temp_free_i32(shift
);
506 #define PAS_OP(pfx) \
508 case 0: gen_pas_helper(glue(pfx,add16)); break; \
509 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
510 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
511 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
512 case 4: gen_pas_helper(glue(pfx,add8)); break; \
513 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
515 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
520 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
522 tmp
= tcg_temp_new_ptr();
523 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
525 tcg_temp_free_ptr(tmp
);
528 tmp
= tcg_temp_new_ptr();
529 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
531 tcg_temp_free_ptr(tmp
);
533 #undef gen_pas_helper
534 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
547 #undef gen_pas_helper
552 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
553 #define PAS_OP(pfx) \
555 case 0: gen_pas_helper(glue(pfx,add8)); break; \
556 case 1: gen_pas_helper(glue(pfx,add16)); break; \
557 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
558 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
559 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
560 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
562 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
567 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
569 tmp
= tcg_temp_new_ptr();
570 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
572 tcg_temp_free_ptr(tmp
);
575 tmp
= tcg_temp_new_ptr();
576 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
578 tcg_temp_free_ptr(tmp
);
580 #undef gen_pas_helper
581 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
594 #undef gen_pas_helper
599 static void gen_test_cc(int cc
, int label
)
607 tmp
= load_cpu_field(ZF
);
608 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
611 tmp
= load_cpu_field(ZF
);
612 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
615 tmp
= load_cpu_field(CF
);
616 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
619 tmp
= load_cpu_field(CF
);
620 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
623 tmp
= load_cpu_field(NF
);
624 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
627 tmp
= load_cpu_field(NF
);
628 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
631 tmp
= load_cpu_field(VF
);
632 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
635 tmp
= load_cpu_field(VF
);
636 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
638 case 8: /* hi: C && !Z */
639 inv
= gen_new_label();
640 tmp
= load_cpu_field(CF
);
641 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
642 tcg_temp_free_i32(tmp
);
643 tmp
= load_cpu_field(ZF
);
644 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
647 case 9: /* ls: !C || Z */
648 tmp
= load_cpu_field(CF
);
649 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
650 tcg_temp_free_i32(tmp
);
651 tmp
= load_cpu_field(ZF
);
652 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
654 case 10: /* ge: N == V -> N ^ V == 0 */
655 tmp
= load_cpu_field(VF
);
656 tmp2
= load_cpu_field(NF
);
657 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
658 tcg_temp_free_i32(tmp2
);
659 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
661 case 11: /* lt: N != V -> N ^ V != 0 */
662 tmp
= load_cpu_field(VF
);
663 tmp2
= load_cpu_field(NF
);
664 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
665 tcg_temp_free_i32(tmp2
);
666 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
668 case 12: /* gt: !Z && N == V */
669 inv
= gen_new_label();
670 tmp
= load_cpu_field(ZF
);
671 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
672 tcg_temp_free_i32(tmp
);
673 tmp
= load_cpu_field(VF
);
674 tmp2
= load_cpu_field(NF
);
675 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
676 tcg_temp_free_i32(tmp2
);
677 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
680 case 13: /* le: Z || N != V */
681 tmp
= load_cpu_field(ZF
);
682 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
683 tcg_temp_free_i32(tmp
);
684 tmp
= load_cpu_field(VF
);
685 tmp2
= load_cpu_field(NF
);
686 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
687 tcg_temp_free_i32(tmp2
);
688 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
691 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
694 tcg_temp_free_i32(tmp
);
697 static const uint8_t table_logic_cc
[16] = {
716 /* Set PC and Thumb state from an immediate address. */
717 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
721 s
->is_jmp
= DISAS_UPDATE
;
722 if (s
->thumb
!= (addr
& 1)) {
723 tmp
= tcg_temp_new_i32();
724 tcg_gen_movi_i32(tmp
, addr
& 1);
725 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, thumb
));
726 tcg_temp_free_i32(tmp
);
728 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
731 /* Set PC and Thumb state from var. var is marked as dead. */
732 static inline void gen_bx(DisasContext
*s
, TCGv var
)
734 s
->is_jmp
= DISAS_UPDATE
;
735 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
736 tcg_gen_andi_i32(var
, var
, 1);
737 store_cpu_field(var
, thumb
);
740 /* Variant of store_reg which uses branch&exchange logic when storing
741 to r15 in ARM architecture v7 and above. The source must be a temporary
742 and will be marked as dead. */
743 static inline void store_reg_bx(CPUState
*env
, DisasContext
*s
,
746 if (reg
== 15 && ENABLE_ARCH_7
) {
749 store_reg(s
, reg
, var
);
753 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
755 TCGv tmp
= tcg_temp_new_i32();
756 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
759 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
761 TCGv tmp
= tcg_temp_new_i32();
762 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
765 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
767 TCGv tmp
= tcg_temp_new_i32();
768 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
771 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
773 TCGv tmp
= tcg_temp_new_i32();
774 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
777 static inline TCGv
gen_ld32(TCGv addr
, int index
)
779 TCGv tmp
= tcg_temp_new_i32();
780 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
783 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
785 TCGv_i64 tmp
= tcg_temp_new_i64();
786 tcg_gen_qemu_ld64(tmp
, addr
, index
);
789 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
791 tcg_gen_qemu_st8(val
, addr
, index
);
792 tcg_temp_free_i32(val
);
794 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
796 tcg_gen_qemu_st16(val
, addr
, index
);
797 tcg_temp_free_i32(val
);
799 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
801 tcg_gen_qemu_st32(val
, addr
, index
);
802 tcg_temp_free_i32(val
);
804 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
806 tcg_gen_qemu_st64(val
, addr
, index
);
807 tcg_temp_free_i64(val
);
810 static inline void gen_set_pc_im(uint32_t val
)
812 tcg_gen_movi_i32(cpu_R
[15], val
);
815 /* Force a TB lookup after an instruction that changes the CPU state. */
816 static inline void gen_lookup_tb(DisasContext
*s
)
818 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
819 s
->is_jmp
= DISAS_UPDATE
;
822 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
825 int val
, rm
, shift
, shiftop
;
828 if (!(insn
& (1 << 25))) {
831 if (!(insn
& (1 << 23)))
834 tcg_gen_addi_i32(var
, var
, val
);
838 shift
= (insn
>> 7) & 0x1f;
839 shiftop
= (insn
>> 5) & 3;
840 offset
= load_reg(s
, rm
);
841 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
842 if (!(insn
& (1 << 23)))
843 tcg_gen_sub_i32(var
, var
, offset
);
845 tcg_gen_add_i32(var
, var
, offset
);
846 tcg_temp_free_i32(offset
);
850 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
856 if (insn
& (1 << 22)) {
858 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
859 if (!(insn
& (1 << 23)))
863 tcg_gen_addi_i32(var
, var
, val
);
867 tcg_gen_addi_i32(var
, var
, extra
);
869 offset
= load_reg(s
, rm
);
870 if (!(insn
& (1 << 23)))
871 tcg_gen_sub_i32(var
, var
, offset
);
873 tcg_gen_add_i32(var
, var
, offset
);
874 tcg_temp_free_i32(offset
);
878 #define VFP_OP2(name) \
879 static inline void gen_vfp_##name(int dp) \
882 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
884 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
894 static inline void gen_vfp_abs(int dp
)
897 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
899 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
902 static inline void gen_vfp_neg(int dp
)
905 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
907 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
910 static inline void gen_vfp_sqrt(int dp
)
913 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
915 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
918 static inline void gen_vfp_cmp(int dp
)
921 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
923 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
926 static inline void gen_vfp_cmpe(int dp
)
929 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
931 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
934 static inline void gen_vfp_F1_ld0(int dp
)
937 tcg_gen_movi_i64(cpu_F1d
, 0);
939 tcg_gen_movi_i32(cpu_F1s
, 0);
942 static inline void gen_vfp_uito(int dp
)
945 gen_helper_vfp_uitod(cpu_F0d
, cpu_F0s
, cpu_env
);
947 gen_helper_vfp_uitos(cpu_F0s
, cpu_F0s
, cpu_env
);
950 static inline void gen_vfp_sito(int dp
)
953 gen_helper_vfp_sitod(cpu_F0d
, cpu_F0s
, cpu_env
);
955 gen_helper_vfp_sitos(cpu_F0s
, cpu_F0s
, cpu_env
);
958 static inline void gen_vfp_toui(int dp
)
961 gen_helper_vfp_touid(cpu_F0s
, cpu_F0d
, cpu_env
);
963 gen_helper_vfp_touis(cpu_F0s
, cpu_F0s
, cpu_env
);
966 static inline void gen_vfp_touiz(int dp
)
969 gen_helper_vfp_touizd(cpu_F0s
, cpu_F0d
, cpu_env
);
971 gen_helper_vfp_touizs(cpu_F0s
, cpu_F0s
, cpu_env
);
974 static inline void gen_vfp_tosi(int dp
)
977 gen_helper_vfp_tosid(cpu_F0s
, cpu_F0d
, cpu_env
);
979 gen_helper_vfp_tosis(cpu_F0s
, cpu_F0s
, cpu_env
);
982 static inline void gen_vfp_tosiz(int dp
)
985 gen_helper_vfp_tosizd(cpu_F0s
, cpu_F0d
, cpu_env
);
987 gen_helper_vfp_tosizs(cpu_F0s
, cpu_F0s
, cpu_env
);
990 #define VFP_GEN_FIX(name) \
991 static inline void gen_vfp_##name(int dp, int shift) \
993 TCGv tmp_shift = tcg_const_i32(shift); \
995 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
997 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
998 tcg_temp_free_i32(tmp_shift); \
1010 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv addr
)
1013 tcg_gen_qemu_ld64(cpu_F0d
, addr
, IS_USER(s
));
1015 tcg_gen_qemu_ld32u(cpu_F0s
, addr
, IS_USER(s
));
1018 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv addr
)
1021 tcg_gen_qemu_st64(cpu_F0d
, addr
, IS_USER(s
));
1023 tcg_gen_qemu_st32(cpu_F0s
, addr
, IS_USER(s
));
1027 vfp_reg_offset (int dp
, int reg
)
1030 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1032 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1033 + offsetof(CPU_DoubleU
, l
.upper
);
1035 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1036 + offsetof(CPU_DoubleU
, l
.lower
);
1040 /* Return the offset of a 32-bit piece of a NEON register.
1041 zero is the least significant end of the register. */
1043 neon_reg_offset (int reg
, int n
)
1047 return vfp_reg_offset(0, sreg
);
1050 static TCGv
neon_load_reg(int reg
, int pass
)
1052 TCGv tmp
= tcg_temp_new_i32();
1053 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1057 static void neon_store_reg(int reg
, int pass
, TCGv var
)
1059 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1060 tcg_temp_free_i32(var
);
1063 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1065 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1068 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1070 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1073 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1074 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1075 #define tcg_gen_st_f32 tcg_gen_st_i32
1076 #define tcg_gen_st_f64 tcg_gen_st_i64
1078 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1081 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1083 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1086 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1089 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1091 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1094 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1097 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1099 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1102 #define ARM_CP_RW_BIT (1 << 20)
1104 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1106 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1109 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1111 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1114 static inline TCGv
iwmmxt_load_creg(int reg
)
1116 TCGv var
= tcg_temp_new_i32();
1117 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1121 static inline void iwmmxt_store_creg(int reg
, TCGv var
)
1123 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1124 tcg_temp_free_i32(var
);
1127 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1129 iwmmxt_store_reg(cpu_M0
, rn
);
1132 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1134 iwmmxt_load_reg(cpu_M0
, rn
);
1137 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1139 iwmmxt_load_reg(cpu_V1
, rn
);
1140 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1143 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1145 iwmmxt_load_reg(cpu_V1
, rn
);
1146 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1149 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1151 iwmmxt_load_reg(cpu_V1
, rn
);
1152 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1155 #define IWMMXT_OP(name) \
1156 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1158 iwmmxt_load_reg(cpu_V1, rn); \
1159 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1162 #define IWMMXT_OP_ENV(name) \
1163 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1165 iwmmxt_load_reg(cpu_V1, rn); \
1166 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1169 #define IWMMXT_OP_ENV_SIZE(name) \
1170 IWMMXT_OP_ENV(name##b) \
1171 IWMMXT_OP_ENV(name##w) \
1172 IWMMXT_OP_ENV(name##l)
1174 #define IWMMXT_OP_ENV1(name) \
1175 static inline void gen_op_iwmmxt_##name##_M0(void) \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1191 IWMMXT_OP_ENV_SIZE(unpackl
)
1192 IWMMXT_OP_ENV_SIZE(unpackh
)
1194 IWMMXT_OP_ENV1(unpacklub
)
1195 IWMMXT_OP_ENV1(unpackluw
)
1196 IWMMXT_OP_ENV1(unpacklul
)
1197 IWMMXT_OP_ENV1(unpackhub
)
1198 IWMMXT_OP_ENV1(unpackhuw
)
1199 IWMMXT_OP_ENV1(unpackhul
)
1200 IWMMXT_OP_ENV1(unpacklsb
)
1201 IWMMXT_OP_ENV1(unpacklsw
)
1202 IWMMXT_OP_ENV1(unpacklsl
)
1203 IWMMXT_OP_ENV1(unpackhsb
)
1204 IWMMXT_OP_ENV1(unpackhsw
)
1205 IWMMXT_OP_ENV1(unpackhsl
)
1207 IWMMXT_OP_ENV_SIZE(cmpeq
)
1208 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1209 IWMMXT_OP_ENV_SIZE(cmpgts
)
1211 IWMMXT_OP_ENV_SIZE(mins
)
1212 IWMMXT_OP_ENV_SIZE(minu
)
1213 IWMMXT_OP_ENV_SIZE(maxs
)
1214 IWMMXT_OP_ENV_SIZE(maxu
)
1216 IWMMXT_OP_ENV_SIZE(subn
)
1217 IWMMXT_OP_ENV_SIZE(addn
)
1218 IWMMXT_OP_ENV_SIZE(subu
)
1219 IWMMXT_OP_ENV_SIZE(addu
)
1220 IWMMXT_OP_ENV_SIZE(subs
)
1221 IWMMXT_OP_ENV_SIZE(adds
)
1223 IWMMXT_OP_ENV(avgb0
)
1224 IWMMXT_OP_ENV(avgb1
)
1225 IWMMXT_OP_ENV(avgw0
)
1226 IWMMXT_OP_ENV(avgw1
)
1230 IWMMXT_OP_ENV(packuw
)
1231 IWMMXT_OP_ENV(packul
)
1232 IWMMXT_OP_ENV(packuq
)
1233 IWMMXT_OP_ENV(packsw
)
1234 IWMMXT_OP_ENV(packsl
)
1235 IWMMXT_OP_ENV(packsq
)
1237 static void gen_op_iwmmxt_set_mup(void)
1240 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1241 tcg_gen_ori_i32(tmp
, tmp
, 2);
1242 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1245 static void gen_op_iwmmxt_set_cup(void)
1248 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1249 tcg_gen_ori_i32(tmp
, tmp
, 1);
1250 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1253 static void gen_op_iwmmxt_setpsr_nz(void)
1255 TCGv tmp
= tcg_temp_new_i32();
1256 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1257 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1260 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1262 iwmmxt_load_reg(cpu_V1
, rn
);
1263 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1264 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1267 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
, TCGv dest
)
1273 rd
= (insn
>> 16) & 0xf;
1274 tmp
= load_reg(s
, rd
);
1276 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1277 if (insn
& (1 << 24)) {
1279 if (insn
& (1 << 23))
1280 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1282 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1283 tcg_gen_mov_i32(dest
, tmp
);
1284 if (insn
& (1 << 21))
1285 store_reg(s
, rd
, tmp
);
1287 tcg_temp_free_i32(tmp
);
1288 } else if (insn
& (1 << 21)) {
1290 tcg_gen_mov_i32(dest
, tmp
);
1291 if (insn
& (1 << 23))
1292 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1294 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1295 store_reg(s
, rd
, tmp
);
1296 } else if (!(insn
& (1 << 23)))
1301 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv dest
)
1303 int rd
= (insn
>> 0) & 0xf;
1306 if (insn
& (1 << 8)) {
1307 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1310 tmp
= iwmmxt_load_creg(rd
);
1313 tmp
= tcg_temp_new_i32();
1314 iwmmxt_load_reg(cpu_V0
, rd
);
1315 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
1317 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1318 tcg_gen_mov_i32(dest
, tmp
);
1319 tcg_temp_free_i32(tmp
);
1323 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1324 (ie. an undefined instruction). */
1325 static int disas_iwmmxt_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
1328 int rdhi
, rdlo
, rd0
, rd1
, i
;
1330 TCGv tmp
, tmp2
, tmp3
;
1332 if ((insn
& 0x0e000e00) == 0x0c000000) {
1333 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1335 rdlo
= (insn
>> 12) & 0xf;
1336 rdhi
= (insn
>> 16) & 0xf;
1337 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1338 iwmmxt_load_reg(cpu_V0
, wrd
);
1339 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1340 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1341 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1342 } else { /* TMCRR */
1343 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1344 iwmmxt_store_reg(cpu_V0
, wrd
);
1345 gen_op_iwmmxt_set_mup();
1350 wrd
= (insn
>> 12) & 0xf;
1351 addr
= tcg_temp_new_i32();
1352 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1353 tcg_temp_free_i32(addr
);
1356 if (insn
& ARM_CP_RW_BIT
) {
1357 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1358 tmp
= tcg_temp_new_i32();
1359 tcg_gen_qemu_ld32u(tmp
, addr
, IS_USER(s
));
1360 iwmmxt_store_creg(wrd
, tmp
);
1363 if (insn
& (1 << 8)) {
1364 if (insn
& (1 << 22)) { /* WLDRD */
1365 tcg_gen_qemu_ld64(cpu_M0
, addr
, IS_USER(s
));
1367 } else { /* WLDRW wRd */
1368 tmp
= gen_ld32(addr
, IS_USER(s
));
1371 if (insn
& (1 << 22)) { /* WLDRH */
1372 tmp
= gen_ld16u(addr
, IS_USER(s
));
1373 } else { /* WLDRB */
1374 tmp
= gen_ld8u(addr
, IS_USER(s
));
1378 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1379 tcg_temp_free_i32(tmp
);
1381 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1384 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1385 tmp
= iwmmxt_load_creg(wrd
);
1386 gen_st32(tmp
, addr
, IS_USER(s
));
1388 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1389 tmp
= tcg_temp_new_i32();
1390 if (insn
& (1 << 8)) {
1391 if (insn
& (1 << 22)) { /* WSTRD */
1392 tcg_temp_free_i32(tmp
);
1393 tcg_gen_qemu_st64(cpu_M0
, addr
, IS_USER(s
));
1394 } else { /* WSTRW wRd */
1395 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1396 gen_st32(tmp
, addr
, IS_USER(s
));
1399 if (insn
& (1 << 22)) { /* WSTRH */
1400 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1401 gen_st16(tmp
, addr
, IS_USER(s
));
1402 } else { /* WSTRB */
1403 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1404 gen_st8(tmp
, addr
, IS_USER(s
));
1409 tcg_temp_free_i32(addr
);
1413 if ((insn
& 0x0f000000) != 0x0e000000)
1416 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1417 case 0x000: /* WOR */
1418 wrd
= (insn
>> 12) & 0xf;
1419 rd0
= (insn
>> 0) & 0xf;
1420 rd1
= (insn
>> 16) & 0xf;
1421 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1422 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1423 gen_op_iwmmxt_setpsr_nz();
1424 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1425 gen_op_iwmmxt_set_mup();
1426 gen_op_iwmmxt_set_cup();
1428 case 0x011: /* TMCR */
1431 rd
= (insn
>> 12) & 0xf;
1432 wrd
= (insn
>> 16) & 0xf;
1434 case ARM_IWMMXT_wCID
:
1435 case ARM_IWMMXT_wCASF
:
1437 case ARM_IWMMXT_wCon
:
1438 gen_op_iwmmxt_set_cup();
1440 case ARM_IWMMXT_wCSSF
:
1441 tmp
= iwmmxt_load_creg(wrd
);
1442 tmp2
= load_reg(s
, rd
);
1443 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1444 tcg_temp_free_i32(tmp2
);
1445 iwmmxt_store_creg(wrd
, tmp
);
1447 case ARM_IWMMXT_wCGR0
:
1448 case ARM_IWMMXT_wCGR1
:
1449 case ARM_IWMMXT_wCGR2
:
1450 case ARM_IWMMXT_wCGR3
:
1451 gen_op_iwmmxt_set_cup();
1452 tmp
= load_reg(s
, rd
);
1453 iwmmxt_store_creg(wrd
, tmp
);
1459 case 0x100: /* WXOR */
1460 wrd
= (insn
>> 12) & 0xf;
1461 rd0
= (insn
>> 0) & 0xf;
1462 rd1
= (insn
>> 16) & 0xf;
1463 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1464 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1465 gen_op_iwmmxt_setpsr_nz();
1466 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1467 gen_op_iwmmxt_set_mup();
1468 gen_op_iwmmxt_set_cup();
1470 case 0x111: /* TMRC */
1473 rd
= (insn
>> 12) & 0xf;
1474 wrd
= (insn
>> 16) & 0xf;
1475 tmp
= iwmmxt_load_creg(wrd
);
1476 store_reg(s
, rd
, tmp
);
1478 case 0x300: /* WANDN */
1479 wrd
= (insn
>> 12) & 0xf;
1480 rd0
= (insn
>> 0) & 0xf;
1481 rd1
= (insn
>> 16) & 0xf;
1482 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1483 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1484 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1485 gen_op_iwmmxt_setpsr_nz();
1486 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1487 gen_op_iwmmxt_set_mup();
1488 gen_op_iwmmxt_set_cup();
1490 case 0x200: /* WAND */
1491 wrd
= (insn
>> 12) & 0xf;
1492 rd0
= (insn
>> 0) & 0xf;
1493 rd1
= (insn
>> 16) & 0xf;
1494 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1501 case 0x810: case 0xa10: /* WMADD */
1502 wrd
= (insn
>> 12) & 0xf;
1503 rd0
= (insn
>> 0) & 0xf;
1504 rd1
= (insn
>> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1506 if (insn
& (1 << 21))
1507 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1509 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1510 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1511 gen_op_iwmmxt_set_mup();
1513 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1514 wrd
= (insn
>> 12) & 0xf;
1515 rd0
= (insn
>> 16) & 0xf;
1516 rd1
= (insn
>> 0) & 0xf;
1517 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1518 switch ((insn
>> 22) & 3) {
1520 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1523 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1526 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1531 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1532 gen_op_iwmmxt_set_mup();
1533 gen_op_iwmmxt_set_cup();
1535 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1536 wrd
= (insn
>> 12) & 0xf;
1537 rd0
= (insn
>> 16) & 0xf;
1538 rd1
= (insn
>> 0) & 0xf;
1539 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1540 switch ((insn
>> 22) & 3) {
1542 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1545 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1548 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1553 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1554 gen_op_iwmmxt_set_mup();
1555 gen_op_iwmmxt_set_cup();
1557 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1558 wrd
= (insn
>> 12) & 0xf;
1559 rd0
= (insn
>> 16) & 0xf;
1560 rd1
= (insn
>> 0) & 0xf;
1561 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1562 if (insn
& (1 << 22))
1563 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1565 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1566 if (!(insn
& (1 << 20)))
1567 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1568 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1569 gen_op_iwmmxt_set_mup();
1571 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1572 wrd
= (insn
>> 12) & 0xf;
1573 rd0
= (insn
>> 16) & 0xf;
1574 rd1
= (insn
>> 0) & 0xf;
1575 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1576 if (insn
& (1 << 21)) {
1577 if (insn
& (1 << 20))
1578 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1580 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1582 if (insn
& (1 << 20))
1583 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1585 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1587 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1588 gen_op_iwmmxt_set_mup();
1590 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1591 wrd
= (insn
>> 12) & 0xf;
1592 rd0
= (insn
>> 16) & 0xf;
1593 rd1
= (insn
>> 0) & 0xf;
1594 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1595 if (insn
& (1 << 21))
1596 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1598 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1599 if (!(insn
& (1 << 20))) {
1600 iwmmxt_load_reg(cpu_V1
, wrd
);
1601 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1603 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1604 gen_op_iwmmxt_set_mup();
1606 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1607 wrd
= (insn
>> 12) & 0xf;
1608 rd0
= (insn
>> 16) & 0xf;
1609 rd1
= (insn
>> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1611 switch ((insn
>> 22) & 3) {
1613 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1616 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1619 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1624 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1625 gen_op_iwmmxt_set_mup();
1626 gen_op_iwmmxt_set_cup();
1628 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1629 wrd
= (insn
>> 12) & 0xf;
1630 rd0
= (insn
>> 16) & 0xf;
1631 rd1
= (insn
>> 0) & 0xf;
1632 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1633 if (insn
& (1 << 22)) {
1634 if (insn
& (1 << 20))
1635 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1637 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1639 if (insn
& (1 << 20))
1640 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1642 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1644 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1645 gen_op_iwmmxt_set_mup();
1646 gen_op_iwmmxt_set_cup();
1648 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1649 wrd
= (insn
>> 12) & 0xf;
1650 rd0
= (insn
>> 16) & 0xf;
1651 rd1
= (insn
>> 0) & 0xf;
1652 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1653 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1654 tcg_gen_andi_i32(tmp
, tmp
, 7);
1655 iwmmxt_load_reg(cpu_V1
, rd1
);
1656 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1657 tcg_temp_free_i32(tmp
);
1658 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1659 gen_op_iwmmxt_set_mup();
1661 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1662 if (((insn
>> 6) & 3) == 3)
1664 rd
= (insn
>> 12) & 0xf;
1665 wrd
= (insn
>> 16) & 0xf;
1666 tmp
= load_reg(s
, rd
);
1667 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1668 switch ((insn
>> 6) & 3) {
1670 tmp2
= tcg_const_i32(0xff);
1671 tmp3
= tcg_const_i32((insn
& 7) << 3);
1674 tmp2
= tcg_const_i32(0xffff);
1675 tmp3
= tcg_const_i32((insn
& 3) << 4);
1678 tmp2
= tcg_const_i32(0xffffffff);
1679 tmp3
= tcg_const_i32((insn
& 1) << 5);
1685 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1686 tcg_temp_free(tmp3
);
1687 tcg_temp_free(tmp2
);
1688 tcg_temp_free_i32(tmp
);
1689 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1690 gen_op_iwmmxt_set_mup();
1692 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1693 rd
= (insn
>> 12) & 0xf;
1694 wrd
= (insn
>> 16) & 0xf;
1695 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1697 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1698 tmp
= tcg_temp_new_i32();
1699 switch ((insn
>> 22) & 3) {
1701 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1702 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1704 tcg_gen_ext8s_i32(tmp
, tmp
);
1706 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1710 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1711 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1713 tcg_gen_ext16s_i32(tmp
, tmp
);
1715 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1719 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1720 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1723 store_reg(s
, rd
, tmp
);
1725 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1726 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1728 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1729 switch ((insn
>> 22) & 3) {
1731 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1734 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1737 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1740 tcg_gen_shli_i32(tmp
, tmp
, 28);
1742 tcg_temp_free_i32(tmp
);
1744 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1745 if (((insn
>> 6) & 3) == 3)
1747 rd
= (insn
>> 12) & 0xf;
1748 wrd
= (insn
>> 16) & 0xf;
1749 tmp
= load_reg(s
, rd
);
1750 switch ((insn
>> 6) & 3) {
1752 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1755 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1758 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1761 tcg_temp_free_i32(tmp
);
1762 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1763 gen_op_iwmmxt_set_mup();
1765 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1766 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1768 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1769 tmp2
= tcg_temp_new_i32();
1770 tcg_gen_mov_i32(tmp2
, tmp
);
1771 switch ((insn
>> 22) & 3) {
1773 for (i
= 0; i
< 7; i
++) {
1774 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1775 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1779 for (i
= 0; i
< 3; i
++) {
1780 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1781 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1785 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1786 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1790 tcg_temp_free_i32(tmp2
);
1791 tcg_temp_free_i32(tmp
);
1793 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1794 wrd
= (insn
>> 12) & 0xf;
1795 rd0
= (insn
>> 16) & 0xf;
1796 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1797 switch ((insn
>> 22) & 3) {
1799 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
1802 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
1805 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
1810 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1811 gen_op_iwmmxt_set_mup();
1813 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1814 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1816 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1817 tmp2
= tcg_temp_new_i32();
1818 tcg_gen_mov_i32(tmp2
, tmp
);
1819 switch ((insn
>> 22) & 3) {
1821 for (i
= 0; i
< 7; i
++) {
1822 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1823 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1827 for (i
= 0; i
< 3; i
++) {
1828 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1829 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1833 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1834 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1838 tcg_temp_free_i32(tmp2
);
1839 tcg_temp_free_i32(tmp
);
1841 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1842 rd
= (insn
>> 12) & 0xf;
1843 rd0
= (insn
>> 16) & 0xf;
1844 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
1846 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1847 tmp
= tcg_temp_new_i32();
1848 switch ((insn
>> 22) & 3) {
1850 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
1853 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
1856 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
1859 store_reg(s
, rd
, tmp
);
1861 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1862 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1863 wrd
= (insn
>> 12) & 0xf;
1864 rd0
= (insn
>> 16) & 0xf;
1865 rd1
= (insn
>> 0) & 0xf;
1866 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1867 switch ((insn
>> 22) & 3) {
1869 if (insn
& (1 << 21))
1870 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
1872 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
1875 if (insn
& (1 << 21))
1876 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
1878 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
1881 if (insn
& (1 << 21))
1882 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
1884 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
1889 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1890 gen_op_iwmmxt_set_mup();
1891 gen_op_iwmmxt_set_cup();
1893 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1894 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1895 wrd
= (insn
>> 12) & 0xf;
1896 rd0
= (insn
>> 16) & 0xf;
1897 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1898 switch ((insn
>> 22) & 3) {
1900 if (insn
& (1 << 21))
1901 gen_op_iwmmxt_unpacklsb_M0();
1903 gen_op_iwmmxt_unpacklub_M0();
1906 if (insn
& (1 << 21))
1907 gen_op_iwmmxt_unpacklsw_M0();
1909 gen_op_iwmmxt_unpackluw_M0();
1912 if (insn
& (1 << 21))
1913 gen_op_iwmmxt_unpacklsl_M0();
1915 gen_op_iwmmxt_unpacklul_M0();
1920 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1921 gen_op_iwmmxt_set_mup();
1922 gen_op_iwmmxt_set_cup();
1924 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1925 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1926 wrd
= (insn
>> 12) & 0xf;
1927 rd0
= (insn
>> 16) & 0xf;
1928 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1929 switch ((insn
>> 22) & 3) {
1931 if (insn
& (1 << 21))
1932 gen_op_iwmmxt_unpackhsb_M0();
1934 gen_op_iwmmxt_unpackhub_M0();
1937 if (insn
& (1 << 21))
1938 gen_op_iwmmxt_unpackhsw_M0();
1940 gen_op_iwmmxt_unpackhuw_M0();
1943 if (insn
& (1 << 21))
1944 gen_op_iwmmxt_unpackhsl_M0();
1946 gen_op_iwmmxt_unpackhul_M0();
1951 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1952 gen_op_iwmmxt_set_mup();
1953 gen_op_iwmmxt_set_cup();
1955 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1956 case 0x214: case 0x614: case 0xa14: case 0xe14:
1957 if (((insn
>> 22) & 3) == 0)
1959 wrd
= (insn
>> 12) & 0xf;
1960 rd0
= (insn
>> 16) & 0xf;
1961 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1962 tmp
= tcg_temp_new_i32();
1963 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
1964 tcg_temp_free_i32(tmp
);
1967 switch ((insn
>> 22) & 3) {
1969 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1972 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1975 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1978 tcg_temp_free_i32(tmp
);
1979 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1980 gen_op_iwmmxt_set_mup();
1981 gen_op_iwmmxt_set_cup();
1983 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1984 case 0x014: case 0x414: case 0x814: case 0xc14:
1985 if (((insn
>> 22) & 3) == 0)
1987 wrd
= (insn
>> 12) & 0xf;
1988 rd0
= (insn
>> 16) & 0xf;
1989 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1990 tmp
= tcg_temp_new_i32();
1991 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
1992 tcg_temp_free_i32(tmp
);
1995 switch ((insn
>> 22) & 3) {
1997 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2000 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2003 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2006 tcg_temp_free_i32(tmp
);
2007 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2008 gen_op_iwmmxt_set_mup();
2009 gen_op_iwmmxt_set_cup();
2011 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2012 case 0x114: case 0x514: case 0x914: case 0xd14:
2013 if (((insn
>> 22) & 3) == 0)
2015 wrd
= (insn
>> 12) & 0xf;
2016 rd0
= (insn
>> 16) & 0xf;
2017 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2018 tmp
= tcg_temp_new_i32();
2019 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2020 tcg_temp_free_i32(tmp
);
2023 switch ((insn
>> 22) & 3) {
2025 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2028 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2031 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2034 tcg_temp_free_i32(tmp
);
2035 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2036 gen_op_iwmmxt_set_mup();
2037 gen_op_iwmmxt_set_cup();
2039 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2040 case 0x314: case 0x714: case 0xb14: case 0xf14:
2041 if (((insn
>> 22) & 3) == 0)
2043 wrd
= (insn
>> 12) & 0xf;
2044 rd0
= (insn
>> 16) & 0xf;
2045 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2046 tmp
= tcg_temp_new_i32();
2047 switch ((insn
>> 22) & 3) {
2049 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2050 tcg_temp_free_i32(tmp
);
2053 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2056 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2057 tcg_temp_free_i32(tmp
);
2060 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2063 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2064 tcg_temp_free_i32(tmp
);
2067 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2070 tcg_temp_free_i32(tmp
);
2071 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2072 gen_op_iwmmxt_set_mup();
2073 gen_op_iwmmxt_set_cup();
2075 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2076 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2077 wrd
= (insn
>> 12) & 0xf;
2078 rd0
= (insn
>> 16) & 0xf;
2079 rd1
= (insn
>> 0) & 0xf;
2080 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2081 switch ((insn
>> 22) & 3) {
2083 if (insn
& (1 << 21))
2084 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2086 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2089 if (insn
& (1 << 21))
2090 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2092 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2095 if (insn
& (1 << 21))
2096 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2098 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2103 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2104 gen_op_iwmmxt_set_mup();
2106 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2107 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2108 wrd
= (insn
>> 12) & 0xf;
2109 rd0
= (insn
>> 16) & 0xf;
2110 rd1
= (insn
>> 0) & 0xf;
2111 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2112 switch ((insn
>> 22) & 3) {
2114 if (insn
& (1 << 21))
2115 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2117 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2120 if (insn
& (1 << 21))
2121 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2123 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2126 if (insn
& (1 << 21))
2127 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2129 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2134 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2135 gen_op_iwmmxt_set_mup();
2137 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2138 case 0x402: case 0x502: case 0x602: case 0x702:
2139 wrd
= (insn
>> 12) & 0xf;
2140 rd0
= (insn
>> 16) & 0xf;
2141 rd1
= (insn
>> 0) & 0xf;
2142 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2143 tmp
= tcg_const_i32((insn
>> 20) & 3);
2144 iwmmxt_load_reg(cpu_V1
, rd1
);
2145 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2147 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2148 gen_op_iwmmxt_set_mup();
2150 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2151 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2152 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2153 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2154 wrd
= (insn
>> 12) & 0xf;
2155 rd0
= (insn
>> 16) & 0xf;
2156 rd1
= (insn
>> 0) & 0xf;
2157 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2158 switch ((insn
>> 20) & 0xf) {
2160 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2163 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2166 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2169 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2172 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2175 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2178 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2181 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2184 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2189 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2190 gen_op_iwmmxt_set_mup();
2191 gen_op_iwmmxt_set_cup();
2193 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2194 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2195 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2196 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2197 wrd
= (insn
>> 12) & 0xf;
2198 rd0
= (insn
>> 16) & 0xf;
2199 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2200 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2201 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2203 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2204 gen_op_iwmmxt_set_mup();
2205 gen_op_iwmmxt_set_cup();
2207 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2208 case 0x418: case 0x518: case 0x618: case 0x718:
2209 case 0x818: case 0x918: case 0xa18: case 0xb18:
2210 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2211 wrd
= (insn
>> 12) & 0xf;
2212 rd0
= (insn
>> 16) & 0xf;
2213 rd1
= (insn
>> 0) & 0xf;
2214 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2215 switch ((insn
>> 20) & 0xf) {
2217 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2220 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2223 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2226 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2229 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2232 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2235 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2238 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2241 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2246 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2247 gen_op_iwmmxt_set_mup();
2248 gen_op_iwmmxt_set_cup();
2250 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2251 case 0x408: case 0x508: case 0x608: case 0x708:
2252 case 0x808: case 0x908: case 0xa08: case 0xb08:
2253 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2254 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2256 wrd
= (insn
>> 12) & 0xf;
2257 rd0
= (insn
>> 16) & 0xf;
2258 rd1
= (insn
>> 0) & 0xf;
2259 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2260 switch ((insn
>> 22) & 3) {
2262 if (insn
& (1 << 21))
2263 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2265 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2268 if (insn
& (1 << 21))
2269 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2271 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2274 if (insn
& (1 << 21))
2275 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2277 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2280 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2281 gen_op_iwmmxt_set_mup();
2282 gen_op_iwmmxt_set_cup();
2284 case 0x201: case 0x203: case 0x205: case 0x207:
2285 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2286 case 0x211: case 0x213: case 0x215: case 0x217:
2287 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2288 wrd
= (insn
>> 5) & 0xf;
2289 rd0
= (insn
>> 12) & 0xf;
2290 rd1
= (insn
>> 0) & 0xf;
2291 if (rd0
== 0xf || rd1
== 0xf)
2293 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2294 tmp
= load_reg(s
, rd0
);
2295 tmp2
= load_reg(s
, rd1
);
2296 switch ((insn
>> 16) & 0xf) {
2297 case 0x0: /* TMIA */
2298 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2300 case 0x8: /* TMIAPH */
2301 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2303 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2304 if (insn
& (1 << 16))
2305 tcg_gen_shri_i32(tmp
, tmp
, 16);
2306 if (insn
& (1 << 17))
2307 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2308 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2311 tcg_temp_free_i32(tmp2
);
2312 tcg_temp_free_i32(tmp
);
2315 tcg_temp_free_i32(tmp2
);
2316 tcg_temp_free_i32(tmp
);
2317 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2318 gen_op_iwmmxt_set_mup();
2327 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2328 (ie. an undefined instruction). */
2329 static int disas_dsp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2331 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2334 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2335 /* Multiply with Internal Accumulate Format */
2336 rd0
= (insn
>> 12) & 0xf;
2338 acc
= (insn
>> 5) & 7;
2343 tmp
= load_reg(s
, rd0
);
2344 tmp2
= load_reg(s
, rd1
);
2345 switch ((insn
>> 16) & 0xf) {
2347 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2349 case 0x8: /* MIAPH */
2350 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2352 case 0xc: /* MIABB */
2353 case 0xd: /* MIABT */
2354 case 0xe: /* MIATB */
2355 case 0xf: /* MIATT */
2356 if (insn
& (1 << 16))
2357 tcg_gen_shri_i32(tmp
, tmp
, 16);
2358 if (insn
& (1 << 17))
2359 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2360 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2365 tcg_temp_free_i32(tmp2
);
2366 tcg_temp_free_i32(tmp
);
2368 gen_op_iwmmxt_movq_wRn_M0(acc
);
2372 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2373 /* Internal Accumulator Access Format */
2374 rdhi
= (insn
>> 16) & 0xf;
2375 rdlo
= (insn
>> 12) & 0xf;
2381 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2382 iwmmxt_load_reg(cpu_V0
, acc
);
2383 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2384 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2385 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2386 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2388 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2389 iwmmxt_store_reg(cpu_V0
, acc
);
2397 /* Disassemble system coprocessor instruction. Return nonzero if
2398 instruction is not defined. */
2399 static int disas_cp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2402 uint32_t rd
= (insn
>> 12) & 0xf;
2403 uint32_t cp
= (insn
>> 8) & 0xf;
2408 if (insn
& ARM_CP_RW_BIT
) {
2409 if (!env
->cp
[cp
].cp_read
)
2411 gen_set_pc_im(s
->pc
);
2412 tmp
= tcg_temp_new_i32();
2413 tmp2
= tcg_const_i32(insn
);
2414 gen_helper_get_cp(tmp
, cpu_env
, tmp2
);
2415 tcg_temp_free(tmp2
);
2416 store_reg(s
, rd
, tmp
);
2418 if (!env
->cp
[cp
].cp_write
)
2420 gen_set_pc_im(s
->pc
);
2421 tmp
= load_reg(s
, rd
);
2422 tmp2
= tcg_const_i32(insn
);
2423 gen_helper_set_cp(cpu_env
, tmp2
, tmp
);
2424 tcg_temp_free(tmp2
);
2425 tcg_temp_free_i32(tmp
);
2430 static int cp15_user_ok(uint32_t insn
)
2432 int cpn
= (insn
>> 16) & 0xf;
2433 int cpm
= insn
& 0xf;
2434 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2436 if (cpn
== 13 && cpm
== 0) {
2438 if (op
== 2 || (op
== 3 && (insn
& ARM_CP_RW_BIT
)))
2442 /* ISB, DSB, DMB. */
2443 if ((cpm
== 5 && op
== 4)
2444 || (cpm
== 10 && (op
== 4 || op
== 5)))
2450 static int cp15_tls_load_store(CPUState
*env
, DisasContext
*s
, uint32_t insn
, uint32_t rd
)
2453 int cpn
= (insn
>> 16) & 0xf;
2454 int cpm
= insn
& 0xf;
2455 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2457 if (!arm_feature(env
, ARM_FEATURE_V6K
))
2460 if (!(cpn
== 13 && cpm
== 0))
2463 if (insn
& ARM_CP_RW_BIT
) {
2466 tmp
= load_cpu_field(cp15
.c13_tls1
);
2469 tmp
= load_cpu_field(cp15
.c13_tls2
);
2472 tmp
= load_cpu_field(cp15
.c13_tls3
);
2477 store_reg(s
, rd
, tmp
);
2480 tmp
= load_reg(s
, rd
);
2483 store_cpu_field(tmp
, cp15
.c13_tls1
);
2486 store_cpu_field(tmp
, cp15
.c13_tls2
);
2489 store_cpu_field(tmp
, cp15
.c13_tls3
);
2492 tcg_temp_free_i32(tmp
);
2499 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2500 instruction is not defined. */
2501 static int disas_cp15_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2506 /* M profile cores use memory mapped registers instead of cp15. */
2507 if (arm_feature(env
, ARM_FEATURE_M
))
2510 if ((insn
& (1 << 25)) == 0) {
2511 if (insn
& (1 << 20)) {
2515 /* mcrr. Used for block cache operations, so implement as no-op. */
2518 if ((insn
& (1 << 4)) == 0) {
2522 if (IS_USER(s
) && !cp15_user_ok(insn
)) {
2526 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2527 * instructions rather than a separate instruction.
2529 if ((insn
& 0x0fff0fff) == 0x0e070f90) {
2530 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2531 * In v7, this must NOP.
2533 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2534 /* Wait for interrupt. */
2535 gen_set_pc_im(s
->pc
);
2536 s
->is_jmp
= DISAS_WFI
;
2541 if ((insn
& 0x0fff0fff) == 0x0e070f58) {
2542 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2543 * so this is slightly over-broad.
2545 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2546 /* Wait for interrupt. */
2547 gen_set_pc_im(s
->pc
);
2548 s
->is_jmp
= DISAS_WFI
;
2551 /* Otherwise fall through to handle via helper function.
2552 * In particular, on v7 and some v6 cores this is one of
2553 * the VA-PA registers.
2557 rd
= (insn
>> 12) & 0xf;
2559 if (cp15_tls_load_store(env
, s
, insn
, rd
))
2562 tmp2
= tcg_const_i32(insn
);
2563 if (insn
& ARM_CP_RW_BIT
) {
2564 tmp
= tcg_temp_new_i32();
2565 gen_helper_get_cp15(tmp
, cpu_env
, tmp2
);
2566 /* If the destination register is r15 then sets condition codes. */
2568 store_reg(s
, rd
, tmp
);
2570 tcg_temp_free_i32(tmp
);
2572 tmp
= load_reg(s
, rd
);
2573 gen_helper_set_cp15(cpu_env
, tmp2
, tmp
);
2574 tcg_temp_free_i32(tmp
);
2575 /* Normally we would always end the TB here, but Linux
2576 * arch/arm/mach-pxa/sleep.S expects two instructions following
2577 * an MMU enable to execute from cache. Imitate this behaviour. */
2578 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) ||
2579 (insn
& 0x0fff0fff) != 0x0e010f10)
2582 tcg_temp_free_i32(tmp2
);
2586 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2587 #define VFP_SREG(insn, bigbit, smallbit) \
2588 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2589 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2590 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2591 reg = (((insn) >> (bigbit)) & 0x0f) \
2592 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2594 if (insn & (1 << (smallbit))) \
2596 reg = ((insn) >> (bigbit)) & 0x0f; \
2599 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2600 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2601 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2602 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2603 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2604 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2606 /* Move between integer and VFP cores. */
2607 static TCGv
gen_vfp_mrs(void)
2609 TCGv tmp
= tcg_temp_new_i32();
2610 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2614 static void gen_vfp_msr(TCGv tmp
)
2616 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2617 tcg_temp_free_i32(tmp
);
2620 static void gen_neon_dup_u8(TCGv var
, int shift
)
2622 TCGv tmp
= tcg_temp_new_i32();
2624 tcg_gen_shri_i32(var
, var
, shift
);
2625 tcg_gen_ext8u_i32(var
, var
);
2626 tcg_gen_shli_i32(tmp
, var
, 8);
2627 tcg_gen_or_i32(var
, var
, tmp
);
2628 tcg_gen_shli_i32(tmp
, var
, 16);
2629 tcg_gen_or_i32(var
, var
, tmp
);
2630 tcg_temp_free_i32(tmp
);
2633 static void gen_neon_dup_low16(TCGv var
)
2635 TCGv tmp
= tcg_temp_new_i32();
2636 tcg_gen_ext16u_i32(var
, var
);
2637 tcg_gen_shli_i32(tmp
, var
, 16);
2638 tcg_gen_or_i32(var
, var
, tmp
);
2639 tcg_temp_free_i32(tmp
);
2642 static void gen_neon_dup_high16(TCGv var
)
2644 TCGv tmp
= tcg_temp_new_i32();
2645 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2646 tcg_gen_shri_i32(tmp
, var
, 16);
2647 tcg_gen_or_i32(var
, var
, tmp
);
2648 tcg_temp_free_i32(tmp
);
2651 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2652 (ie. an undefined instruction). */
2653 static int disas_vfp_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
2655 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
2661 if (!arm_feature(env
, ARM_FEATURE_VFP
))
2664 if (!s
->vfp_enabled
) {
2665 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2666 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
2668 rn
= (insn
>> 16) & 0xf;
2669 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
2670 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
)
2673 dp
= ((insn
& 0xf00) == 0xb00);
2674 switch ((insn
>> 24) & 0xf) {
2676 if (insn
& (1 << 4)) {
2677 /* single register transfer */
2678 rd
= (insn
>> 12) & 0xf;
2683 VFP_DREG_N(rn
, insn
);
2686 if (insn
& 0x00c00060
2687 && !arm_feature(env
, ARM_FEATURE_NEON
))
2690 pass
= (insn
>> 21) & 1;
2691 if (insn
& (1 << 22)) {
2693 offset
= ((insn
>> 5) & 3) * 8;
2694 } else if (insn
& (1 << 5)) {
2696 offset
= (insn
& (1 << 6)) ? 16 : 0;
2701 if (insn
& ARM_CP_RW_BIT
) {
2703 tmp
= neon_load_reg(rn
, pass
);
2707 tcg_gen_shri_i32(tmp
, tmp
, offset
);
2708 if (insn
& (1 << 23))
2714 if (insn
& (1 << 23)) {
2716 tcg_gen_shri_i32(tmp
, tmp
, 16);
2722 tcg_gen_sari_i32(tmp
, tmp
, 16);
2731 store_reg(s
, rd
, tmp
);
2734 tmp
= load_reg(s
, rd
);
2735 if (insn
& (1 << 23)) {
2738 gen_neon_dup_u8(tmp
, 0);
2739 } else if (size
== 1) {
2740 gen_neon_dup_low16(tmp
);
2742 for (n
= 0; n
<= pass
* 2; n
++) {
2743 tmp2
= tcg_temp_new_i32();
2744 tcg_gen_mov_i32(tmp2
, tmp
);
2745 neon_store_reg(rn
, n
, tmp2
);
2747 neon_store_reg(rn
, n
, tmp
);
2752 tmp2
= neon_load_reg(rn
, pass
);
2753 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xff);
2754 tcg_temp_free_i32(tmp2
);
2757 tmp2
= neon_load_reg(rn
, pass
);
2758 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xffff);
2759 tcg_temp_free_i32(tmp2
);
2764 neon_store_reg(rn
, pass
, tmp
);
2768 if ((insn
& 0x6f) != 0x00)
2770 rn
= VFP_SREG_N(insn
);
2771 if (insn
& ARM_CP_RW_BIT
) {
2773 if (insn
& (1 << 21)) {
2774 /* system register */
2779 /* VFP2 allows access to FSID from userspace.
2780 VFP3 restricts all id registers to privileged
2783 && arm_feature(env
, ARM_FEATURE_VFP3
))
2785 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2790 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2792 case ARM_VFP_FPINST
:
2793 case ARM_VFP_FPINST2
:
2794 /* Not present in VFP3. */
2796 || arm_feature(env
, ARM_FEATURE_VFP3
))
2798 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2802 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
2803 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
2805 tmp
= tcg_temp_new_i32();
2806 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
2812 || !arm_feature(env
, ARM_FEATURE_VFP3
))
2814 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2820 gen_mov_F0_vreg(0, rn
);
2821 tmp
= gen_vfp_mrs();
2824 /* Set the 4 flag bits in the CPSR. */
2826 tcg_temp_free_i32(tmp
);
2828 store_reg(s
, rd
, tmp
);
2832 tmp
= load_reg(s
, rd
);
2833 if (insn
& (1 << 21)) {
2835 /* system register */
2840 /* Writes are ignored. */
2843 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
2844 tcg_temp_free_i32(tmp
);
2850 /* TODO: VFP subarchitecture support.
2851 * For now, keep the EN bit only */
2852 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
2853 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2856 case ARM_VFP_FPINST
:
2857 case ARM_VFP_FPINST2
:
2858 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2865 gen_mov_vreg_F0(0, rn
);
2870 /* data processing */
2871 /* The opcode is in bits 23, 21, 20 and 6. */
2872 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
2876 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
2878 /* rn is register number */
2879 VFP_DREG_N(rn
, insn
);
2882 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18))) {
2883 /* Integer or single precision destination. */
2884 rd
= VFP_SREG_D(insn
);
2886 VFP_DREG_D(rd
, insn
);
2889 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14))) {
2890 /* VCVT from int is always from S reg regardless of dp bit.
2891 * VCVT with immediate frac_bits has same format as SREG_M
2893 rm
= VFP_SREG_M(insn
);
2895 VFP_DREG_M(rm
, insn
);
2898 rn
= VFP_SREG_N(insn
);
2899 if (op
== 15 && rn
== 15) {
2900 /* Double precision destination. */
2901 VFP_DREG_D(rd
, insn
);
2903 rd
= VFP_SREG_D(insn
);
2905 /* NB that we implicitly rely on the encoding for the frac_bits
2906 * in VCVT of fixed to float being the same as that of an SREG_M
2908 rm
= VFP_SREG_M(insn
);
2911 veclen
= s
->vec_len
;
2912 if (op
== 15 && rn
> 3)
2915 /* Shut up compiler warnings. */
2926 /* Figure out what type of vector operation this is. */
2927 if ((rd
& bank_mask
) == 0) {
2932 delta_d
= (s
->vec_stride
>> 1) + 1;
2934 delta_d
= s
->vec_stride
+ 1;
2936 if ((rm
& bank_mask
) == 0) {
2937 /* mixed scalar/vector */
2946 /* Load the initial operands. */
2951 /* Integer source */
2952 gen_mov_F0_vreg(0, rm
);
2957 gen_mov_F0_vreg(dp
, rd
);
2958 gen_mov_F1_vreg(dp
, rm
);
2962 /* Compare with zero */
2963 gen_mov_F0_vreg(dp
, rd
);
2974 /* Source and destination the same. */
2975 gen_mov_F0_vreg(dp
, rd
);
2978 /* One source operand. */
2979 gen_mov_F0_vreg(dp
, rm
);
2983 /* Two source operands. */
2984 gen_mov_F0_vreg(dp
, rn
);
2985 gen_mov_F1_vreg(dp
, rm
);
2989 /* Perform the calculation. */
2991 case 0: /* mac: fd + (fn * fm) */
2993 gen_mov_F1_vreg(dp
, rd
);
2996 case 1: /* nmac: fd - (fn * fm) */
2999 gen_mov_F1_vreg(dp
, rd
);
3002 case 2: /* msc: -fd + (fn * fm) */
3004 gen_mov_F1_vreg(dp
, rd
);
3007 case 3: /* nmsc: -fd - (fn * fm) */
3010 gen_mov_F1_vreg(dp
, rd
);
3013 case 4: /* mul: fn * fm */
3016 case 5: /* nmul: -(fn * fm) */
3020 case 6: /* add: fn + fm */
3023 case 7: /* sub: fn - fm */
3026 case 8: /* div: fn / fm */
3029 case 14: /* fconst */
3030 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3033 n
= (insn
<< 12) & 0x80000000;
3034 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3041 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3048 tcg_gen_movi_i32(cpu_F0s
, n
);
3051 case 15: /* extension space */
3065 case 4: /* vcvtb.f32.f16 */
3066 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3068 tmp
= gen_vfp_mrs();
3069 tcg_gen_ext16u_i32(tmp
, tmp
);
3070 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3071 tcg_temp_free_i32(tmp
);
3073 case 5: /* vcvtt.f32.f16 */
3074 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3076 tmp
= gen_vfp_mrs();
3077 tcg_gen_shri_i32(tmp
, tmp
, 16);
3078 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3079 tcg_temp_free_i32(tmp
);
3081 case 6: /* vcvtb.f16.f32 */
3082 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3084 tmp
= tcg_temp_new_i32();
3085 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3086 gen_mov_F0_vreg(0, rd
);
3087 tmp2
= gen_vfp_mrs();
3088 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3089 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3090 tcg_temp_free_i32(tmp2
);
3093 case 7: /* vcvtt.f16.f32 */
3094 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3096 tmp
= tcg_temp_new_i32();
3097 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3098 tcg_gen_shli_i32(tmp
, tmp
, 16);
3099 gen_mov_F0_vreg(0, rd
);
3100 tmp2
= gen_vfp_mrs();
3101 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3102 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3103 tcg_temp_free_i32(tmp2
);
3115 case 11: /* cmpez */
3119 case 15: /* single<->double conversion */
3121 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3123 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3125 case 16: /* fuito */
3128 case 17: /* fsito */
3131 case 20: /* fshto */
3132 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3134 gen_vfp_shto(dp
, 16 - rm
);
3136 case 21: /* fslto */
3137 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3139 gen_vfp_slto(dp
, 32 - rm
);
3141 case 22: /* fuhto */
3142 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3144 gen_vfp_uhto(dp
, 16 - rm
);
3146 case 23: /* fulto */
3147 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3149 gen_vfp_ulto(dp
, 32 - rm
);
3151 case 24: /* ftoui */
3154 case 25: /* ftouiz */
3157 case 26: /* ftosi */
3160 case 27: /* ftosiz */
3163 case 28: /* ftosh */
3164 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3166 gen_vfp_tosh(dp
, 16 - rm
);
3168 case 29: /* ftosl */
3169 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3171 gen_vfp_tosl(dp
, 32 - rm
);
3173 case 30: /* ftouh */
3174 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3176 gen_vfp_touh(dp
, 16 - rm
);
3178 case 31: /* ftoul */
3179 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3181 gen_vfp_toul(dp
, 32 - rm
);
3183 default: /* undefined */
3184 printf ("rn:%d\n", rn
);
3188 default: /* undefined */
3189 printf ("op:%d\n", op
);
3193 /* Write back the result. */
3194 if (op
== 15 && (rn
>= 8 && rn
<= 11))
3195 ; /* Comparison, do nothing. */
3196 else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18))
3197 /* VCVT double to int: always integer result. */
3198 gen_mov_vreg_F0(0, rd
);
3199 else if (op
== 15 && rn
== 15)
3201 gen_mov_vreg_F0(!dp
, rd
);
3203 gen_mov_vreg_F0(dp
, rd
);
3205 /* break out of the loop if we have finished */
3209 if (op
== 15 && delta_m
== 0) {
3210 /* single source one-many */
3212 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3214 gen_mov_vreg_F0(dp
, rd
);
3218 /* Setup the next operands. */
3220 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3224 /* One source operand. */
3225 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3227 gen_mov_F0_vreg(dp
, rm
);
3229 /* Two source operands. */
3230 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3232 gen_mov_F0_vreg(dp
, rn
);
3234 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3236 gen_mov_F1_vreg(dp
, rm
);
3244 if ((insn
& 0x03e00000) == 0x00400000) {
3245 /* two-register transfer */
3246 rn
= (insn
>> 16) & 0xf;
3247 rd
= (insn
>> 12) & 0xf;
3249 VFP_DREG_M(rm
, insn
);
3251 rm
= VFP_SREG_M(insn
);
3254 if (insn
& ARM_CP_RW_BIT
) {
3257 gen_mov_F0_vreg(0, rm
* 2);
3258 tmp
= gen_vfp_mrs();
3259 store_reg(s
, rd
, tmp
);
3260 gen_mov_F0_vreg(0, rm
* 2 + 1);
3261 tmp
= gen_vfp_mrs();
3262 store_reg(s
, rn
, tmp
);
3264 gen_mov_F0_vreg(0, rm
);
3265 tmp
= gen_vfp_mrs();
3266 store_reg(s
, rd
, tmp
);
3267 gen_mov_F0_vreg(0, rm
+ 1);
3268 tmp
= gen_vfp_mrs();
3269 store_reg(s
, rn
, tmp
);
3274 tmp
= load_reg(s
, rd
);
3276 gen_mov_vreg_F0(0, rm
* 2);
3277 tmp
= load_reg(s
, rn
);
3279 gen_mov_vreg_F0(0, rm
* 2 + 1);
3281 tmp
= load_reg(s
, rd
);
3283 gen_mov_vreg_F0(0, rm
);
3284 tmp
= load_reg(s
, rn
);
3286 gen_mov_vreg_F0(0, rm
+ 1);
3291 rn
= (insn
>> 16) & 0xf;
3293 VFP_DREG_D(rd
, insn
);
3295 rd
= VFP_SREG_D(insn
);
3296 if (s
->thumb
&& rn
== 15) {
3297 addr
= tcg_temp_new_i32();
3298 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3300 addr
= load_reg(s
, rn
);
3302 if ((insn
& 0x01200000) == 0x01000000) {
3303 /* Single load/store */
3304 offset
= (insn
& 0xff) << 2;
3305 if ((insn
& (1 << 23)) == 0)
3307 tcg_gen_addi_i32(addr
, addr
, offset
);
3308 if (insn
& (1 << 20)) {
3309 gen_vfp_ld(s
, dp
, addr
);
3310 gen_mov_vreg_F0(dp
, rd
);
3312 gen_mov_F0_vreg(dp
, rd
);
3313 gen_vfp_st(s
, dp
, addr
);
3315 tcg_temp_free_i32(addr
);
3317 /* load/store multiple */
3319 n
= (insn
>> 1) & 0x7f;
3323 if (insn
& (1 << 24)) /* pre-decrement */
3324 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
3330 for (i
= 0; i
< n
; i
++) {
3331 if (insn
& ARM_CP_RW_BIT
) {
3333 gen_vfp_ld(s
, dp
, addr
);
3334 gen_mov_vreg_F0(dp
, rd
+ i
);
3337 gen_mov_F0_vreg(dp
, rd
+ i
);
3338 gen_vfp_st(s
, dp
, addr
);
3340 tcg_gen_addi_i32(addr
, addr
, offset
);
3342 if (insn
& (1 << 21)) {
3344 if (insn
& (1 << 24))
3345 offset
= -offset
* n
;
3346 else if (dp
&& (insn
& 1))
3352 tcg_gen_addi_i32(addr
, addr
, offset
);
3353 store_reg(s
, rn
, addr
);
3355 tcg_temp_free_i32(addr
);
3361 /* Should never happen. */
3367 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
3369 TranslationBlock
*tb
;
3372 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3374 gen_set_pc_im(dest
);
3375 tcg_gen_exit_tb((long)tb
+ n
);
3377 gen_set_pc_im(dest
);
3382 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
3384 if (unlikely(s
->singlestep_enabled
)) {
3385 /* An indirect jump so that we still trigger the debug exception. */
3390 gen_goto_tb(s
, 0, dest
);
3391 s
->is_jmp
= DISAS_TB_JUMP
;
3395 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
3398 tcg_gen_sari_i32(t0
, t0
, 16);
3402 tcg_gen_sari_i32(t1
, t1
, 16);
3405 tcg_gen_mul_i32(t0
, t0
, t1
);
3408 /* Return the mask of PSR bits set by a MSR instruction. */
3409 static uint32_t msr_mask(CPUState
*env
, DisasContext
*s
, int flags
, int spsr
) {
3413 if (flags
& (1 << 0))
3415 if (flags
& (1 << 1))
3417 if (flags
& (1 << 2))
3419 if (flags
& (1 << 3))
3422 /* Mask out undefined bits. */
3423 mask
&= ~CPSR_RESERVED
;
3424 if (!arm_feature(env
, ARM_FEATURE_V6
))
3425 mask
&= ~(CPSR_E
| CPSR_GE
);
3426 if (!arm_feature(env
, ARM_FEATURE_THUMB2
))
3428 /* Mask out execution state bits. */
3431 /* Mask out privileged bits. */
3437 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3438 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv t0
)
3442 /* ??? This is also undefined in system mode. */
3446 tmp
= load_cpu_field(spsr
);
3447 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
3448 tcg_gen_andi_i32(t0
, t0
, mask
);
3449 tcg_gen_or_i32(tmp
, tmp
, t0
);
3450 store_cpu_field(tmp
, spsr
);
3452 gen_set_cpsr(t0
, mask
);
3454 tcg_temp_free_i32(t0
);
3459 /* Returns nonzero if access to the PSR is not permitted. */
3460 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3463 tmp
= tcg_temp_new_i32();
3464 tcg_gen_movi_i32(tmp
, val
);
3465 return gen_set_psr(s
, mask
, spsr
, tmp
);
3468 /* Generate an old-style exception return. Marks pc as dead. */
3469 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
3472 store_reg(s
, 15, pc
);
3473 tmp
= load_cpu_field(spsr
);
3474 gen_set_cpsr(tmp
, 0xffffffff);
3475 tcg_temp_free_i32(tmp
);
3476 s
->is_jmp
= DISAS_UPDATE
;
3479 /* Generate a v6 exception return. Marks both values as dead. */
3480 static void gen_rfe(DisasContext
*s
, TCGv pc
, TCGv cpsr
)
3482 gen_set_cpsr(cpsr
, 0xffffffff);
3483 tcg_temp_free_i32(cpsr
);
3484 store_reg(s
, 15, pc
);
3485 s
->is_jmp
= DISAS_UPDATE
;
3489 gen_set_condexec (DisasContext
*s
)
3491 if (s
->condexec_mask
) {
3492 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
3493 TCGv tmp
= tcg_temp_new_i32();
3494 tcg_gen_movi_i32(tmp
, val
);
3495 store_cpu_field(tmp
, condexec_bits
);
3499 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
3501 gen_set_condexec(s
);
3502 gen_set_pc_im(s
->pc
- offset
);
3503 gen_exception(excp
);
3504 s
->is_jmp
= DISAS_JUMP
;
3507 static void gen_nop_hint(DisasContext
*s
, int val
)
3511 gen_set_pc_im(s
->pc
);
3512 s
->is_jmp
= DISAS_WFI
;
3516 /* TODO: Implement SEV and WFE. May help SMP performance. */
3522 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3524 static inline int gen_neon_add(int size
, TCGv t0
, TCGv t1
)
3527 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3528 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3529 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3535 static inline void gen_neon_rsb(int size
, TCGv t0
, TCGv t1
)
3538 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3539 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3540 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3545 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3546 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3547 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3548 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3549 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3551 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3552 switch ((size << 1) | u) { \
3554 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3557 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3560 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3563 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3566 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3569 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3571 default: return 1; \
3574 #define GEN_NEON_INTEGER_OP(name) do { \
3575 switch ((size << 1) | u) { \
3577 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3580 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3583 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3586 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3589 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3592 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3594 default: return 1; \
3597 static TCGv
neon_load_scratch(int scratch
)
3599 TCGv tmp
= tcg_temp_new_i32();
3600 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3604 static void neon_store_scratch(int scratch
, TCGv var
)
3606 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3607 tcg_temp_free_i32(var
);
3610 static inline TCGv
neon_get_scalar(int size
, int reg
)
3614 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3616 gen_neon_dup_high16(tmp
);
3618 gen_neon_dup_low16(tmp
);
3621 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3626 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3629 if (size
== 3 || (!q
&& size
== 2)) {
3632 tmp
= tcg_const_i32(rd
);
3633 tmp2
= tcg_const_i32(rm
);
3637 gen_helper_neon_qunzip8(cpu_env
, tmp
, tmp2
);
3640 gen_helper_neon_qunzip16(cpu_env
, tmp
, tmp2
);
3643 gen_helper_neon_qunzip32(cpu_env
, tmp
, tmp2
);
3651 gen_helper_neon_unzip8(cpu_env
, tmp
, tmp2
);
3654 gen_helper_neon_unzip16(cpu_env
, tmp
, tmp2
);
3660 tcg_temp_free_i32(tmp
);
3661 tcg_temp_free_i32(tmp2
);
3665 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3668 if (size
== 3 || (!q
&& size
== 2)) {
3671 tmp
= tcg_const_i32(rd
);
3672 tmp2
= tcg_const_i32(rm
);
3676 gen_helper_neon_qzip8(cpu_env
, tmp
, tmp2
);
3679 gen_helper_neon_qzip16(cpu_env
, tmp
, tmp2
);
3682 gen_helper_neon_qzip32(cpu_env
, tmp
, tmp2
);
3690 gen_helper_neon_zip8(cpu_env
, tmp
, tmp2
);
3693 gen_helper_neon_zip16(cpu_env
, tmp
, tmp2
);
3699 tcg_temp_free_i32(tmp
);
3700 tcg_temp_free_i32(tmp2
);
3704 static void gen_neon_trn_u8(TCGv t0
, TCGv t1
)
3708 rd
= tcg_temp_new_i32();
3709 tmp
= tcg_temp_new_i32();
3711 tcg_gen_shli_i32(rd
, t0
, 8);
3712 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3713 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3714 tcg_gen_or_i32(rd
, rd
, tmp
);
3716 tcg_gen_shri_i32(t1
, t1
, 8);
3717 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3718 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3719 tcg_gen_or_i32(t1
, t1
, tmp
);
3720 tcg_gen_mov_i32(t0
, rd
);
3722 tcg_temp_free_i32(tmp
);
3723 tcg_temp_free_i32(rd
);
3726 static void gen_neon_trn_u16(TCGv t0
, TCGv t1
)
3730 rd
= tcg_temp_new_i32();
3731 tmp
= tcg_temp_new_i32();
3733 tcg_gen_shli_i32(rd
, t0
, 16);
3734 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3735 tcg_gen_or_i32(rd
, rd
, tmp
);
3736 tcg_gen_shri_i32(t1
, t1
, 16);
3737 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3738 tcg_gen_or_i32(t1
, t1
, tmp
);
3739 tcg_gen_mov_i32(t0
, rd
);
3741 tcg_temp_free_i32(tmp
);
3742 tcg_temp_free_i32(rd
);
3750 } neon_ls_element_type
[11] = {
3764 /* Translate a NEON load/store element instruction. Return nonzero if the
3765 instruction is invalid. */
3766 static int disas_neon_ls_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
3785 if (!s
->vfp_enabled
)
3787 VFP_DREG_D(rd
, insn
);
3788 rn
= (insn
>> 16) & 0xf;
3790 load
= (insn
& (1 << 21)) != 0;
3791 addr
= tcg_temp_new_i32();
3792 if ((insn
& (1 << 23)) == 0) {
3793 /* Load store all elements. */
3794 op
= (insn
>> 8) & 0xf;
3795 size
= (insn
>> 6) & 3;
3798 nregs
= neon_ls_element_type
[op
].nregs
;
3799 interleave
= neon_ls_element_type
[op
].interleave
;
3800 spacing
= neon_ls_element_type
[op
].spacing
;
3801 if (size
== 3 && (interleave
| spacing
) != 1)
3803 load_reg_var(s
, addr
, rn
);
3804 stride
= (1 << size
) * interleave
;
3805 for (reg
= 0; reg
< nregs
; reg
++) {
3806 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
3807 load_reg_var(s
, addr
, rn
);
3808 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
3809 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
3810 load_reg_var(s
, addr
, rn
);
3811 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3815 tmp64
= gen_ld64(addr
, IS_USER(s
));
3816 neon_store_reg64(tmp64
, rd
);
3817 tcg_temp_free_i64(tmp64
);
3819 tmp64
= tcg_temp_new_i64();
3820 neon_load_reg64(tmp64
, rd
);
3821 gen_st64(tmp64
, addr
, IS_USER(s
));
3823 tcg_gen_addi_i32(addr
, addr
, stride
);
3825 for (pass
= 0; pass
< 2; pass
++) {
3828 tmp
= gen_ld32(addr
, IS_USER(s
));
3829 neon_store_reg(rd
, pass
, tmp
);
3831 tmp
= neon_load_reg(rd
, pass
);
3832 gen_st32(tmp
, addr
, IS_USER(s
));
3834 tcg_gen_addi_i32(addr
, addr
, stride
);
3835 } else if (size
== 1) {
3837 tmp
= gen_ld16u(addr
, IS_USER(s
));
3838 tcg_gen_addi_i32(addr
, addr
, stride
);
3839 tmp2
= gen_ld16u(addr
, IS_USER(s
));
3840 tcg_gen_addi_i32(addr
, addr
, stride
);
3841 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
3842 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3843 tcg_temp_free_i32(tmp2
);
3844 neon_store_reg(rd
, pass
, tmp
);
3846 tmp
= neon_load_reg(rd
, pass
);
3847 tmp2
= tcg_temp_new_i32();
3848 tcg_gen_shri_i32(tmp2
, tmp
, 16);
3849 gen_st16(tmp
, addr
, IS_USER(s
));
3850 tcg_gen_addi_i32(addr
, addr
, stride
);
3851 gen_st16(tmp2
, addr
, IS_USER(s
));
3852 tcg_gen_addi_i32(addr
, addr
, stride
);
3854 } else /* size == 0 */ {
3857 for (n
= 0; n
< 4; n
++) {
3858 tmp
= gen_ld8u(addr
, IS_USER(s
));
3859 tcg_gen_addi_i32(addr
, addr
, stride
);
3863 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
3864 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
3865 tcg_temp_free_i32(tmp
);
3868 neon_store_reg(rd
, pass
, tmp2
);
3870 tmp2
= neon_load_reg(rd
, pass
);
3871 for (n
= 0; n
< 4; n
++) {
3872 tmp
= tcg_temp_new_i32();
3874 tcg_gen_mov_i32(tmp
, tmp2
);
3876 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
3878 gen_st8(tmp
, addr
, IS_USER(s
));
3879 tcg_gen_addi_i32(addr
, addr
, stride
);
3881 tcg_temp_free_i32(tmp2
);
3890 size
= (insn
>> 10) & 3;
3892 /* Load single element to all lanes. */
3895 size
= (insn
>> 6) & 3;
3896 nregs
= ((insn
>> 8) & 3) + 1;
3897 stride
= (insn
& (1 << 5)) ? 2 : 1;
3898 load_reg_var(s
, addr
, rn
);
3899 for (reg
= 0; reg
< nregs
; reg
++) {
3902 tmp
= gen_ld8u(addr
, IS_USER(s
));
3903 gen_neon_dup_u8(tmp
, 0);
3906 tmp
= gen_ld16u(addr
, IS_USER(s
));
3907 gen_neon_dup_low16(tmp
);
3910 tmp
= gen_ld32(addr
, IS_USER(s
));
3914 default: /* Avoid compiler warnings. */
3917 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3918 tmp2
= tcg_temp_new_i32();
3919 tcg_gen_mov_i32(tmp2
, tmp
);
3920 neon_store_reg(rd
, 0, tmp2
);
3921 neon_store_reg(rd
, 1, tmp
);
3924 stride
= (1 << size
) * nregs
;
3926 /* Single element. */
3927 pass
= (insn
>> 7) & 1;
3930 shift
= ((insn
>> 5) & 3) * 8;
3934 shift
= ((insn
>> 6) & 1) * 16;
3935 stride
= (insn
& (1 << 5)) ? 2 : 1;
3939 stride
= (insn
& (1 << 6)) ? 2 : 1;
3944 nregs
= ((insn
>> 8) & 3) + 1;
3945 load_reg_var(s
, addr
, rn
);
3946 for (reg
= 0; reg
< nregs
; reg
++) {
3950 tmp
= gen_ld8u(addr
, IS_USER(s
));
3953 tmp
= gen_ld16u(addr
, IS_USER(s
));
3956 tmp
= gen_ld32(addr
, IS_USER(s
));
3958 default: /* Avoid compiler warnings. */
3962 tmp2
= neon_load_reg(rd
, pass
);
3963 gen_bfi(tmp
, tmp2
, tmp
, shift
, size
? 0xffff : 0xff);
3964 tcg_temp_free_i32(tmp2
);
3966 neon_store_reg(rd
, pass
, tmp
);
3967 } else { /* Store */
3968 tmp
= neon_load_reg(rd
, pass
);
3970 tcg_gen_shri_i32(tmp
, tmp
, shift
);
3973 gen_st8(tmp
, addr
, IS_USER(s
));
3976 gen_st16(tmp
, addr
, IS_USER(s
));
3979 gen_st32(tmp
, addr
, IS_USER(s
));
3984 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3986 stride
= nregs
* (1 << size
);
3989 tcg_temp_free_i32(addr
);
3993 base
= load_reg(s
, rn
);
3995 tcg_gen_addi_i32(base
, base
, stride
);
3998 index
= load_reg(s
, rm
);
3999 tcg_gen_add_i32(base
, base
, index
);
4000 tcg_temp_free_i32(index
);
4002 store_reg(s
, rn
, base
);
4007 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4008 static void gen_neon_bsl(TCGv dest
, TCGv t
, TCGv f
, TCGv c
)
4010 tcg_gen_and_i32(t
, t
, c
);
4011 tcg_gen_andc_i32(f
, f
, c
);
4012 tcg_gen_or_i32(dest
, t
, f
);
4015 static inline void gen_neon_narrow(int size
, TCGv dest
, TCGv_i64 src
)
4018 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
4019 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
4020 case 2: tcg_gen_trunc_i64_i32(dest
, src
); break;
4025 static inline void gen_neon_narrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4028 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
4029 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
4030 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
4035 static inline void gen_neon_narrow_satu(int size
, TCGv dest
, TCGv_i64 src
)
4038 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
4039 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
4040 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
4045 static inline void gen_neon_unarrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4048 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
4049 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
4050 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
4055 static inline void gen_neon_shift_narrow(int size
, TCGv var
, TCGv shift
,
4061 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
4062 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
4067 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
4068 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
4075 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
4076 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
4081 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
4082 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
4089 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv src
, int size
, int u
)
4093 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
4094 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
4095 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
4100 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
4101 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
4102 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
4106 tcg_temp_free_i32(src
);
4109 static inline void gen_neon_addl(int size
)
4112 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
4113 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
4114 case 2: tcg_gen_add_i64(CPU_V001
); break;
4119 static inline void gen_neon_subl(int size
)
4122 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
4123 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
4124 case 2: tcg_gen_sub_i64(CPU_V001
); break;
4129 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
4132 case 0: gen_helper_neon_negl_u16(var
, var
); break;
4133 case 1: gen_helper_neon_negl_u32(var
, var
); break;
4134 case 2: gen_helper_neon_negl_u64(var
, var
); break;
4139 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
4142 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
4143 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
4148 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv a
, TCGv b
, int size
, int u
)
4152 switch ((size
<< 1) | u
) {
4153 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
4154 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
4155 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
4156 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
4158 tmp
= gen_muls_i64_i32(a
, b
);
4159 tcg_gen_mov_i64(dest
, tmp
);
4162 tmp
= gen_mulu_i64_i32(a
, b
);
4163 tcg_gen_mov_i64(dest
, tmp
);
4168 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4169 Don't forget to clean them now. */
4171 tcg_temp_free_i32(a
);
4172 tcg_temp_free_i32(b
);
4176 static void gen_neon_narrow_op(int op
, int u
, int size
, TCGv dest
, TCGv_i64 src
)
4180 gen_neon_unarrow_sats(size
, dest
, src
);
4182 gen_neon_narrow(size
, dest
, src
);
4186 gen_neon_narrow_satu(size
, dest
, src
);
4188 gen_neon_narrow_sats(size
, dest
, src
);
4193 /* Translate a NEON data processing instruction. Return nonzero if the
4194 instruction is invalid.
4195 We process data in a mixture of 32-bit and 64-bit chunks.
4196 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4198 static int disas_neon_data_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
4211 TCGv tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4214 if (!s
->vfp_enabled
)
4216 q
= (insn
& (1 << 6)) != 0;
4217 u
= (insn
>> 24) & 1;
4218 VFP_DREG_D(rd
, insn
);
4219 VFP_DREG_N(rn
, insn
);
4220 VFP_DREG_M(rm
, insn
);
4221 size
= (insn
>> 20) & 3;
4222 if ((insn
& (1 << 23)) == 0) {
4223 /* Three register same length. */
4224 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4225 if (size
== 3 && (op
== 1 || op
== 5 || op
== 8 || op
== 9
4226 || op
== 10 || op
== 11 || op
== 16)) {
4227 /* 64-bit element instructions. */
4228 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
4229 neon_load_reg64(cpu_V0
, rn
+ pass
);
4230 neon_load_reg64(cpu_V1
, rm
+ pass
);
4234 gen_helper_neon_qadd_u64(cpu_V0
, cpu_env
,
4237 gen_helper_neon_qadd_s64(cpu_V0
, cpu_env
,
4243 gen_helper_neon_qsub_u64(cpu_V0
, cpu_env
,
4246 gen_helper_neon_qsub_s64(cpu_V0
, cpu_env
,
4252 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4254 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4259 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
4262 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
4266 case 10: /* VRSHL */
4268 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4270 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4273 case 11: /* VQRSHL */
4275 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
4278 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
4284 tcg_gen_sub_i64(CPU_V001
);
4286 tcg_gen_add_i64(CPU_V001
);
4292 neon_store_reg64(cpu_V0
, rd
+ pass
);
4299 case 10: /* VRSHL */
4300 case 11: /* VQRSHL */
4303 /* Shift instruction operands are reversed. */
4310 case 20: /* VPMAX */
4311 case 21: /* VPMIN */
4312 case 23: /* VPADD */
4315 case 26: /* VPADD (float) */
4316 pairwise
= (u
&& size
< 2);
4318 case 30: /* VPMIN/VPMAX (float) */
4326 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4335 tmp
= neon_load_reg(rn
, n
);
4336 tmp2
= neon_load_reg(rn
, n
+ 1);
4338 tmp
= neon_load_reg(rm
, n
);
4339 tmp2
= neon_load_reg(rm
, n
+ 1);
4343 tmp
= neon_load_reg(rn
, pass
);
4344 tmp2
= neon_load_reg(rm
, pass
);
4348 GEN_NEON_INTEGER_OP(hadd
);
4351 GEN_NEON_INTEGER_OP_ENV(qadd
);
4353 case 2: /* VRHADD */
4354 GEN_NEON_INTEGER_OP(rhadd
);
4356 case 3: /* Logic ops. */
4357 switch ((u
<< 2) | size
) {
4359 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
4362 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
4365 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4368 tcg_gen_orc_i32(tmp
, tmp
, tmp2
);
4371 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
4374 tmp3
= neon_load_reg(rd
, pass
);
4375 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
4376 tcg_temp_free_i32(tmp3
);
4379 tmp3
= neon_load_reg(rd
, pass
);
4380 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
4381 tcg_temp_free_i32(tmp3
);
4384 tmp3
= neon_load_reg(rd
, pass
);
4385 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
4386 tcg_temp_free_i32(tmp3
);
4391 GEN_NEON_INTEGER_OP(hsub
);
4394 GEN_NEON_INTEGER_OP_ENV(qsub
);
4397 GEN_NEON_INTEGER_OP(cgt
);
4400 GEN_NEON_INTEGER_OP(cge
);
4403 GEN_NEON_INTEGER_OP(shl
);
4406 GEN_NEON_INTEGER_OP_ENV(qshl
);
4408 case 10: /* VRSHL */
4409 GEN_NEON_INTEGER_OP(rshl
);
4411 case 11: /* VQRSHL */
4412 GEN_NEON_INTEGER_OP_ENV(qrshl
);
4415 GEN_NEON_INTEGER_OP(max
);
4418 GEN_NEON_INTEGER_OP(min
);
4421 GEN_NEON_INTEGER_OP(abd
);
4424 GEN_NEON_INTEGER_OP(abd
);
4425 tcg_temp_free_i32(tmp2
);
4426 tmp2
= neon_load_reg(rd
, pass
);
4427 gen_neon_add(size
, tmp
, tmp2
);
4430 if (!u
) { /* VADD */
4431 if (gen_neon_add(size
, tmp
, tmp2
))
4435 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
4436 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
4437 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
4443 if (!u
) { /* VTST */
4445 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
4446 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
4447 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
4452 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
4453 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
4454 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
4459 case 18: /* Multiply. */
4461 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4462 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4463 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4466 tcg_temp_free_i32(tmp2
);
4467 tmp2
= neon_load_reg(rd
, pass
);
4469 gen_neon_rsb(size
, tmp
, tmp2
);
4471 gen_neon_add(size
, tmp
, tmp2
);
4475 if (u
) { /* polynomial */
4476 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
4477 } else { /* Integer */
4479 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4480 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4481 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4486 case 20: /* VPMAX */
4487 GEN_NEON_INTEGER_OP(pmax
);
4489 case 21: /* VPMIN */
4490 GEN_NEON_INTEGER_OP(pmin
);
4492 case 22: /* Hultiply high. */
4493 if (!u
) { /* VQDMULH */
4495 case 1: gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
); break;
4496 case 2: gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
); break;
4499 } else { /* VQRDHMUL */
4501 case 1: gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
); break;
4502 case 2: gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
); break;
4507 case 23: /* VPADD */
4511 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
4512 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
4513 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
4517 case 26: /* Floating point arithnetic. */
4518 switch ((u
<< 2) | size
) {
4520 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4523 gen_helper_neon_sub_f32(tmp
, tmp
, tmp2
);
4526 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4529 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
);
4535 case 27: /* Float multiply. */
4536 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
4538 tcg_temp_free_i32(tmp2
);
4539 tmp2
= neon_load_reg(rd
, pass
);
4541 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4543 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
4547 case 28: /* Float compare. */
4549 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
4552 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
4554 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
4557 case 29: /* Float compare absolute. */
4561 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
);
4563 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
);
4565 case 30: /* Float min/max. */
4567 gen_helper_neon_max_f32(tmp
, tmp
, tmp2
);
4569 gen_helper_neon_min_f32(tmp
, tmp
, tmp2
);
4573 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
4575 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
4580 tcg_temp_free_i32(tmp2
);
4582 /* Save the result. For elementwise operations we can put it
4583 straight into the destination register. For pairwise operations
4584 we have to be careful to avoid clobbering the source operands. */
4585 if (pairwise
&& rd
== rm
) {
4586 neon_store_scratch(pass
, tmp
);
4588 neon_store_reg(rd
, pass
, tmp
);
4592 if (pairwise
&& rd
== rm
) {
4593 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4594 tmp
= neon_load_scratch(pass
);
4595 neon_store_reg(rd
, pass
, tmp
);
4598 /* End of 3 register same size operations. */
4599 } else if (insn
& (1 << 4)) {
4600 if ((insn
& 0x00380080) != 0) {
4601 /* Two registers and shift. */
4602 op
= (insn
>> 8) & 0xf;
4603 if (insn
& (1 << 7)) {
4608 while ((insn
& (1 << (size
+ 19))) == 0)
4611 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
4612 /* To avoid excessive dumplication of ops we implement shift
4613 by immediate using the variable shift operations. */
4615 /* Shift by immediate:
4616 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4617 /* Right shifts are encoded as N - shift, where N is the
4618 element size in bits. */
4620 shift
= shift
- (1 << (size
+ 3));
4628 imm
= (uint8_t) shift
;
4633 imm
= (uint16_t) shift
;
4644 for (pass
= 0; pass
< count
; pass
++) {
4646 neon_load_reg64(cpu_V0
, rm
+ pass
);
4647 tcg_gen_movi_i64(cpu_V1
, imm
);
4652 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4654 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4659 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4661 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4666 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4668 case 5: /* VSHL, VSLI */
4669 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4671 case 6: /* VQSHLU */
4673 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
4681 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
4684 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
4689 if (op
== 1 || op
== 3) {
4691 neon_load_reg64(cpu_V1
, rd
+ pass
);
4692 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4693 } else if (op
== 4 || (op
== 5 && u
)) {
4695 neon_load_reg64(cpu_V1
, rd
+ pass
);
4697 if (shift
< -63 || shift
> 63) {
4701 mask
= 0xffffffffffffffffull
>> -shift
;
4703 mask
= 0xffffffffffffffffull
<< shift
;
4706 tcg_gen_andi_i64(cpu_V1
, cpu_V1
, ~mask
);
4707 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4709 neon_store_reg64(cpu_V0
, rd
+ pass
);
4710 } else { /* size < 3 */
4711 /* Operands in T0 and T1. */
4712 tmp
= neon_load_reg(rm
, pass
);
4713 tmp2
= tcg_temp_new_i32();
4714 tcg_gen_movi_i32(tmp2
, imm
);
4718 GEN_NEON_INTEGER_OP(shl
);
4722 GEN_NEON_INTEGER_OP(rshl
);
4727 GEN_NEON_INTEGER_OP(shl
);
4729 case 5: /* VSHL, VSLI */
4731 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
4732 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
4733 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
4737 case 6: /* VQSHLU */
4743 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
4747 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
4751 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
4759 GEN_NEON_INTEGER_OP_ENV(qshl
);
4762 tcg_temp_free_i32(tmp2
);
4764 if (op
== 1 || op
== 3) {
4766 tmp2
= neon_load_reg(rd
, pass
);
4767 gen_neon_add(size
, tmp
, tmp2
);
4768 tcg_temp_free_i32(tmp2
);
4769 } else if (op
== 4 || (op
== 5 && u
)) {
4774 mask
= 0xff >> -shift
;
4776 mask
= (uint8_t)(0xff << shift
);
4782 mask
= 0xffff >> -shift
;
4784 mask
= (uint16_t)(0xffff << shift
);
4788 if (shift
< -31 || shift
> 31) {
4792 mask
= 0xffffffffu
>> -shift
;
4794 mask
= 0xffffffffu
<< shift
;
4800 tmp2
= neon_load_reg(rd
, pass
);
4801 tcg_gen_andi_i32(tmp
, tmp
, mask
);
4802 tcg_gen_andi_i32(tmp2
, tmp2
, ~mask
);
4803 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4804 tcg_temp_free_i32(tmp2
);
4806 neon_store_reg(rd
, pass
, tmp
);
4809 } else if (op
< 10) {
4810 /* Shift by immediate and narrow:
4811 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4812 int input_unsigned
= (op
== 8) ? !u
: u
;
4814 shift
= shift
- (1 << (size
+ 3));
4817 tmp64
= tcg_const_i64(shift
);
4818 neon_load_reg64(cpu_V0
, rm
);
4819 neon_load_reg64(cpu_V1
, rm
+ 1);
4820 for (pass
= 0; pass
< 2; pass
++) {
4828 if (input_unsigned
) {
4829 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
4831 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
4834 if (input_unsigned
) {
4835 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
4837 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
4840 tmp
= tcg_temp_new_i32();
4841 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
4842 neon_store_reg(rd
, pass
, tmp
);
4844 tcg_temp_free_i64(tmp64
);
4847 imm
= (uint16_t)shift
;
4851 imm
= (uint32_t)shift
;
4853 tmp2
= tcg_const_i32(imm
);
4854 tmp4
= neon_load_reg(rm
+ 1, 0);
4855 tmp5
= neon_load_reg(rm
+ 1, 1);
4856 for (pass
= 0; pass
< 2; pass
++) {
4858 tmp
= neon_load_reg(rm
, 0);
4862 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
4865 tmp3
= neon_load_reg(rm
, 1);
4869 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
4871 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
4872 tcg_temp_free_i32(tmp
);
4873 tcg_temp_free_i32(tmp3
);
4874 tmp
= tcg_temp_new_i32();
4875 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
4876 neon_store_reg(rd
, pass
, tmp
);
4878 tcg_temp_free_i32(tmp2
);
4880 } else if (op
== 10) {
4884 tmp
= neon_load_reg(rm
, 0);
4885 tmp2
= neon_load_reg(rm
, 1);
4886 for (pass
= 0; pass
< 2; pass
++) {
4890 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
4893 /* The shift is less than the width of the source
4894 type, so we can just shift the whole register. */
4895 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
4896 /* Widen the result of shift: we need to clear
4897 * the potential overflow bits resulting from
4898 * left bits of the narrow input appearing as
4899 * right bits of left the neighbour narrow
4901 if (size
< 2 || !u
) {
4904 imm
= (0xffu
>> (8 - shift
));
4906 } else if (size
== 1) {
4907 imm
= 0xffff >> (16 - shift
);
4910 imm
= 0xffffffff >> (32 - shift
);
4913 imm64
= imm
| (((uint64_t)imm
) << 32);
4917 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
4920 neon_store_reg64(cpu_V0
, rd
+ pass
);
4922 } else if (op
>= 14) {
4923 /* VCVT fixed-point. */
4924 /* We have already masked out the must-be-1 top bit of imm6,
4925 * hence this 32-shift where the ARM ARM has 64-imm6.
4928 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4929 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
4932 gen_vfp_ulto(0, shift
);
4934 gen_vfp_slto(0, shift
);
4937 gen_vfp_toul(0, shift
);
4939 gen_vfp_tosl(0, shift
);
4941 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
4946 } else { /* (insn & 0x00380080) == 0 */
4949 op
= (insn
>> 8) & 0xf;
4950 /* One register and immediate. */
4951 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
4952 invert
= (insn
& (1 << 5)) != 0;
4970 imm
= (imm
<< 8) | (imm
<< 24);
4973 imm
= (imm
<< 8) | 0xff;
4976 imm
= (imm
<< 16) | 0xffff;
4979 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
4984 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
4985 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
4991 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4992 if (op
& 1 && op
< 12) {
4993 tmp
= neon_load_reg(rd
, pass
);
4995 /* The immediate value has already been inverted, so
4997 tcg_gen_andi_i32(tmp
, tmp
, imm
);
4999 tcg_gen_ori_i32(tmp
, tmp
, imm
);
5003 tmp
= tcg_temp_new_i32();
5004 if (op
== 14 && invert
) {
5007 for (n
= 0; n
< 4; n
++) {
5008 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
5009 val
|= 0xff << (n
* 8);
5011 tcg_gen_movi_i32(tmp
, val
);
5013 tcg_gen_movi_i32(tmp
, imm
);
5016 neon_store_reg(rd
, pass
, tmp
);
5019 } else { /* (insn & 0x00800010 == 0x00800000) */
5021 op
= (insn
>> 8) & 0xf;
5022 if ((insn
& (1 << 6)) == 0) {
5023 /* Three registers of different lengths. */
5027 /* prewiden, src1_wide, src2_wide */
5028 static const int neon_3reg_wide
[16][3] = {
5029 {1, 0, 0}, /* VADDL */
5030 {1, 1, 0}, /* VADDW */
5031 {1, 0, 0}, /* VSUBL */
5032 {1, 1, 0}, /* VSUBW */
5033 {0, 1, 1}, /* VADDHN */
5034 {0, 0, 0}, /* VABAL */
5035 {0, 1, 1}, /* VSUBHN */
5036 {0, 0, 0}, /* VABDL */
5037 {0, 0, 0}, /* VMLAL */
5038 {0, 0, 0}, /* VQDMLAL */
5039 {0, 0, 0}, /* VMLSL */
5040 {0, 0, 0}, /* VQDMLSL */
5041 {0, 0, 0}, /* Integer VMULL */
5042 {0, 0, 0}, /* VQDMULL */
5043 {0, 0, 0} /* Polynomial VMULL */
5046 prewiden
= neon_3reg_wide
[op
][0];
5047 src1_wide
= neon_3reg_wide
[op
][1];
5048 src2_wide
= neon_3reg_wide
[op
][2];
5050 if (size
== 0 && (op
== 9 || op
== 11 || op
== 13))
5053 /* Avoid overlapping operands. Wide source operands are
5054 always aligned so will never overlap with wide
5055 destinations in problematic ways. */
5056 if (rd
== rm
&& !src2_wide
) {
5057 tmp
= neon_load_reg(rm
, 1);
5058 neon_store_scratch(2, tmp
);
5059 } else if (rd
== rn
&& !src1_wide
) {
5060 tmp
= neon_load_reg(rn
, 1);
5061 neon_store_scratch(2, tmp
);
5064 for (pass
= 0; pass
< 2; pass
++) {
5066 neon_load_reg64(cpu_V0
, rn
+ pass
);
5069 if (pass
== 1 && rd
== rn
) {
5070 tmp
= neon_load_scratch(2);
5072 tmp
= neon_load_reg(rn
, pass
);
5075 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5079 neon_load_reg64(cpu_V1
, rm
+ pass
);
5082 if (pass
== 1 && rd
== rm
) {
5083 tmp2
= neon_load_scratch(2);
5085 tmp2
= neon_load_reg(rm
, pass
);
5088 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
5092 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5093 gen_neon_addl(size
);
5095 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5096 gen_neon_subl(size
);
5098 case 5: case 7: /* VABAL, VABDL */
5099 switch ((size
<< 1) | u
) {
5101 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
5104 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
5107 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
5110 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
5113 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
5116 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
5120 tcg_temp_free_i32(tmp2
);
5121 tcg_temp_free_i32(tmp
);
5123 case 8: case 9: case 10: case 11: case 12: case 13:
5124 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5125 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5127 case 14: /* Polynomial VMULL */
5128 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
5129 tcg_temp_free_i32(tmp2
);
5130 tcg_temp_free_i32(tmp
);
5132 default: /* 15 is RESERVED. */
5137 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5138 neon_store_reg64(cpu_V0
, rd
+ pass
);
5139 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
5141 neon_load_reg64(cpu_V1
, rd
+ pass
);
5143 case 10: /* VMLSL */
5144 gen_neon_negl(cpu_V0
, size
);
5146 case 5: case 8: /* VABAL, VMLAL */
5147 gen_neon_addl(size
);
5149 case 9: case 11: /* VQDMLAL, VQDMLSL */
5150 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5152 gen_neon_negl(cpu_V0
, size
);
5154 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5159 neon_store_reg64(cpu_V0
, rd
+ pass
);
5160 } else if (op
== 4 || op
== 6) {
5161 /* Narrowing operation. */
5162 tmp
= tcg_temp_new_i32();
5166 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
5169 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
5172 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5173 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5180 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
5183 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
5186 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
5187 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5188 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5196 neon_store_reg(rd
, 0, tmp3
);
5197 neon_store_reg(rd
, 1, tmp
);
5200 /* Write back the result. */
5201 neon_store_reg64(cpu_V0
, rd
+ pass
);
5205 /* Two registers and a scalar. */
5207 case 0: /* Integer VMLA scalar */
5208 case 1: /* Float VMLA scalar */
5209 case 4: /* Integer VMLS scalar */
5210 case 5: /* Floating point VMLS scalar */
5211 case 8: /* Integer VMUL scalar */
5212 case 9: /* Floating point VMUL scalar */
5213 case 12: /* VQDMULH scalar */
5214 case 13: /* VQRDMULH scalar */
5215 tmp
= neon_get_scalar(size
, rm
);
5216 neon_store_scratch(0, tmp
);
5217 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5218 tmp
= neon_load_scratch(0);
5219 tmp2
= neon_load_reg(rn
, pass
);
5222 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5224 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5226 } else if (op
== 13) {
5228 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5230 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5232 } else if (op
& 1) {
5233 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
5236 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5237 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5238 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5242 tcg_temp_free_i32(tmp2
);
5245 tmp2
= neon_load_reg(rd
, pass
);
5248 gen_neon_add(size
, tmp
, tmp2
);
5251 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
5254 gen_neon_rsb(size
, tmp
, tmp2
);
5257 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
5262 tcg_temp_free_i32(tmp2
);
5264 neon_store_reg(rd
, pass
, tmp
);
5267 case 2: /* VMLAL sclar */
5268 case 3: /* VQDMLAL scalar */
5269 case 6: /* VMLSL scalar */
5270 case 7: /* VQDMLSL scalar */
5271 case 10: /* VMULL scalar */
5272 case 11: /* VQDMULL scalar */
5273 if (size
== 0 && (op
== 3 || op
== 7 || op
== 11))
5276 tmp2
= neon_get_scalar(size
, rm
);
5277 /* We need a copy of tmp2 because gen_neon_mull
5278 * deletes it during pass 0. */
5279 tmp4
= tcg_temp_new_i32();
5280 tcg_gen_mov_i32(tmp4
, tmp2
);
5281 tmp3
= neon_load_reg(rn
, 1);
5283 for (pass
= 0; pass
< 2; pass
++) {
5285 tmp
= neon_load_reg(rn
, 0);
5290 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5292 neon_load_reg64(cpu_V1
, rd
+ pass
);
5296 gen_neon_negl(cpu_V0
, size
);
5299 gen_neon_addl(size
);
5302 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5304 gen_neon_negl(cpu_V0
, size
);
5306 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5312 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5317 neon_store_reg64(cpu_V0
, rd
+ pass
);
5322 default: /* 14 and 15 are RESERVED */
5326 } else { /* size == 3 */
5329 imm
= (insn
>> 8) & 0xf;
5335 neon_load_reg64(cpu_V0
, rn
);
5337 neon_load_reg64(cpu_V1
, rn
+ 1);
5339 } else if (imm
== 8) {
5340 neon_load_reg64(cpu_V0
, rn
+ 1);
5342 neon_load_reg64(cpu_V1
, rm
);
5345 tmp64
= tcg_temp_new_i64();
5347 neon_load_reg64(cpu_V0
, rn
);
5348 neon_load_reg64(tmp64
, rn
+ 1);
5350 neon_load_reg64(cpu_V0
, rn
+ 1);
5351 neon_load_reg64(tmp64
, rm
);
5353 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
5354 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
5355 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5357 neon_load_reg64(cpu_V1
, rm
);
5359 neon_load_reg64(cpu_V1
, rm
+ 1);
5362 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5363 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
5364 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
5365 tcg_temp_free_i64(tmp64
);
5368 neon_load_reg64(cpu_V0
, rn
);
5369 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
5370 neon_load_reg64(cpu_V1
, rm
);
5371 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5372 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5374 neon_store_reg64(cpu_V0
, rd
);
5376 neon_store_reg64(cpu_V1
, rd
+ 1);
5378 } else if ((insn
& (1 << 11)) == 0) {
5379 /* Two register misc. */
5380 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
5381 size
= (insn
>> 18) & 3;
5383 case 0: /* VREV64 */
5386 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5387 tmp
= neon_load_reg(rm
, pass
* 2);
5388 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
5390 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5391 case 1: gen_swap_half(tmp
); break;
5392 case 2: /* no-op */ break;
5395 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
5397 neon_store_reg(rd
, pass
* 2, tmp2
);
5400 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
5401 case 1: gen_swap_half(tmp2
); break;
5404 neon_store_reg(rd
, pass
* 2, tmp2
);
5408 case 4: case 5: /* VPADDL */
5409 case 12: case 13: /* VPADAL */
5412 for (pass
= 0; pass
< q
+ 1; pass
++) {
5413 tmp
= neon_load_reg(rm
, pass
* 2);
5414 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
5415 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
5416 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
5418 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
5419 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
5420 case 2: tcg_gen_add_i64(CPU_V001
); break;
5425 neon_load_reg64(cpu_V1
, rd
+ pass
);
5426 gen_neon_addl(size
);
5428 neon_store_reg64(cpu_V0
, rd
+ pass
);
5433 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
5434 tmp
= neon_load_reg(rm
, n
);
5435 tmp2
= neon_load_reg(rd
, n
+ 1);
5436 neon_store_reg(rm
, n
, tmp2
);
5437 neon_store_reg(rd
, n
+ 1, tmp
);
5444 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
5449 if (gen_neon_zip(rd
, rm
, size
, q
)) {
5453 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5457 for (pass
= 0; pass
< 2; pass
++) {
5458 neon_load_reg64(cpu_V0
, rm
+ pass
);
5459 tmp
= tcg_temp_new_i32();
5460 gen_neon_narrow_op(op
== 36, q
, size
, tmp
, cpu_V0
);
5464 neon_store_reg(rd
, 0, tmp2
);
5465 neon_store_reg(rd
, 1, tmp
);
5469 case 38: /* VSHLL */
5472 tmp
= neon_load_reg(rm
, 0);
5473 tmp2
= neon_load_reg(rm
, 1);
5474 for (pass
= 0; pass
< 2; pass
++) {
5477 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
5478 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
5479 neon_store_reg64(cpu_V0
, rd
+ pass
);
5482 case 44: /* VCVT.F16.F32 */
5483 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
5485 tmp
= tcg_temp_new_i32();
5486 tmp2
= tcg_temp_new_i32();
5487 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
5488 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5489 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
5490 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5491 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5492 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5493 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
5494 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5495 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
5496 neon_store_reg(rd
, 0, tmp2
);
5497 tmp2
= tcg_temp_new_i32();
5498 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5499 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5500 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5501 neon_store_reg(rd
, 1, tmp2
);
5502 tcg_temp_free_i32(tmp
);
5504 case 46: /* VCVT.F32.F16 */
5505 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
5507 tmp3
= tcg_temp_new_i32();
5508 tmp
= neon_load_reg(rm
, 0);
5509 tmp2
= neon_load_reg(rm
, 1);
5510 tcg_gen_ext16u_i32(tmp3
, tmp
);
5511 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5512 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
5513 tcg_gen_shri_i32(tmp3
, tmp
, 16);
5514 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5515 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
5516 tcg_temp_free_i32(tmp
);
5517 tcg_gen_ext16u_i32(tmp3
, tmp2
);
5518 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5519 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
5520 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
5521 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5522 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
5523 tcg_temp_free_i32(tmp2
);
5524 tcg_temp_free_i32(tmp3
);
5528 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5529 if (op
== 30 || op
== 31 || op
>= 58) {
5530 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
5531 neon_reg_offset(rm
, pass
));
5534 tmp
= neon_load_reg(rm
, pass
);
5537 case 1: /* VREV32 */
5539 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5540 case 1: gen_swap_half(tmp
); break;
5544 case 2: /* VREV16 */
5551 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
5552 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
5553 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
5559 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
5560 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
5561 case 2: gen_helper_clz(tmp
, tmp
); break;
5568 gen_helper_neon_cnt_u8(tmp
, tmp
);
5573 tcg_gen_not_i32(tmp
, tmp
);
5575 case 14: /* VQABS */
5577 case 0: gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
); break;
5578 case 1: gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
); break;
5579 case 2: gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
); break;
5583 case 15: /* VQNEG */
5585 case 0: gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
); break;
5586 case 1: gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
); break;
5587 case 2: gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
); break;
5591 case 16: case 19: /* VCGT #0, VCLE #0 */
5592 tmp2
= tcg_const_i32(0);
5594 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
5595 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
5596 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
5599 tcg_temp_free(tmp2
);
5601 tcg_gen_not_i32(tmp
, tmp
);
5603 case 17: case 20: /* VCGE #0, VCLT #0 */
5604 tmp2
= tcg_const_i32(0);
5606 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
5607 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
5608 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
5611 tcg_temp_free(tmp2
);
5613 tcg_gen_not_i32(tmp
, tmp
);
5615 case 18: /* VCEQ #0 */
5616 tmp2
= tcg_const_i32(0);
5618 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5619 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5620 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5623 tcg_temp_free(tmp2
);
5627 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
5628 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
5629 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
5636 tmp2
= tcg_const_i32(0);
5637 gen_neon_rsb(size
, tmp
, tmp2
);
5638 tcg_temp_free(tmp2
);
5640 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5641 tmp2
= tcg_const_i32(0);
5642 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
5643 tcg_temp_free(tmp2
);
5645 tcg_gen_not_i32(tmp
, tmp
);
5647 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5648 tmp2
= tcg_const_i32(0);
5649 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
5650 tcg_temp_free(tmp2
);
5652 tcg_gen_not_i32(tmp
, tmp
);
5654 case 26: /* Float VCEQ #0 */
5655 tmp2
= tcg_const_i32(0);
5656 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
5657 tcg_temp_free(tmp2
);
5659 case 30: /* Float VABS */
5662 case 31: /* Float VNEG */
5666 tmp2
= neon_load_reg(rd
, pass
);
5667 neon_store_reg(rm
, pass
, tmp2
);
5670 tmp2
= neon_load_reg(rd
, pass
);
5672 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
5673 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
5677 neon_store_reg(rm
, pass
, tmp2
);
5679 case 56: /* Integer VRECPE */
5680 gen_helper_recpe_u32(tmp
, tmp
, cpu_env
);
5682 case 57: /* Integer VRSQRTE */
5683 gen_helper_rsqrte_u32(tmp
, tmp
, cpu_env
);
5685 case 58: /* Float VRECPE */
5686 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5688 case 59: /* Float VRSQRTE */
5689 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5691 case 60: /* VCVT.F32.S32 */
5694 case 61: /* VCVT.F32.U32 */
5697 case 62: /* VCVT.S32.F32 */
5700 case 63: /* VCVT.U32.F32 */
5704 /* Reserved: 21, 29, 39-56 */
5707 if (op
== 30 || op
== 31 || op
>= 58) {
5708 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
5709 neon_reg_offset(rd
, pass
));
5711 neon_store_reg(rd
, pass
, tmp
);
5716 } else if ((insn
& (1 << 10)) == 0) {
5718 n
= ((insn
>> 5) & 0x18) + 8;
5719 if (insn
& (1 << 6)) {
5720 tmp
= neon_load_reg(rd
, 0);
5722 tmp
= tcg_temp_new_i32();
5723 tcg_gen_movi_i32(tmp
, 0);
5725 tmp2
= neon_load_reg(rm
, 0);
5726 tmp4
= tcg_const_i32(rn
);
5727 tmp5
= tcg_const_i32(n
);
5728 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, tmp4
, tmp5
);
5729 tcg_temp_free_i32(tmp
);
5730 if (insn
& (1 << 6)) {
5731 tmp
= neon_load_reg(rd
, 1);
5733 tmp
= tcg_temp_new_i32();
5734 tcg_gen_movi_i32(tmp
, 0);
5736 tmp3
= neon_load_reg(rm
, 1);
5737 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, tmp4
, tmp5
);
5738 tcg_temp_free_i32(tmp5
);
5739 tcg_temp_free_i32(tmp4
);
5740 neon_store_reg(rd
, 0, tmp2
);
5741 neon_store_reg(rd
, 1, tmp3
);
5742 tcg_temp_free_i32(tmp
);
5743 } else if ((insn
& 0x380) == 0) {
5745 if (insn
& (1 << 19)) {
5746 tmp
= neon_load_reg(rm
, 1);
5748 tmp
= neon_load_reg(rm
, 0);
5750 if (insn
& (1 << 16)) {
5751 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
5752 } else if (insn
& (1 << 17)) {
5753 if ((insn
>> 18) & 1)
5754 gen_neon_dup_high16(tmp
);
5756 gen_neon_dup_low16(tmp
);
5758 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5759 tmp2
= tcg_temp_new_i32();
5760 tcg_gen_mov_i32(tmp2
, tmp
);
5761 neon_store_reg(rd
, pass
, tmp2
);
5763 tcg_temp_free_i32(tmp
);
5772 static int disas_cp14_read(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5774 int crn
= (insn
>> 16) & 0xf;
5775 int crm
= insn
& 0xf;
5776 int op1
= (insn
>> 21) & 7;
5777 int op2
= (insn
>> 5) & 7;
5778 int rt
= (insn
>> 12) & 0xf;
5781 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5782 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5786 tmp
= load_cpu_field(teecr
);
5787 store_reg(s
, rt
, tmp
);
5790 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5792 if (IS_USER(s
) && (env
->teecr
& 1))
5794 tmp
= load_cpu_field(teehbr
);
5795 store_reg(s
, rt
, tmp
);
5799 fprintf(stderr
, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5800 op1
, crn
, crm
, op2
);
5804 static int disas_cp14_write(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5806 int crn
= (insn
>> 16) & 0xf;
5807 int crm
= insn
& 0xf;
5808 int op1
= (insn
>> 21) & 7;
5809 int op2
= (insn
>> 5) & 7;
5810 int rt
= (insn
>> 12) & 0xf;
5813 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5814 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5818 tmp
= load_reg(s
, rt
);
5819 gen_helper_set_teecr(cpu_env
, tmp
);
5820 tcg_temp_free_i32(tmp
);
5823 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5825 if (IS_USER(s
) && (env
->teecr
& 1))
5827 tmp
= load_reg(s
, rt
);
5828 store_cpu_field(tmp
, teehbr
);
5832 fprintf(stderr
, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5833 op1
, crn
, crm
, op2
);
5837 static int disas_coproc_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5841 cpnum
= (insn
>> 8) & 0xf;
5842 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
5843 && ((env
->cp15
.c15_cpar
^ 0x3fff) & (1 << cpnum
)))
5849 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
5850 return disas_iwmmxt_insn(env
, s
, insn
);
5851 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5852 return disas_dsp_insn(env
, s
, insn
);
5857 return disas_vfp_insn (env
, s
, insn
);
5859 /* Coprocessors 7-15 are architecturally reserved by ARM.
5860 Unfortunately Intel decided to ignore this. */
5861 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
5863 if (insn
& (1 << 20))
5864 return disas_cp14_read(env
, s
, insn
);
5866 return disas_cp14_write(env
, s
, insn
);
5868 return disas_cp15_insn (env
, s
, insn
);
5871 /* Unknown coprocessor. See if the board has hooked it. */
5872 return disas_cp_insn (env
, s
, insn
);
5877 /* Store a 64-bit value to a register pair. Clobbers val. */
5878 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
5881 tmp
= tcg_temp_new_i32();
5882 tcg_gen_trunc_i64_i32(tmp
, val
);
5883 store_reg(s
, rlow
, tmp
);
5884 tmp
= tcg_temp_new_i32();
5885 tcg_gen_shri_i64(val
, val
, 32);
5886 tcg_gen_trunc_i64_i32(tmp
, val
);
5887 store_reg(s
, rhigh
, tmp
);
5890 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5891 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
5896 /* Load value and extend to 64 bits. */
5897 tmp
= tcg_temp_new_i64();
5898 tmp2
= load_reg(s
, rlow
);
5899 tcg_gen_extu_i32_i64(tmp
, tmp2
);
5900 tcg_temp_free_i32(tmp2
);
5901 tcg_gen_add_i64(val
, val
, tmp
);
5902 tcg_temp_free_i64(tmp
);
5905 /* load and add a 64-bit value from a register pair. */
5906 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
5912 /* Load 64-bit value rd:rn. */
5913 tmpl
= load_reg(s
, rlow
);
5914 tmph
= load_reg(s
, rhigh
);
5915 tmp
= tcg_temp_new_i64();
5916 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
5917 tcg_temp_free_i32(tmpl
);
5918 tcg_temp_free_i32(tmph
);
5919 tcg_gen_add_i64(val
, val
, tmp
);
5920 tcg_temp_free_i64(tmp
);
5923 /* Set N and Z flags from a 64-bit value. */
5924 static void gen_logicq_cc(TCGv_i64 val
)
5926 TCGv tmp
= tcg_temp_new_i32();
5927 gen_helper_logicq_cc(tmp
, val
);
5929 tcg_temp_free_i32(tmp
);
5932 /* Load/Store exclusive instructions are implemented by remembering
5933 the value/address loaded, and seeing if these are the same
5934 when the store is performed. This should be is sufficient to implement
5935 the architecturally mandated semantics, and avoids having to monitor
5938 In system emulation mode only one CPU will be running at once, so
5939 this sequence is effectively atomic. In user emulation mode we
5940 throw an exception and handle the atomic operation elsewhere. */
5941 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
5942 TCGv addr
, int size
)
5948 tmp
= gen_ld8u(addr
, IS_USER(s
));
5951 tmp
= gen_ld16u(addr
, IS_USER(s
));
5955 tmp
= gen_ld32(addr
, IS_USER(s
));
5960 tcg_gen_mov_i32(cpu_exclusive_val
, tmp
);
5961 store_reg(s
, rt
, tmp
);
5963 TCGv tmp2
= tcg_temp_new_i32();
5964 tcg_gen_addi_i32(tmp2
, addr
, 4);
5965 tmp
= gen_ld32(tmp2
, IS_USER(s
));
5966 tcg_temp_free_i32(tmp2
);
5967 tcg_gen_mov_i32(cpu_exclusive_high
, tmp
);
5968 store_reg(s
, rt2
, tmp
);
5970 tcg_gen_mov_i32(cpu_exclusive_addr
, addr
);
5973 static void gen_clrex(DisasContext
*s
)
5975 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
5978 #ifdef CONFIG_USER_ONLY
5979 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
5980 TCGv addr
, int size
)
5982 tcg_gen_mov_i32(cpu_exclusive_test
, addr
);
5983 tcg_gen_movi_i32(cpu_exclusive_info
,
5984 size
| (rd
<< 4) | (rt
<< 8) | (rt2
<< 12));
5985 gen_exception_insn(s
, 4, EXCP_STREX
);
5988 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
5989 TCGv addr
, int size
)
5995 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6001 fail_label
= gen_new_label();
6002 done_label
= gen_new_label();
6003 tcg_gen_brcond_i32(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
6006 tmp
= gen_ld8u(addr
, IS_USER(s
));
6009 tmp
= gen_ld16u(addr
, IS_USER(s
));
6013 tmp
= gen_ld32(addr
, IS_USER(s
));
6018 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
6019 tcg_temp_free_i32(tmp
);
6021 TCGv tmp2
= tcg_temp_new_i32();
6022 tcg_gen_addi_i32(tmp2
, addr
, 4);
6023 tmp
= gen_ld32(tmp2
, IS_USER(s
));
6024 tcg_temp_free_i32(tmp2
);
6025 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_high
, fail_label
);
6026 tcg_temp_free_i32(tmp
);
6028 tmp
= load_reg(s
, rt
);
6031 gen_st8(tmp
, addr
, IS_USER(s
));
6034 gen_st16(tmp
, addr
, IS_USER(s
));
6038 gen_st32(tmp
, addr
, IS_USER(s
));
6044 tcg_gen_addi_i32(addr
, addr
, 4);
6045 tmp
= load_reg(s
, rt2
);
6046 gen_st32(tmp
, addr
, IS_USER(s
));
6048 tcg_gen_movi_i32(cpu_R
[rd
], 0);
6049 tcg_gen_br(done_label
);
6050 gen_set_label(fail_label
);
6051 tcg_gen_movi_i32(cpu_R
[rd
], 1);
6052 gen_set_label(done_label
);
6053 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
6057 static void disas_arm_insn(CPUState
* env
, DisasContext
*s
)
6059 unsigned int cond
, insn
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
6066 insn
= ldl_code(s
->pc
);
6069 /* M variants do not implement ARM mode. */
6074 /* Unconditional instructions. */
6075 if (((insn
>> 25) & 7) == 1) {
6076 /* NEON Data processing. */
6077 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6080 if (disas_neon_data_insn(env
, s
, insn
))
6084 if ((insn
& 0x0f100000) == 0x04000000) {
6085 /* NEON load/store. */
6086 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6089 if (disas_neon_ls_insn(env
, s
, insn
))
6093 if (((insn
& 0x0f30f000) == 0x0510f000) ||
6094 ((insn
& 0x0f30f010) == 0x0710f000)) {
6095 if ((insn
& (1 << 22)) == 0) {
6097 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6101 /* Otherwise PLD; v5TE+ */
6104 if (((insn
& 0x0f70f000) == 0x0450f000) ||
6105 ((insn
& 0x0f70f010) == 0x0650f000)) {
6107 return; /* PLI; V7 */
6109 if (((insn
& 0x0f700000) == 0x04100000) ||
6110 ((insn
& 0x0f700010) == 0x06100000)) {
6111 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6114 return; /* v7MP: Unallocated memory hint: must NOP */
6117 if ((insn
& 0x0ffffdff) == 0x01010000) {
6120 if (insn
& (1 << 9)) {
6121 /* BE8 mode not implemented. */
6125 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
6126 switch ((insn
>> 4) & 0xf) {
6135 /* We don't emulate caches so these are a no-op. */
6140 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
6146 op1
= (insn
& 0x1f);
6147 addr
= tcg_temp_new_i32();
6148 tmp
= tcg_const_i32(op1
);
6149 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
6150 tcg_temp_free_i32(tmp
);
6151 i
= (insn
>> 23) & 3;
6153 case 0: offset
= -4; break; /* DA */
6154 case 1: offset
= 0; break; /* IA */
6155 case 2: offset
= -8; break; /* DB */
6156 case 3: offset
= 4; break; /* IB */
6160 tcg_gen_addi_i32(addr
, addr
, offset
);
6161 tmp
= load_reg(s
, 14);
6162 gen_st32(tmp
, addr
, 0);
6163 tmp
= load_cpu_field(spsr
);
6164 tcg_gen_addi_i32(addr
, addr
, 4);
6165 gen_st32(tmp
, addr
, 0);
6166 if (insn
& (1 << 21)) {
6167 /* Base writeback. */
6169 case 0: offset
= -8; break;
6170 case 1: offset
= 4; break;
6171 case 2: offset
= -4; break;
6172 case 3: offset
= 0; break;
6176 tcg_gen_addi_i32(addr
, addr
, offset
);
6177 tmp
= tcg_const_i32(op1
);
6178 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
6179 tcg_temp_free_i32(tmp
);
6180 tcg_temp_free_i32(addr
);
6182 tcg_temp_free_i32(addr
);
6185 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
6191 rn
= (insn
>> 16) & 0xf;
6192 addr
= load_reg(s
, rn
);
6193 i
= (insn
>> 23) & 3;
6195 case 0: offset
= -4; break; /* DA */
6196 case 1: offset
= 0; break; /* IA */
6197 case 2: offset
= -8; break; /* DB */
6198 case 3: offset
= 4; break; /* IB */
6202 tcg_gen_addi_i32(addr
, addr
, offset
);
6203 /* Load PC into tmp and CPSR into tmp2. */
6204 tmp
= gen_ld32(addr
, 0);
6205 tcg_gen_addi_i32(addr
, addr
, 4);
6206 tmp2
= gen_ld32(addr
, 0);
6207 if (insn
& (1 << 21)) {
6208 /* Base writeback. */
6210 case 0: offset
= -8; break;
6211 case 1: offset
= 4; break;
6212 case 2: offset
= -4; break;
6213 case 3: offset
= 0; break;
6217 tcg_gen_addi_i32(addr
, addr
, offset
);
6218 store_reg(s
, rn
, addr
);
6220 tcg_temp_free_i32(addr
);
6222 gen_rfe(s
, tmp
, tmp2
);
6224 } else if ((insn
& 0x0e000000) == 0x0a000000) {
6225 /* branch link and change to thumb (blx <offset>) */
6228 val
= (uint32_t)s
->pc
;
6229 tmp
= tcg_temp_new_i32();
6230 tcg_gen_movi_i32(tmp
, val
);
6231 store_reg(s
, 14, tmp
);
6232 /* Sign-extend the 24-bit offset */
6233 offset
= (((int32_t)insn
) << 8) >> 8;
6234 /* offset * 4 + bit24 * 2 + (thumb bit) */
6235 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
6236 /* pipeline offset */
6240 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
6241 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
6242 /* iWMMXt register transfer. */
6243 if (env
->cp15
.c15_cpar
& (1 << 1))
6244 if (!disas_iwmmxt_insn(env
, s
, insn
))
6247 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
6248 /* Coprocessor double register transfer. */
6249 } else if ((insn
& 0x0f000010) == 0x0e000010) {
6250 /* Additional coprocessor register transfer. */
6251 } else if ((insn
& 0x0ff10020) == 0x01000000) {
6254 /* cps (privileged) */
6258 if (insn
& (1 << 19)) {
6259 if (insn
& (1 << 8))
6261 if (insn
& (1 << 7))
6263 if (insn
& (1 << 6))
6265 if (insn
& (1 << 18))
6268 if (insn
& (1 << 17)) {
6270 val
|= (insn
& 0x1f);
6273 gen_set_psr_im(s
, mask
, 0, val
);
6280 /* if not always execute, we generate a conditional jump to
6282 s
->condlabel
= gen_new_label();
6283 gen_test_cc(cond
^ 1, s
->condlabel
);
6286 if ((insn
& 0x0f900000) == 0x03000000) {
6287 if ((insn
& (1 << 21)) == 0) {
6289 rd
= (insn
>> 12) & 0xf;
6290 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
6291 if ((insn
& (1 << 22)) == 0) {
6293 tmp
= tcg_temp_new_i32();
6294 tcg_gen_movi_i32(tmp
, val
);
6297 tmp
= load_reg(s
, rd
);
6298 tcg_gen_ext16u_i32(tmp
, tmp
);
6299 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
6301 store_reg(s
, rd
, tmp
);
6303 if (((insn
>> 12) & 0xf) != 0xf)
6305 if (((insn
>> 16) & 0xf) == 0) {
6306 gen_nop_hint(s
, insn
& 0xff);
6308 /* CPSR = immediate */
6310 shift
= ((insn
>> 8) & 0xf) * 2;
6312 val
= (val
>> shift
) | (val
<< (32 - shift
));
6313 i
= ((insn
& (1 << 22)) != 0);
6314 if (gen_set_psr_im(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, val
))
6318 } else if ((insn
& 0x0f900000) == 0x01000000
6319 && (insn
& 0x00000090) != 0x00000090) {
6320 /* miscellaneous instructions */
6321 op1
= (insn
>> 21) & 3;
6322 sh
= (insn
>> 4) & 0xf;
6325 case 0x0: /* move program status register */
6328 tmp
= load_reg(s
, rm
);
6329 i
= ((op1
& 2) != 0);
6330 if (gen_set_psr(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
6334 rd
= (insn
>> 12) & 0xf;
6338 tmp
= load_cpu_field(spsr
);
6340 tmp
= tcg_temp_new_i32();
6341 gen_helper_cpsr_read(tmp
);
6343 store_reg(s
, rd
, tmp
);
6348 /* branch/exchange thumb (bx). */
6349 tmp
= load_reg(s
, rm
);
6351 } else if (op1
== 3) {
6353 rd
= (insn
>> 12) & 0xf;
6354 tmp
= load_reg(s
, rm
);
6355 gen_helper_clz(tmp
, tmp
);
6356 store_reg(s
, rd
, tmp
);
6364 /* Trivial implementation equivalent to bx. */
6365 tmp
= load_reg(s
, rm
);
6375 /* branch link/exchange thumb (blx) */
6376 tmp
= load_reg(s
, rm
);
6377 tmp2
= tcg_temp_new_i32();
6378 tcg_gen_movi_i32(tmp2
, s
->pc
);
6379 store_reg(s
, 14, tmp2
);
6382 case 0x5: /* saturating add/subtract */
6383 rd
= (insn
>> 12) & 0xf;
6384 rn
= (insn
>> 16) & 0xf;
6385 tmp
= load_reg(s
, rm
);
6386 tmp2
= load_reg(s
, rn
);
6388 gen_helper_double_saturate(tmp2
, tmp2
);
6390 gen_helper_sub_saturate(tmp
, tmp
, tmp2
);
6392 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
6393 tcg_temp_free_i32(tmp2
);
6394 store_reg(s
, rd
, tmp
);
6397 /* SMC instruction (op1 == 3)
6398 and undefined instructions (op1 == 0 || op1 == 2)
6404 gen_exception_insn(s
, 4, EXCP_BKPT
);
6406 case 0x8: /* signed multiply */
6410 rs
= (insn
>> 8) & 0xf;
6411 rn
= (insn
>> 12) & 0xf;
6412 rd
= (insn
>> 16) & 0xf;
6414 /* (32 * 16) >> 16 */
6415 tmp
= load_reg(s
, rm
);
6416 tmp2
= load_reg(s
, rs
);
6418 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
6421 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6422 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
6423 tmp
= tcg_temp_new_i32();
6424 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6425 tcg_temp_free_i64(tmp64
);
6426 if ((sh
& 2) == 0) {
6427 tmp2
= load_reg(s
, rn
);
6428 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6429 tcg_temp_free_i32(tmp2
);
6431 store_reg(s
, rd
, tmp
);
6434 tmp
= load_reg(s
, rm
);
6435 tmp2
= load_reg(s
, rs
);
6436 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
6437 tcg_temp_free_i32(tmp2
);
6439 tmp64
= tcg_temp_new_i64();
6440 tcg_gen_ext_i32_i64(tmp64
, tmp
);
6441 tcg_temp_free_i32(tmp
);
6442 gen_addq(s
, tmp64
, rn
, rd
);
6443 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6444 tcg_temp_free_i64(tmp64
);
6447 tmp2
= load_reg(s
, rn
);
6448 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6449 tcg_temp_free_i32(tmp2
);
6451 store_reg(s
, rd
, tmp
);
6458 } else if (((insn
& 0x0e000000) == 0 &&
6459 (insn
& 0x00000090) != 0x90) ||
6460 ((insn
& 0x0e000000) == (1 << 25))) {
6461 int set_cc
, logic_cc
, shiftop
;
6463 op1
= (insn
>> 21) & 0xf;
6464 set_cc
= (insn
>> 20) & 1;
6465 logic_cc
= table_logic_cc
[op1
] & set_cc
;
6467 /* data processing instruction */
6468 if (insn
& (1 << 25)) {
6469 /* immediate operand */
6471 shift
= ((insn
>> 8) & 0xf) * 2;
6473 val
= (val
>> shift
) | (val
<< (32 - shift
));
6475 tmp2
= tcg_temp_new_i32();
6476 tcg_gen_movi_i32(tmp2
, val
);
6477 if (logic_cc
&& shift
) {
6478 gen_set_CF_bit31(tmp2
);
6483 tmp2
= load_reg(s
, rm
);
6484 shiftop
= (insn
>> 5) & 3;
6485 if (!(insn
& (1 << 4))) {
6486 shift
= (insn
>> 7) & 0x1f;
6487 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
6489 rs
= (insn
>> 8) & 0xf;
6490 tmp
= load_reg(s
, rs
);
6491 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
6494 if (op1
!= 0x0f && op1
!= 0x0d) {
6495 rn
= (insn
>> 16) & 0xf;
6496 tmp
= load_reg(s
, rn
);
6500 rd
= (insn
>> 12) & 0xf;
6503 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6507 store_reg_bx(env
, s
, rd
, tmp
);
6510 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6514 store_reg_bx(env
, s
, rd
, tmp
);
6517 if (set_cc
&& rd
== 15) {
6518 /* SUBS r15, ... is used for exception return. */
6522 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6523 gen_exception_return(s
, tmp
);
6526 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6528 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6530 store_reg_bx(env
, s
, rd
, tmp
);
6535 gen_helper_sub_cc(tmp
, tmp2
, tmp
);
6537 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6539 store_reg_bx(env
, s
, rd
, tmp
);
6543 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6545 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6547 store_reg_bx(env
, s
, rd
, tmp
);
6551 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
6553 gen_add_carry(tmp
, tmp
, tmp2
);
6555 store_reg_bx(env
, s
, rd
, tmp
);
6559 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
6561 gen_sub_carry(tmp
, tmp
, tmp2
);
6563 store_reg_bx(env
, s
, rd
, tmp
);
6567 gen_helper_sbc_cc(tmp
, tmp2
, tmp
);
6569 gen_sub_carry(tmp
, tmp2
, tmp
);
6571 store_reg_bx(env
, s
, rd
, tmp
);
6575 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6578 tcg_temp_free_i32(tmp
);
6582 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6585 tcg_temp_free_i32(tmp
);
6589 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6591 tcg_temp_free_i32(tmp
);
6595 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6597 tcg_temp_free_i32(tmp
);
6600 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6604 store_reg_bx(env
, s
, rd
, tmp
);
6607 if (logic_cc
&& rd
== 15) {
6608 /* MOVS r15, ... is used for exception return. */
6612 gen_exception_return(s
, tmp2
);
6617 store_reg_bx(env
, s
, rd
, tmp2
);
6621 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
6625 store_reg_bx(env
, s
, rd
, tmp
);
6629 tcg_gen_not_i32(tmp2
, tmp2
);
6633 store_reg_bx(env
, s
, rd
, tmp2
);
6636 if (op1
!= 0x0f && op1
!= 0x0d) {
6637 tcg_temp_free_i32(tmp2
);
6640 /* other instructions */
6641 op1
= (insn
>> 24) & 0xf;
6645 /* multiplies, extra load/stores */
6646 sh
= (insn
>> 5) & 3;
6649 rd
= (insn
>> 16) & 0xf;
6650 rn
= (insn
>> 12) & 0xf;
6651 rs
= (insn
>> 8) & 0xf;
6653 op1
= (insn
>> 20) & 0xf;
6655 case 0: case 1: case 2: case 3: case 6:
6657 tmp
= load_reg(s
, rs
);
6658 tmp2
= load_reg(s
, rm
);
6659 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
6660 tcg_temp_free_i32(tmp2
);
6661 if (insn
& (1 << 22)) {
6662 /* Subtract (mls) */
6664 tmp2
= load_reg(s
, rn
);
6665 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6666 tcg_temp_free_i32(tmp2
);
6667 } else if (insn
& (1 << 21)) {
6669 tmp2
= load_reg(s
, rn
);
6670 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6671 tcg_temp_free_i32(tmp2
);
6673 if (insn
& (1 << 20))
6675 store_reg(s
, rd
, tmp
);
6678 /* 64 bit mul double accumulate (UMAAL) */
6680 tmp
= load_reg(s
, rs
);
6681 tmp2
= load_reg(s
, rm
);
6682 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
6683 gen_addq_lo(s
, tmp64
, rn
);
6684 gen_addq_lo(s
, tmp64
, rd
);
6685 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6686 tcg_temp_free_i64(tmp64
);
6688 case 8: case 9: case 10: case 11:
6689 case 12: case 13: case 14: case 15:
6690 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6691 tmp
= load_reg(s
, rs
);
6692 tmp2
= load_reg(s
, rm
);
6693 if (insn
& (1 << 22)) {
6694 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6696 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
6698 if (insn
& (1 << 21)) { /* mult accumulate */
6699 gen_addq(s
, tmp64
, rn
, rd
);
6701 if (insn
& (1 << 20)) {
6702 gen_logicq_cc(tmp64
);
6704 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6705 tcg_temp_free_i64(tmp64
);
6711 rn
= (insn
>> 16) & 0xf;
6712 rd
= (insn
>> 12) & 0xf;
6713 if (insn
& (1 << 23)) {
6714 /* load/store exclusive */
6715 op1
= (insn
>> 21) & 0x3;
6720 addr
= tcg_temp_local_new_i32();
6721 load_reg_var(s
, addr
, rn
);
6722 if (insn
& (1 << 20)) {
6725 gen_load_exclusive(s
, rd
, 15, addr
, 2);
6727 case 1: /* ldrexd */
6728 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
6730 case 2: /* ldrexb */
6731 gen_load_exclusive(s
, rd
, 15, addr
, 0);
6733 case 3: /* ldrexh */
6734 gen_load_exclusive(s
, rd
, 15, addr
, 1);
6743 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
6745 case 1: /* strexd */
6746 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
6748 case 2: /* strexb */
6749 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
6751 case 3: /* strexh */
6752 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
6758 tcg_temp_free(addr
);
6760 /* SWP instruction */
6763 /* ??? This is not really atomic. However we know
6764 we never have multiple CPUs running in parallel,
6765 so it is good enough. */
6766 addr
= load_reg(s
, rn
);
6767 tmp
= load_reg(s
, rm
);
6768 if (insn
& (1 << 22)) {
6769 tmp2
= gen_ld8u(addr
, IS_USER(s
));
6770 gen_st8(tmp
, addr
, IS_USER(s
));
6772 tmp2
= gen_ld32(addr
, IS_USER(s
));
6773 gen_st32(tmp
, addr
, IS_USER(s
));
6775 tcg_temp_free_i32(addr
);
6776 store_reg(s
, rd
, tmp2
);
6782 /* Misc load/store */
6783 rn
= (insn
>> 16) & 0xf;
6784 rd
= (insn
>> 12) & 0xf;
6785 addr
= load_reg(s
, rn
);
6786 if (insn
& (1 << 24))
6787 gen_add_datah_offset(s
, insn
, 0, addr
);
6789 if (insn
& (1 << 20)) {
6793 tmp
= gen_ld16u(addr
, IS_USER(s
));
6796 tmp
= gen_ld8s(addr
, IS_USER(s
));
6800 tmp
= gen_ld16s(addr
, IS_USER(s
));
6804 } else if (sh
& 2) {
6808 tmp
= load_reg(s
, rd
);
6809 gen_st32(tmp
, addr
, IS_USER(s
));
6810 tcg_gen_addi_i32(addr
, addr
, 4);
6811 tmp
= load_reg(s
, rd
+ 1);
6812 gen_st32(tmp
, addr
, IS_USER(s
));
6816 tmp
= gen_ld32(addr
, IS_USER(s
));
6817 store_reg(s
, rd
, tmp
);
6818 tcg_gen_addi_i32(addr
, addr
, 4);
6819 tmp
= gen_ld32(addr
, IS_USER(s
));
6823 address_offset
= -4;
6826 tmp
= load_reg(s
, rd
);
6827 gen_st16(tmp
, addr
, IS_USER(s
));
6830 /* Perform base writeback before the loaded value to
6831 ensure correct behavior with overlapping index registers.
6832 ldrd with base writeback is is undefined if the
6833 destination and index registers overlap. */
6834 if (!(insn
& (1 << 24))) {
6835 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
6836 store_reg(s
, rn
, addr
);
6837 } else if (insn
& (1 << 21)) {
6839 tcg_gen_addi_i32(addr
, addr
, address_offset
);
6840 store_reg(s
, rn
, addr
);
6842 tcg_temp_free_i32(addr
);
6845 /* Complete the load. */
6846 store_reg(s
, rd
, tmp
);
6855 if (insn
& (1 << 4)) {
6857 /* Armv6 Media instructions. */
6859 rn
= (insn
>> 16) & 0xf;
6860 rd
= (insn
>> 12) & 0xf;
6861 rs
= (insn
>> 8) & 0xf;
6862 switch ((insn
>> 23) & 3) {
6863 case 0: /* Parallel add/subtract. */
6864 op1
= (insn
>> 20) & 7;
6865 tmp
= load_reg(s
, rn
);
6866 tmp2
= load_reg(s
, rm
);
6867 sh
= (insn
>> 5) & 7;
6868 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
6870 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
6871 tcg_temp_free_i32(tmp2
);
6872 store_reg(s
, rd
, tmp
);
6875 if ((insn
& 0x00700020) == 0) {
6876 /* Halfword pack. */
6877 tmp
= load_reg(s
, rn
);
6878 tmp2
= load_reg(s
, rm
);
6879 shift
= (insn
>> 7) & 0x1f;
6880 if (insn
& (1 << 6)) {
6884 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
6885 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
6886 tcg_gen_ext16u_i32(tmp2
, tmp2
);
6890 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
6891 tcg_gen_ext16u_i32(tmp
, tmp
);
6892 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
6894 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6895 tcg_temp_free_i32(tmp2
);
6896 store_reg(s
, rd
, tmp
);
6897 } else if ((insn
& 0x00200020) == 0x00200000) {
6899 tmp
= load_reg(s
, rm
);
6900 shift
= (insn
>> 7) & 0x1f;
6901 if (insn
& (1 << 6)) {
6904 tcg_gen_sari_i32(tmp
, tmp
, shift
);
6906 tcg_gen_shli_i32(tmp
, tmp
, shift
);
6908 sh
= (insn
>> 16) & 0x1f;
6909 tmp2
= tcg_const_i32(sh
);
6910 if (insn
& (1 << 22))
6911 gen_helper_usat(tmp
, tmp
, tmp2
);
6913 gen_helper_ssat(tmp
, tmp
, tmp2
);
6914 tcg_temp_free_i32(tmp2
);
6915 store_reg(s
, rd
, tmp
);
6916 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
6918 tmp
= load_reg(s
, rm
);
6919 sh
= (insn
>> 16) & 0x1f;
6920 tmp2
= tcg_const_i32(sh
);
6921 if (insn
& (1 << 22))
6922 gen_helper_usat16(tmp
, tmp
, tmp2
);
6924 gen_helper_ssat16(tmp
, tmp
, tmp2
);
6925 tcg_temp_free_i32(tmp2
);
6926 store_reg(s
, rd
, tmp
);
6927 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
6929 tmp
= load_reg(s
, rn
);
6930 tmp2
= load_reg(s
, rm
);
6931 tmp3
= tcg_temp_new_i32();
6932 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
6933 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
6934 tcg_temp_free_i32(tmp3
);
6935 tcg_temp_free_i32(tmp2
);
6936 store_reg(s
, rd
, tmp
);
6937 } else if ((insn
& 0x000003e0) == 0x00000060) {
6938 tmp
= load_reg(s
, rm
);
6939 shift
= (insn
>> 10) & 3;
6940 /* ??? In many cases it's not neccessary to do a
6941 rotate, a shift is sufficient. */
6943 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
6944 op1
= (insn
>> 20) & 7;
6946 case 0: gen_sxtb16(tmp
); break;
6947 case 2: gen_sxtb(tmp
); break;
6948 case 3: gen_sxth(tmp
); break;
6949 case 4: gen_uxtb16(tmp
); break;
6950 case 6: gen_uxtb(tmp
); break;
6951 case 7: gen_uxth(tmp
); break;
6952 default: goto illegal_op
;
6955 tmp2
= load_reg(s
, rn
);
6956 if ((op1
& 3) == 0) {
6957 gen_add16(tmp
, tmp2
);
6959 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6960 tcg_temp_free_i32(tmp2
);
6963 store_reg(s
, rd
, tmp
);
6964 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
6966 tmp
= load_reg(s
, rm
);
6967 if (insn
& (1 << 22)) {
6968 if (insn
& (1 << 7)) {
6972 gen_helper_rbit(tmp
, tmp
);
6975 if (insn
& (1 << 7))
6978 tcg_gen_bswap32_i32(tmp
, tmp
);
6980 store_reg(s
, rd
, tmp
);
6985 case 2: /* Multiplies (Type 3). */
6986 tmp
= load_reg(s
, rm
);
6987 tmp2
= load_reg(s
, rs
);
6988 if (insn
& (1 << 20)) {
6989 /* Signed multiply most significant [accumulate].
6990 (SMMUL, SMMLA, SMMLS) */
6991 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6994 tmp
= load_reg(s
, rd
);
6995 if (insn
& (1 << 6)) {
6996 tmp64
= gen_subq_msw(tmp64
, tmp
);
6998 tmp64
= gen_addq_msw(tmp64
, tmp
);
7001 if (insn
& (1 << 5)) {
7002 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
7004 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7005 tmp
= tcg_temp_new_i32();
7006 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7007 tcg_temp_free_i64(tmp64
);
7008 store_reg(s
, rn
, tmp
);
7010 if (insn
& (1 << 5))
7011 gen_swap_half(tmp2
);
7012 gen_smul_dual(tmp
, tmp2
);
7013 /* This addition cannot overflow. */
7014 if (insn
& (1 << 6)) {
7015 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7017 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7019 tcg_temp_free_i32(tmp2
);
7020 if (insn
& (1 << 22)) {
7021 /* smlald, smlsld */
7022 tmp64
= tcg_temp_new_i64();
7023 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7024 tcg_temp_free_i32(tmp
);
7025 gen_addq(s
, tmp64
, rd
, rn
);
7026 gen_storeq_reg(s
, rd
, rn
, tmp64
);
7027 tcg_temp_free_i64(tmp64
);
7029 /* smuad, smusd, smlad, smlsd */
7032 tmp2
= load_reg(s
, rd
);
7033 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7034 tcg_temp_free_i32(tmp2
);
7036 store_reg(s
, rn
, tmp
);
7041 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
7043 case 0: /* Unsigned sum of absolute differences. */
7045 tmp
= load_reg(s
, rm
);
7046 tmp2
= load_reg(s
, rs
);
7047 gen_helper_usad8(tmp
, tmp
, tmp2
);
7048 tcg_temp_free_i32(tmp2
);
7050 tmp2
= load_reg(s
, rd
);
7051 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7052 tcg_temp_free_i32(tmp2
);
7054 store_reg(s
, rn
, tmp
);
7056 case 0x20: case 0x24: case 0x28: case 0x2c:
7057 /* Bitfield insert/clear. */
7059 shift
= (insn
>> 7) & 0x1f;
7060 i
= (insn
>> 16) & 0x1f;
7063 tmp
= tcg_temp_new_i32();
7064 tcg_gen_movi_i32(tmp
, 0);
7066 tmp
= load_reg(s
, rm
);
7069 tmp2
= load_reg(s
, rd
);
7070 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << i
) - 1);
7071 tcg_temp_free_i32(tmp2
);
7073 store_reg(s
, rd
, tmp
);
7075 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7076 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7078 tmp
= load_reg(s
, rm
);
7079 shift
= (insn
>> 7) & 0x1f;
7080 i
= ((insn
>> 16) & 0x1f) + 1;
7085 gen_ubfx(tmp
, shift
, (1u << i
) - 1);
7087 gen_sbfx(tmp
, shift
, i
);
7090 store_reg(s
, rd
, tmp
);
7100 /* Check for undefined extension instructions
7101 * per the ARM Bible IE:
7102 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7104 sh
= (0xf << 20) | (0xf << 4);
7105 if (op1
== 0x7 && ((insn
& sh
) == sh
))
7109 /* load/store byte/word */
7110 rn
= (insn
>> 16) & 0xf;
7111 rd
= (insn
>> 12) & 0xf;
7112 tmp2
= load_reg(s
, rn
);
7113 i
= (IS_USER(s
) || (insn
& 0x01200000) == 0x00200000);
7114 if (insn
& (1 << 24))
7115 gen_add_data_offset(s
, insn
, tmp2
);
7116 if (insn
& (1 << 20)) {
7118 if (insn
& (1 << 22)) {
7119 tmp
= gen_ld8u(tmp2
, i
);
7121 tmp
= gen_ld32(tmp2
, i
);
7125 tmp
= load_reg(s
, rd
);
7126 if (insn
& (1 << 22))
7127 gen_st8(tmp
, tmp2
, i
);
7129 gen_st32(tmp
, tmp2
, i
);
7131 if (!(insn
& (1 << 24))) {
7132 gen_add_data_offset(s
, insn
, tmp2
);
7133 store_reg(s
, rn
, tmp2
);
7134 } else if (insn
& (1 << 21)) {
7135 store_reg(s
, rn
, tmp2
);
7137 tcg_temp_free_i32(tmp2
);
7139 if (insn
& (1 << 20)) {
7140 /* Complete the load. */
7144 store_reg(s
, rd
, tmp
);
7150 int j
, n
, user
, loaded_base
;
7152 /* load/store multiple words */
7153 /* XXX: store correct base if write back */
7155 if (insn
& (1 << 22)) {
7157 goto illegal_op
; /* only usable in supervisor mode */
7159 if ((insn
& (1 << 15)) == 0)
7162 rn
= (insn
>> 16) & 0xf;
7163 addr
= load_reg(s
, rn
);
7165 /* compute total size */
7167 TCGV_UNUSED(loaded_var
);
7170 if (insn
& (1 << i
))
7173 /* XXX: test invalid n == 0 case ? */
7174 if (insn
& (1 << 23)) {
7175 if (insn
& (1 << 24)) {
7177 tcg_gen_addi_i32(addr
, addr
, 4);
7179 /* post increment */
7182 if (insn
& (1 << 24)) {
7184 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7186 /* post decrement */
7188 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7193 if (insn
& (1 << i
)) {
7194 if (insn
& (1 << 20)) {
7196 tmp
= gen_ld32(addr
, IS_USER(s
));
7200 tmp2
= tcg_const_i32(i
);
7201 gen_helper_set_user_reg(tmp2
, tmp
);
7202 tcg_temp_free_i32(tmp2
);
7203 tcg_temp_free_i32(tmp
);
7204 } else if (i
== rn
) {
7208 store_reg(s
, i
, tmp
);
7213 /* special case: r15 = PC + 8 */
7214 val
= (long)s
->pc
+ 4;
7215 tmp
= tcg_temp_new_i32();
7216 tcg_gen_movi_i32(tmp
, val
);
7218 tmp
= tcg_temp_new_i32();
7219 tmp2
= tcg_const_i32(i
);
7220 gen_helper_get_user_reg(tmp
, tmp2
);
7221 tcg_temp_free_i32(tmp2
);
7223 tmp
= load_reg(s
, i
);
7225 gen_st32(tmp
, addr
, IS_USER(s
));
7228 /* no need to add after the last transfer */
7230 tcg_gen_addi_i32(addr
, addr
, 4);
7233 if (insn
& (1 << 21)) {
7235 if (insn
& (1 << 23)) {
7236 if (insn
& (1 << 24)) {
7239 /* post increment */
7240 tcg_gen_addi_i32(addr
, addr
, 4);
7243 if (insn
& (1 << 24)) {
7246 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7248 /* post decrement */
7249 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7252 store_reg(s
, rn
, addr
);
7254 tcg_temp_free_i32(addr
);
7257 store_reg(s
, rn
, loaded_var
);
7259 if ((insn
& (1 << 22)) && !user
) {
7260 /* Restore CPSR from SPSR. */
7261 tmp
= load_cpu_field(spsr
);
7262 gen_set_cpsr(tmp
, 0xffffffff);
7263 tcg_temp_free_i32(tmp
);
7264 s
->is_jmp
= DISAS_UPDATE
;
7273 /* branch (and link) */
7274 val
= (int32_t)s
->pc
;
7275 if (insn
& (1 << 24)) {
7276 tmp
= tcg_temp_new_i32();
7277 tcg_gen_movi_i32(tmp
, val
);
7278 store_reg(s
, 14, tmp
);
7280 offset
= (((int32_t)insn
<< 8) >> 8);
7281 val
+= (offset
<< 2) + 4;
7289 if (disas_coproc_insn(env
, s
, insn
))
7294 gen_set_pc_im(s
->pc
);
7295 s
->is_jmp
= DISAS_SWI
;
7299 gen_exception_insn(s
, 4, EXCP_UDEF
);
7305 /* Return true if this is a Thumb-2 logical op. */
7307 thumb2_logic_op(int op
)
7312 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7313 then set condition code flags based on the result of the operation.
7314 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7315 to the high bit of T1.
7316 Returns zero if the opcode is valid. */
7319 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
, TCGv t0
, TCGv t1
)
7326 tcg_gen_and_i32(t0
, t0
, t1
);
7330 tcg_gen_andc_i32(t0
, t0
, t1
);
7334 tcg_gen_or_i32(t0
, t0
, t1
);
7338 tcg_gen_orc_i32(t0
, t0
, t1
);
7342 tcg_gen_xor_i32(t0
, t0
, t1
);
7347 gen_helper_add_cc(t0
, t0
, t1
);
7349 tcg_gen_add_i32(t0
, t0
, t1
);
7353 gen_helper_adc_cc(t0
, t0
, t1
);
7359 gen_helper_sbc_cc(t0
, t0
, t1
);
7361 gen_sub_carry(t0
, t0
, t1
);
7365 gen_helper_sub_cc(t0
, t0
, t1
);
7367 tcg_gen_sub_i32(t0
, t0
, t1
);
7371 gen_helper_sub_cc(t0
, t1
, t0
);
7373 tcg_gen_sub_i32(t0
, t1
, t0
);
7375 default: /* 5, 6, 7, 9, 12, 15. */
7381 gen_set_CF_bit31(t1
);
7386 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7388 static int disas_thumb2_insn(CPUState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
7390 uint32_t insn
, imm
, shift
, offset
;
7391 uint32_t rd
, rn
, rm
, rs
;
7402 if (!(arm_feature(env
, ARM_FEATURE_THUMB2
)
7403 || arm_feature (env
, ARM_FEATURE_M
))) {
7404 /* Thumb-1 cores may need to treat bl and blx as a pair of
7405 16-bit instructions to get correct prefetch abort behavior. */
7407 if ((insn
& (1 << 12)) == 0) {
7408 /* Second half of blx. */
7409 offset
= ((insn
& 0x7ff) << 1);
7410 tmp
= load_reg(s
, 14);
7411 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7412 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
7414 tmp2
= tcg_temp_new_i32();
7415 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7416 store_reg(s
, 14, tmp2
);
7420 if (insn
& (1 << 11)) {
7421 /* Second half of bl. */
7422 offset
= ((insn
& 0x7ff) << 1) | 1;
7423 tmp
= load_reg(s
, 14);
7424 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7426 tmp2
= tcg_temp_new_i32();
7427 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7428 store_reg(s
, 14, tmp2
);
7432 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
7433 /* Instruction spans a page boundary. Implement it as two
7434 16-bit instructions in case the second half causes an
7436 offset
= ((int32_t)insn
<< 21) >> 9;
7437 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
7440 /* Fall through to 32-bit decode. */
7443 insn
= lduw_code(s
->pc
);
7445 insn
|= (uint32_t)insn_hw1
<< 16;
7447 if ((insn
& 0xf800e800) != 0xf000e800) {
7451 rn
= (insn
>> 16) & 0xf;
7452 rs
= (insn
>> 12) & 0xf;
7453 rd
= (insn
>> 8) & 0xf;
7455 switch ((insn
>> 25) & 0xf) {
7456 case 0: case 1: case 2: case 3:
7457 /* 16-bit instructions. Should never happen. */
7460 if (insn
& (1 << 22)) {
7461 /* Other load/store, table branch. */
7462 if (insn
& 0x01200000) {
7463 /* Load/store doubleword. */
7465 addr
= tcg_temp_new_i32();
7466 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
7468 addr
= load_reg(s
, rn
);
7470 offset
= (insn
& 0xff) * 4;
7471 if ((insn
& (1 << 23)) == 0)
7473 if (insn
& (1 << 24)) {
7474 tcg_gen_addi_i32(addr
, addr
, offset
);
7477 if (insn
& (1 << 20)) {
7479 tmp
= gen_ld32(addr
, IS_USER(s
));
7480 store_reg(s
, rs
, tmp
);
7481 tcg_gen_addi_i32(addr
, addr
, 4);
7482 tmp
= gen_ld32(addr
, IS_USER(s
));
7483 store_reg(s
, rd
, tmp
);
7486 tmp
= load_reg(s
, rs
);
7487 gen_st32(tmp
, addr
, IS_USER(s
));
7488 tcg_gen_addi_i32(addr
, addr
, 4);
7489 tmp
= load_reg(s
, rd
);
7490 gen_st32(tmp
, addr
, IS_USER(s
));
7492 if (insn
& (1 << 21)) {
7493 /* Base writeback. */
7496 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
7497 store_reg(s
, rn
, addr
);
7499 tcg_temp_free_i32(addr
);
7501 } else if ((insn
& (1 << 23)) == 0) {
7502 /* Load/store exclusive word. */
7503 addr
= tcg_temp_local_new();
7504 load_reg_var(s
, addr
, rn
);
7505 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
7506 if (insn
& (1 << 20)) {
7507 gen_load_exclusive(s
, rs
, 15, addr
, 2);
7509 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
7511 tcg_temp_free(addr
);
7512 } else if ((insn
& (1 << 6)) == 0) {
7515 addr
= tcg_temp_new_i32();
7516 tcg_gen_movi_i32(addr
, s
->pc
);
7518 addr
= load_reg(s
, rn
);
7520 tmp
= load_reg(s
, rm
);
7521 tcg_gen_add_i32(addr
, addr
, tmp
);
7522 if (insn
& (1 << 4)) {
7524 tcg_gen_add_i32(addr
, addr
, tmp
);
7525 tcg_temp_free_i32(tmp
);
7526 tmp
= gen_ld16u(addr
, IS_USER(s
));
7528 tcg_temp_free_i32(tmp
);
7529 tmp
= gen_ld8u(addr
, IS_USER(s
));
7531 tcg_temp_free_i32(addr
);
7532 tcg_gen_shli_i32(tmp
, tmp
, 1);
7533 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
7534 store_reg(s
, 15, tmp
);
7536 /* Load/store exclusive byte/halfword/doubleword. */
7538 op
= (insn
>> 4) & 0x3;
7542 addr
= tcg_temp_local_new();
7543 load_reg_var(s
, addr
, rn
);
7544 if (insn
& (1 << 20)) {
7545 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
7547 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
7549 tcg_temp_free(addr
);
7552 /* Load/store multiple, RFE, SRS. */
7553 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
7554 /* Not available in user mode. */
7557 if (insn
& (1 << 20)) {
7559 addr
= load_reg(s
, rn
);
7560 if ((insn
& (1 << 24)) == 0)
7561 tcg_gen_addi_i32(addr
, addr
, -8);
7562 /* Load PC into tmp and CPSR into tmp2. */
7563 tmp
= gen_ld32(addr
, 0);
7564 tcg_gen_addi_i32(addr
, addr
, 4);
7565 tmp2
= gen_ld32(addr
, 0);
7566 if (insn
& (1 << 21)) {
7567 /* Base writeback. */
7568 if (insn
& (1 << 24)) {
7569 tcg_gen_addi_i32(addr
, addr
, 4);
7571 tcg_gen_addi_i32(addr
, addr
, -4);
7573 store_reg(s
, rn
, addr
);
7575 tcg_temp_free_i32(addr
);
7577 gen_rfe(s
, tmp
, tmp2
);
7581 addr
= tcg_temp_new_i32();
7582 tmp
= tcg_const_i32(op
);
7583 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7584 tcg_temp_free_i32(tmp
);
7585 if ((insn
& (1 << 24)) == 0) {
7586 tcg_gen_addi_i32(addr
, addr
, -8);
7588 tmp
= load_reg(s
, 14);
7589 gen_st32(tmp
, addr
, 0);
7590 tcg_gen_addi_i32(addr
, addr
, 4);
7591 tmp
= tcg_temp_new_i32();
7592 gen_helper_cpsr_read(tmp
);
7593 gen_st32(tmp
, addr
, 0);
7594 if (insn
& (1 << 21)) {
7595 if ((insn
& (1 << 24)) == 0) {
7596 tcg_gen_addi_i32(addr
, addr
, -4);
7598 tcg_gen_addi_i32(addr
, addr
, 4);
7600 tmp
= tcg_const_i32(op
);
7601 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7602 tcg_temp_free_i32(tmp
);
7604 tcg_temp_free_i32(addr
);
7609 /* Load/store multiple. */
7610 addr
= load_reg(s
, rn
);
7612 for (i
= 0; i
< 16; i
++) {
7613 if (insn
& (1 << i
))
7616 if (insn
& (1 << 24)) {
7617 tcg_gen_addi_i32(addr
, addr
, -offset
);
7620 for (i
= 0; i
< 16; i
++) {
7621 if ((insn
& (1 << i
)) == 0)
7623 if (insn
& (1 << 20)) {
7625 tmp
= gen_ld32(addr
, IS_USER(s
));
7629 store_reg(s
, i
, tmp
);
7633 tmp
= load_reg(s
, i
);
7634 gen_st32(tmp
, addr
, IS_USER(s
));
7636 tcg_gen_addi_i32(addr
, addr
, 4);
7638 if (insn
& (1 << 21)) {
7639 /* Base register writeback. */
7640 if (insn
& (1 << 24)) {
7641 tcg_gen_addi_i32(addr
, addr
, -offset
);
7643 /* Fault if writeback register is in register list. */
7644 if (insn
& (1 << rn
))
7646 store_reg(s
, rn
, addr
);
7648 tcg_temp_free_i32(addr
);
7655 op
= (insn
>> 21) & 0xf;
7657 /* Halfword pack. */
7658 tmp
= load_reg(s
, rn
);
7659 tmp2
= load_reg(s
, rm
);
7660 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
7661 if (insn
& (1 << 5)) {
7665 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
7666 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
7667 tcg_gen_ext16u_i32(tmp2
, tmp2
);
7671 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
7672 tcg_gen_ext16u_i32(tmp
, tmp
);
7673 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
7675 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
7676 tcg_temp_free_i32(tmp2
);
7677 store_reg(s
, rd
, tmp
);
7679 /* Data processing register constant shift. */
7681 tmp
= tcg_temp_new_i32();
7682 tcg_gen_movi_i32(tmp
, 0);
7684 tmp
= load_reg(s
, rn
);
7686 tmp2
= load_reg(s
, rm
);
7688 shiftop
= (insn
>> 4) & 3;
7689 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
7690 conds
= (insn
& (1 << 20)) != 0;
7691 logic_cc
= (conds
&& thumb2_logic_op(op
));
7692 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
7693 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
7695 tcg_temp_free_i32(tmp2
);
7697 store_reg(s
, rd
, tmp
);
7699 tcg_temp_free_i32(tmp
);
7703 case 13: /* Misc data processing. */
7704 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
7705 if (op
< 4 && (insn
& 0xf000) != 0xf000)
7708 case 0: /* Register controlled shift. */
7709 tmp
= load_reg(s
, rn
);
7710 tmp2
= load_reg(s
, rm
);
7711 if ((insn
& 0x70) != 0)
7713 op
= (insn
>> 21) & 3;
7714 logic_cc
= (insn
& (1 << 20)) != 0;
7715 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
7718 store_reg_bx(env
, s
, rd
, tmp
);
7720 case 1: /* Sign/zero extend. */
7721 tmp
= load_reg(s
, rm
);
7722 shift
= (insn
>> 4) & 3;
7723 /* ??? In many cases it's not neccessary to do a
7724 rotate, a shift is sufficient. */
7726 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
7727 op
= (insn
>> 20) & 7;
7729 case 0: gen_sxth(tmp
); break;
7730 case 1: gen_uxth(tmp
); break;
7731 case 2: gen_sxtb16(tmp
); break;
7732 case 3: gen_uxtb16(tmp
); break;
7733 case 4: gen_sxtb(tmp
); break;
7734 case 5: gen_uxtb(tmp
); break;
7735 default: goto illegal_op
;
7738 tmp2
= load_reg(s
, rn
);
7739 if ((op
>> 1) == 1) {
7740 gen_add16(tmp
, tmp2
);
7742 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7743 tcg_temp_free_i32(tmp2
);
7746 store_reg(s
, rd
, tmp
);
7748 case 2: /* SIMD add/subtract. */
7749 op
= (insn
>> 20) & 7;
7750 shift
= (insn
>> 4) & 7;
7751 if ((op
& 3) == 3 || (shift
& 3) == 3)
7753 tmp
= load_reg(s
, rn
);
7754 tmp2
= load_reg(s
, rm
);
7755 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
7756 tcg_temp_free_i32(tmp2
);
7757 store_reg(s
, rd
, tmp
);
7759 case 3: /* Other data processing. */
7760 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
7762 /* Saturating add/subtract. */
7763 tmp
= load_reg(s
, rn
);
7764 tmp2
= load_reg(s
, rm
);
7766 gen_helper_double_saturate(tmp
, tmp
);
7768 gen_helper_sub_saturate(tmp
, tmp2
, tmp
);
7770 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
7771 tcg_temp_free_i32(tmp2
);
7773 tmp
= load_reg(s
, rn
);
7775 case 0x0a: /* rbit */
7776 gen_helper_rbit(tmp
, tmp
);
7778 case 0x08: /* rev */
7779 tcg_gen_bswap32_i32(tmp
, tmp
);
7781 case 0x09: /* rev16 */
7784 case 0x0b: /* revsh */
7787 case 0x10: /* sel */
7788 tmp2
= load_reg(s
, rm
);
7789 tmp3
= tcg_temp_new_i32();
7790 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
7791 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
7792 tcg_temp_free_i32(tmp3
);
7793 tcg_temp_free_i32(tmp2
);
7795 case 0x18: /* clz */
7796 gen_helper_clz(tmp
, tmp
);
7802 store_reg(s
, rd
, tmp
);
7804 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7805 op
= (insn
>> 4) & 0xf;
7806 tmp
= load_reg(s
, rn
);
7807 tmp2
= load_reg(s
, rm
);
7808 switch ((insn
>> 20) & 7) {
7809 case 0: /* 32 x 32 -> 32 */
7810 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
7811 tcg_temp_free_i32(tmp2
);
7813 tmp2
= load_reg(s
, rs
);
7815 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7817 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7818 tcg_temp_free_i32(tmp2
);
7821 case 1: /* 16 x 16 -> 32 */
7822 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
7823 tcg_temp_free_i32(tmp2
);
7825 tmp2
= load_reg(s
, rs
);
7826 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7827 tcg_temp_free_i32(tmp2
);
7830 case 2: /* Dual multiply add. */
7831 case 4: /* Dual multiply subtract. */
7833 gen_swap_half(tmp2
);
7834 gen_smul_dual(tmp
, tmp2
);
7835 /* This addition cannot overflow. */
7836 if (insn
& (1 << 22)) {
7837 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7839 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7841 tcg_temp_free_i32(tmp2
);
7844 tmp2
= load_reg(s
, rs
);
7845 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7846 tcg_temp_free_i32(tmp2
);
7849 case 3: /* 32 * 16 -> 32msb */
7851 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
7854 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7855 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
7856 tmp
= tcg_temp_new_i32();
7857 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7858 tcg_temp_free_i64(tmp64
);
7861 tmp2
= load_reg(s
, rs
);
7862 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7863 tcg_temp_free_i32(tmp2
);
7866 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7867 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7869 tmp
= load_reg(s
, rs
);
7870 if (insn
& (1 << 20)) {
7871 tmp64
= gen_addq_msw(tmp64
, tmp
);
7873 tmp64
= gen_subq_msw(tmp64
, tmp
);
7876 if (insn
& (1 << 4)) {
7877 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
7879 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7880 tmp
= tcg_temp_new_i32();
7881 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7882 tcg_temp_free_i64(tmp64
);
7884 case 7: /* Unsigned sum of absolute differences. */
7885 gen_helper_usad8(tmp
, tmp
, tmp2
);
7886 tcg_temp_free_i32(tmp2
);
7888 tmp2
= load_reg(s
, rs
);
7889 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7890 tcg_temp_free_i32(tmp2
);
7894 store_reg(s
, rd
, tmp
);
7896 case 6: case 7: /* 64-bit multiply, Divide. */
7897 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
7898 tmp
= load_reg(s
, rn
);
7899 tmp2
= load_reg(s
, rm
);
7900 if ((op
& 0x50) == 0x10) {
7902 if (!arm_feature(env
, ARM_FEATURE_DIV
))
7905 gen_helper_udiv(tmp
, tmp
, tmp2
);
7907 gen_helper_sdiv(tmp
, tmp
, tmp2
);
7908 tcg_temp_free_i32(tmp2
);
7909 store_reg(s
, rd
, tmp
);
7910 } else if ((op
& 0xe) == 0xc) {
7911 /* Dual multiply accumulate long. */
7913 gen_swap_half(tmp2
);
7914 gen_smul_dual(tmp
, tmp2
);
7916 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7918 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7920 tcg_temp_free_i32(tmp2
);
7922 tmp64
= tcg_temp_new_i64();
7923 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7924 tcg_temp_free_i32(tmp
);
7925 gen_addq(s
, tmp64
, rs
, rd
);
7926 gen_storeq_reg(s
, rs
, rd
, tmp64
);
7927 tcg_temp_free_i64(tmp64
);
7930 /* Unsigned 64-bit multiply */
7931 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
7935 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
7936 tcg_temp_free_i32(tmp2
);
7937 tmp64
= tcg_temp_new_i64();
7938 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7939 tcg_temp_free_i32(tmp
);
7941 /* Signed 64-bit multiply */
7942 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7947 gen_addq_lo(s
, tmp64
, rs
);
7948 gen_addq_lo(s
, tmp64
, rd
);
7949 } else if (op
& 0x40) {
7950 /* 64-bit accumulate. */
7951 gen_addq(s
, tmp64
, rs
, rd
);
7953 gen_storeq_reg(s
, rs
, rd
, tmp64
);
7954 tcg_temp_free_i64(tmp64
);
7959 case 6: case 7: case 14: case 15:
7961 if (((insn
>> 24) & 3) == 3) {
7962 /* Translate into the equivalent ARM encoding. */
7963 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
7964 if (disas_neon_data_insn(env
, s
, insn
))
7967 if (insn
& (1 << 28))
7969 if (disas_coproc_insn (env
, s
, insn
))
7973 case 8: case 9: case 10: case 11:
7974 if (insn
& (1 << 15)) {
7975 /* Branches, misc control. */
7976 if (insn
& 0x5000) {
7977 /* Unconditional branch. */
7978 /* signextend(hw1[10:0]) -> offset[:12]. */
7979 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
7980 /* hw1[10:0] -> offset[11:1]. */
7981 offset
|= (insn
& 0x7ff) << 1;
7982 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7983 offset[24:22] already have the same value because of the
7984 sign extension above. */
7985 offset
^= ((~insn
) & (1 << 13)) << 10;
7986 offset
^= ((~insn
) & (1 << 11)) << 11;
7988 if (insn
& (1 << 14)) {
7989 /* Branch and link. */
7990 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
7994 if (insn
& (1 << 12)) {
7999 offset
&= ~(uint32_t)2;
8000 gen_bx_im(s
, offset
);
8002 } else if (((insn
>> 23) & 7) == 7) {
8004 if (insn
& (1 << 13))
8007 if (insn
& (1 << 26)) {
8008 /* Secure monitor call (v6Z) */
8009 goto illegal_op
; /* not implemented. */
8011 op
= (insn
>> 20) & 7;
8013 case 0: /* msr cpsr. */
8015 tmp
= load_reg(s
, rn
);
8016 addr
= tcg_const_i32(insn
& 0xff);
8017 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8018 tcg_temp_free_i32(addr
);
8019 tcg_temp_free_i32(tmp
);
8024 case 1: /* msr spsr. */
8027 tmp
= load_reg(s
, rn
);
8029 msr_mask(env
, s
, (insn
>> 8) & 0xf, op
== 1),
8033 case 2: /* cps, nop-hint. */
8034 if (((insn
>> 8) & 7) == 0) {
8035 gen_nop_hint(s
, insn
& 0xff);
8037 /* Implemented as NOP in user mode. */
8042 if (insn
& (1 << 10)) {
8043 if (insn
& (1 << 7))
8045 if (insn
& (1 << 6))
8047 if (insn
& (1 << 5))
8049 if (insn
& (1 << 9))
8050 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
8052 if (insn
& (1 << 8)) {
8054 imm
|= (insn
& 0x1f);
8057 gen_set_psr_im(s
, offset
, 0, imm
);
8060 case 3: /* Special control operations. */
8062 op
= (insn
>> 4) & 0xf;
8070 /* These execute as NOPs. */
8077 /* Trivial implementation equivalent to bx. */
8078 tmp
= load_reg(s
, rn
);
8081 case 5: /* Exception return. */
8085 if (rn
!= 14 || rd
!= 15) {
8088 tmp
= load_reg(s
, rn
);
8089 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
8090 gen_exception_return(s
, tmp
);
8092 case 6: /* mrs cpsr. */
8093 tmp
= tcg_temp_new_i32();
8095 addr
= tcg_const_i32(insn
& 0xff);
8096 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
8097 tcg_temp_free_i32(addr
);
8099 gen_helper_cpsr_read(tmp
);
8101 store_reg(s
, rd
, tmp
);
8103 case 7: /* mrs spsr. */
8104 /* Not accessible in user mode. */
8105 if (IS_USER(s
) || IS_M(env
))
8107 tmp
= load_cpu_field(spsr
);
8108 store_reg(s
, rd
, tmp
);
8113 /* Conditional branch. */
8114 op
= (insn
>> 22) & 0xf;
8115 /* Generate a conditional jump to next instruction. */
8116 s
->condlabel
= gen_new_label();
8117 gen_test_cc(op
^ 1, s
->condlabel
);
8120 /* offset[11:1] = insn[10:0] */
8121 offset
= (insn
& 0x7ff) << 1;
8122 /* offset[17:12] = insn[21:16]. */
8123 offset
|= (insn
& 0x003f0000) >> 4;
8124 /* offset[31:20] = insn[26]. */
8125 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
8126 /* offset[18] = insn[13]. */
8127 offset
|= (insn
& (1 << 13)) << 5;
8128 /* offset[19] = insn[11]. */
8129 offset
|= (insn
& (1 << 11)) << 8;
8131 /* jump to the offset */
8132 gen_jmp(s
, s
->pc
+ offset
);
8135 /* Data processing immediate. */
8136 if (insn
& (1 << 25)) {
8137 if (insn
& (1 << 24)) {
8138 if (insn
& (1 << 20))
8140 /* Bitfield/Saturate. */
8141 op
= (insn
>> 21) & 7;
8143 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
8145 tmp
= tcg_temp_new_i32();
8146 tcg_gen_movi_i32(tmp
, 0);
8148 tmp
= load_reg(s
, rn
);
8151 case 2: /* Signed bitfield extract. */
8153 if (shift
+ imm
> 32)
8156 gen_sbfx(tmp
, shift
, imm
);
8158 case 6: /* Unsigned bitfield extract. */
8160 if (shift
+ imm
> 32)
8163 gen_ubfx(tmp
, shift
, (1u << imm
) - 1);
8165 case 3: /* Bitfield insert/clear. */
8168 imm
= imm
+ 1 - shift
;
8170 tmp2
= load_reg(s
, rd
);
8171 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << imm
) - 1);
8172 tcg_temp_free_i32(tmp2
);
8177 default: /* Saturate. */
8180 tcg_gen_sari_i32(tmp
, tmp
, shift
);
8182 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8184 tmp2
= tcg_const_i32(imm
);
8187 if ((op
& 1) && shift
== 0)
8188 gen_helper_usat16(tmp
, tmp
, tmp2
);
8190 gen_helper_usat(tmp
, tmp
, tmp2
);
8193 if ((op
& 1) && shift
== 0)
8194 gen_helper_ssat16(tmp
, tmp
, tmp2
);
8196 gen_helper_ssat(tmp
, tmp
, tmp2
);
8198 tcg_temp_free_i32(tmp2
);
8201 store_reg(s
, rd
, tmp
);
8203 imm
= ((insn
& 0x04000000) >> 15)
8204 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
8205 if (insn
& (1 << 22)) {
8206 /* 16-bit immediate. */
8207 imm
|= (insn
>> 4) & 0xf000;
8208 if (insn
& (1 << 23)) {
8210 tmp
= load_reg(s
, rd
);
8211 tcg_gen_ext16u_i32(tmp
, tmp
);
8212 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
8215 tmp
= tcg_temp_new_i32();
8216 tcg_gen_movi_i32(tmp
, imm
);
8219 /* Add/sub 12-bit immediate. */
8221 offset
= s
->pc
& ~(uint32_t)3;
8222 if (insn
& (1 << 23))
8226 tmp
= tcg_temp_new_i32();
8227 tcg_gen_movi_i32(tmp
, offset
);
8229 tmp
= load_reg(s
, rn
);
8230 if (insn
& (1 << 23))
8231 tcg_gen_subi_i32(tmp
, tmp
, imm
);
8233 tcg_gen_addi_i32(tmp
, tmp
, imm
);
8236 store_reg(s
, rd
, tmp
);
8239 int shifter_out
= 0;
8240 /* modified 12-bit immediate. */
8241 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
8242 imm
= (insn
& 0xff);
8245 /* Nothing to do. */
8247 case 1: /* 00XY00XY */
8250 case 2: /* XY00XY00 */
8254 case 3: /* XYXYXYXY */
8258 default: /* Rotated constant. */
8259 shift
= (shift
<< 1) | (imm
>> 7);
8261 imm
= imm
<< (32 - shift
);
8265 tmp2
= tcg_temp_new_i32();
8266 tcg_gen_movi_i32(tmp2
, imm
);
8267 rn
= (insn
>> 16) & 0xf;
8269 tmp
= tcg_temp_new_i32();
8270 tcg_gen_movi_i32(tmp
, 0);
8272 tmp
= load_reg(s
, rn
);
8274 op
= (insn
>> 21) & 0xf;
8275 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
8276 shifter_out
, tmp
, tmp2
))
8278 tcg_temp_free_i32(tmp2
);
8279 rd
= (insn
>> 8) & 0xf;
8281 store_reg(s
, rd
, tmp
);
8283 tcg_temp_free_i32(tmp
);
8288 case 12: /* Load/store single data item. */
8293 if ((insn
& 0x01100000) == 0x01000000) {
8294 if (disas_neon_ls_insn(env
, s
, insn
))
8298 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
8300 if (!(insn
& (1 << 20))) {
8304 /* Byte or halfword load space with dest == r15 : memory hints.
8305 * Catch them early so we don't emit pointless addressing code.
8306 * This space is a mix of:
8307 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8308 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8310 * unallocated hints, which must be treated as NOPs
8311 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8312 * which is easiest for the decoding logic
8313 * Some space which must UNDEF
8315 int op1
= (insn
>> 23) & 3;
8316 int op2
= (insn
>> 6) & 0x3f;
8321 /* UNPREDICTABLE or unallocated hint */
8325 return 0; /* PLD* or unallocated hint */
8327 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
8328 return 0; /* PLD* or unallocated hint */
8330 /* UNDEF space, or an UNPREDICTABLE */
8336 addr
= tcg_temp_new_i32();
8338 /* s->pc has already been incremented by 4. */
8339 imm
= s
->pc
& 0xfffffffc;
8340 if (insn
& (1 << 23))
8341 imm
+= insn
& 0xfff;
8343 imm
-= insn
& 0xfff;
8344 tcg_gen_movi_i32(addr
, imm
);
8346 addr
= load_reg(s
, rn
);
8347 if (insn
& (1 << 23)) {
8348 /* Positive offset. */
8350 tcg_gen_addi_i32(addr
, addr
, imm
);
8353 switch ((insn
>> 8) & 7) {
8354 case 0: case 8: /* Shifted Register. */
8355 shift
= (insn
>> 4) & 0xf;
8358 tmp
= load_reg(s
, rm
);
8360 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8361 tcg_gen_add_i32(addr
, addr
, tmp
);
8362 tcg_temp_free_i32(tmp
);
8364 case 4: /* Negative offset. */
8365 tcg_gen_addi_i32(addr
, addr
, -imm
);
8367 case 6: /* User privilege. */
8368 tcg_gen_addi_i32(addr
, addr
, imm
);
8371 case 1: /* Post-decrement. */
8374 case 3: /* Post-increment. */
8378 case 5: /* Pre-decrement. */
8381 case 7: /* Pre-increment. */
8382 tcg_gen_addi_i32(addr
, addr
, imm
);
8390 if (insn
& (1 << 20)) {
8393 case 0: tmp
= gen_ld8u(addr
, user
); break;
8394 case 4: tmp
= gen_ld8s(addr
, user
); break;
8395 case 1: tmp
= gen_ld16u(addr
, user
); break;
8396 case 5: tmp
= gen_ld16s(addr
, user
); break;
8397 case 2: tmp
= gen_ld32(addr
, user
); break;
8398 default: goto illegal_op
;
8403 store_reg(s
, rs
, tmp
);
8407 tmp
= load_reg(s
, rs
);
8409 case 0: gen_st8(tmp
, addr
, user
); break;
8410 case 1: gen_st16(tmp
, addr
, user
); break;
8411 case 2: gen_st32(tmp
, addr
, user
); break;
8412 default: goto illegal_op
;
8416 tcg_gen_addi_i32(addr
, addr
, imm
);
8418 store_reg(s
, rn
, addr
);
8420 tcg_temp_free_i32(addr
);
8432 static void disas_thumb_insn(CPUState
*env
, DisasContext
*s
)
8434 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
8441 if (s
->condexec_mask
) {
8442 cond
= s
->condexec_cond
;
8443 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
8444 s
->condlabel
= gen_new_label();
8445 gen_test_cc(cond
^ 1, s
->condlabel
);
8450 insn
= lduw_code(s
->pc
);
8453 switch (insn
>> 12) {
8457 op
= (insn
>> 11) & 3;
8460 rn
= (insn
>> 3) & 7;
8461 tmp
= load_reg(s
, rn
);
8462 if (insn
& (1 << 10)) {
8464 tmp2
= tcg_temp_new_i32();
8465 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
8468 rm
= (insn
>> 6) & 7;
8469 tmp2
= load_reg(s
, rm
);
8471 if (insn
& (1 << 9)) {
8472 if (s
->condexec_mask
)
8473 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8475 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8477 if (s
->condexec_mask
)
8478 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8480 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8482 tcg_temp_free_i32(tmp2
);
8483 store_reg(s
, rd
, tmp
);
8485 /* shift immediate */
8486 rm
= (insn
>> 3) & 7;
8487 shift
= (insn
>> 6) & 0x1f;
8488 tmp
= load_reg(s
, rm
);
8489 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
8490 if (!s
->condexec_mask
)
8492 store_reg(s
, rd
, tmp
);
8496 /* arithmetic large immediate */
8497 op
= (insn
>> 11) & 3;
8498 rd
= (insn
>> 8) & 0x7;
8499 if (op
== 0) { /* mov */
8500 tmp
= tcg_temp_new_i32();
8501 tcg_gen_movi_i32(tmp
, insn
& 0xff);
8502 if (!s
->condexec_mask
)
8504 store_reg(s
, rd
, tmp
);
8506 tmp
= load_reg(s
, rd
);
8507 tmp2
= tcg_temp_new_i32();
8508 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
8511 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8512 tcg_temp_free_i32(tmp
);
8513 tcg_temp_free_i32(tmp2
);
8516 if (s
->condexec_mask
)
8517 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8519 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8520 tcg_temp_free_i32(tmp2
);
8521 store_reg(s
, rd
, tmp
);
8524 if (s
->condexec_mask
)
8525 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8527 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8528 tcg_temp_free_i32(tmp2
);
8529 store_reg(s
, rd
, tmp
);
8535 if (insn
& (1 << 11)) {
8536 rd
= (insn
>> 8) & 7;
8537 /* load pc-relative. Bit 1 of PC is ignored. */
8538 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
8539 val
&= ~(uint32_t)2;
8540 addr
= tcg_temp_new_i32();
8541 tcg_gen_movi_i32(addr
, val
);
8542 tmp
= gen_ld32(addr
, IS_USER(s
));
8543 tcg_temp_free_i32(addr
);
8544 store_reg(s
, rd
, tmp
);
8547 if (insn
& (1 << 10)) {
8548 /* data processing extended or blx */
8549 rd
= (insn
& 7) | ((insn
>> 4) & 8);
8550 rm
= (insn
>> 3) & 0xf;
8551 op
= (insn
>> 8) & 3;
8554 tmp
= load_reg(s
, rd
);
8555 tmp2
= load_reg(s
, rm
);
8556 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8557 tcg_temp_free_i32(tmp2
);
8558 store_reg(s
, rd
, tmp
);
8561 tmp
= load_reg(s
, rd
);
8562 tmp2
= load_reg(s
, rm
);
8563 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8564 tcg_temp_free_i32(tmp2
);
8565 tcg_temp_free_i32(tmp
);
8567 case 2: /* mov/cpy */
8568 tmp
= load_reg(s
, rm
);
8569 store_reg(s
, rd
, tmp
);
8571 case 3:/* branch [and link] exchange thumb register */
8572 tmp
= load_reg(s
, rm
);
8573 if (insn
& (1 << 7)) {
8574 val
= (uint32_t)s
->pc
| 1;
8575 tmp2
= tcg_temp_new_i32();
8576 tcg_gen_movi_i32(tmp2
, val
);
8577 store_reg(s
, 14, tmp2
);
8585 /* data processing register */
8587 rm
= (insn
>> 3) & 7;
8588 op
= (insn
>> 6) & 0xf;
8589 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
8590 /* the shift/rotate ops want the operands backwards */
8599 if (op
== 9) { /* neg */
8600 tmp
= tcg_temp_new_i32();
8601 tcg_gen_movi_i32(tmp
, 0);
8602 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
8603 tmp
= load_reg(s
, rd
);
8608 tmp2
= load_reg(s
, rm
);
8611 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8612 if (!s
->condexec_mask
)
8616 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8617 if (!s
->condexec_mask
)
8621 if (s
->condexec_mask
) {
8622 gen_helper_shl(tmp2
, tmp2
, tmp
);
8624 gen_helper_shl_cc(tmp2
, tmp2
, tmp
);
8629 if (s
->condexec_mask
) {
8630 gen_helper_shr(tmp2
, tmp2
, tmp
);
8632 gen_helper_shr_cc(tmp2
, tmp2
, tmp
);
8637 if (s
->condexec_mask
) {
8638 gen_helper_sar(tmp2
, tmp2
, tmp
);
8640 gen_helper_sar_cc(tmp2
, tmp2
, tmp
);
8645 if (s
->condexec_mask
)
8648 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
8651 if (s
->condexec_mask
)
8652 gen_sub_carry(tmp
, tmp
, tmp2
);
8654 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
8657 if (s
->condexec_mask
) {
8658 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
8659 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
8661 gen_helper_ror_cc(tmp2
, tmp2
, tmp
);
8666 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8671 if (s
->condexec_mask
)
8672 tcg_gen_neg_i32(tmp
, tmp2
);
8674 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8677 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8681 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8685 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8686 if (!s
->condexec_mask
)
8690 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8691 if (!s
->condexec_mask
)
8695 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
8696 if (!s
->condexec_mask
)
8700 tcg_gen_not_i32(tmp2
, tmp2
);
8701 if (!s
->condexec_mask
)
8709 store_reg(s
, rm
, tmp2
);
8711 tcg_temp_free_i32(tmp
);
8713 store_reg(s
, rd
, tmp
);
8714 tcg_temp_free_i32(tmp2
);
8717 tcg_temp_free_i32(tmp
);
8718 tcg_temp_free_i32(tmp2
);
8723 /* load/store register offset. */
8725 rn
= (insn
>> 3) & 7;
8726 rm
= (insn
>> 6) & 7;
8727 op
= (insn
>> 9) & 7;
8728 addr
= load_reg(s
, rn
);
8729 tmp
= load_reg(s
, rm
);
8730 tcg_gen_add_i32(addr
, addr
, tmp
);
8731 tcg_temp_free_i32(tmp
);
8733 if (op
< 3) /* store */
8734 tmp
= load_reg(s
, rd
);
8738 gen_st32(tmp
, addr
, IS_USER(s
));
8741 gen_st16(tmp
, addr
, IS_USER(s
));
8744 gen_st8(tmp
, addr
, IS_USER(s
));
8747 tmp
= gen_ld8s(addr
, IS_USER(s
));
8750 tmp
= gen_ld32(addr
, IS_USER(s
));
8753 tmp
= gen_ld16u(addr
, IS_USER(s
));
8756 tmp
= gen_ld8u(addr
, IS_USER(s
));
8759 tmp
= gen_ld16s(addr
, IS_USER(s
));
8762 if (op
>= 3) /* load */
8763 store_reg(s
, rd
, tmp
);
8764 tcg_temp_free_i32(addr
);
8768 /* load/store word immediate offset */
8770 rn
= (insn
>> 3) & 7;
8771 addr
= load_reg(s
, rn
);
8772 val
= (insn
>> 4) & 0x7c;
8773 tcg_gen_addi_i32(addr
, addr
, val
);
8775 if (insn
& (1 << 11)) {
8777 tmp
= gen_ld32(addr
, IS_USER(s
));
8778 store_reg(s
, rd
, tmp
);
8781 tmp
= load_reg(s
, rd
);
8782 gen_st32(tmp
, addr
, IS_USER(s
));
8784 tcg_temp_free_i32(addr
);
8788 /* load/store byte immediate offset */
8790 rn
= (insn
>> 3) & 7;
8791 addr
= load_reg(s
, rn
);
8792 val
= (insn
>> 6) & 0x1f;
8793 tcg_gen_addi_i32(addr
, addr
, val
);
8795 if (insn
& (1 << 11)) {
8797 tmp
= gen_ld8u(addr
, IS_USER(s
));
8798 store_reg(s
, rd
, tmp
);
8801 tmp
= load_reg(s
, rd
);
8802 gen_st8(tmp
, addr
, IS_USER(s
));
8804 tcg_temp_free_i32(addr
);
8808 /* load/store halfword immediate offset */
8810 rn
= (insn
>> 3) & 7;
8811 addr
= load_reg(s
, rn
);
8812 val
= (insn
>> 5) & 0x3e;
8813 tcg_gen_addi_i32(addr
, addr
, val
);
8815 if (insn
& (1 << 11)) {
8817 tmp
= gen_ld16u(addr
, IS_USER(s
));
8818 store_reg(s
, rd
, tmp
);
8821 tmp
= load_reg(s
, rd
);
8822 gen_st16(tmp
, addr
, IS_USER(s
));
8824 tcg_temp_free_i32(addr
);
8828 /* load/store from stack */
8829 rd
= (insn
>> 8) & 7;
8830 addr
= load_reg(s
, 13);
8831 val
= (insn
& 0xff) * 4;
8832 tcg_gen_addi_i32(addr
, addr
, val
);
8834 if (insn
& (1 << 11)) {
8836 tmp
= gen_ld32(addr
, IS_USER(s
));
8837 store_reg(s
, rd
, tmp
);
8840 tmp
= load_reg(s
, rd
);
8841 gen_st32(tmp
, addr
, IS_USER(s
));
8843 tcg_temp_free_i32(addr
);
8847 /* add to high reg */
8848 rd
= (insn
>> 8) & 7;
8849 if (insn
& (1 << 11)) {
8851 tmp
= load_reg(s
, 13);
8853 /* PC. bit 1 is ignored. */
8854 tmp
= tcg_temp_new_i32();
8855 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
8857 val
= (insn
& 0xff) * 4;
8858 tcg_gen_addi_i32(tmp
, tmp
, val
);
8859 store_reg(s
, rd
, tmp
);
8864 op
= (insn
>> 8) & 0xf;
8867 /* adjust stack pointer */
8868 tmp
= load_reg(s
, 13);
8869 val
= (insn
& 0x7f) * 4;
8870 if (insn
& (1 << 7))
8871 val
= -(int32_t)val
;
8872 tcg_gen_addi_i32(tmp
, tmp
, val
);
8873 store_reg(s
, 13, tmp
);
8876 case 2: /* sign/zero extend. */
8879 rm
= (insn
>> 3) & 7;
8880 tmp
= load_reg(s
, rm
);
8881 switch ((insn
>> 6) & 3) {
8882 case 0: gen_sxth(tmp
); break;
8883 case 1: gen_sxtb(tmp
); break;
8884 case 2: gen_uxth(tmp
); break;
8885 case 3: gen_uxtb(tmp
); break;
8887 store_reg(s
, rd
, tmp
);
8889 case 4: case 5: case 0xc: case 0xd:
8891 addr
= load_reg(s
, 13);
8892 if (insn
& (1 << 8))
8896 for (i
= 0; i
< 8; i
++) {
8897 if (insn
& (1 << i
))
8900 if ((insn
& (1 << 11)) == 0) {
8901 tcg_gen_addi_i32(addr
, addr
, -offset
);
8903 for (i
= 0; i
< 8; i
++) {
8904 if (insn
& (1 << i
)) {
8905 if (insn
& (1 << 11)) {
8907 tmp
= gen_ld32(addr
, IS_USER(s
));
8908 store_reg(s
, i
, tmp
);
8911 tmp
= load_reg(s
, i
);
8912 gen_st32(tmp
, addr
, IS_USER(s
));
8914 /* advance to the next address. */
8915 tcg_gen_addi_i32(addr
, addr
, 4);
8919 if (insn
& (1 << 8)) {
8920 if (insn
& (1 << 11)) {
8922 tmp
= gen_ld32(addr
, IS_USER(s
));
8923 /* don't set the pc until the rest of the instruction
8927 tmp
= load_reg(s
, 14);
8928 gen_st32(tmp
, addr
, IS_USER(s
));
8930 tcg_gen_addi_i32(addr
, addr
, 4);
8932 if ((insn
& (1 << 11)) == 0) {
8933 tcg_gen_addi_i32(addr
, addr
, -offset
);
8935 /* write back the new stack pointer */
8936 store_reg(s
, 13, addr
);
8937 /* set the new PC value */
8938 if ((insn
& 0x0900) == 0x0900)
8942 case 1: case 3: case 9: case 11: /* czb */
8944 tmp
= load_reg(s
, rm
);
8945 s
->condlabel
= gen_new_label();
8947 if (insn
& (1 << 11))
8948 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
8950 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
8951 tcg_temp_free_i32(tmp
);
8952 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
8953 val
= (uint32_t)s
->pc
+ 2;
8958 case 15: /* IT, nop-hint. */
8959 if ((insn
& 0xf) == 0) {
8960 gen_nop_hint(s
, (insn
>> 4) & 0xf);
8964 s
->condexec_cond
= (insn
>> 4) & 0xe;
8965 s
->condexec_mask
= insn
& 0x1f;
8966 /* No actual code generated for this insn, just setup state. */
8969 case 0xe: /* bkpt */
8970 gen_exception_insn(s
, 2, EXCP_BKPT
);
8975 rn
= (insn
>> 3) & 0x7;
8977 tmp
= load_reg(s
, rn
);
8978 switch ((insn
>> 6) & 3) {
8979 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
8980 case 1: gen_rev16(tmp
); break;
8981 case 3: gen_revsh(tmp
); break;
8982 default: goto illegal_op
;
8984 store_reg(s
, rd
, tmp
);
8992 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
8995 addr
= tcg_const_i32(16);
8996 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8997 tcg_temp_free_i32(addr
);
9001 addr
= tcg_const_i32(17);
9002 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9003 tcg_temp_free_i32(addr
);
9005 tcg_temp_free_i32(tmp
);
9008 if (insn
& (1 << 4))
9009 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
9012 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
9022 /* load/store multiple */
9023 rn
= (insn
>> 8) & 0x7;
9024 addr
= load_reg(s
, rn
);
9025 for (i
= 0; i
< 8; i
++) {
9026 if (insn
& (1 << i
)) {
9027 if (insn
& (1 << 11)) {
9029 tmp
= gen_ld32(addr
, IS_USER(s
));
9030 store_reg(s
, i
, tmp
);
9033 tmp
= load_reg(s
, i
);
9034 gen_st32(tmp
, addr
, IS_USER(s
));
9036 /* advance to the next address */
9037 tcg_gen_addi_i32(addr
, addr
, 4);
9040 /* Base register writeback. */
9041 if ((insn
& (1 << rn
)) == 0) {
9042 store_reg(s
, rn
, addr
);
9044 tcg_temp_free_i32(addr
);
9049 /* conditional branch or swi */
9050 cond
= (insn
>> 8) & 0xf;
9056 gen_set_pc_im(s
->pc
);
9057 s
->is_jmp
= DISAS_SWI
;
9060 /* generate a conditional jump to next instruction */
9061 s
->condlabel
= gen_new_label();
9062 gen_test_cc(cond
^ 1, s
->condlabel
);
9065 /* jump to the offset */
9066 val
= (uint32_t)s
->pc
+ 2;
9067 offset
= ((int32_t)insn
<< 24) >> 24;
9073 if (insn
& (1 << 11)) {
9074 if (disas_thumb2_insn(env
, s
, insn
))
9078 /* unconditional branch */
9079 val
= (uint32_t)s
->pc
;
9080 offset
= ((int32_t)insn
<< 21) >> 21;
9081 val
+= (offset
<< 1) + 2;
9086 if (disas_thumb2_insn(env
, s
, insn
))
9092 gen_exception_insn(s
, 4, EXCP_UDEF
);
9096 gen_exception_insn(s
, 2, EXCP_UDEF
);
9099 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9100 basic block 'tb'. If search_pc is TRUE, also generate PC
9101 information for each intermediate instruction. */
9102 static inline void gen_intermediate_code_internal(CPUState
*env
,
9103 TranslationBlock
*tb
,
9106 DisasContext dc1
, *dc
= &dc1
;
9108 uint16_t *gen_opc_end
;
9110 target_ulong pc_start
;
9111 uint32_t next_page_start
;
9115 /* generate intermediate code */
9120 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9122 dc
->is_jmp
= DISAS_NEXT
;
9124 dc
->singlestep_enabled
= env
->singlestep_enabled
;
9126 dc
->thumb
= ARM_TBFLAG_THUMB(tb
->flags
);
9127 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(tb
->flags
) & 0xf) << 1;
9128 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(tb
->flags
) >> 4;
9129 #if !defined(CONFIG_USER_ONLY)
9130 dc
->user
= (ARM_TBFLAG_PRIV(tb
->flags
) == 0);
9132 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(tb
->flags
);
9133 dc
->vec_len
= ARM_TBFLAG_VECLEN(tb
->flags
);
9134 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(tb
->flags
);
9135 cpu_F0s
= tcg_temp_new_i32();
9136 cpu_F1s
= tcg_temp_new_i32();
9137 cpu_F0d
= tcg_temp_new_i64();
9138 cpu_F1d
= tcg_temp_new_i64();
9141 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9142 cpu_M0
= tcg_temp_new_i64();
9143 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
9146 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9148 max_insns
= CF_COUNT_MASK
;
9152 tcg_clear_temp_count();
9154 /* A note on handling of the condexec (IT) bits:
9156 * We want to avoid the overhead of having to write the updated condexec
9157 * bits back to the CPUState for every instruction in an IT block. So:
9158 * (1) if the condexec bits are not already zero then we write
9159 * zero back into the CPUState now. This avoids complications trying
9160 * to do it at the end of the block. (For example if we don't do this
9161 * it's hard to identify whether we can safely skip writing condexec
9162 * at the end of the TB, which we definitely want to do for the case
9163 * where a TB doesn't do anything with the IT state at all.)
9164 * (2) if we are going to leave the TB then we call gen_set_condexec()
9165 * which will write the correct value into CPUState if zero is wrong.
9166 * This is done both for leaving the TB at the end, and for leaving
9167 * it because of an exception we know will happen, which is done in
9168 * gen_exception_insn(). The latter is necessary because we need to
9169 * leave the TB with the PC/IT state just prior to execution of the
9170 * instruction which caused the exception.
9171 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9172 * then the CPUState will be wrong and we need to reset it.
9173 * This is handled in the same way as restoration of the
9174 * PC in these situations: we will be called again with search_pc=1
9175 * and generate a mapping of the condexec bits for each PC in
9176 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9177 * the condexec bits.
9179 * Note that there are no instructions which can read the condexec
9180 * bits, and none which can write non-static values to them, so
9181 * we don't need to care about whether CPUState is correct in the
9185 /* Reset the conditional execution bits immediately. This avoids
9186 complications trying to do it at the end of the block. */
9187 if (dc
->condexec_mask
|| dc
->condexec_cond
)
9189 TCGv tmp
= tcg_temp_new_i32();
9190 tcg_gen_movi_i32(tmp
, 0);
9191 store_cpu_field(tmp
, condexec_bits
);
9194 #ifdef CONFIG_USER_ONLY
9195 /* Intercept jump to the magic kernel page. */
9196 if (dc
->pc
>= 0xffff0000) {
9197 /* We always get here via a jump, so know we are not in a
9198 conditional execution block. */
9199 gen_exception(EXCP_KERNEL_TRAP
);
9200 dc
->is_jmp
= DISAS_UPDATE
;
9204 if (dc
->pc
>= 0xfffffff0 && IS_M(env
)) {
9205 /* We always get here via a jump, so know we are not in a
9206 conditional execution block. */
9207 gen_exception(EXCP_EXCEPTION_EXIT
);
9208 dc
->is_jmp
= DISAS_UPDATE
;
9213 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9214 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9215 if (bp
->pc
== dc
->pc
) {
9216 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
9217 /* Advance PC so that clearing the breakpoint will
9218 invalidate this TB. */
9220 goto done_generating
;
9226 j
= gen_opc_ptr
- gen_opc_buf
;
9230 gen_opc_instr_start
[lj
++] = 0;
9232 gen_opc_pc
[lj
] = dc
->pc
;
9233 gen_opc_condexec_bits
[lj
] = (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1);
9234 gen_opc_instr_start
[lj
] = 1;
9235 gen_opc_icount
[lj
] = num_insns
;
9238 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9241 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
9242 tcg_gen_debug_insn_start(dc
->pc
);
9246 disas_thumb_insn(env
, dc
);
9247 if (dc
->condexec_mask
) {
9248 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
9249 | ((dc
->condexec_mask
>> 4) & 1);
9250 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
9251 if (dc
->condexec_mask
== 0) {
9252 dc
->condexec_cond
= 0;
9256 disas_arm_insn(env
, dc
);
9259 if (dc
->condjmp
&& !dc
->is_jmp
) {
9260 gen_set_label(dc
->condlabel
);
9264 if (tcg_check_temp_count()) {
9265 fprintf(stderr
, "TCG temporary leak before %08x\n", dc
->pc
);
9268 /* Translation stops when a conditional branch is encountered.
9269 * Otherwise the subsequent code could get translated several times.
9270 * Also stop translation when a page boundary is reached. This
9271 * ensures prefetch aborts occur at the right place. */
9273 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
9274 !env
->singlestep_enabled
&&
9276 dc
->pc
< next_page_start
&&
9277 num_insns
< max_insns
);
9279 if (tb
->cflags
& CF_LAST_IO
) {
9281 /* FIXME: This can theoretically happen with self-modifying
9283 cpu_abort(env
, "IO on conditional branch instruction");
9288 /* At this stage dc->condjmp will only be set when the skipped
9289 instruction was a conditional branch or trap, and the PC has
9290 already been written. */
9291 if (unlikely(env
->singlestep_enabled
)) {
9292 /* Make sure the pc is updated, and raise a debug exception. */
9294 gen_set_condexec(dc
);
9295 if (dc
->is_jmp
== DISAS_SWI
) {
9296 gen_exception(EXCP_SWI
);
9298 gen_exception(EXCP_DEBUG
);
9300 gen_set_label(dc
->condlabel
);
9302 if (dc
->condjmp
|| !dc
->is_jmp
) {
9303 gen_set_pc_im(dc
->pc
);
9306 gen_set_condexec(dc
);
9307 if (dc
->is_jmp
== DISAS_SWI
&& !dc
->condjmp
) {
9308 gen_exception(EXCP_SWI
);
9310 /* FIXME: Single stepping a WFI insn will not halt
9312 gen_exception(EXCP_DEBUG
);
9315 /* While branches must always occur at the end of an IT block,
9316 there are a few other things that can cause us to terminate
9317 the TB in the middel of an IT block:
9318 - Exception generating instructions (bkpt, swi, undefined).
9320 - Hardware watchpoints.
9321 Hardware breakpoints have already been handled and skip this code.
9323 gen_set_condexec(dc
);
9324 switch(dc
->is_jmp
) {
9326 gen_goto_tb(dc
, 1, dc
->pc
);
9331 /* indicate that the hash table must be used to find the next TB */
9335 /* nothing more to generate */
9341 gen_exception(EXCP_SWI
);
9345 gen_set_label(dc
->condlabel
);
9346 gen_set_condexec(dc
);
9347 gen_goto_tb(dc
, 1, dc
->pc
);
9353 gen_icount_end(tb
, num_insns
);
9354 *gen_opc_ptr
= INDEX_op_end
;
9357 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9358 qemu_log("----------------\n");
9359 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9360 log_target_disas(pc_start
, dc
->pc
- pc_start
, dc
->thumb
);
9365 j
= gen_opc_ptr
- gen_opc_buf
;
9368 gen_opc_instr_start
[lj
++] = 0;
9370 tb
->size
= dc
->pc
- pc_start
;
9371 tb
->icount
= num_insns
;
9375 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
9377 gen_intermediate_code_internal(env
, tb
, 0);
9380 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
9382 gen_intermediate_code_internal(env
, tb
, 1);
9385 static const char *cpu_mode_names
[16] = {
9386 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9387 "???", "???", "???", "und", "???", "???", "???", "sys"
9390 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9400 /* ??? This assumes float64 and double have the same layout.
9401 Oh well, it's only debug dumps. */
9410 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
9412 cpu_fprintf(f
, "\n");
9414 cpu_fprintf(f
, " ");
9416 psr
= cpsr_read(env
);
9417 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%d\n",
9419 psr
& (1 << 31) ? 'N' : '-',
9420 psr
& (1 << 30) ? 'Z' : '-',
9421 psr
& (1 << 29) ? 'C' : '-',
9422 psr
& (1 << 28) ? 'V' : '-',
9423 psr
& CPSR_T
? 'T' : 'A',
9424 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
9427 for (i
= 0; i
< 16; i
++) {
9428 d
.d
= env
->vfp
.regs
[i
];
9432 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9433 i
* 2, (int)s0
.i
, s0
.s
,
9434 i
* 2 + 1, (int)s1
.i
, s1
.s
,
9435 i
, (int)(uint32_t)d
.l
.upper
, (int)(uint32_t)d
.l
.lower
,
9438 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
9442 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
9443 unsigned long searched_pc
, int pc_pos
, void *puc
)
9445 env
->regs
[15] = gen_opc_pc
[pc_pos
];
9446 env
->condexec_bits
= gen_opc_condexec_bits
[pc_pos
];