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[qemu.git] / target-arm / translate.c
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
46
47 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
48
49 /* internal defines */
50 typedef struct DisasContext {
51 target_ulong pc;
52 int is_jmp;
53 /* Nonzero if this instruction has been conditionally skipped. */
54 int condjmp;
55 /* The label that will be jumped to when the instruction is skipped. */
56 int condlabel;
57 /* Thumb-2 condtional execution bits. */
58 int condexec_mask;
59 int condexec_cond;
60 struct TranslationBlock *tb;
61 int singlestep_enabled;
62 int thumb;
63 #if !defined(CONFIG_USER_ONLY)
64 int user;
65 #endif
66 int vfp_enabled;
67 int vec_len;
68 int vec_stride;
69 } DisasContext;
70
71 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
72
73 #if defined(CONFIG_USER_ONLY)
74 #define IS_USER(s) 1
75 #else
76 #define IS_USER(s) (s->user)
77 #endif
78
79 /* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
81 #define DISAS_WFI 4
82 #define DISAS_SWI 5
83
84 static TCGv_ptr cpu_env;
85 /* We reuse the same 64-bit temporaries for efficiency. */
86 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
87 static TCGv_i32 cpu_R[16];
88 static TCGv_i32 cpu_exclusive_addr;
89 static TCGv_i32 cpu_exclusive_val;
90 static TCGv_i32 cpu_exclusive_high;
91 #ifdef CONFIG_USER_ONLY
92 static TCGv_i32 cpu_exclusive_test;
93 static TCGv_i32 cpu_exclusive_info;
94 #endif
95
96 /* FIXME: These should be removed. */
97 static TCGv cpu_F0s, cpu_F1s;
98 static TCGv_i64 cpu_F0d, cpu_F1d;
99
100 #include "gen-icount.h"
101
102 static const char *regnames[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
105
106 /* initialize TCG globals. */
107 void arm_translate_init(void)
108 {
109 int i;
110
111 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
112
113 for (i = 0; i < 16; i++) {
114 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, regs[i]),
116 regnames[i]);
117 }
118 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_addr), "exclusive_addr");
120 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, exclusive_val), "exclusive_val");
122 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, exclusive_high), "exclusive_high");
124 #ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
126 offsetof(CPUState, exclusive_test), "exclusive_test");
127 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
128 offsetof(CPUState, exclusive_info), "exclusive_info");
129 #endif
130
131 #define GEN_HELPER 2
132 #include "helpers.h"
133 }
134
135 static inline TCGv load_cpu_offset(int offset)
136 {
137 TCGv tmp = tcg_temp_new_i32();
138 tcg_gen_ld_i32(tmp, cpu_env, offset);
139 return tmp;
140 }
141
142 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
143
144 static inline void store_cpu_offset(TCGv var, int offset)
145 {
146 tcg_gen_st_i32(var, cpu_env, offset);
147 tcg_temp_free_i32(var);
148 }
149
150 #define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
152
153 /* Set a variable to the value of a CPU register. */
154 static void load_reg_var(DisasContext *s, TCGv var, int reg)
155 {
156 if (reg == 15) {
157 uint32_t addr;
158 /* normaly, since we updated PC, we need only to add one insn */
159 if (s->thumb)
160 addr = (long)s->pc + 2;
161 else
162 addr = (long)s->pc + 4;
163 tcg_gen_movi_i32(var, addr);
164 } else {
165 tcg_gen_mov_i32(var, cpu_R[reg]);
166 }
167 }
168
169 /* Create a new temporary and set it to the value of a CPU register. */
170 static inline TCGv load_reg(DisasContext *s, int reg)
171 {
172 TCGv tmp = tcg_temp_new_i32();
173 load_reg_var(s, tmp, reg);
174 return tmp;
175 }
176
177 /* Set a CPU register. The source must be a temporary and will be
178 marked as dead. */
179 static void store_reg(DisasContext *s, int reg, TCGv var)
180 {
181 if (reg == 15) {
182 tcg_gen_andi_i32(var, var, ~1);
183 s->is_jmp = DISAS_JUMP;
184 }
185 tcg_gen_mov_i32(cpu_R[reg], var);
186 tcg_temp_free_i32(var);
187 }
188
189 /* Value extensions. */
190 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
192 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
194
195 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
197
198
199 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
200 {
201 TCGv tmp_mask = tcg_const_i32(mask);
202 gen_helper_cpsr_write(var, tmp_mask);
203 tcg_temp_free_i32(tmp_mask);
204 }
205 /* Set NZCV flags from the high 4 bits of var. */
206 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
207
208 static void gen_exception(int excp)
209 {
210 TCGv tmp = tcg_temp_new_i32();
211 tcg_gen_movi_i32(tmp, excp);
212 gen_helper_exception(tmp);
213 tcg_temp_free_i32(tmp);
214 }
215
216 static void gen_smul_dual(TCGv a, TCGv b)
217 {
218 TCGv tmp1 = tcg_temp_new_i32();
219 TCGv tmp2 = tcg_temp_new_i32();
220 tcg_gen_ext16s_i32(tmp1, a);
221 tcg_gen_ext16s_i32(tmp2, b);
222 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
223 tcg_temp_free_i32(tmp2);
224 tcg_gen_sari_i32(a, a, 16);
225 tcg_gen_sari_i32(b, b, 16);
226 tcg_gen_mul_i32(b, b, a);
227 tcg_gen_mov_i32(a, tmp1);
228 tcg_temp_free_i32(tmp1);
229 }
230
231 /* Byteswap each halfword. */
232 static void gen_rev16(TCGv var)
233 {
234 TCGv tmp = tcg_temp_new_i32();
235 tcg_gen_shri_i32(tmp, var, 8);
236 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
237 tcg_gen_shli_i32(var, var, 8);
238 tcg_gen_andi_i32(var, var, 0xff00ff00);
239 tcg_gen_or_i32(var, var, tmp);
240 tcg_temp_free_i32(tmp);
241 }
242
243 /* Byteswap low halfword and sign extend. */
244 static void gen_revsh(TCGv var)
245 {
246 tcg_gen_ext16u_i32(var, var);
247 tcg_gen_bswap16_i32(var, var);
248 tcg_gen_ext16s_i32(var, var);
249 }
250
251 /* Unsigned bitfield extract. */
252 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
253 {
254 if (shift)
255 tcg_gen_shri_i32(var, var, shift);
256 tcg_gen_andi_i32(var, var, mask);
257 }
258
259 /* Signed bitfield extract. */
260 static void gen_sbfx(TCGv var, int shift, int width)
261 {
262 uint32_t signbit;
263
264 if (shift)
265 tcg_gen_sari_i32(var, var, shift);
266 if (shift + width < 32) {
267 signbit = 1u << (width - 1);
268 tcg_gen_andi_i32(var, var, (1u << width) - 1);
269 tcg_gen_xori_i32(var, var, signbit);
270 tcg_gen_subi_i32(var, var, signbit);
271 }
272 }
273
274 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
275 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
276 {
277 tcg_gen_andi_i32(val, val, mask);
278 tcg_gen_shli_i32(val, val, shift);
279 tcg_gen_andi_i32(base, base, ~(mask << shift));
280 tcg_gen_or_i32(dest, base, val);
281 }
282
283 /* Return (b << 32) + a. Mark inputs as dead */
284 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
285 {
286 TCGv_i64 tmp64 = tcg_temp_new_i64();
287
288 tcg_gen_extu_i32_i64(tmp64, b);
289 tcg_temp_free_i32(b);
290 tcg_gen_shli_i64(tmp64, tmp64, 32);
291 tcg_gen_add_i64(a, tmp64, a);
292
293 tcg_temp_free_i64(tmp64);
294 return a;
295 }
296
297 /* Return (b << 32) - a. Mark inputs as dead. */
298 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
299 {
300 TCGv_i64 tmp64 = tcg_temp_new_i64();
301
302 tcg_gen_extu_i32_i64(tmp64, b);
303 tcg_temp_free_i32(b);
304 tcg_gen_shli_i64(tmp64, tmp64, 32);
305 tcg_gen_sub_i64(a, tmp64, a);
306
307 tcg_temp_free_i64(tmp64);
308 return a;
309 }
310
311 /* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
313 /* 32x32->64 multiply. Marks inputs as dead. */
314 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
315 {
316 TCGv_i64 tmp1 = tcg_temp_new_i64();
317 TCGv_i64 tmp2 = tcg_temp_new_i64();
318
319 tcg_gen_extu_i32_i64(tmp1, a);
320 tcg_temp_free_i32(a);
321 tcg_gen_extu_i32_i64(tmp2, b);
322 tcg_temp_free_i32(b);
323 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
324 tcg_temp_free_i64(tmp2);
325 return tmp1;
326 }
327
328 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
329 {
330 TCGv_i64 tmp1 = tcg_temp_new_i64();
331 TCGv_i64 tmp2 = tcg_temp_new_i64();
332
333 tcg_gen_ext_i32_i64(tmp1, a);
334 tcg_temp_free_i32(a);
335 tcg_gen_ext_i32_i64(tmp2, b);
336 tcg_temp_free_i32(b);
337 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
338 tcg_temp_free_i64(tmp2);
339 return tmp1;
340 }
341
342 /* Swap low and high halfwords. */
343 static void gen_swap_half(TCGv var)
344 {
345 TCGv tmp = tcg_temp_new_i32();
346 tcg_gen_shri_i32(tmp, var, 16);
347 tcg_gen_shli_i32(var, var, 16);
348 tcg_gen_or_i32(var, var, tmp);
349 tcg_temp_free_i32(tmp);
350 }
351
352 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
354 t0 &= ~0x8000;
355 t1 &= ~0x8000;
356 t0 = (t0 + t1) ^ tmp;
357 */
358
359 static void gen_add16(TCGv t0, TCGv t1)
360 {
361 TCGv tmp = tcg_temp_new_i32();
362 tcg_gen_xor_i32(tmp, t0, t1);
363 tcg_gen_andi_i32(tmp, tmp, 0x8000);
364 tcg_gen_andi_i32(t0, t0, ~0x8000);
365 tcg_gen_andi_i32(t1, t1, ~0x8000);
366 tcg_gen_add_i32(t0, t0, t1);
367 tcg_gen_xor_i32(t0, t0, tmp);
368 tcg_temp_free_i32(tmp);
369 tcg_temp_free_i32(t1);
370 }
371
372 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
373
374 /* Set CF to the top bit of var. */
375 static void gen_set_CF_bit31(TCGv var)
376 {
377 TCGv tmp = tcg_temp_new_i32();
378 tcg_gen_shri_i32(tmp, var, 31);
379 gen_set_CF(tmp);
380 tcg_temp_free_i32(tmp);
381 }
382
383 /* Set N and Z flags from var. */
384 static inline void gen_logic_CC(TCGv var)
385 {
386 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
387 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
388 }
389
390 /* T0 += T1 + CF. */
391 static void gen_adc(TCGv t0, TCGv t1)
392 {
393 TCGv tmp;
394 tcg_gen_add_i32(t0, t0, t1);
395 tmp = load_cpu_field(CF);
396 tcg_gen_add_i32(t0, t0, tmp);
397 tcg_temp_free_i32(tmp);
398 }
399
400 /* dest = T0 + T1 + CF. */
401 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
402 {
403 TCGv tmp;
404 tcg_gen_add_i32(dest, t0, t1);
405 tmp = load_cpu_field(CF);
406 tcg_gen_add_i32(dest, dest, tmp);
407 tcg_temp_free_i32(tmp);
408 }
409
410 /* dest = T0 - T1 + CF - 1. */
411 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
412 {
413 TCGv tmp;
414 tcg_gen_sub_i32(dest, t0, t1);
415 tmp = load_cpu_field(CF);
416 tcg_gen_add_i32(dest, dest, tmp);
417 tcg_gen_subi_i32(dest, dest, 1);
418 tcg_temp_free_i32(tmp);
419 }
420
421 /* FIXME: Implement this natively. */
422 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
423
424 static void shifter_out_im(TCGv var, int shift)
425 {
426 TCGv tmp = tcg_temp_new_i32();
427 if (shift == 0) {
428 tcg_gen_andi_i32(tmp, var, 1);
429 } else {
430 tcg_gen_shri_i32(tmp, var, shift);
431 if (shift != 31)
432 tcg_gen_andi_i32(tmp, tmp, 1);
433 }
434 gen_set_CF(tmp);
435 tcg_temp_free_i32(tmp);
436 }
437
438 /* Shift by immediate. Includes special handling for shift == 0. */
439 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
440 {
441 switch (shiftop) {
442 case 0: /* LSL */
443 if (shift != 0) {
444 if (flags)
445 shifter_out_im(var, 32 - shift);
446 tcg_gen_shli_i32(var, var, shift);
447 }
448 break;
449 case 1: /* LSR */
450 if (shift == 0) {
451 if (flags) {
452 tcg_gen_shri_i32(var, var, 31);
453 gen_set_CF(var);
454 }
455 tcg_gen_movi_i32(var, 0);
456 } else {
457 if (flags)
458 shifter_out_im(var, shift - 1);
459 tcg_gen_shri_i32(var, var, shift);
460 }
461 break;
462 case 2: /* ASR */
463 if (shift == 0)
464 shift = 32;
465 if (flags)
466 shifter_out_im(var, shift - 1);
467 if (shift == 32)
468 shift = 31;
469 tcg_gen_sari_i32(var, var, shift);
470 break;
471 case 3: /* ROR/RRX */
472 if (shift != 0) {
473 if (flags)
474 shifter_out_im(var, shift - 1);
475 tcg_gen_rotri_i32(var, var, shift); break;
476 } else {
477 TCGv tmp = load_cpu_field(CF);
478 if (flags)
479 shifter_out_im(var, 0);
480 tcg_gen_shri_i32(var, var, 1);
481 tcg_gen_shli_i32(tmp, tmp, 31);
482 tcg_gen_or_i32(var, var, tmp);
483 tcg_temp_free_i32(tmp);
484 }
485 }
486 };
487
488 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
489 TCGv shift, int flags)
490 {
491 if (flags) {
492 switch (shiftop) {
493 case 0: gen_helper_shl_cc(var, var, shift); break;
494 case 1: gen_helper_shr_cc(var, var, shift); break;
495 case 2: gen_helper_sar_cc(var, var, shift); break;
496 case 3: gen_helper_ror_cc(var, var, shift); break;
497 }
498 } else {
499 switch (shiftop) {
500 case 0: gen_helper_shl(var, var, shift); break;
501 case 1: gen_helper_shr(var, var, shift); break;
502 case 2: gen_helper_sar(var, var, shift); break;
503 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
504 tcg_gen_rotr_i32(var, var, shift); break;
505 }
506 }
507 tcg_temp_free_i32(shift);
508 }
509
510 #define PAS_OP(pfx) \
511 switch (op2) { \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
518 }
519 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
520 {
521 TCGv_ptr tmp;
522
523 switch (op1) {
524 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
525 case 1:
526 tmp = tcg_temp_new_ptr();
527 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
528 PAS_OP(s)
529 tcg_temp_free_ptr(tmp);
530 break;
531 case 5:
532 tmp = tcg_temp_new_ptr();
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(u)
535 tcg_temp_free_ptr(tmp);
536 break;
537 #undef gen_pas_helper
538 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
539 case 2:
540 PAS_OP(q);
541 break;
542 case 3:
543 PAS_OP(sh);
544 break;
545 case 6:
546 PAS_OP(uq);
547 break;
548 case 7:
549 PAS_OP(uh);
550 break;
551 #undef gen_pas_helper
552 }
553 }
554 #undef PAS_OP
555
556 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557 #define PAS_OP(pfx) \
558 switch (op1) { \
559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
565 }
566 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
567 {
568 TCGv_ptr tmp;
569
570 switch (op2) {
571 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
572 case 0:
573 tmp = tcg_temp_new_ptr();
574 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
575 PAS_OP(s)
576 tcg_temp_free_ptr(tmp);
577 break;
578 case 4:
579 tmp = tcg_temp_new_ptr();
580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(u)
582 tcg_temp_free_ptr(tmp);
583 break;
584 #undef gen_pas_helper
585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
586 case 1:
587 PAS_OP(q);
588 break;
589 case 2:
590 PAS_OP(sh);
591 break;
592 case 5:
593 PAS_OP(uq);
594 break;
595 case 6:
596 PAS_OP(uh);
597 break;
598 #undef gen_pas_helper
599 }
600 }
601 #undef PAS_OP
602
603 static void gen_test_cc(int cc, int label)
604 {
605 TCGv tmp;
606 TCGv tmp2;
607 int inv;
608
609 switch (cc) {
610 case 0: /* eq: Z */
611 tmp = load_cpu_field(ZF);
612 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
613 break;
614 case 1: /* ne: !Z */
615 tmp = load_cpu_field(ZF);
616 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
617 break;
618 case 2: /* cs: C */
619 tmp = load_cpu_field(CF);
620 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
621 break;
622 case 3: /* cc: !C */
623 tmp = load_cpu_field(CF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 4: /* mi: N */
627 tmp = load_cpu_field(NF);
628 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
629 break;
630 case 5: /* pl: !N */
631 tmp = load_cpu_field(NF);
632 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
633 break;
634 case 6: /* vs: V */
635 tmp = load_cpu_field(VF);
636 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
637 break;
638 case 7: /* vc: !V */
639 tmp = load_cpu_field(VF);
640 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
641 break;
642 case 8: /* hi: C && !Z */
643 inv = gen_new_label();
644 tmp = load_cpu_field(CF);
645 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
646 tcg_temp_free_i32(tmp);
647 tmp = load_cpu_field(ZF);
648 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
649 gen_set_label(inv);
650 break;
651 case 9: /* ls: !C || Z */
652 tmp = load_cpu_field(CF);
653 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
654 tcg_temp_free_i32(tmp);
655 tmp = load_cpu_field(ZF);
656 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
657 break;
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp = load_cpu_field(VF);
660 tmp2 = load_cpu_field(NF);
661 tcg_gen_xor_i32(tmp, tmp, tmp2);
662 tcg_temp_free_i32(tmp2);
663 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
664 break;
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp = load_cpu_field(VF);
667 tmp2 = load_cpu_field(NF);
668 tcg_gen_xor_i32(tmp, tmp, tmp2);
669 tcg_temp_free_i32(tmp2);
670 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
671 break;
672 case 12: /* gt: !Z && N == V */
673 inv = gen_new_label();
674 tmp = load_cpu_field(ZF);
675 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
676 tcg_temp_free_i32(tmp);
677 tmp = load_cpu_field(VF);
678 tmp2 = load_cpu_field(NF);
679 tcg_gen_xor_i32(tmp, tmp, tmp2);
680 tcg_temp_free_i32(tmp2);
681 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
682 gen_set_label(inv);
683 break;
684 case 13: /* le: Z || N != V */
685 tmp = load_cpu_field(ZF);
686 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
687 tcg_temp_free_i32(tmp);
688 tmp = load_cpu_field(VF);
689 tmp2 = load_cpu_field(NF);
690 tcg_gen_xor_i32(tmp, tmp, tmp2);
691 tcg_temp_free_i32(tmp2);
692 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
693 break;
694 default:
695 fprintf(stderr, "Bad condition code 0x%x\n", cc);
696 abort();
697 }
698 tcg_temp_free_i32(tmp);
699 }
700
701 static const uint8_t table_logic_cc[16] = {
702 1, /* and */
703 1, /* xor */
704 0, /* sub */
705 0, /* rsb */
706 0, /* add */
707 0, /* adc */
708 0, /* sbc */
709 0, /* rsc */
710 1, /* andl */
711 1, /* xorl */
712 0, /* cmp */
713 0, /* cmn */
714 1, /* orr */
715 1, /* mov */
716 1, /* bic */
717 1, /* mvn */
718 };
719
720 /* Set PC and Thumb state from an immediate address. */
721 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
722 {
723 TCGv tmp;
724
725 s->is_jmp = DISAS_UPDATE;
726 if (s->thumb != (addr & 1)) {
727 tmp = tcg_temp_new_i32();
728 tcg_gen_movi_i32(tmp, addr & 1);
729 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
730 tcg_temp_free_i32(tmp);
731 }
732 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
733 }
734
735 /* Set PC and Thumb state from var. var is marked as dead. */
736 static inline void gen_bx(DisasContext *s, TCGv var)
737 {
738 s->is_jmp = DISAS_UPDATE;
739 tcg_gen_andi_i32(cpu_R[15], var, ~1);
740 tcg_gen_andi_i32(var, var, 1);
741 store_cpu_field(var, thumb);
742 }
743
744 /* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747 static inline void store_reg_bx(CPUState *env, DisasContext *s,
748 int reg, TCGv var)
749 {
750 if (reg == 15 && ENABLE_ARCH_7) {
751 gen_bx(s, var);
752 } else {
753 store_reg(s, reg, var);
754 }
755 }
756
757 /* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761 static inline void store_reg_from_load(CPUState *env, DisasContext *s,
762 int reg, TCGv var)
763 {
764 if (reg == 15 && ENABLE_ARCH_5) {
765 gen_bx(s, var);
766 } else {
767 store_reg(s, reg, var);
768 }
769 }
770
771 static inline TCGv gen_ld8s(TCGv addr, int index)
772 {
773 TCGv tmp = tcg_temp_new_i32();
774 tcg_gen_qemu_ld8s(tmp, addr, index);
775 return tmp;
776 }
777 static inline TCGv gen_ld8u(TCGv addr, int index)
778 {
779 TCGv tmp = tcg_temp_new_i32();
780 tcg_gen_qemu_ld8u(tmp, addr, index);
781 return tmp;
782 }
783 static inline TCGv gen_ld16s(TCGv addr, int index)
784 {
785 TCGv tmp = tcg_temp_new_i32();
786 tcg_gen_qemu_ld16s(tmp, addr, index);
787 return tmp;
788 }
789 static inline TCGv gen_ld16u(TCGv addr, int index)
790 {
791 TCGv tmp = tcg_temp_new_i32();
792 tcg_gen_qemu_ld16u(tmp, addr, index);
793 return tmp;
794 }
795 static inline TCGv gen_ld32(TCGv addr, int index)
796 {
797 TCGv tmp = tcg_temp_new_i32();
798 tcg_gen_qemu_ld32u(tmp, addr, index);
799 return tmp;
800 }
801 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
802 {
803 TCGv_i64 tmp = tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp, addr, index);
805 return tmp;
806 }
807 static inline void gen_st8(TCGv val, TCGv addr, int index)
808 {
809 tcg_gen_qemu_st8(val, addr, index);
810 tcg_temp_free_i32(val);
811 }
812 static inline void gen_st16(TCGv val, TCGv addr, int index)
813 {
814 tcg_gen_qemu_st16(val, addr, index);
815 tcg_temp_free_i32(val);
816 }
817 static inline void gen_st32(TCGv val, TCGv addr, int index)
818 {
819 tcg_gen_qemu_st32(val, addr, index);
820 tcg_temp_free_i32(val);
821 }
822 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
823 {
824 tcg_gen_qemu_st64(val, addr, index);
825 tcg_temp_free_i64(val);
826 }
827
828 static inline void gen_set_pc_im(uint32_t val)
829 {
830 tcg_gen_movi_i32(cpu_R[15], val);
831 }
832
833 /* Force a TB lookup after an instruction that changes the CPU state. */
834 static inline void gen_lookup_tb(DisasContext *s)
835 {
836 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
837 s->is_jmp = DISAS_UPDATE;
838 }
839
840 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
841 TCGv var)
842 {
843 int val, rm, shift, shiftop;
844 TCGv offset;
845
846 if (!(insn & (1 << 25))) {
847 /* immediate */
848 val = insn & 0xfff;
849 if (!(insn & (1 << 23)))
850 val = -val;
851 if (val != 0)
852 tcg_gen_addi_i32(var, var, val);
853 } else {
854 /* shift/register */
855 rm = (insn) & 0xf;
856 shift = (insn >> 7) & 0x1f;
857 shiftop = (insn >> 5) & 3;
858 offset = load_reg(s, rm);
859 gen_arm_shift_im(offset, shiftop, shift, 0);
860 if (!(insn & (1 << 23)))
861 tcg_gen_sub_i32(var, var, offset);
862 else
863 tcg_gen_add_i32(var, var, offset);
864 tcg_temp_free_i32(offset);
865 }
866 }
867
868 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
869 int extra, TCGv var)
870 {
871 int val, rm;
872 TCGv offset;
873
874 if (insn & (1 << 22)) {
875 /* immediate */
876 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
877 if (!(insn & (1 << 23)))
878 val = -val;
879 val += extra;
880 if (val != 0)
881 tcg_gen_addi_i32(var, var, val);
882 } else {
883 /* register */
884 if (extra)
885 tcg_gen_addi_i32(var, var, extra);
886 rm = (insn) & 0xf;
887 offset = load_reg(s, rm);
888 if (!(insn & (1 << 23)))
889 tcg_gen_sub_i32(var, var, offset);
890 else
891 tcg_gen_add_i32(var, var, offset);
892 tcg_temp_free_i32(offset);
893 }
894 }
895
896 #define VFP_OP2(name) \
897 static inline void gen_vfp_##name(int dp) \
898 { \
899 if (dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
901 else \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
903 }
904
905 VFP_OP2(add)
906 VFP_OP2(sub)
907 VFP_OP2(mul)
908 VFP_OP2(div)
909
910 #undef VFP_OP2
911
912 static inline void gen_vfp_abs(int dp)
913 {
914 if (dp)
915 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
918 }
919
920 static inline void gen_vfp_neg(int dp)
921 {
922 if (dp)
923 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
924 else
925 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
926 }
927
928 static inline void gen_vfp_sqrt(int dp)
929 {
930 if (dp)
931 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
932 else
933 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
934 }
935
936 static inline void gen_vfp_cmp(int dp)
937 {
938 if (dp)
939 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
942 }
943
944 static inline void gen_vfp_cmpe(int dp)
945 {
946 if (dp)
947 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
948 else
949 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
950 }
951
952 static inline void gen_vfp_F1_ld0(int dp)
953 {
954 if (dp)
955 tcg_gen_movi_i64(cpu_F1d, 0);
956 else
957 tcg_gen_movi_i32(cpu_F1s, 0);
958 }
959
960 static inline void gen_vfp_uito(int dp)
961 {
962 if (dp)
963 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
964 else
965 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
966 }
967
968 static inline void gen_vfp_sito(int dp)
969 {
970 if (dp)
971 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
972 else
973 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
974 }
975
976 static inline void gen_vfp_toui(int dp)
977 {
978 if (dp)
979 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
982 }
983
984 static inline void gen_vfp_touiz(int dp)
985 {
986 if (dp)
987 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
990 }
991
992 static inline void gen_vfp_tosi(int dp)
993 {
994 if (dp)
995 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
996 else
997 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
998 }
999
1000 static inline void gen_vfp_tosiz(int dp)
1001 {
1002 if (dp)
1003 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1004 else
1005 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1006 }
1007
1008 #define VFP_GEN_FIX(name) \
1009 static inline void gen_vfp_##name(int dp, int shift) \
1010 { \
1011 TCGv tmp_shift = tcg_const_i32(shift); \
1012 if (dp) \
1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1014 else \
1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
1017 }
1018 VFP_GEN_FIX(tosh)
1019 VFP_GEN_FIX(tosl)
1020 VFP_GEN_FIX(touh)
1021 VFP_GEN_FIX(toul)
1022 VFP_GEN_FIX(shto)
1023 VFP_GEN_FIX(slto)
1024 VFP_GEN_FIX(uhto)
1025 VFP_GEN_FIX(ulto)
1026 #undef VFP_GEN_FIX
1027
1028 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1029 {
1030 if (dp)
1031 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1032 else
1033 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1034 }
1035
1036 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1037 {
1038 if (dp)
1039 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1040 else
1041 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1042 }
1043
1044 static inline long
1045 vfp_reg_offset (int dp, int reg)
1046 {
1047 if (dp)
1048 return offsetof(CPUARMState, vfp.regs[reg]);
1049 else if (reg & 1) {
1050 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1051 + offsetof(CPU_DoubleU, l.upper);
1052 } else {
1053 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1054 + offsetof(CPU_DoubleU, l.lower);
1055 }
1056 }
1057
1058 /* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1060 static inline long
1061 neon_reg_offset (int reg, int n)
1062 {
1063 int sreg;
1064 sreg = reg * 2 + n;
1065 return vfp_reg_offset(0, sreg);
1066 }
1067
1068 static TCGv neon_load_reg(int reg, int pass)
1069 {
1070 TCGv tmp = tcg_temp_new_i32();
1071 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1072 return tmp;
1073 }
1074
1075 static void neon_store_reg(int reg, int pass, TCGv var)
1076 {
1077 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1078 tcg_temp_free_i32(var);
1079 }
1080
1081 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1082 {
1083 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1084 }
1085
1086 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1087 {
1088 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1089 }
1090
1091 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1092 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1093 #define tcg_gen_st_f32 tcg_gen_st_i32
1094 #define tcg_gen_st_f64 tcg_gen_st_i64
1095
1096 static inline void gen_mov_F0_vreg(int dp, int reg)
1097 {
1098 if (dp)
1099 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1100 else
1101 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1102 }
1103
1104 static inline void gen_mov_F1_vreg(int dp, int reg)
1105 {
1106 if (dp)
1107 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1108 else
1109 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1110 }
1111
1112 static inline void gen_mov_vreg_F0(int dp, int reg)
1113 {
1114 if (dp)
1115 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1116 else
1117 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1118 }
1119
1120 #define ARM_CP_RW_BIT (1 << 20)
1121
1122 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1123 {
1124 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1125 }
1126
1127 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1128 {
1129 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1130 }
1131
1132 static inline TCGv iwmmxt_load_creg(int reg)
1133 {
1134 TCGv var = tcg_temp_new_i32();
1135 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1136 return var;
1137 }
1138
1139 static inline void iwmmxt_store_creg(int reg, TCGv var)
1140 {
1141 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1142 tcg_temp_free_i32(var);
1143 }
1144
1145 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1146 {
1147 iwmmxt_store_reg(cpu_M0, rn);
1148 }
1149
1150 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1151 {
1152 iwmmxt_load_reg(cpu_M0, rn);
1153 }
1154
1155 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1156 {
1157 iwmmxt_load_reg(cpu_V1, rn);
1158 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1159 }
1160
1161 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1162 {
1163 iwmmxt_load_reg(cpu_V1, rn);
1164 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1165 }
1166
1167 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1168 {
1169 iwmmxt_load_reg(cpu_V1, rn);
1170 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1171 }
1172
1173 #define IWMMXT_OP(name) \
1174 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1175 { \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1178 }
1179
1180 #define IWMMXT_OP_SIZE(name) \
1181 IWMMXT_OP(name##b) \
1182 IWMMXT_OP(name##w) \
1183 IWMMXT_OP(name##l)
1184
1185 #define IWMMXT_OP_1(name) \
1186 static inline void gen_op_iwmmxt_##name##_M0(void) \
1187 { \
1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
1189 }
1190
1191 IWMMXT_OP(maddsq)
1192 IWMMXT_OP(madduq)
1193 IWMMXT_OP(sadb)
1194 IWMMXT_OP(sadw)
1195 IWMMXT_OP(mulslw)
1196 IWMMXT_OP(mulshw)
1197 IWMMXT_OP(mululw)
1198 IWMMXT_OP(muluhw)
1199 IWMMXT_OP(macsw)
1200 IWMMXT_OP(macuw)
1201
1202 IWMMXT_OP_SIZE(unpackl)
1203 IWMMXT_OP_SIZE(unpackh)
1204
1205 IWMMXT_OP_1(unpacklub)
1206 IWMMXT_OP_1(unpackluw)
1207 IWMMXT_OP_1(unpacklul)
1208 IWMMXT_OP_1(unpackhub)
1209 IWMMXT_OP_1(unpackhuw)
1210 IWMMXT_OP_1(unpackhul)
1211 IWMMXT_OP_1(unpacklsb)
1212 IWMMXT_OP_1(unpacklsw)
1213 IWMMXT_OP_1(unpacklsl)
1214 IWMMXT_OP_1(unpackhsb)
1215 IWMMXT_OP_1(unpackhsw)
1216 IWMMXT_OP_1(unpackhsl)
1217
1218 IWMMXT_OP_SIZE(cmpeq)
1219 IWMMXT_OP_SIZE(cmpgtu)
1220 IWMMXT_OP_SIZE(cmpgts)
1221
1222 IWMMXT_OP_SIZE(mins)
1223 IWMMXT_OP_SIZE(minu)
1224 IWMMXT_OP_SIZE(maxs)
1225 IWMMXT_OP_SIZE(maxu)
1226
1227 IWMMXT_OP_SIZE(subn)
1228 IWMMXT_OP_SIZE(addn)
1229 IWMMXT_OP_SIZE(subu)
1230 IWMMXT_OP_SIZE(addu)
1231 IWMMXT_OP_SIZE(subs)
1232 IWMMXT_OP_SIZE(adds)
1233
1234 IWMMXT_OP(avgb0)
1235 IWMMXT_OP(avgb1)
1236 IWMMXT_OP(avgw0)
1237 IWMMXT_OP(avgw1)
1238
1239 IWMMXT_OP(msadb)
1240
1241 IWMMXT_OP(packuw)
1242 IWMMXT_OP(packul)
1243 IWMMXT_OP(packuq)
1244 IWMMXT_OP(packsw)
1245 IWMMXT_OP(packsl)
1246 IWMMXT_OP(packsq)
1247
1248 static void gen_op_iwmmxt_set_mup(void)
1249 {
1250 TCGv tmp;
1251 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1252 tcg_gen_ori_i32(tmp, tmp, 2);
1253 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1254 }
1255
1256 static void gen_op_iwmmxt_set_cup(void)
1257 {
1258 TCGv tmp;
1259 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1260 tcg_gen_ori_i32(tmp, tmp, 1);
1261 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1262 }
1263
1264 static void gen_op_iwmmxt_setpsr_nz(void)
1265 {
1266 TCGv tmp = tcg_temp_new_i32();
1267 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1268 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1269 }
1270
1271 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1272 {
1273 iwmmxt_load_reg(cpu_V1, rn);
1274 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1275 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1276 }
1277
1278 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1279 {
1280 int rd;
1281 uint32_t offset;
1282 TCGv tmp;
1283
1284 rd = (insn >> 16) & 0xf;
1285 tmp = load_reg(s, rd);
1286
1287 offset = (insn & 0xff) << ((insn >> 7) & 2);
1288 if (insn & (1 << 24)) {
1289 /* Pre indexed */
1290 if (insn & (1 << 23))
1291 tcg_gen_addi_i32(tmp, tmp, offset);
1292 else
1293 tcg_gen_addi_i32(tmp, tmp, -offset);
1294 tcg_gen_mov_i32(dest, tmp);
1295 if (insn & (1 << 21))
1296 store_reg(s, rd, tmp);
1297 else
1298 tcg_temp_free_i32(tmp);
1299 } else if (insn & (1 << 21)) {
1300 /* Post indexed */
1301 tcg_gen_mov_i32(dest, tmp);
1302 if (insn & (1 << 23))
1303 tcg_gen_addi_i32(tmp, tmp, offset);
1304 else
1305 tcg_gen_addi_i32(tmp, tmp, -offset);
1306 store_reg(s, rd, tmp);
1307 } else if (!(insn & (1 << 23)))
1308 return 1;
1309 return 0;
1310 }
1311
1312 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1313 {
1314 int rd = (insn >> 0) & 0xf;
1315 TCGv tmp;
1316
1317 if (insn & (1 << 8)) {
1318 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1319 return 1;
1320 } else {
1321 tmp = iwmmxt_load_creg(rd);
1322 }
1323 } else {
1324 tmp = tcg_temp_new_i32();
1325 iwmmxt_load_reg(cpu_V0, rd);
1326 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1327 }
1328 tcg_gen_andi_i32(tmp, tmp, mask);
1329 tcg_gen_mov_i32(dest, tmp);
1330 tcg_temp_free_i32(tmp);
1331 return 0;
1332 }
1333
1334 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1337 {
1338 int rd, wrd;
1339 int rdhi, rdlo, rd0, rd1, i;
1340 TCGv addr;
1341 TCGv tmp, tmp2, tmp3;
1342
1343 if ((insn & 0x0e000e00) == 0x0c000000) {
1344 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1345 wrd = insn & 0xf;
1346 rdlo = (insn >> 12) & 0xf;
1347 rdhi = (insn >> 16) & 0xf;
1348 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1349 iwmmxt_load_reg(cpu_V0, wrd);
1350 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1351 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1353 } else { /* TMCRR */
1354 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1355 iwmmxt_store_reg(cpu_V0, wrd);
1356 gen_op_iwmmxt_set_mup();
1357 }
1358 return 0;
1359 }
1360
1361 wrd = (insn >> 12) & 0xf;
1362 addr = tcg_temp_new_i32();
1363 if (gen_iwmmxt_address(s, insn, addr)) {
1364 tcg_temp_free_i32(addr);
1365 return 1;
1366 }
1367 if (insn & ARM_CP_RW_BIT) {
1368 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1369 tmp = tcg_temp_new_i32();
1370 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1371 iwmmxt_store_creg(wrd, tmp);
1372 } else {
1373 i = 1;
1374 if (insn & (1 << 8)) {
1375 if (insn & (1 << 22)) { /* WLDRD */
1376 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1377 i = 0;
1378 } else { /* WLDRW wRd */
1379 tmp = gen_ld32(addr, IS_USER(s));
1380 }
1381 } else {
1382 if (insn & (1 << 22)) { /* WLDRH */
1383 tmp = gen_ld16u(addr, IS_USER(s));
1384 } else { /* WLDRB */
1385 tmp = gen_ld8u(addr, IS_USER(s));
1386 }
1387 }
1388 if (i) {
1389 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1390 tcg_temp_free_i32(tmp);
1391 }
1392 gen_op_iwmmxt_movq_wRn_M0(wrd);
1393 }
1394 } else {
1395 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1396 tmp = iwmmxt_load_creg(wrd);
1397 gen_st32(tmp, addr, IS_USER(s));
1398 } else {
1399 gen_op_iwmmxt_movq_M0_wRn(wrd);
1400 tmp = tcg_temp_new_i32();
1401 if (insn & (1 << 8)) {
1402 if (insn & (1 << 22)) { /* WSTRD */
1403 tcg_temp_free_i32(tmp);
1404 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1407 gen_st32(tmp, addr, IS_USER(s));
1408 }
1409 } else {
1410 if (insn & (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st16(tmp, addr, IS_USER(s));
1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1415 gen_st8(tmp, addr, IS_USER(s));
1416 }
1417 }
1418 }
1419 }
1420 tcg_temp_free_i32(addr);
1421 return 0;
1422 }
1423
1424 if ((insn & 0x0f000000) != 0x0e000000)
1425 return 1;
1426
1427 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd = (insn >> 12) & 0xf;
1430 rd0 = (insn >> 0) & 0xf;
1431 rd1 = (insn >> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1438 break;
1439 case 0x011: /* TMCR */
1440 if (insn & 0xf)
1441 return 1;
1442 rd = (insn >> 12) & 0xf;
1443 wrd = (insn >> 16) & 0xf;
1444 switch (wrd) {
1445 case ARM_IWMMXT_wCID:
1446 case ARM_IWMMXT_wCASF:
1447 break;
1448 case ARM_IWMMXT_wCon:
1449 gen_op_iwmmxt_set_cup();
1450 /* Fall through. */
1451 case ARM_IWMMXT_wCSSF:
1452 tmp = iwmmxt_load_creg(wrd);
1453 tmp2 = load_reg(s, rd);
1454 tcg_gen_andc_i32(tmp, tmp, tmp2);
1455 tcg_temp_free_i32(tmp2);
1456 iwmmxt_store_creg(wrd, tmp);
1457 break;
1458 case ARM_IWMMXT_wCGR0:
1459 case ARM_IWMMXT_wCGR1:
1460 case ARM_IWMMXT_wCGR2:
1461 case ARM_IWMMXT_wCGR3:
1462 gen_op_iwmmxt_set_cup();
1463 tmp = load_reg(s, rd);
1464 iwmmxt_store_creg(wrd, tmp);
1465 break;
1466 default:
1467 return 1;
1468 }
1469 break;
1470 case 0x100: /* WXOR */
1471 wrd = (insn >> 12) & 0xf;
1472 rd0 = (insn >> 0) & 0xf;
1473 rd1 = (insn >> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1480 break;
1481 case 0x111: /* TMRC */
1482 if (insn & 0xf)
1483 return 1;
1484 rd = (insn >> 12) & 0xf;
1485 wrd = (insn >> 16) & 0xf;
1486 tmp = iwmmxt_load_creg(wrd);
1487 store_reg(s, rd, tmp);
1488 break;
1489 case 0x300: /* WANDN */
1490 wrd = (insn >> 12) & 0xf;
1491 rd0 = (insn >> 0) & 0xf;
1492 rd1 = (insn >> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0);
1494 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1500 break;
1501 case 0x200: /* WAND */
1502 wrd = (insn >> 12) & 0xf;
1503 rd0 = (insn >> 0) & 0xf;
1504 rd1 = (insn >> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1511 break;
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd = (insn >> 12) & 0xf;
1514 rd0 = (insn >> 0) & 0xf;
1515 rd1 = (insn >> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0);
1517 if (insn & (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1519 else
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd);
1522 gen_op_iwmmxt_set_mup();
1523 break;
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd = (insn >> 12) & 0xf;
1526 rd0 = (insn >> 16) & 0xf;
1527 rd1 = (insn >> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0);
1529 switch ((insn >> 22) & 3) {
1530 case 0:
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1532 break;
1533 case 1:
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1535 break;
1536 case 2:
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1538 break;
1539 case 3:
1540 return 1;
1541 }
1542 gen_op_iwmmxt_movq_wRn_M0(wrd);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1545 break;
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd = (insn >> 12) & 0xf;
1548 rd0 = (insn >> 16) & 0xf;
1549 rd1 = (insn >> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0);
1551 switch ((insn >> 22) & 3) {
1552 case 0:
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1554 break;
1555 case 1:
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1557 break;
1558 case 2:
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1560 break;
1561 case 3:
1562 return 1;
1563 }
1564 gen_op_iwmmxt_movq_wRn_M0(wrd);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1567 break;
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd = (insn >> 12) & 0xf;
1570 rd0 = (insn >> 16) & 0xf;
1571 rd1 = (insn >> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0);
1573 if (insn & (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1575 else
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1577 if (!(insn & (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd);
1580 gen_op_iwmmxt_set_mup();
1581 break;
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd = (insn >> 12) & 0xf;
1584 rd0 = (insn >> 16) & 0xf;
1585 rd1 = (insn >> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0);
1587 if (insn & (1 << 21)) {
1588 if (insn & (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1590 else
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1592 } else {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1597 }
1598 gen_op_iwmmxt_movq_wRn_M0(wrd);
1599 gen_op_iwmmxt_set_mup();
1600 break;
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd = (insn >> 12) & 0xf;
1603 rd0 = (insn >> 16) & 0xf;
1604 rd1 = (insn >> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0);
1606 if (insn & (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1608 else
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1610 if (!(insn & (1 << 20))) {
1611 iwmmxt_load_reg(cpu_V1, wrd);
1612 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1613 }
1614 gen_op_iwmmxt_movq_wRn_M0(wrd);
1615 gen_op_iwmmxt_set_mup();
1616 break;
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd = (insn >> 12) & 0xf;
1619 rd0 = (insn >> 16) & 0xf;
1620 rd1 = (insn >> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0);
1622 switch ((insn >> 22) & 3) {
1623 case 0:
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1625 break;
1626 case 1:
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1628 break;
1629 case 2:
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1631 break;
1632 case 3:
1633 return 1;
1634 }
1635 gen_op_iwmmxt_movq_wRn_M0(wrd);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1638 break;
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd = (insn >> 12) & 0xf;
1641 rd0 = (insn >> 16) & 0xf;
1642 rd1 = (insn >> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0);
1644 if (insn & (1 << 22)) {
1645 if (insn & (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1647 else
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1649 } else {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1654 }
1655 gen_op_iwmmxt_movq_wRn_M0(wrd);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1658 break;
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd = (insn >> 12) & 0xf;
1661 rd0 = (insn >> 16) & 0xf;
1662 rd1 = (insn >> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0);
1664 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1665 tcg_gen_andi_i32(tmp, tmp, 7);
1666 iwmmxt_load_reg(cpu_V1, rd1);
1667 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1668 tcg_temp_free_i32(tmp);
1669 gen_op_iwmmxt_movq_wRn_M0(wrd);
1670 gen_op_iwmmxt_set_mup();
1671 break;
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1673 if (((insn >> 6) & 3) == 3)
1674 return 1;
1675 rd = (insn >> 12) & 0xf;
1676 wrd = (insn >> 16) & 0xf;
1677 tmp = load_reg(s, rd);
1678 gen_op_iwmmxt_movq_M0_wRn(wrd);
1679 switch ((insn >> 6) & 3) {
1680 case 0:
1681 tmp2 = tcg_const_i32(0xff);
1682 tmp3 = tcg_const_i32((insn & 7) << 3);
1683 break;
1684 case 1:
1685 tmp2 = tcg_const_i32(0xffff);
1686 tmp3 = tcg_const_i32((insn & 3) << 4);
1687 break;
1688 case 2:
1689 tmp2 = tcg_const_i32(0xffffffff);
1690 tmp3 = tcg_const_i32((insn & 1) << 5);
1691 break;
1692 default:
1693 TCGV_UNUSED(tmp2);
1694 TCGV_UNUSED(tmp3);
1695 }
1696 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1697 tcg_temp_free(tmp3);
1698 tcg_temp_free(tmp2);
1699 tcg_temp_free_i32(tmp);
1700 gen_op_iwmmxt_movq_wRn_M0(wrd);
1701 gen_op_iwmmxt_set_mup();
1702 break;
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd = (insn >> 12) & 0xf;
1705 wrd = (insn >> 16) & 0xf;
1706 if (rd == 15 || ((insn >> 22) & 3) == 3)
1707 return 1;
1708 gen_op_iwmmxt_movq_M0_wRn(wrd);
1709 tmp = tcg_temp_new_i32();
1710 switch ((insn >> 22) & 3) {
1711 case 0:
1712 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1714 if (insn & 8) {
1715 tcg_gen_ext8s_i32(tmp, tmp);
1716 } else {
1717 tcg_gen_andi_i32(tmp, tmp, 0xff);
1718 }
1719 break;
1720 case 1:
1721 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1723 if (insn & 8) {
1724 tcg_gen_ext16s_i32(tmp, tmp);
1725 } else {
1726 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1727 }
1728 break;
1729 case 2:
1730 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1732 break;
1733 }
1734 store_reg(s, rd, tmp);
1735 break;
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1737 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1738 return 1;
1739 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1740 switch ((insn >> 22) & 3) {
1741 case 0:
1742 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1743 break;
1744 case 1:
1745 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1746 break;
1747 case 2:
1748 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1749 break;
1750 }
1751 tcg_gen_shli_i32(tmp, tmp, 28);
1752 gen_set_nzcv(tmp);
1753 tcg_temp_free_i32(tmp);
1754 break;
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1756 if (((insn >> 6) & 3) == 3)
1757 return 1;
1758 rd = (insn >> 12) & 0xf;
1759 wrd = (insn >> 16) & 0xf;
1760 tmp = load_reg(s, rd);
1761 switch ((insn >> 6) & 3) {
1762 case 0:
1763 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1764 break;
1765 case 1:
1766 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1767 break;
1768 case 2:
1769 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1770 break;
1771 }
1772 tcg_temp_free_i32(tmp);
1773 gen_op_iwmmxt_movq_wRn_M0(wrd);
1774 gen_op_iwmmxt_set_mup();
1775 break;
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1777 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1778 return 1;
1779 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1780 tmp2 = tcg_temp_new_i32();
1781 tcg_gen_mov_i32(tmp2, tmp);
1782 switch ((insn >> 22) & 3) {
1783 case 0:
1784 for (i = 0; i < 7; i ++) {
1785 tcg_gen_shli_i32(tmp2, tmp2, 4);
1786 tcg_gen_and_i32(tmp, tmp, tmp2);
1787 }
1788 break;
1789 case 1:
1790 for (i = 0; i < 3; i ++) {
1791 tcg_gen_shli_i32(tmp2, tmp2, 8);
1792 tcg_gen_and_i32(tmp, tmp, tmp2);
1793 }
1794 break;
1795 case 2:
1796 tcg_gen_shli_i32(tmp2, tmp2, 16);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 break;
1799 }
1800 gen_set_nzcv(tmp);
1801 tcg_temp_free_i32(tmp2);
1802 tcg_temp_free_i32(tmp);
1803 break;
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd = (insn >> 12) & 0xf;
1806 rd0 = (insn >> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0);
1808 switch ((insn >> 22) & 3) {
1809 case 0:
1810 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1811 break;
1812 case 1:
1813 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1814 break;
1815 case 2:
1816 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1817 break;
1818 case 3:
1819 return 1;
1820 }
1821 gen_op_iwmmxt_movq_wRn_M0(wrd);
1822 gen_op_iwmmxt_set_mup();
1823 break;
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1825 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1826 return 1;
1827 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1828 tmp2 = tcg_temp_new_i32();
1829 tcg_gen_mov_i32(tmp2, tmp);
1830 switch ((insn >> 22) & 3) {
1831 case 0:
1832 for (i = 0; i < 7; i ++) {
1833 tcg_gen_shli_i32(tmp2, tmp2, 4);
1834 tcg_gen_or_i32(tmp, tmp, tmp2);
1835 }
1836 break;
1837 case 1:
1838 for (i = 0; i < 3; i ++) {
1839 tcg_gen_shli_i32(tmp2, tmp2, 8);
1840 tcg_gen_or_i32(tmp, tmp, tmp2);
1841 }
1842 break;
1843 case 2:
1844 tcg_gen_shli_i32(tmp2, tmp2, 16);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 break;
1847 }
1848 gen_set_nzcv(tmp);
1849 tcg_temp_free_i32(tmp2);
1850 tcg_temp_free_i32(tmp);
1851 break;
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd = (insn >> 12) & 0xf;
1854 rd0 = (insn >> 16) & 0xf;
1855 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1856 return 1;
1857 gen_op_iwmmxt_movq_M0_wRn(rd0);
1858 tmp = tcg_temp_new_i32();
1859 switch ((insn >> 22) & 3) {
1860 case 0:
1861 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1862 break;
1863 case 1:
1864 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1865 break;
1866 case 2:
1867 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1868 break;
1869 }
1870 store_reg(s, rd, tmp);
1871 break;
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd = (insn >> 12) & 0xf;
1875 rd0 = (insn >> 16) & 0xf;
1876 rd1 = (insn >> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0);
1878 switch ((insn >> 22) & 3) {
1879 case 0:
1880 if (insn & (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1882 else
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1884 break;
1885 case 1:
1886 if (insn & (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1888 else
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1890 break;
1891 case 2:
1892 if (insn & (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1894 else
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1896 break;
1897 case 3:
1898 return 1;
1899 }
1900 gen_op_iwmmxt_movq_wRn_M0(wrd);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1903 break;
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd = (insn >> 12) & 0xf;
1907 rd0 = (insn >> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0);
1909 switch ((insn >> 22) & 3) {
1910 case 0:
1911 if (insn & (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1913 else
1914 gen_op_iwmmxt_unpacklub_M0();
1915 break;
1916 case 1:
1917 if (insn & (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1919 else
1920 gen_op_iwmmxt_unpackluw_M0();
1921 break;
1922 case 2:
1923 if (insn & (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1925 else
1926 gen_op_iwmmxt_unpacklul_M0();
1927 break;
1928 case 3:
1929 return 1;
1930 }
1931 gen_op_iwmmxt_movq_wRn_M0(wrd);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1934 break;
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd = (insn >> 12) & 0xf;
1938 rd0 = (insn >> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0);
1940 switch ((insn >> 22) & 3) {
1941 case 0:
1942 if (insn & (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1944 else
1945 gen_op_iwmmxt_unpackhub_M0();
1946 break;
1947 case 1:
1948 if (insn & (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1950 else
1951 gen_op_iwmmxt_unpackhuw_M0();
1952 break;
1953 case 2:
1954 if (insn & (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1956 else
1957 gen_op_iwmmxt_unpackhul_M0();
1958 break;
1959 case 3:
1960 return 1;
1961 }
1962 gen_op_iwmmxt_movq_wRn_M0(wrd);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1965 break;
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
1968 if (((insn >> 22) & 3) == 0)
1969 return 1;
1970 wrd = (insn >> 12) & 0xf;
1971 rd0 = (insn >> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0);
1973 tmp = tcg_temp_new_i32();
1974 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1975 tcg_temp_free_i32(tmp);
1976 return 1;
1977 }
1978 switch ((insn >> 22) & 3) {
1979 case 1:
1980 gen_helper_iwmmxt_srlw(cpu_M0, cpu_M0, tmp);
1981 break;
1982 case 2:
1983 gen_helper_iwmmxt_srll(cpu_M0, cpu_M0, tmp);
1984 break;
1985 case 3:
1986 gen_helper_iwmmxt_srlq(cpu_M0, cpu_M0, tmp);
1987 break;
1988 }
1989 tcg_temp_free_i32(tmp);
1990 gen_op_iwmmxt_movq_wRn_M0(wrd);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1993 break;
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
1996 if (((insn >> 22) & 3) == 0)
1997 return 1;
1998 wrd = (insn >> 12) & 0xf;
1999 rd0 = (insn >> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0);
2001 tmp = tcg_temp_new_i32();
2002 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2003 tcg_temp_free_i32(tmp);
2004 return 1;
2005 }
2006 switch ((insn >> 22) & 3) {
2007 case 1:
2008 gen_helper_iwmmxt_sraw(cpu_M0, cpu_M0, tmp);
2009 break;
2010 case 2:
2011 gen_helper_iwmmxt_sral(cpu_M0, cpu_M0, tmp);
2012 break;
2013 case 3:
2014 gen_helper_iwmmxt_sraq(cpu_M0, cpu_M0, tmp);
2015 break;
2016 }
2017 tcg_temp_free_i32(tmp);
2018 gen_op_iwmmxt_movq_wRn_M0(wrd);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2021 break;
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
2024 if (((insn >> 22) & 3) == 0)
2025 return 1;
2026 wrd = (insn >> 12) & 0xf;
2027 rd0 = (insn >> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0);
2029 tmp = tcg_temp_new_i32();
2030 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2031 tcg_temp_free_i32(tmp);
2032 return 1;
2033 }
2034 switch ((insn >> 22) & 3) {
2035 case 1:
2036 gen_helper_iwmmxt_sllw(cpu_M0, cpu_M0, tmp);
2037 break;
2038 case 2:
2039 gen_helper_iwmmxt_slll(cpu_M0, cpu_M0, tmp);
2040 break;
2041 case 3:
2042 gen_helper_iwmmxt_sllq(cpu_M0, cpu_M0, tmp);
2043 break;
2044 }
2045 tcg_temp_free_i32(tmp);
2046 gen_op_iwmmxt_movq_wRn_M0(wrd);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2049 break;
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
2052 if (((insn >> 22) & 3) == 0)
2053 return 1;
2054 wrd = (insn >> 12) & 0xf;
2055 rd0 = (insn >> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0);
2057 tmp = tcg_temp_new_i32();
2058 switch ((insn >> 22) & 3) {
2059 case 1:
2060 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2061 tcg_temp_free_i32(tmp);
2062 return 1;
2063 }
2064 gen_helper_iwmmxt_rorw(cpu_M0, cpu_M0, tmp);
2065 break;
2066 case 2:
2067 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2068 tcg_temp_free_i32(tmp);
2069 return 1;
2070 }
2071 gen_helper_iwmmxt_rorl(cpu_M0, cpu_M0, tmp);
2072 break;
2073 case 3:
2074 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2075 tcg_temp_free_i32(tmp);
2076 return 1;
2077 }
2078 gen_helper_iwmmxt_rorq(cpu_M0, cpu_M0, tmp);
2079 break;
2080 }
2081 tcg_temp_free_i32(tmp);
2082 gen_op_iwmmxt_movq_wRn_M0(wrd);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2085 break;
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd = (insn >> 12) & 0xf;
2089 rd0 = (insn >> 16) & 0xf;
2090 rd1 = (insn >> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0);
2092 switch ((insn >> 22) & 3) {
2093 case 0:
2094 if (insn & (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2096 else
2097 gen_op_iwmmxt_minub_M0_wRn(rd1);
2098 break;
2099 case 1:
2100 if (insn & (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2102 else
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2104 break;
2105 case 2:
2106 if (insn & (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2108 else
2109 gen_op_iwmmxt_minul_M0_wRn(rd1);
2110 break;
2111 case 3:
2112 return 1;
2113 }
2114 gen_op_iwmmxt_movq_wRn_M0(wrd);
2115 gen_op_iwmmxt_set_mup();
2116 break;
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd = (insn >> 12) & 0xf;
2120 rd0 = (insn >> 16) & 0xf;
2121 rd1 = (insn >> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0);
2123 switch ((insn >> 22) & 3) {
2124 case 0:
2125 if (insn & (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2127 else
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2129 break;
2130 case 1:
2131 if (insn & (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2133 else
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2135 break;
2136 case 2:
2137 if (insn & (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2139 else
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2141 break;
2142 case 3:
2143 return 1;
2144 }
2145 gen_op_iwmmxt_movq_wRn_M0(wrd);
2146 gen_op_iwmmxt_set_mup();
2147 break;
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd = (insn >> 12) & 0xf;
2151 rd0 = (insn >> 16) & 0xf;
2152 rd1 = (insn >> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0);
2154 tmp = tcg_const_i32((insn >> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1, rd1);
2156 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2157 tcg_temp_free(tmp);
2158 gen_op_iwmmxt_movq_wRn_M0(wrd);
2159 gen_op_iwmmxt_set_mup();
2160 break;
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd = (insn >> 12) & 0xf;
2166 rd0 = (insn >> 16) & 0xf;
2167 rd1 = (insn >> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0);
2169 switch ((insn >> 20) & 0xf) {
2170 case 0x0:
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2172 break;
2173 case 0x1:
2174 gen_op_iwmmxt_subub_M0_wRn(rd1);
2175 break;
2176 case 0x3:
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2178 break;
2179 case 0x4:
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2181 break;
2182 case 0x5:
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2184 break;
2185 case 0x7:
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2187 break;
2188 case 0x8:
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2190 break;
2191 case 0x9:
2192 gen_op_iwmmxt_subul_M0_wRn(rd1);
2193 break;
2194 case 0xb:
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2196 break;
2197 default:
2198 return 1;
2199 }
2200 gen_op_iwmmxt_movq_wRn_M0(wrd);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2203 break;
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd = (insn >> 12) & 0xf;
2209 rd0 = (insn >> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0);
2211 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2212 gen_helper_iwmmxt_shufh(cpu_M0, cpu_M0, tmp);
2213 tcg_temp_free(tmp);
2214 gen_op_iwmmxt_movq_wRn_M0(wrd);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2217 break;
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd = (insn >> 12) & 0xf;
2223 rd0 = (insn >> 16) & 0xf;
2224 rd1 = (insn >> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0);
2226 switch ((insn >> 20) & 0xf) {
2227 case 0x0:
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2229 break;
2230 case 0x1:
2231 gen_op_iwmmxt_addub_M0_wRn(rd1);
2232 break;
2233 case 0x3:
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2235 break;
2236 case 0x4:
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2238 break;
2239 case 0x5:
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2241 break;
2242 case 0x7:
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2244 break;
2245 case 0x8:
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2247 break;
2248 case 0x9:
2249 gen_op_iwmmxt_addul_M0_wRn(rd1);
2250 break;
2251 case 0xb:
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2253 break;
2254 default:
2255 return 1;
2256 }
2257 gen_op_iwmmxt_movq_wRn_M0(wrd);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2260 break;
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2265 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2266 return 1;
2267 wrd = (insn >> 12) & 0xf;
2268 rd0 = (insn >> 16) & 0xf;
2269 rd1 = (insn >> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0);
2271 switch ((insn >> 22) & 3) {
2272 case 1:
2273 if (insn & (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2275 else
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2277 break;
2278 case 2:
2279 if (insn & (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2281 else
2282 gen_op_iwmmxt_packul_M0_wRn(rd1);
2283 break;
2284 case 3:
2285 if (insn & (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2287 else
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2289 break;
2290 }
2291 gen_op_iwmmxt_movq_wRn_M0(wrd);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2294 break;
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd = (insn >> 5) & 0xf;
2300 rd0 = (insn >> 12) & 0xf;
2301 rd1 = (insn >> 0) & 0xf;
2302 if (rd0 == 0xf || rd1 == 0xf)
2303 return 1;
2304 gen_op_iwmmxt_movq_M0_wRn(wrd);
2305 tmp = load_reg(s, rd0);
2306 tmp2 = load_reg(s, rd1);
2307 switch ((insn >> 16) & 0xf) {
2308 case 0x0: /* TMIA */
2309 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2310 break;
2311 case 0x8: /* TMIAPH */
2312 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2313 break;
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2315 if (insn & (1 << 16))
2316 tcg_gen_shri_i32(tmp, tmp, 16);
2317 if (insn & (1 << 17))
2318 tcg_gen_shri_i32(tmp2, tmp2, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2320 break;
2321 default:
2322 tcg_temp_free_i32(tmp2);
2323 tcg_temp_free_i32(tmp);
2324 return 1;
2325 }
2326 tcg_temp_free_i32(tmp2);
2327 tcg_temp_free_i32(tmp);
2328 gen_op_iwmmxt_movq_wRn_M0(wrd);
2329 gen_op_iwmmxt_set_mup();
2330 break;
2331 default:
2332 return 1;
2333 }
2334
2335 return 0;
2336 }
2337
2338 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2341 {
2342 int acc, rd0, rd1, rdhi, rdlo;
2343 TCGv tmp, tmp2;
2344
2345 if ((insn & 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0 = (insn >> 12) & 0xf;
2348 rd1 = insn & 0xf;
2349 acc = (insn >> 5) & 7;
2350
2351 if (acc != 0)
2352 return 1;
2353
2354 tmp = load_reg(s, rd0);
2355 tmp2 = load_reg(s, rd1);
2356 switch ((insn >> 16) & 0xf) {
2357 case 0x0: /* MIA */
2358 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2359 break;
2360 case 0x8: /* MIAPH */
2361 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2362 break;
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
2367 if (insn & (1 << 16))
2368 tcg_gen_shri_i32(tmp, tmp, 16);
2369 if (insn & (1 << 17))
2370 tcg_gen_shri_i32(tmp2, tmp2, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2372 break;
2373 default:
2374 return 1;
2375 }
2376 tcg_temp_free_i32(tmp2);
2377 tcg_temp_free_i32(tmp);
2378
2379 gen_op_iwmmxt_movq_wRn_M0(acc);
2380 return 0;
2381 }
2382
2383 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi = (insn >> 16) & 0xf;
2386 rdlo = (insn >> 12) & 0xf;
2387 acc = insn & 7;
2388
2389 if (acc != 0)
2390 return 1;
2391
2392 if (insn & ARM_CP_RW_BIT) { /* MRA */
2393 iwmmxt_load_reg(cpu_V0, acc);
2394 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2395 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2397 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2398 } else { /* MAR */
2399 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2400 iwmmxt_store_reg(cpu_V0, acc);
2401 }
2402 return 0;
2403 }
2404
2405 return 1;
2406 }
2407
2408 /* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2411 {
2412 TCGv tmp, tmp2;
2413 uint32_t rd = (insn >> 12) & 0xf;
2414 uint32_t cp = (insn >> 8) & 0xf;
2415 if (IS_USER(s)) {
2416 return 1;
2417 }
2418
2419 if (insn & ARM_CP_RW_BIT) {
2420 if (!env->cp[cp].cp_read)
2421 return 1;
2422 gen_set_pc_im(s->pc);
2423 tmp = tcg_temp_new_i32();
2424 tmp2 = tcg_const_i32(insn);
2425 gen_helper_get_cp(tmp, cpu_env, tmp2);
2426 tcg_temp_free(tmp2);
2427 store_reg(s, rd, tmp);
2428 } else {
2429 if (!env->cp[cp].cp_write)
2430 return 1;
2431 gen_set_pc_im(s->pc);
2432 tmp = load_reg(s, rd);
2433 tmp2 = tcg_const_i32(insn);
2434 gen_helper_set_cp(cpu_env, tmp2, tmp);
2435 tcg_temp_free(tmp2);
2436 tcg_temp_free_i32(tmp);
2437 }
2438 return 0;
2439 }
2440
2441 static int cp15_user_ok(uint32_t insn)
2442 {
2443 int cpn = (insn >> 16) & 0xf;
2444 int cpm = insn & 0xf;
2445 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2446
2447 if (cpn == 13 && cpm == 0) {
2448 /* TLS register. */
2449 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2450 return 1;
2451 }
2452 if (cpn == 7) {
2453 /* ISB, DSB, DMB. */
2454 if ((cpm == 5 && op == 4)
2455 || (cpm == 10 && (op == 4 || op == 5)))
2456 return 1;
2457 }
2458 return 0;
2459 }
2460
2461 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2462 {
2463 TCGv tmp;
2464 int cpn = (insn >> 16) & 0xf;
2465 int cpm = insn & 0xf;
2466 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2467
2468 if (!arm_feature(env, ARM_FEATURE_V6K))
2469 return 0;
2470
2471 if (!(cpn == 13 && cpm == 0))
2472 return 0;
2473
2474 if (insn & ARM_CP_RW_BIT) {
2475 switch (op) {
2476 case 2:
2477 tmp = load_cpu_field(cp15.c13_tls1);
2478 break;
2479 case 3:
2480 tmp = load_cpu_field(cp15.c13_tls2);
2481 break;
2482 case 4:
2483 tmp = load_cpu_field(cp15.c13_tls3);
2484 break;
2485 default:
2486 return 0;
2487 }
2488 store_reg(s, rd, tmp);
2489
2490 } else {
2491 tmp = load_reg(s, rd);
2492 switch (op) {
2493 case 2:
2494 store_cpu_field(tmp, cp15.c13_tls1);
2495 break;
2496 case 3:
2497 store_cpu_field(tmp, cp15.c13_tls2);
2498 break;
2499 case 4:
2500 store_cpu_field(tmp, cp15.c13_tls3);
2501 break;
2502 default:
2503 tcg_temp_free_i32(tmp);
2504 return 0;
2505 }
2506 }
2507 return 1;
2508 }
2509
2510 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
2512 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2513 {
2514 uint32_t rd;
2515 TCGv tmp, tmp2;
2516
2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env, ARM_FEATURE_M))
2519 return 1;
2520
2521 if ((insn & (1 << 25)) == 0) {
2522 if (insn & (1 << 20)) {
2523 /* mrrc */
2524 return 1;
2525 }
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2527 return 0;
2528 }
2529 if ((insn & (1 << 4)) == 0) {
2530 /* cdp */
2531 return 1;
2532 }
2533 if (IS_USER(s) && !cp15_user_ok(insn)) {
2534 return 1;
2535 }
2536
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2539 */
2540 if ((insn & 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2543 */
2544 if (!arm_feature(env, ARM_FEATURE_V7)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s->pc);
2547 s->is_jmp = DISAS_WFI;
2548 }
2549 return 0;
2550 }
2551
2552 if ((insn & 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2555 */
2556 if (!arm_feature(env, ARM_FEATURE_V6)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s->pc);
2559 s->is_jmp = DISAS_WFI;
2560 return 0;
2561 }
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2565 */
2566 }
2567
2568 rd = (insn >> 12) & 0xf;
2569
2570 if (cp15_tls_load_store(env, s, insn, rd))
2571 return 0;
2572
2573 tmp2 = tcg_const_i32(insn);
2574 if (insn & ARM_CP_RW_BIT) {
2575 tmp = tcg_temp_new_i32();
2576 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2577 /* If the destination register is r15 then sets condition codes. */
2578 if (rd != 15)
2579 store_reg(s, rd, tmp);
2580 else
2581 tcg_temp_free_i32(tmp);
2582 } else {
2583 tmp = load_reg(s, rd);
2584 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2585 tcg_temp_free_i32(tmp);
2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2590 (insn & 0x0fff0fff) != 0x0e010f10)
2591 gen_lookup_tb(s);
2592 }
2593 tcg_temp_free_i32(tmp2);
2594 return 0;
2595 }
2596
2597 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598 #define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2604 } else { \
2605 if (insn & (1 << (smallbit))) \
2606 return 1; \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2608 }} while (0)
2609
2610 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2616
2617 /* Move between integer and VFP cores. */
2618 static TCGv gen_vfp_mrs(void)
2619 {
2620 TCGv tmp = tcg_temp_new_i32();
2621 tcg_gen_mov_i32(tmp, cpu_F0s);
2622 return tmp;
2623 }
2624
2625 static void gen_vfp_msr(TCGv tmp)
2626 {
2627 tcg_gen_mov_i32(cpu_F0s, tmp);
2628 tcg_temp_free_i32(tmp);
2629 }
2630
2631 static void gen_neon_dup_u8(TCGv var, int shift)
2632 {
2633 TCGv tmp = tcg_temp_new_i32();
2634 if (shift)
2635 tcg_gen_shri_i32(var, var, shift);
2636 tcg_gen_ext8u_i32(var, var);
2637 tcg_gen_shli_i32(tmp, var, 8);
2638 tcg_gen_or_i32(var, var, tmp);
2639 tcg_gen_shli_i32(tmp, var, 16);
2640 tcg_gen_or_i32(var, var, tmp);
2641 tcg_temp_free_i32(tmp);
2642 }
2643
2644 static void gen_neon_dup_low16(TCGv var)
2645 {
2646 TCGv tmp = tcg_temp_new_i32();
2647 tcg_gen_ext16u_i32(var, var);
2648 tcg_gen_shli_i32(tmp, var, 16);
2649 tcg_gen_or_i32(var, var, tmp);
2650 tcg_temp_free_i32(tmp);
2651 }
2652
2653 static void gen_neon_dup_high16(TCGv var)
2654 {
2655 TCGv tmp = tcg_temp_new_i32();
2656 tcg_gen_andi_i32(var, var, 0xffff0000);
2657 tcg_gen_shri_i32(tmp, var, 16);
2658 tcg_gen_or_i32(var, var, tmp);
2659 tcg_temp_free_i32(tmp);
2660 }
2661
2662 static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
2663 {
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2665 TCGv tmp;
2666 switch (size) {
2667 case 0:
2668 tmp = gen_ld8u(addr, IS_USER(s));
2669 gen_neon_dup_u8(tmp, 0);
2670 break;
2671 case 1:
2672 tmp = gen_ld16u(addr, IS_USER(s));
2673 gen_neon_dup_low16(tmp);
2674 break;
2675 case 2:
2676 tmp = gen_ld32(addr, IS_USER(s));
2677 break;
2678 default: /* Avoid compiler warnings. */
2679 abort();
2680 }
2681 return tmp;
2682 }
2683
2684 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2687 {
2688 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2689 int dp, veclen;
2690 TCGv addr;
2691 TCGv tmp;
2692 TCGv tmp2;
2693
2694 if (!arm_feature(env, ARM_FEATURE_VFP))
2695 return 1;
2696
2697 if (!s->vfp_enabled) {
2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2699 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2700 return 1;
2701 rn = (insn >> 16) & 0xf;
2702 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2703 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2704 return 1;
2705 }
2706 dp = ((insn & 0xf00) == 0xb00);
2707 switch ((insn >> 24) & 0xf) {
2708 case 0xe:
2709 if (insn & (1 << 4)) {
2710 /* single register transfer */
2711 rd = (insn >> 12) & 0xf;
2712 if (dp) {
2713 int size;
2714 int pass;
2715
2716 VFP_DREG_N(rn, insn);
2717 if (insn & 0xf)
2718 return 1;
2719 if (insn & 0x00c00060
2720 && !arm_feature(env, ARM_FEATURE_NEON))
2721 return 1;
2722
2723 pass = (insn >> 21) & 1;
2724 if (insn & (1 << 22)) {
2725 size = 0;
2726 offset = ((insn >> 5) & 3) * 8;
2727 } else if (insn & (1 << 5)) {
2728 size = 1;
2729 offset = (insn & (1 << 6)) ? 16 : 0;
2730 } else {
2731 size = 2;
2732 offset = 0;
2733 }
2734 if (insn & ARM_CP_RW_BIT) {
2735 /* vfp->arm */
2736 tmp = neon_load_reg(rn, pass);
2737 switch (size) {
2738 case 0:
2739 if (offset)
2740 tcg_gen_shri_i32(tmp, tmp, offset);
2741 if (insn & (1 << 23))
2742 gen_uxtb(tmp);
2743 else
2744 gen_sxtb(tmp);
2745 break;
2746 case 1:
2747 if (insn & (1 << 23)) {
2748 if (offset) {
2749 tcg_gen_shri_i32(tmp, tmp, 16);
2750 } else {
2751 gen_uxth(tmp);
2752 }
2753 } else {
2754 if (offset) {
2755 tcg_gen_sari_i32(tmp, tmp, 16);
2756 } else {
2757 gen_sxth(tmp);
2758 }
2759 }
2760 break;
2761 case 2:
2762 break;
2763 }
2764 store_reg(s, rd, tmp);
2765 } else {
2766 /* arm->vfp */
2767 tmp = load_reg(s, rd);
2768 if (insn & (1 << 23)) {
2769 /* VDUP */
2770 if (size == 0) {
2771 gen_neon_dup_u8(tmp, 0);
2772 } else if (size == 1) {
2773 gen_neon_dup_low16(tmp);
2774 }
2775 for (n = 0; n <= pass * 2; n++) {
2776 tmp2 = tcg_temp_new_i32();
2777 tcg_gen_mov_i32(tmp2, tmp);
2778 neon_store_reg(rn, n, tmp2);
2779 }
2780 neon_store_reg(rn, n, tmp);
2781 } else {
2782 /* VMOV */
2783 switch (size) {
2784 case 0:
2785 tmp2 = neon_load_reg(rn, pass);
2786 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2787 tcg_temp_free_i32(tmp2);
2788 break;
2789 case 1:
2790 tmp2 = neon_load_reg(rn, pass);
2791 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2792 tcg_temp_free_i32(tmp2);
2793 break;
2794 case 2:
2795 break;
2796 }
2797 neon_store_reg(rn, pass, tmp);
2798 }
2799 }
2800 } else { /* !dp */
2801 if ((insn & 0x6f) != 0x00)
2802 return 1;
2803 rn = VFP_SREG_N(insn);
2804 if (insn & ARM_CP_RW_BIT) {
2805 /* vfp->arm */
2806 if (insn & (1 << 21)) {
2807 /* system register */
2808 rn >>= 1;
2809
2810 switch (rn) {
2811 case ARM_VFP_FPSID:
2812 /* VFP2 allows access to FSID from userspace.
2813 VFP3 restricts all id registers to privileged
2814 accesses. */
2815 if (IS_USER(s)
2816 && arm_feature(env, ARM_FEATURE_VFP3))
2817 return 1;
2818 tmp = load_cpu_field(vfp.xregs[rn]);
2819 break;
2820 case ARM_VFP_FPEXC:
2821 if (IS_USER(s))
2822 return 1;
2823 tmp = load_cpu_field(vfp.xregs[rn]);
2824 break;
2825 case ARM_VFP_FPINST:
2826 case ARM_VFP_FPINST2:
2827 /* Not present in VFP3. */
2828 if (IS_USER(s)
2829 || arm_feature(env, ARM_FEATURE_VFP3))
2830 return 1;
2831 tmp = load_cpu_field(vfp.xregs[rn]);
2832 break;
2833 case ARM_VFP_FPSCR:
2834 if (rd == 15) {
2835 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2836 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2837 } else {
2838 tmp = tcg_temp_new_i32();
2839 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2840 }
2841 break;
2842 case ARM_VFP_MVFR0:
2843 case ARM_VFP_MVFR1:
2844 if (IS_USER(s)
2845 || !arm_feature(env, ARM_FEATURE_VFP3))
2846 return 1;
2847 tmp = load_cpu_field(vfp.xregs[rn]);
2848 break;
2849 default:
2850 return 1;
2851 }
2852 } else {
2853 gen_mov_F0_vreg(0, rn);
2854 tmp = gen_vfp_mrs();
2855 }
2856 if (rd == 15) {
2857 /* Set the 4 flag bits in the CPSR. */
2858 gen_set_nzcv(tmp);
2859 tcg_temp_free_i32(tmp);
2860 } else {
2861 store_reg(s, rd, tmp);
2862 }
2863 } else {
2864 /* arm->vfp */
2865 tmp = load_reg(s, rd);
2866 if (insn & (1 << 21)) {
2867 rn >>= 1;
2868 /* system register */
2869 switch (rn) {
2870 case ARM_VFP_FPSID:
2871 case ARM_VFP_MVFR0:
2872 case ARM_VFP_MVFR1:
2873 /* Writes are ignored. */
2874 break;
2875 case ARM_VFP_FPSCR:
2876 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2877 tcg_temp_free_i32(tmp);
2878 gen_lookup_tb(s);
2879 break;
2880 case ARM_VFP_FPEXC:
2881 if (IS_USER(s))
2882 return 1;
2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2886 store_cpu_field(tmp, vfp.xregs[rn]);
2887 gen_lookup_tb(s);
2888 break;
2889 case ARM_VFP_FPINST:
2890 case ARM_VFP_FPINST2:
2891 store_cpu_field(tmp, vfp.xregs[rn]);
2892 break;
2893 default:
2894 return 1;
2895 }
2896 } else {
2897 gen_vfp_msr(tmp);
2898 gen_mov_vreg_F0(0, rn);
2899 }
2900 }
2901 }
2902 } else {
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2906 if (dp) {
2907 if (op == 15) {
2908 /* rn is opcode */
2909 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2910 } else {
2911 /* rn is register number */
2912 VFP_DREG_N(rn, insn);
2913 }
2914
2915 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2916 /* Integer or single precision destination. */
2917 rd = VFP_SREG_D(insn);
2918 } else {
2919 VFP_DREG_D(rd, insn);
2920 }
2921 if (op == 15 &&
2922 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2925 */
2926 rm = VFP_SREG_M(insn);
2927 } else {
2928 VFP_DREG_M(rm, insn);
2929 }
2930 } else {
2931 rn = VFP_SREG_N(insn);
2932 if (op == 15 && rn == 15) {
2933 /* Double precision destination. */
2934 VFP_DREG_D(rd, insn);
2935 } else {
2936 rd = VFP_SREG_D(insn);
2937 }
2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2940 */
2941 rm = VFP_SREG_M(insn);
2942 }
2943
2944 veclen = s->vec_len;
2945 if (op == 15 && rn > 3)
2946 veclen = 0;
2947
2948 /* Shut up compiler warnings. */
2949 delta_m = 0;
2950 delta_d = 0;
2951 bank_mask = 0;
2952
2953 if (veclen > 0) {
2954 if (dp)
2955 bank_mask = 0xc;
2956 else
2957 bank_mask = 0x18;
2958
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd & bank_mask) == 0) {
2961 /* scalar */
2962 veclen = 0;
2963 } else {
2964 if (dp)
2965 delta_d = (s->vec_stride >> 1) + 1;
2966 else
2967 delta_d = s->vec_stride + 1;
2968
2969 if ((rm & bank_mask) == 0) {
2970 /* mixed scalar/vector */
2971 delta_m = 0;
2972 } else {
2973 /* vector */
2974 delta_m = delta_d;
2975 }
2976 }
2977 }
2978
2979 /* Load the initial operands. */
2980 if (op == 15) {
2981 switch (rn) {
2982 case 16:
2983 case 17:
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm);
2986 break;
2987 case 8:
2988 case 9:
2989 /* Compare */
2990 gen_mov_F0_vreg(dp, rd);
2991 gen_mov_F1_vreg(dp, rm);
2992 break;
2993 case 10:
2994 case 11:
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp, rd);
2997 gen_vfp_F1_ld0(dp);
2998 break;
2999 case 20:
3000 case 21:
3001 case 22:
3002 case 23:
3003 case 28:
3004 case 29:
3005 case 30:
3006 case 31:
3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp, rd);
3009 break;
3010 default:
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp, rm);
3013 break;
3014 }
3015 } else {
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp, rn);
3018 gen_mov_F1_vreg(dp, rm);
3019 }
3020
3021 for (;;) {
3022 /* Perform the calculation. */
3023 switch (op) {
3024 case 0: /* mac: fd + (fn * fm) */
3025 gen_vfp_mul(dp);
3026 gen_mov_F1_vreg(dp, rd);
3027 gen_vfp_add(dp);
3028 break;
3029 case 1: /* nmac: fd - (fn * fm) */
3030 gen_vfp_mul(dp);
3031 gen_vfp_neg(dp);
3032 gen_mov_F1_vreg(dp, rd);
3033 gen_vfp_add(dp);
3034 break;
3035 case 2: /* msc: -fd + (fn * fm) */
3036 gen_vfp_mul(dp);
3037 gen_mov_F1_vreg(dp, rd);
3038 gen_vfp_sub(dp);
3039 break;
3040 case 3: /* nmsc: -fd - (fn * fm) */
3041 gen_vfp_mul(dp);
3042 gen_vfp_neg(dp);
3043 gen_mov_F1_vreg(dp, rd);
3044 gen_vfp_sub(dp);
3045 break;
3046 case 4: /* mul: fn * fm */
3047 gen_vfp_mul(dp);
3048 break;
3049 case 5: /* nmul: -(fn * fm) */
3050 gen_vfp_mul(dp);
3051 gen_vfp_neg(dp);
3052 break;
3053 case 6: /* add: fn + fm */
3054 gen_vfp_add(dp);
3055 break;
3056 case 7: /* sub: fn - fm */
3057 gen_vfp_sub(dp);
3058 break;
3059 case 8: /* div: fn / fm */
3060 gen_vfp_div(dp);
3061 break;
3062 case 14: /* fconst */
3063 if (!arm_feature(env, ARM_FEATURE_VFP3))
3064 return 1;
3065
3066 n = (insn << 12) & 0x80000000;
3067 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3068 if (dp) {
3069 if (i & 0x40)
3070 i |= 0x3f80;
3071 else
3072 i |= 0x4000;
3073 n |= i << 16;
3074 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3075 } else {
3076 if (i & 0x40)
3077 i |= 0x780;
3078 else
3079 i |= 0x800;
3080 n |= i << 19;
3081 tcg_gen_movi_i32(cpu_F0s, n);
3082 }
3083 break;
3084 case 15: /* extension space */
3085 switch (rn) {
3086 case 0: /* cpy */
3087 /* no-op */
3088 break;
3089 case 1: /* abs */
3090 gen_vfp_abs(dp);
3091 break;
3092 case 2: /* neg */
3093 gen_vfp_neg(dp);
3094 break;
3095 case 3: /* sqrt */
3096 gen_vfp_sqrt(dp);
3097 break;
3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3100 return 1;
3101 tmp = gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp, tmp);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3104 tcg_temp_free_i32(tmp);
3105 break;
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3108 return 1;
3109 tmp = gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp, tmp, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3112 tcg_temp_free_i32(tmp);
3113 break;
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3116 return 1;
3117 tmp = tcg_temp_new_i32();
3118 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3119 gen_mov_F0_vreg(0, rd);
3120 tmp2 = gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3122 tcg_gen_or_i32(tmp, tmp, tmp2);
3123 tcg_temp_free_i32(tmp2);
3124 gen_vfp_msr(tmp);
3125 break;
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3128 return 1;
3129 tmp = tcg_temp_new_i32();
3130 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3131 tcg_gen_shli_i32(tmp, tmp, 16);
3132 gen_mov_F0_vreg(0, rd);
3133 tmp2 = gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2, tmp2);
3135 tcg_gen_or_i32(tmp, tmp, tmp2);
3136 tcg_temp_free_i32(tmp2);
3137 gen_vfp_msr(tmp);
3138 break;
3139 case 8: /* cmp */
3140 gen_vfp_cmp(dp);
3141 break;
3142 case 9: /* cmpe */
3143 gen_vfp_cmpe(dp);
3144 break;
3145 case 10: /* cmpz */
3146 gen_vfp_cmp(dp);
3147 break;
3148 case 11: /* cmpez */
3149 gen_vfp_F1_ld0(dp);
3150 gen_vfp_cmpe(dp);
3151 break;
3152 case 15: /* single<->double conversion */
3153 if (dp)
3154 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3155 else
3156 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3157 break;
3158 case 16: /* fuito */
3159 gen_vfp_uito(dp);
3160 break;
3161 case 17: /* fsito */
3162 gen_vfp_sito(dp);
3163 break;
3164 case 20: /* fshto */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_shto(dp, 16 - rm);
3168 break;
3169 case 21: /* fslto */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_slto(dp, 32 - rm);
3173 break;
3174 case 22: /* fuhto */
3175 if (!arm_feature(env, ARM_FEATURE_VFP3))
3176 return 1;
3177 gen_vfp_uhto(dp, 16 - rm);
3178 break;
3179 case 23: /* fulto */
3180 if (!arm_feature(env, ARM_FEATURE_VFP3))
3181 return 1;
3182 gen_vfp_ulto(dp, 32 - rm);
3183 break;
3184 case 24: /* ftoui */
3185 gen_vfp_toui(dp);
3186 break;
3187 case 25: /* ftouiz */
3188 gen_vfp_touiz(dp);
3189 break;
3190 case 26: /* ftosi */
3191 gen_vfp_tosi(dp);
3192 break;
3193 case 27: /* ftosiz */
3194 gen_vfp_tosiz(dp);
3195 break;
3196 case 28: /* ftosh */
3197 if (!arm_feature(env, ARM_FEATURE_VFP3))
3198 return 1;
3199 gen_vfp_tosh(dp, 16 - rm);
3200 break;
3201 case 29: /* ftosl */
3202 if (!arm_feature(env, ARM_FEATURE_VFP3))
3203 return 1;
3204 gen_vfp_tosl(dp, 32 - rm);
3205 break;
3206 case 30: /* ftouh */
3207 if (!arm_feature(env, ARM_FEATURE_VFP3))
3208 return 1;
3209 gen_vfp_touh(dp, 16 - rm);
3210 break;
3211 case 31: /* ftoul */
3212 if (!arm_feature(env, ARM_FEATURE_VFP3))
3213 return 1;
3214 gen_vfp_toul(dp, 32 - rm);
3215 break;
3216 default: /* undefined */
3217 printf ("rn:%d\n", rn);
3218 return 1;
3219 }
3220 break;
3221 default: /* undefined */
3222 printf ("op:%d\n", op);
3223 return 1;
3224 }
3225
3226 /* Write back the result. */
3227 if (op == 15 && (rn >= 8 && rn <= 11))
3228 ; /* Comparison, do nothing. */
3229 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
3231 gen_mov_vreg_F0(0, rd);
3232 else if (op == 15 && rn == 15)
3233 /* conversion */
3234 gen_mov_vreg_F0(!dp, rd);
3235 else
3236 gen_mov_vreg_F0(dp, rd);
3237
3238 /* break out of the loop if we have finished */
3239 if (veclen == 0)
3240 break;
3241
3242 if (op == 15 && delta_m == 0) {
3243 /* single source one-many */
3244 while (veclen--) {
3245 rd = ((rd + delta_d) & (bank_mask - 1))
3246 | (rd & bank_mask);
3247 gen_mov_vreg_F0(dp, rd);
3248 }
3249 break;
3250 }
3251 /* Setup the next operands. */
3252 veclen--;
3253 rd = ((rd + delta_d) & (bank_mask - 1))
3254 | (rd & bank_mask);
3255
3256 if (op == 15) {
3257 /* One source operand. */
3258 rm = ((rm + delta_m) & (bank_mask - 1))
3259 | (rm & bank_mask);
3260 gen_mov_F0_vreg(dp, rm);
3261 } else {
3262 /* Two source operands. */
3263 rn = ((rn + delta_d) & (bank_mask - 1))
3264 | (rn & bank_mask);
3265 gen_mov_F0_vreg(dp, rn);
3266 if (delta_m) {
3267 rm = ((rm + delta_m) & (bank_mask - 1))
3268 | (rm & bank_mask);
3269 gen_mov_F1_vreg(dp, rm);
3270 }
3271 }
3272 }
3273 }
3274 break;
3275 case 0xc:
3276 case 0xd:
3277 if ((insn & 0x03e00000) == 0x00400000) {
3278 /* two-register transfer */
3279 rn = (insn >> 16) & 0xf;
3280 rd = (insn >> 12) & 0xf;
3281 if (dp) {
3282 VFP_DREG_M(rm, insn);
3283 } else {
3284 rm = VFP_SREG_M(insn);
3285 }
3286
3287 if (insn & ARM_CP_RW_BIT) {
3288 /* vfp->arm */
3289 if (dp) {
3290 gen_mov_F0_vreg(0, rm * 2);
3291 tmp = gen_vfp_mrs();
3292 store_reg(s, rd, tmp);
3293 gen_mov_F0_vreg(0, rm * 2 + 1);
3294 tmp = gen_vfp_mrs();
3295 store_reg(s, rn, tmp);
3296 } else {
3297 gen_mov_F0_vreg(0, rm);
3298 tmp = gen_vfp_mrs();
3299 store_reg(s, rd, tmp);
3300 gen_mov_F0_vreg(0, rm + 1);
3301 tmp = gen_vfp_mrs();
3302 store_reg(s, rn, tmp);
3303 }
3304 } else {
3305 /* arm->vfp */
3306 if (dp) {
3307 tmp = load_reg(s, rd);
3308 gen_vfp_msr(tmp);
3309 gen_mov_vreg_F0(0, rm * 2);
3310 tmp = load_reg(s, rn);
3311 gen_vfp_msr(tmp);
3312 gen_mov_vreg_F0(0, rm * 2 + 1);
3313 } else {
3314 tmp = load_reg(s, rd);
3315 gen_vfp_msr(tmp);
3316 gen_mov_vreg_F0(0, rm);
3317 tmp = load_reg(s, rn);
3318 gen_vfp_msr(tmp);
3319 gen_mov_vreg_F0(0, rm + 1);
3320 }
3321 }
3322 } else {
3323 /* Load/store */
3324 rn = (insn >> 16) & 0xf;
3325 if (dp)
3326 VFP_DREG_D(rd, insn);
3327 else
3328 rd = VFP_SREG_D(insn);
3329 if (s->thumb && rn == 15) {
3330 addr = tcg_temp_new_i32();
3331 tcg_gen_movi_i32(addr, s->pc & ~2);
3332 } else {
3333 addr = load_reg(s, rn);
3334 }
3335 if ((insn & 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset = (insn & 0xff) << 2;
3338 if ((insn & (1 << 23)) == 0)
3339 offset = -offset;
3340 tcg_gen_addi_i32(addr, addr, offset);
3341 if (insn & (1 << 20)) {
3342 gen_vfp_ld(s, dp, addr);
3343 gen_mov_vreg_F0(dp, rd);
3344 } else {
3345 gen_mov_F0_vreg(dp, rd);
3346 gen_vfp_st(s, dp, addr);
3347 }
3348 tcg_temp_free_i32(addr);
3349 } else {
3350 /* load/store multiple */
3351 if (dp)
3352 n = (insn >> 1) & 0x7f;
3353 else
3354 n = insn & 0xff;
3355
3356 if (insn & (1 << 24)) /* pre-decrement */
3357 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3358
3359 if (dp)
3360 offset = 8;
3361 else
3362 offset = 4;
3363 for (i = 0; i < n; i++) {
3364 if (insn & ARM_CP_RW_BIT) {
3365 /* load */
3366 gen_vfp_ld(s, dp, addr);
3367 gen_mov_vreg_F0(dp, rd + i);
3368 } else {
3369 /* store */
3370 gen_mov_F0_vreg(dp, rd + i);
3371 gen_vfp_st(s, dp, addr);
3372 }
3373 tcg_gen_addi_i32(addr, addr, offset);
3374 }
3375 if (insn & (1 << 21)) {
3376 /* writeback */
3377 if (insn & (1 << 24))
3378 offset = -offset * n;
3379 else if (dp && (insn & 1))
3380 offset = 4;
3381 else
3382 offset = 0;
3383
3384 if (offset != 0)
3385 tcg_gen_addi_i32(addr, addr, offset);
3386 store_reg(s, rn, addr);
3387 } else {
3388 tcg_temp_free_i32(addr);
3389 }
3390 }
3391 }
3392 break;
3393 default:
3394 /* Should never happen. */
3395 return 1;
3396 }
3397 return 0;
3398 }
3399
3400 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3401 {
3402 TranslationBlock *tb;
3403
3404 tb = s->tb;
3405 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3406 tcg_gen_goto_tb(n);
3407 gen_set_pc_im(dest);
3408 tcg_gen_exit_tb((tcg_target_long)tb + n);
3409 } else {
3410 gen_set_pc_im(dest);
3411 tcg_gen_exit_tb(0);
3412 }
3413 }
3414
3415 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3416 {
3417 if (unlikely(s->singlestep_enabled)) {
3418 /* An indirect jump so that we still trigger the debug exception. */
3419 if (s->thumb)
3420 dest |= 1;
3421 gen_bx_im(s, dest);
3422 } else {
3423 gen_goto_tb(s, 0, dest);
3424 s->is_jmp = DISAS_TB_JUMP;
3425 }
3426 }
3427
3428 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3429 {
3430 if (x)
3431 tcg_gen_sari_i32(t0, t0, 16);
3432 else
3433 gen_sxth(t0);
3434 if (y)
3435 tcg_gen_sari_i32(t1, t1, 16);
3436 else
3437 gen_sxth(t1);
3438 tcg_gen_mul_i32(t0, t0, t1);
3439 }
3440
3441 /* Return the mask of PSR bits set by a MSR instruction. */
3442 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3443 uint32_t mask;
3444
3445 mask = 0;
3446 if (flags & (1 << 0))
3447 mask |= 0xff;
3448 if (flags & (1 << 1))
3449 mask |= 0xff00;
3450 if (flags & (1 << 2))
3451 mask |= 0xff0000;
3452 if (flags & (1 << 3))
3453 mask |= 0xff000000;
3454
3455 /* Mask out undefined bits. */
3456 mask &= ~CPSR_RESERVED;
3457 if (!arm_feature(env, ARM_FEATURE_V4T))
3458 mask &= ~CPSR_T;
3459 if (!arm_feature(env, ARM_FEATURE_V5))
3460 mask &= ~CPSR_Q; /* V5TE in reality*/
3461 if (!arm_feature(env, ARM_FEATURE_V6))
3462 mask &= ~(CPSR_E | CPSR_GE);
3463 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3464 mask &= ~CPSR_IT;
3465 /* Mask out execution state bits. */
3466 if (!spsr)
3467 mask &= ~CPSR_EXEC;
3468 /* Mask out privileged bits. */
3469 if (IS_USER(s))
3470 mask &= CPSR_USER;
3471 return mask;
3472 }
3473
3474 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3476 {
3477 TCGv tmp;
3478 if (spsr) {
3479 /* ??? This is also undefined in system mode. */
3480 if (IS_USER(s))
3481 return 1;
3482
3483 tmp = load_cpu_field(spsr);
3484 tcg_gen_andi_i32(tmp, tmp, ~mask);
3485 tcg_gen_andi_i32(t0, t0, mask);
3486 tcg_gen_or_i32(tmp, tmp, t0);
3487 store_cpu_field(tmp, spsr);
3488 } else {
3489 gen_set_cpsr(t0, mask);
3490 }
3491 tcg_temp_free_i32(t0);
3492 gen_lookup_tb(s);
3493 return 0;
3494 }
3495
3496 /* Returns nonzero if access to the PSR is not permitted. */
3497 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3498 {
3499 TCGv tmp;
3500 tmp = tcg_temp_new_i32();
3501 tcg_gen_movi_i32(tmp, val);
3502 return gen_set_psr(s, mask, spsr, tmp);
3503 }
3504
3505 /* Generate an old-style exception return. Marks pc as dead. */
3506 static void gen_exception_return(DisasContext *s, TCGv pc)
3507 {
3508 TCGv tmp;
3509 store_reg(s, 15, pc);
3510 tmp = load_cpu_field(spsr);
3511 gen_set_cpsr(tmp, 0xffffffff);
3512 tcg_temp_free_i32(tmp);
3513 s->is_jmp = DISAS_UPDATE;
3514 }
3515
3516 /* Generate a v6 exception return. Marks both values as dead. */
3517 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3518 {
3519 gen_set_cpsr(cpsr, 0xffffffff);
3520 tcg_temp_free_i32(cpsr);
3521 store_reg(s, 15, pc);
3522 s->is_jmp = DISAS_UPDATE;
3523 }
3524
3525 static inline void
3526 gen_set_condexec (DisasContext *s)
3527 {
3528 if (s->condexec_mask) {
3529 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3530 TCGv tmp = tcg_temp_new_i32();
3531 tcg_gen_movi_i32(tmp, val);
3532 store_cpu_field(tmp, condexec_bits);
3533 }
3534 }
3535
3536 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3537 {
3538 gen_set_condexec(s);
3539 gen_set_pc_im(s->pc - offset);
3540 gen_exception(excp);
3541 s->is_jmp = DISAS_JUMP;
3542 }
3543
3544 static void gen_nop_hint(DisasContext *s, int val)
3545 {
3546 switch (val) {
3547 case 3: /* wfi */
3548 gen_set_pc_im(s->pc);
3549 s->is_jmp = DISAS_WFI;
3550 break;
3551 case 2: /* wfe */
3552 case 4: /* sev */
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3554 default: /* nop */
3555 break;
3556 }
3557 }
3558
3559 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3560
3561 static inline void gen_neon_add(int size, TCGv t0, TCGv t1)
3562 {
3563 switch (size) {
3564 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3565 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3566 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3567 default: abort();
3568 }
3569 }
3570
3571 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3572 {
3573 switch (size) {
3574 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3575 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3576 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3577 default: return;
3578 }
3579 }
3580
3581 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3582 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3583 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3584 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3585 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3586
3587 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3588 switch ((size << 1) | u) { \
3589 case 0: \
3590 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3591 break; \
3592 case 1: \
3593 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3594 break; \
3595 case 2: \
3596 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3597 break; \
3598 case 3: \
3599 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3600 break; \
3601 case 4: \
3602 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3603 break; \
3604 case 5: \
3605 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3606 break; \
3607 default: return 1; \
3608 }} while (0)
3609
3610 #define GEN_NEON_INTEGER_OP(name) do { \
3611 switch ((size << 1) | u) { \
3612 case 0: \
3613 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3614 break; \
3615 case 1: \
3616 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3617 break; \
3618 case 2: \
3619 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3620 break; \
3621 case 3: \
3622 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3623 break; \
3624 case 4: \
3625 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3626 break; \
3627 case 5: \
3628 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3629 break; \
3630 default: return 1; \
3631 }} while (0)
3632
3633 static TCGv neon_load_scratch(int scratch)
3634 {
3635 TCGv tmp = tcg_temp_new_i32();
3636 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3637 return tmp;
3638 }
3639
3640 static void neon_store_scratch(int scratch, TCGv var)
3641 {
3642 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3643 tcg_temp_free_i32(var);
3644 }
3645
3646 static inline TCGv neon_get_scalar(int size, int reg)
3647 {
3648 TCGv tmp;
3649 if (size == 1) {
3650 tmp = neon_load_reg(reg & 7, reg >> 4);
3651 if (reg & 8) {
3652 gen_neon_dup_high16(tmp);
3653 } else {
3654 gen_neon_dup_low16(tmp);
3655 }
3656 } else {
3657 tmp = neon_load_reg(reg & 15, reg >> 4);
3658 }
3659 return tmp;
3660 }
3661
3662 static int gen_neon_unzip(int rd, int rm, int size, int q)
3663 {
3664 TCGv tmp, tmp2;
3665 if (size == 3 || (!q && size == 2)) {
3666 return 1;
3667 }
3668 tmp = tcg_const_i32(rd);
3669 tmp2 = tcg_const_i32(rm);
3670 if (q) {
3671 switch (size) {
3672 case 0:
3673 gen_helper_neon_qunzip8(tmp, tmp2);
3674 break;
3675 case 1:
3676 gen_helper_neon_qunzip16(tmp, tmp2);
3677 break;
3678 case 2:
3679 gen_helper_neon_qunzip32(tmp, tmp2);
3680 break;
3681 default:
3682 abort();
3683 }
3684 } else {
3685 switch (size) {
3686 case 0:
3687 gen_helper_neon_unzip8(tmp, tmp2);
3688 break;
3689 case 1:
3690 gen_helper_neon_unzip16(tmp, tmp2);
3691 break;
3692 default:
3693 abort();
3694 }
3695 }
3696 tcg_temp_free_i32(tmp);
3697 tcg_temp_free_i32(tmp2);
3698 return 0;
3699 }
3700
3701 static int gen_neon_zip(int rd, int rm, int size, int q)
3702 {
3703 TCGv tmp, tmp2;
3704 if (size == 3 || (!q && size == 2)) {
3705 return 1;
3706 }
3707 tmp = tcg_const_i32(rd);
3708 tmp2 = tcg_const_i32(rm);
3709 if (q) {
3710 switch (size) {
3711 case 0:
3712 gen_helper_neon_qzip8(tmp, tmp2);
3713 break;
3714 case 1:
3715 gen_helper_neon_qzip16(tmp, tmp2);
3716 break;
3717 case 2:
3718 gen_helper_neon_qzip32(tmp, tmp2);
3719 break;
3720 default:
3721 abort();
3722 }
3723 } else {
3724 switch (size) {
3725 case 0:
3726 gen_helper_neon_zip8(tmp, tmp2);
3727 break;
3728 case 1:
3729 gen_helper_neon_zip16(tmp, tmp2);
3730 break;
3731 default:
3732 abort();
3733 }
3734 }
3735 tcg_temp_free_i32(tmp);
3736 tcg_temp_free_i32(tmp2);
3737 return 0;
3738 }
3739
3740 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3741 {
3742 TCGv rd, tmp;
3743
3744 rd = tcg_temp_new_i32();
3745 tmp = tcg_temp_new_i32();
3746
3747 tcg_gen_shli_i32(rd, t0, 8);
3748 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3749 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3750 tcg_gen_or_i32(rd, rd, tmp);
3751
3752 tcg_gen_shri_i32(t1, t1, 8);
3753 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3754 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3755 tcg_gen_or_i32(t1, t1, tmp);
3756 tcg_gen_mov_i32(t0, rd);
3757
3758 tcg_temp_free_i32(tmp);
3759 tcg_temp_free_i32(rd);
3760 }
3761
3762 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3763 {
3764 TCGv rd, tmp;
3765
3766 rd = tcg_temp_new_i32();
3767 tmp = tcg_temp_new_i32();
3768
3769 tcg_gen_shli_i32(rd, t0, 16);
3770 tcg_gen_andi_i32(tmp, t1, 0xffff);
3771 tcg_gen_or_i32(rd, rd, tmp);
3772 tcg_gen_shri_i32(t1, t1, 16);
3773 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3774 tcg_gen_or_i32(t1, t1, tmp);
3775 tcg_gen_mov_i32(t0, rd);
3776
3777 tcg_temp_free_i32(tmp);
3778 tcg_temp_free_i32(rd);
3779 }
3780
3781
3782 static struct {
3783 int nregs;
3784 int interleave;
3785 int spacing;
3786 } neon_ls_element_type[11] = {
3787 {4, 4, 1},
3788 {4, 4, 2},
3789 {4, 1, 1},
3790 {4, 2, 1},
3791 {3, 3, 1},
3792 {3, 3, 2},
3793 {3, 1, 1},
3794 {1, 1, 1},
3795 {2, 2, 1},
3796 {2, 2, 2},
3797 {2, 1, 1}
3798 };
3799
3800 /* Translate a NEON load/store element instruction. Return nonzero if the
3801 instruction is invalid. */
3802 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3803 {
3804 int rd, rn, rm;
3805 int op;
3806 int nregs;
3807 int interleave;
3808 int spacing;
3809 int stride;
3810 int size;
3811 int reg;
3812 int pass;
3813 int load;
3814 int shift;
3815 int n;
3816 TCGv addr;
3817 TCGv tmp;
3818 TCGv tmp2;
3819 TCGv_i64 tmp64;
3820
3821 if (!s->vfp_enabled)
3822 return 1;
3823 VFP_DREG_D(rd, insn);
3824 rn = (insn >> 16) & 0xf;
3825 rm = insn & 0xf;
3826 load = (insn & (1 << 21)) != 0;
3827 if ((insn & (1 << 23)) == 0) {
3828 /* Load store all elements. */
3829 op = (insn >> 8) & 0xf;
3830 size = (insn >> 6) & 3;
3831 if (op > 10)
3832 return 1;
3833 nregs = neon_ls_element_type[op].nregs;
3834 interleave = neon_ls_element_type[op].interleave;
3835 spacing = neon_ls_element_type[op].spacing;
3836 if (size == 3 && (interleave | spacing) != 1)
3837 return 1;
3838 addr = tcg_temp_new_i32();
3839 load_reg_var(s, addr, rn);
3840 stride = (1 << size) * interleave;
3841 for (reg = 0; reg < nregs; reg++) {
3842 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3843 load_reg_var(s, addr, rn);
3844 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3845 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3846 load_reg_var(s, addr, rn);
3847 tcg_gen_addi_i32(addr, addr, 1 << size);
3848 }
3849 if (size == 3) {
3850 if (load) {
3851 tmp64 = gen_ld64(addr, IS_USER(s));
3852 neon_store_reg64(tmp64, rd);
3853 tcg_temp_free_i64(tmp64);
3854 } else {
3855 tmp64 = tcg_temp_new_i64();
3856 neon_load_reg64(tmp64, rd);
3857 gen_st64(tmp64, addr, IS_USER(s));
3858 }
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 } else {
3861 for (pass = 0; pass < 2; pass++) {
3862 if (size == 2) {
3863 if (load) {
3864 tmp = gen_ld32(addr, IS_USER(s));
3865 neon_store_reg(rd, pass, tmp);
3866 } else {
3867 tmp = neon_load_reg(rd, pass);
3868 gen_st32(tmp, addr, IS_USER(s));
3869 }
3870 tcg_gen_addi_i32(addr, addr, stride);
3871 } else if (size == 1) {
3872 if (load) {
3873 tmp = gen_ld16u(addr, IS_USER(s));
3874 tcg_gen_addi_i32(addr, addr, stride);
3875 tmp2 = gen_ld16u(addr, IS_USER(s));
3876 tcg_gen_addi_i32(addr, addr, stride);
3877 tcg_gen_shli_i32(tmp2, tmp2, 16);
3878 tcg_gen_or_i32(tmp, tmp, tmp2);
3879 tcg_temp_free_i32(tmp2);
3880 neon_store_reg(rd, pass, tmp);
3881 } else {
3882 tmp = neon_load_reg(rd, pass);
3883 tmp2 = tcg_temp_new_i32();
3884 tcg_gen_shri_i32(tmp2, tmp, 16);
3885 gen_st16(tmp, addr, IS_USER(s));
3886 tcg_gen_addi_i32(addr, addr, stride);
3887 gen_st16(tmp2, addr, IS_USER(s));
3888 tcg_gen_addi_i32(addr, addr, stride);
3889 }
3890 } else /* size == 0 */ {
3891 if (load) {
3892 TCGV_UNUSED(tmp2);
3893 for (n = 0; n < 4; n++) {
3894 tmp = gen_ld8u(addr, IS_USER(s));
3895 tcg_gen_addi_i32(addr, addr, stride);
3896 if (n == 0) {
3897 tmp2 = tmp;
3898 } else {
3899 tcg_gen_shli_i32(tmp, tmp, n * 8);
3900 tcg_gen_or_i32(tmp2, tmp2, tmp);
3901 tcg_temp_free_i32(tmp);
3902 }
3903 }
3904 neon_store_reg(rd, pass, tmp2);
3905 } else {
3906 tmp2 = neon_load_reg(rd, pass);
3907 for (n = 0; n < 4; n++) {
3908 tmp = tcg_temp_new_i32();
3909 if (n == 0) {
3910 tcg_gen_mov_i32(tmp, tmp2);
3911 } else {
3912 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3913 }
3914 gen_st8(tmp, addr, IS_USER(s));
3915 tcg_gen_addi_i32(addr, addr, stride);
3916 }
3917 tcg_temp_free_i32(tmp2);
3918 }
3919 }
3920 }
3921 }
3922 rd += spacing;
3923 }
3924 tcg_temp_free_i32(addr);
3925 stride = nregs * 8;
3926 } else {
3927 size = (insn >> 10) & 3;
3928 if (size == 3) {
3929 /* Load single element to all lanes. */
3930 int a = (insn >> 4) & 1;
3931 if (!load) {
3932 return 1;
3933 }
3934 size = (insn >> 6) & 3;
3935 nregs = ((insn >> 8) & 3) + 1;
3936
3937 if (size == 3) {
3938 if (nregs != 4 || a == 0) {
3939 return 1;
3940 }
3941 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3942 size = 2;
3943 }
3944 if (nregs == 1 && a == 1 && size == 0) {
3945 return 1;
3946 }
3947 if (nregs == 3 && a == 1) {
3948 return 1;
3949 }
3950 addr = tcg_temp_new_i32();
3951 load_reg_var(s, addr, rn);
3952 if (nregs == 1) {
3953 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3954 tmp = gen_load_and_replicate(s, addr, size);
3955 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3956 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3957 if (insn & (1 << 5)) {
3958 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3959 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3960 }
3961 tcg_temp_free_i32(tmp);
3962 } else {
3963 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3964 stride = (insn & (1 << 5)) ? 2 : 1;
3965 for (reg = 0; reg < nregs; reg++) {
3966 tmp = gen_load_and_replicate(s, addr, size);
3967 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3968 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3969 tcg_temp_free_i32(tmp);
3970 tcg_gen_addi_i32(addr, addr, 1 << size);
3971 rd += stride;
3972 }
3973 }
3974 tcg_temp_free_i32(addr);
3975 stride = (1 << size) * nregs;
3976 } else {
3977 /* Single element. */
3978 pass = (insn >> 7) & 1;
3979 switch (size) {
3980 case 0:
3981 shift = ((insn >> 5) & 3) * 8;
3982 stride = 1;
3983 break;
3984 case 1:
3985 shift = ((insn >> 6) & 1) * 16;
3986 stride = (insn & (1 << 5)) ? 2 : 1;
3987 break;
3988 case 2:
3989 shift = 0;
3990 stride = (insn & (1 << 6)) ? 2 : 1;
3991 break;
3992 default:
3993 abort();
3994 }
3995 nregs = ((insn >> 8) & 3) + 1;
3996 addr = tcg_temp_new_i32();
3997 load_reg_var(s, addr, rn);
3998 for (reg = 0; reg < nregs; reg++) {
3999 if (load) {
4000 switch (size) {
4001 case 0:
4002 tmp = gen_ld8u(addr, IS_USER(s));
4003 break;
4004 case 1:
4005 tmp = gen_ld16u(addr, IS_USER(s));
4006 break;
4007 case 2:
4008 tmp = gen_ld32(addr, IS_USER(s));
4009 break;
4010 default: /* Avoid compiler warnings. */
4011 abort();
4012 }
4013 if (size != 2) {
4014 tmp2 = neon_load_reg(rd, pass);
4015 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
4016 tcg_temp_free_i32(tmp2);
4017 }
4018 neon_store_reg(rd, pass, tmp);
4019 } else { /* Store */
4020 tmp = neon_load_reg(rd, pass);
4021 if (shift)
4022 tcg_gen_shri_i32(tmp, tmp, shift);
4023 switch (size) {
4024 case 0:
4025 gen_st8(tmp, addr, IS_USER(s));
4026 break;
4027 case 1:
4028 gen_st16(tmp, addr, IS_USER(s));
4029 break;
4030 case 2:
4031 gen_st32(tmp, addr, IS_USER(s));
4032 break;
4033 }
4034 }
4035 rd += stride;
4036 tcg_gen_addi_i32(addr, addr, 1 << size);
4037 }
4038 tcg_temp_free_i32(addr);
4039 stride = nregs * (1 << size);
4040 }
4041 }
4042 if (rm != 15) {
4043 TCGv base;
4044
4045 base = load_reg(s, rn);
4046 if (rm == 13) {
4047 tcg_gen_addi_i32(base, base, stride);
4048 } else {
4049 TCGv index;
4050 index = load_reg(s, rm);
4051 tcg_gen_add_i32(base, base, index);
4052 tcg_temp_free_i32(index);
4053 }
4054 store_reg(s, rn, base);
4055 }
4056 return 0;
4057 }
4058
4059 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4060 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4061 {
4062 tcg_gen_and_i32(t, t, c);
4063 tcg_gen_andc_i32(f, f, c);
4064 tcg_gen_or_i32(dest, t, f);
4065 }
4066
4067 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4068 {
4069 switch (size) {
4070 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4071 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4072 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4073 default: abort();
4074 }
4075 }
4076
4077 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4078 {
4079 switch (size) {
4080 case 0: gen_helper_neon_narrow_sat_s8(dest, src); break;
4081 case 1: gen_helper_neon_narrow_sat_s16(dest, src); break;
4082 case 2: gen_helper_neon_narrow_sat_s32(dest, src); break;
4083 default: abort();
4084 }
4085 }
4086
4087 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4088 {
4089 switch (size) {
4090 case 0: gen_helper_neon_narrow_sat_u8(dest, src); break;
4091 case 1: gen_helper_neon_narrow_sat_u16(dest, src); break;
4092 case 2: gen_helper_neon_narrow_sat_u32(dest, src); break;
4093 default: abort();
4094 }
4095 }
4096
4097 static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4098 {
4099 switch (size) {
4100 case 0: gen_helper_neon_unarrow_sat8(dest, src); break;
4101 case 1: gen_helper_neon_unarrow_sat16(dest, src); break;
4102 case 2: gen_helper_neon_unarrow_sat32(dest, src); break;
4103 default: abort();
4104 }
4105 }
4106
4107 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4108 int q, int u)
4109 {
4110 if (q) {
4111 if (u) {
4112 switch (size) {
4113 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4114 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4115 default: abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4120 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4121 default: abort();
4122 }
4123 }
4124 } else {
4125 if (u) {
4126 switch (size) {
4127 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4128 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4129 default: abort();
4130 }
4131 } else {
4132 switch (size) {
4133 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4134 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4135 default: abort();
4136 }
4137 }
4138 }
4139 }
4140
4141 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4142 {
4143 if (u) {
4144 switch (size) {
4145 case 0: gen_helper_neon_widen_u8(dest, src); break;
4146 case 1: gen_helper_neon_widen_u16(dest, src); break;
4147 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4148 default: abort();
4149 }
4150 } else {
4151 switch (size) {
4152 case 0: gen_helper_neon_widen_s8(dest, src); break;
4153 case 1: gen_helper_neon_widen_s16(dest, src); break;
4154 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4155 default: abort();
4156 }
4157 }
4158 tcg_temp_free_i32(src);
4159 }
4160
4161 static inline void gen_neon_addl(int size)
4162 {
4163 switch (size) {
4164 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4165 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4166 case 2: tcg_gen_add_i64(CPU_V001); break;
4167 default: abort();
4168 }
4169 }
4170
4171 static inline void gen_neon_subl(int size)
4172 {
4173 switch (size) {
4174 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4175 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4176 case 2: tcg_gen_sub_i64(CPU_V001); break;
4177 default: abort();
4178 }
4179 }
4180
4181 static inline void gen_neon_negl(TCGv_i64 var, int size)
4182 {
4183 switch (size) {
4184 case 0: gen_helper_neon_negl_u16(var, var); break;
4185 case 1: gen_helper_neon_negl_u32(var, var); break;
4186 case 2: gen_helper_neon_negl_u64(var, var); break;
4187 default: abort();
4188 }
4189 }
4190
4191 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4192 {
4193 switch (size) {
4194 case 1: gen_helper_neon_addl_saturate_s32(op0, op0, op1); break;
4195 case 2: gen_helper_neon_addl_saturate_s64(op0, op0, op1); break;
4196 default: abort();
4197 }
4198 }
4199
4200 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4201 {
4202 TCGv_i64 tmp;
4203
4204 switch ((size << 1) | u) {
4205 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4206 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4207 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4208 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4209 case 4:
4210 tmp = gen_muls_i64_i32(a, b);
4211 tcg_gen_mov_i64(dest, tmp);
4212 tcg_temp_free_i64(tmp);
4213 break;
4214 case 5:
4215 tmp = gen_mulu_i64_i32(a, b);
4216 tcg_gen_mov_i64(dest, tmp);
4217 tcg_temp_free_i64(tmp);
4218 break;
4219 default: abort();
4220 }
4221
4222 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4223 Don't forget to clean them now. */
4224 if (size < 2) {
4225 tcg_temp_free_i32(a);
4226 tcg_temp_free_i32(b);
4227 }
4228 }
4229
4230 static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4231 {
4232 if (op) {
4233 if (u) {
4234 gen_neon_unarrow_sats(size, dest, src);
4235 } else {
4236 gen_neon_narrow(size, dest, src);
4237 }
4238 } else {
4239 if (u) {
4240 gen_neon_narrow_satu(size, dest, src);
4241 } else {
4242 gen_neon_narrow_sats(size, dest, src);
4243 }
4244 }
4245 }
4246
4247 /* Symbolic constants for op fields for Neon 3-register same-length.
4248 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4249 * table A7-9.
4250 */
4251 #define NEON_3R_VHADD 0
4252 #define NEON_3R_VQADD 1
4253 #define NEON_3R_VRHADD 2
4254 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4255 #define NEON_3R_VHSUB 4
4256 #define NEON_3R_VQSUB 5
4257 #define NEON_3R_VCGT 6
4258 #define NEON_3R_VCGE 7
4259 #define NEON_3R_VSHL 8
4260 #define NEON_3R_VQSHL 9
4261 #define NEON_3R_VRSHL 10
4262 #define NEON_3R_VQRSHL 11
4263 #define NEON_3R_VMAX 12
4264 #define NEON_3R_VMIN 13
4265 #define NEON_3R_VABD 14
4266 #define NEON_3R_VABA 15
4267 #define NEON_3R_VADD_VSUB 16
4268 #define NEON_3R_VTST_VCEQ 17
4269 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4270 #define NEON_3R_VMUL 19
4271 #define NEON_3R_VPMAX 20
4272 #define NEON_3R_VPMIN 21
4273 #define NEON_3R_VQDMULH_VQRDMULH 22
4274 #define NEON_3R_VPADD 23
4275 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4276 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4277 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4278 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4279 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4280 #define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
4281
4282 static const uint8_t neon_3r_sizes[] = {
4283 [NEON_3R_VHADD] = 0x7,
4284 [NEON_3R_VQADD] = 0xf,
4285 [NEON_3R_VRHADD] = 0x7,
4286 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4287 [NEON_3R_VHSUB] = 0x7,
4288 [NEON_3R_VQSUB] = 0xf,
4289 [NEON_3R_VCGT] = 0x7,
4290 [NEON_3R_VCGE] = 0x7,
4291 [NEON_3R_VSHL] = 0xf,
4292 [NEON_3R_VQSHL] = 0xf,
4293 [NEON_3R_VRSHL] = 0xf,
4294 [NEON_3R_VQRSHL] = 0xf,
4295 [NEON_3R_VMAX] = 0x7,
4296 [NEON_3R_VMIN] = 0x7,
4297 [NEON_3R_VABD] = 0x7,
4298 [NEON_3R_VABA] = 0x7,
4299 [NEON_3R_VADD_VSUB] = 0xf,
4300 [NEON_3R_VTST_VCEQ] = 0x7,
4301 [NEON_3R_VML] = 0x7,
4302 [NEON_3R_VMUL] = 0x7,
4303 [NEON_3R_VPMAX] = 0x7,
4304 [NEON_3R_VPMIN] = 0x7,
4305 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
4306 [NEON_3R_VPADD] = 0x7,
4307 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4308 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4309 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4310 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4311 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4312 [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
4313 };
4314
4315 /* Translate a NEON data processing instruction. Return nonzero if the
4316 instruction is invalid.
4317 We process data in a mixture of 32-bit and 64-bit chunks.
4318 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4319
4320 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4321 {
4322 int op;
4323 int q;
4324 int rd, rn, rm;
4325 int size;
4326 int shift;
4327 int pass;
4328 int count;
4329 int pairwise;
4330 int u;
4331 int n;
4332 uint32_t imm, mask;
4333 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4334 TCGv_i64 tmp64;
4335
4336 if (!s->vfp_enabled)
4337 return 1;
4338 q = (insn & (1 << 6)) != 0;
4339 u = (insn >> 24) & 1;
4340 VFP_DREG_D(rd, insn);
4341 VFP_DREG_N(rn, insn);
4342 VFP_DREG_M(rm, insn);
4343 size = (insn >> 20) & 3;
4344 if ((insn & (1 << 23)) == 0) {
4345 /* Three register same length. */
4346 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4347 /* Catch invalid op and bad size combinations: UNDEF */
4348 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4349 return 1;
4350 }
4351 if (size == 3 && op != NEON_3R_LOGIC) {
4352 /* 64-bit element instructions. */
4353 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4354 neon_load_reg64(cpu_V0, rn + pass);
4355 neon_load_reg64(cpu_V1, rm + pass);
4356 switch (op) {
4357 case NEON_3R_VQADD:
4358 if (u) {
4359 gen_helper_neon_qadd_u64(cpu_V0, cpu_V0, cpu_V1);
4360 } else {
4361 gen_helper_neon_qadd_s64(cpu_V0, cpu_V0, cpu_V1);
4362 }
4363 break;
4364 case NEON_3R_VQSUB:
4365 if (u) {
4366 gen_helper_neon_qsub_u64(cpu_V0, cpu_V0, cpu_V1);
4367 } else {
4368 gen_helper_neon_qsub_s64(cpu_V0, cpu_V0, cpu_V1);
4369 }
4370 break;
4371 case NEON_3R_VSHL:
4372 if (u) {
4373 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4374 } else {
4375 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4376 }
4377 break;
4378 case NEON_3R_VQSHL:
4379 if (u) {
4380 gen_helper_neon_qshl_u64(cpu_V0, cpu_V1, cpu_V0);
4381 } else {
4382 gen_helper_neon_qshl_s64(cpu_V0, cpu_V1, cpu_V0);
4383 }
4384 break;
4385 case NEON_3R_VRSHL:
4386 if (u) {
4387 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4388 } else {
4389 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4390 }
4391 break;
4392 case NEON_3R_VQRSHL:
4393 if (u) {
4394 gen_helper_neon_qrshl_u64(cpu_V0, cpu_V1, cpu_V0);
4395 } else {
4396 gen_helper_neon_qrshl_s64(cpu_V0, cpu_V1, cpu_V0);
4397 }
4398 break;
4399 case NEON_3R_VADD_VSUB:
4400 if (u) {
4401 tcg_gen_sub_i64(CPU_V001);
4402 } else {
4403 tcg_gen_add_i64(CPU_V001);
4404 }
4405 break;
4406 default:
4407 abort();
4408 }
4409 neon_store_reg64(cpu_V0, rd + pass);
4410 }
4411 return 0;
4412 }
4413 switch (op) {
4414 case NEON_3R_VSHL:
4415 case NEON_3R_VQSHL:
4416 case NEON_3R_VRSHL:
4417 case NEON_3R_VQRSHL:
4418 {
4419 int rtmp;
4420 /* Shift instruction operands are reversed. */
4421 rtmp = rn;
4422 rn = rm;
4423 rm = rtmp;
4424 pairwise = 0;
4425 }
4426 break;
4427 case NEON_3R_VPMAX:
4428 case NEON_3R_VPMIN:
4429 case NEON_3R_VPADD:
4430 pairwise = 1;
4431 break;
4432 case NEON_3R_FLOAT_ARITH: /* VADD, VSUB, VPADD, VABD (float) */
4433 pairwise = (u && size < 2);
4434 break;
4435 case NEON_3R_FLOAT_MINMAX: /* VPMIN/VPMAX (float) */
4436 pairwise = u;
4437 break;
4438 default:
4439 pairwise = 0;
4440 break;
4441 }
4442
4443 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4444
4445 if (pairwise) {
4446 /* Pairwise. */
4447 if (q)
4448 n = (pass & 1) * 2;
4449 else
4450 n = 0;
4451 if (pass < q + 1) {
4452 tmp = neon_load_reg(rn, n);
4453 tmp2 = neon_load_reg(rn, n + 1);
4454 } else {
4455 tmp = neon_load_reg(rm, n);
4456 tmp2 = neon_load_reg(rm, n + 1);
4457 }
4458 } else {
4459 /* Elementwise. */
4460 tmp = neon_load_reg(rn, pass);
4461 tmp2 = neon_load_reg(rm, pass);
4462 }
4463 switch (op) {
4464 case NEON_3R_VHADD:
4465 GEN_NEON_INTEGER_OP(hadd);
4466 break;
4467 case NEON_3R_VQADD:
4468 GEN_NEON_INTEGER_OP(qadd);
4469 break;
4470 case NEON_3R_VRHADD:
4471 GEN_NEON_INTEGER_OP(rhadd);
4472 break;
4473 case NEON_3R_LOGIC: /* Logic ops. */
4474 switch ((u << 2) | size) {
4475 case 0: /* VAND */
4476 tcg_gen_and_i32(tmp, tmp, tmp2);
4477 break;
4478 case 1: /* BIC */
4479 tcg_gen_andc_i32(tmp, tmp, tmp2);
4480 break;
4481 case 2: /* VORR */
4482 tcg_gen_or_i32(tmp, tmp, tmp2);
4483 break;
4484 case 3: /* VORN */
4485 tcg_gen_orc_i32(tmp, tmp, tmp2);
4486 break;
4487 case 4: /* VEOR */
4488 tcg_gen_xor_i32(tmp, tmp, tmp2);
4489 break;
4490 case 5: /* VBSL */
4491 tmp3 = neon_load_reg(rd, pass);
4492 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4493 tcg_temp_free_i32(tmp3);
4494 break;
4495 case 6: /* VBIT */
4496 tmp3 = neon_load_reg(rd, pass);
4497 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4498 tcg_temp_free_i32(tmp3);
4499 break;
4500 case 7: /* VBIF */
4501 tmp3 = neon_load_reg(rd, pass);
4502 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4503 tcg_temp_free_i32(tmp3);
4504 break;
4505 }
4506 break;
4507 case NEON_3R_VHSUB:
4508 GEN_NEON_INTEGER_OP(hsub);
4509 break;
4510 case NEON_3R_VQSUB:
4511 GEN_NEON_INTEGER_OP(qsub);
4512 break;
4513 case NEON_3R_VCGT:
4514 GEN_NEON_INTEGER_OP(cgt);
4515 break;
4516 case NEON_3R_VCGE:
4517 GEN_NEON_INTEGER_OP(cge);
4518 break;
4519 case NEON_3R_VSHL:
4520 GEN_NEON_INTEGER_OP(shl);
4521 break;
4522 case NEON_3R_VQSHL:
4523 GEN_NEON_INTEGER_OP(qshl);
4524 break;
4525 case NEON_3R_VRSHL:
4526 GEN_NEON_INTEGER_OP(rshl);
4527 break;
4528 case NEON_3R_VQRSHL:
4529 GEN_NEON_INTEGER_OP(qrshl);
4530 break;
4531 case NEON_3R_VMAX:
4532 GEN_NEON_INTEGER_OP(max);
4533 break;
4534 case NEON_3R_VMIN:
4535 GEN_NEON_INTEGER_OP(min);
4536 break;
4537 case NEON_3R_VABD:
4538 GEN_NEON_INTEGER_OP(abd);
4539 break;
4540 case NEON_3R_VABA:
4541 GEN_NEON_INTEGER_OP(abd);
4542 tcg_temp_free_i32(tmp2);
4543 tmp2 = neon_load_reg(rd, pass);
4544 gen_neon_add(size, tmp, tmp2);
4545 break;
4546 case NEON_3R_VADD_VSUB:
4547 if (!u) { /* VADD */
4548 gen_neon_add(size, tmp, tmp2);
4549 } else { /* VSUB */
4550 switch (size) {
4551 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4552 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4553 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4554 default: abort();
4555 }
4556 }
4557 break;
4558 case NEON_3R_VTST_VCEQ:
4559 if (!u) { /* VTST */
4560 switch (size) {
4561 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4562 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4563 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4564 default: abort();
4565 }
4566 } else { /* VCEQ */
4567 switch (size) {
4568 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4569 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4570 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4571 default: abort();
4572 }
4573 }
4574 break;
4575 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
4576 switch (size) {
4577 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4578 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4579 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4580 default: abort();
4581 }
4582 tcg_temp_free_i32(tmp2);
4583 tmp2 = neon_load_reg(rd, pass);
4584 if (u) { /* VMLS */
4585 gen_neon_rsb(size, tmp, tmp2);
4586 } else { /* VMLA */
4587 gen_neon_add(size, tmp, tmp2);
4588 }
4589 break;
4590 case NEON_3R_VMUL:
4591 if (u) { /* polynomial */
4592 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4593 } else { /* Integer */
4594 switch (size) {
4595 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4596 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4597 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4598 default: abort();
4599 }
4600 }
4601 break;
4602 case NEON_3R_VPMAX:
4603 GEN_NEON_INTEGER_OP(pmax);
4604 break;
4605 case NEON_3R_VPMIN:
4606 GEN_NEON_INTEGER_OP(pmin);
4607 break;
4608 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
4609 if (!u) { /* VQDMULH */
4610 switch (size) {
4611 case 1: gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); break;
4612 case 2: gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); break;
4613 default: abort();
4614 }
4615 } else { /* VQRDMULH */
4616 switch (size) {
4617 case 1: gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); break;
4618 case 2: gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); break;
4619 default: abort();
4620 }
4621 }
4622 break;
4623 case NEON_3R_VPADD:
4624 if (u)
4625 return 1;
4626 switch (size) {
4627 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4628 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4629 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4630 default: abort();
4631 }
4632 break;
4633 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
4634 switch ((u << 2) | size) {
4635 case 0: /* VADD */
4636 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4637 break;
4638 case 2: /* VSUB */
4639 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4640 break;
4641 case 4: /* VPADD */
4642 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4643 break;
4644 case 6: /* VABD */
4645 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4646 break;
4647 default:
4648 abort();
4649 }
4650 break;
4651 case NEON_3R_FLOAT_MULTIPLY:
4652 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4653 if (!u) {
4654 tcg_temp_free_i32(tmp2);
4655 tmp2 = neon_load_reg(rd, pass);
4656 if (size == 0) {
4657 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4658 } else {
4659 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4660 }
4661 }
4662 break;
4663 case NEON_3R_FLOAT_CMP:
4664 if (!u) {
4665 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4666 } else {
4667 if (size == 0)
4668 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4669 else
4670 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4671 }
4672 break;
4673 case NEON_3R_FLOAT_ACMP:
4674 if (!u)
4675 return 1;
4676 if (size == 0)
4677 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4678 else
4679 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4680 break;
4681 case NEON_3R_FLOAT_MINMAX:
4682 if (size == 0)
4683 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4684 else
4685 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4686 break;
4687 case NEON_3R_VRECPS_VRSQRTS:
4688 if (size == 0)
4689 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4690 else
4691 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4692 break;
4693 default:
4694 abort();
4695 }
4696 tcg_temp_free_i32(tmp2);
4697
4698 /* Save the result. For elementwise operations we can put it
4699 straight into the destination register. For pairwise operations
4700 we have to be careful to avoid clobbering the source operands. */
4701 if (pairwise && rd == rm) {
4702 neon_store_scratch(pass, tmp);
4703 } else {
4704 neon_store_reg(rd, pass, tmp);
4705 }
4706
4707 } /* for pass */
4708 if (pairwise && rd == rm) {
4709 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4710 tmp = neon_load_scratch(pass);
4711 neon_store_reg(rd, pass, tmp);
4712 }
4713 }
4714 /* End of 3 register same size operations. */
4715 } else if (insn & (1 << 4)) {
4716 if ((insn & 0x00380080) != 0) {
4717 /* Two registers and shift. */
4718 op = (insn >> 8) & 0xf;
4719 if (insn & (1 << 7)) {
4720 /* 64-bit shift. */
4721 size = 3;
4722 } else {
4723 size = 2;
4724 while ((insn & (1 << (size + 19))) == 0)
4725 size--;
4726 }
4727 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4728 /* To avoid excessive dumplication of ops we implement shift
4729 by immediate using the variable shift operations. */
4730 if (op < 8) {
4731 /* Shift by immediate:
4732 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4733 /* Right shifts are encoded as N - shift, where N is the
4734 element size in bits. */
4735 if (op <= 4)
4736 shift = shift - (1 << (size + 3));
4737 if (size == 3) {
4738 count = q + 1;
4739 } else {
4740 count = q ? 4: 2;
4741 }
4742 switch (size) {
4743 case 0:
4744 imm = (uint8_t) shift;
4745 imm |= imm << 8;
4746 imm |= imm << 16;
4747 break;
4748 case 1:
4749 imm = (uint16_t) shift;
4750 imm |= imm << 16;
4751 break;
4752 case 2:
4753 case 3:
4754 imm = shift;
4755 break;
4756 default:
4757 abort();
4758 }
4759
4760 for (pass = 0; pass < count; pass++) {
4761 if (size == 3) {
4762 neon_load_reg64(cpu_V0, rm + pass);
4763 tcg_gen_movi_i64(cpu_V1, imm);
4764 switch (op) {
4765 case 0: /* VSHR */
4766 case 1: /* VSRA */
4767 if (u)
4768 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4769 else
4770 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4771 break;
4772 case 2: /* VRSHR */
4773 case 3: /* VRSRA */
4774 if (u)
4775 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4776 else
4777 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4778 break;
4779 case 4: /* VSRI */
4780 if (!u)
4781 return 1;
4782 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4783 break;
4784 case 5: /* VSHL, VSLI */
4785 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4786 break;
4787 case 6: /* VQSHLU */
4788 if (u) {
4789 gen_helper_neon_qshlu_s64(cpu_V0,
4790 cpu_V0, cpu_V1);
4791 } else {
4792 return 1;
4793 }
4794 break;
4795 case 7: /* VQSHL */
4796 if (u) {
4797 gen_helper_neon_qshl_u64(cpu_V0,
4798 cpu_V0, cpu_V1);
4799 } else {
4800 gen_helper_neon_qshl_s64(cpu_V0,
4801 cpu_V0, cpu_V1);
4802 }
4803 break;
4804 }
4805 if (op == 1 || op == 3) {
4806 /* Accumulate. */
4807 neon_load_reg64(cpu_V1, rd + pass);
4808 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4809 } else if (op == 4 || (op == 5 && u)) {
4810 /* Insert */
4811 neon_load_reg64(cpu_V1, rd + pass);
4812 uint64_t mask;
4813 if (shift < -63 || shift > 63) {
4814 mask = 0;
4815 } else {
4816 if (op == 4) {
4817 mask = 0xffffffffffffffffull >> -shift;
4818 } else {
4819 mask = 0xffffffffffffffffull << shift;
4820 }
4821 }
4822 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4823 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
4824 }
4825 neon_store_reg64(cpu_V0, rd + pass);
4826 } else { /* size < 3 */
4827 /* Operands in T0 and T1. */
4828 tmp = neon_load_reg(rm, pass);
4829 tmp2 = tcg_temp_new_i32();
4830 tcg_gen_movi_i32(tmp2, imm);
4831 switch (op) {
4832 case 0: /* VSHR */
4833 case 1: /* VSRA */
4834 GEN_NEON_INTEGER_OP(shl);
4835 break;
4836 case 2: /* VRSHR */
4837 case 3: /* VRSRA */
4838 GEN_NEON_INTEGER_OP(rshl);
4839 break;
4840 case 4: /* VSRI */
4841 if (!u)
4842 return 1;
4843 GEN_NEON_INTEGER_OP(shl);
4844 break;
4845 case 5: /* VSHL, VSLI */
4846 switch (size) {
4847 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4848 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4849 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4850 default: return 1;
4851 }
4852 break;
4853 case 6: /* VQSHLU */
4854 if (!u) {
4855 return 1;
4856 }
4857 switch (size) {
4858 case 0:
4859 gen_helper_neon_qshlu_s8(tmp, tmp, tmp2);
4860 break;
4861 case 1:
4862 gen_helper_neon_qshlu_s16(tmp, tmp, tmp2);
4863 break;
4864 case 2:
4865 gen_helper_neon_qshlu_s32(tmp, tmp, tmp2);
4866 break;
4867 default:
4868 return 1;
4869 }
4870 break;
4871 case 7: /* VQSHL */
4872 GEN_NEON_INTEGER_OP(qshl);
4873 break;
4874 }
4875 tcg_temp_free_i32(tmp2);
4876
4877 if (op == 1 || op == 3) {
4878 /* Accumulate. */
4879 tmp2 = neon_load_reg(rd, pass);
4880 gen_neon_add(size, tmp, tmp2);
4881 tcg_temp_free_i32(tmp2);
4882 } else if (op == 4 || (op == 5 && u)) {
4883 /* Insert */
4884 switch (size) {
4885 case 0:
4886 if (op == 4)
4887 mask = 0xff >> -shift;
4888 else
4889 mask = (uint8_t)(0xff << shift);
4890 mask |= mask << 8;
4891 mask |= mask << 16;
4892 break;
4893 case 1:
4894 if (op == 4)
4895 mask = 0xffff >> -shift;
4896 else
4897 mask = (uint16_t)(0xffff << shift);
4898 mask |= mask << 16;
4899 break;
4900 case 2:
4901 if (shift < -31 || shift > 31) {
4902 mask = 0;
4903 } else {
4904 if (op == 4)
4905 mask = 0xffffffffu >> -shift;
4906 else
4907 mask = 0xffffffffu << shift;
4908 }
4909 break;
4910 default:
4911 abort();
4912 }
4913 tmp2 = neon_load_reg(rd, pass);
4914 tcg_gen_andi_i32(tmp, tmp, mask);
4915 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
4916 tcg_gen_or_i32(tmp, tmp, tmp2);
4917 tcg_temp_free_i32(tmp2);
4918 }
4919 neon_store_reg(rd, pass, tmp);
4920 }
4921 } /* for pass */
4922 } else if (op < 10) {
4923 /* Shift by immediate and narrow:
4924 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4925 int input_unsigned = (op == 8) ? !u : u;
4926
4927 shift = shift - (1 << (size + 3));
4928 size++;
4929 if (size == 3) {
4930 tmp64 = tcg_const_i64(shift);
4931 neon_load_reg64(cpu_V0, rm);
4932 neon_load_reg64(cpu_V1, rm + 1);
4933 for (pass = 0; pass < 2; pass++) {
4934 TCGv_i64 in;
4935 if (pass == 0) {
4936 in = cpu_V0;
4937 } else {
4938 in = cpu_V1;
4939 }
4940 if (q) {
4941 if (input_unsigned) {
4942 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
4943 } else {
4944 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
4945 }
4946 } else {
4947 if (input_unsigned) {
4948 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
4949 } else {
4950 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
4951 }
4952 }
4953 tmp = tcg_temp_new_i32();
4954 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4955 neon_store_reg(rd, pass, tmp);
4956 } /* for pass */
4957 tcg_temp_free_i64(tmp64);
4958 } else {
4959 if (size == 1) {
4960 imm = (uint16_t)shift;
4961 imm |= imm << 16;
4962 } else {
4963 /* size == 2 */
4964 imm = (uint32_t)shift;
4965 }
4966 tmp2 = tcg_const_i32(imm);
4967 tmp4 = neon_load_reg(rm + 1, 0);
4968 tmp5 = neon_load_reg(rm + 1, 1);
4969 for (pass = 0; pass < 2; pass++) {
4970 if (pass == 0) {
4971 tmp = neon_load_reg(rm, 0);
4972 } else {
4973 tmp = tmp4;
4974 }
4975 gen_neon_shift_narrow(size, tmp, tmp2, q,
4976 input_unsigned);
4977 if (pass == 0) {
4978 tmp3 = neon_load_reg(rm, 1);
4979 } else {
4980 tmp3 = tmp5;
4981 }
4982 gen_neon_shift_narrow(size, tmp3, tmp2, q,
4983 input_unsigned);
4984 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4985 tcg_temp_free_i32(tmp);
4986 tcg_temp_free_i32(tmp3);
4987 tmp = tcg_temp_new_i32();
4988 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4989 neon_store_reg(rd, pass, tmp);
4990 } /* for pass */
4991 tcg_temp_free_i32(tmp2);
4992 }
4993 } else if (op == 10) {
4994 /* VSHLL */
4995 if (q || size == 3)
4996 return 1;
4997 tmp = neon_load_reg(rm, 0);
4998 tmp2 = neon_load_reg(rm, 1);
4999 for (pass = 0; pass < 2; pass++) {
5000 if (pass == 1)
5001 tmp = tmp2;
5002
5003 gen_neon_widen(cpu_V0, tmp, size, u);
5004
5005 if (shift != 0) {
5006 /* The shift is less than the width of the source
5007 type, so we can just shift the whole register. */
5008 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
5009 /* Widen the result of shift: we need to clear
5010 * the potential overflow bits resulting from
5011 * left bits of the narrow input appearing as
5012 * right bits of left the neighbour narrow
5013 * input. */
5014 if (size < 2 || !u) {
5015 uint64_t imm64;
5016 if (size == 0) {
5017 imm = (0xffu >> (8 - shift));
5018 imm |= imm << 16;
5019 } else if (size == 1) {
5020 imm = 0xffff >> (16 - shift);
5021 } else {
5022 /* size == 2 */
5023 imm = 0xffffffff >> (32 - shift);
5024 }
5025 if (size < 2) {
5026 imm64 = imm | (((uint64_t)imm) << 32);
5027 } else {
5028 imm64 = imm;
5029 }
5030 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
5031 }
5032 }
5033 neon_store_reg64(cpu_V0, rd + pass);
5034 }
5035 } else if (op >= 14) {
5036 /* VCVT fixed-point. */
5037 /* We have already masked out the must-be-1 top bit of imm6,
5038 * hence this 32-shift where the ARM ARM has 64-imm6.
5039 */
5040 shift = 32 - shift;
5041 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5042 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
5043 if (!(op & 1)) {
5044 if (u)
5045 gen_vfp_ulto(0, shift);
5046 else
5047 gen_vfp_slto(0, shift);
5048 } else {
5049 if (u)
5050 gen_vfp_toul(0, shift);
5051 else
5052 gen_vfp_tosl(0, shift);
5053 }
5054 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
5055 }
5056 } else {
5057 return 1;
5058 }
5059 } else { /* (insn & 0x00380080) == 0 */
5060 int invert;
5061
5062 op = (insn >> 8) & 0xf;
5063 /* One register and immediate. */
5064 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5065 invert = (insn & (1 << 5)) != 0;
5066 switch (op) {
5067 case 0: case 1:
5068 /* no-op */
5069 break;
5070 case 2: case 3:
5071 imm <<= 8;
5072 break;
5073 case 4: case 5:
5074 imm <<= 16;
5075 break;
5076 case 6: case 7:
5077 imm <<= 24;
5078 break;
5079 case 8: case 9:
5080 imm |= imm << 16;
5081 break;
5082 case 10: case 11:
5083 imm = (imm << 8) | (imm << 24);
5084 break;
5085 case 12:
5086 imm = (imm << 8) | 0xff;
5087 break;
5088 case 13:
5089 imm = (imm << 16) | 0xffff;
5090 break;
5091 case 14:
5092 imm |= (imm << 8) | (imm << 16) | (imm << 24);
5093 if (invert)
5094 imm = ~imm;
5095 break;
5096 case 15:
5097 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
5098 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
5099 break;
5100 }
5101 if (invert)
5102 imm = ~imm;
5103
5104 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5105 if (op & 1 && op < 12) {
5106 tmp = neon_load_reg(rd, pass);
5107 if (invert) {
5108 /* The immediate value has already been inverted, so
5109 BIC becomes AND. */
5110 tcg_gen_andi_i32(tmp, tmp, imm);
5111 } else {
5112 tcg_gen_ori_i32(tmp, tmp, imm);
5113 }
5114 } else {
5115 /* VMOV, VMVN. */
5116 tmp = tcg_temp_new_i32();
5117 if (op == 14 && invert) {
5118 uint32_t val;
5119 val = 0;
5120 for (n = 0; n < 4; n++) {
5121 if (imm & (1 << (n + (pass & 1) * 4)))
5122 val |= 0xff << (n * 8);
5123 }
5124 tcg_gen_movi_i32(tmp, val);
5125 } else {
5126 tcg_gen_movi_i32(tmp, imm);
5127 }
5128 }
5129 neon_store_reg(rd, pass, tmp);
5130 }
5131 }
5132 } else { /* (insn & 0x00800010 == 0x00800000) */
5133 if (size != 3) {
5134 op = (insn >> 8) & 0xf;
5135 if ((insn & (1 << 6)) == 0) {
5136 /* Three registers of different lengths. */
5137 int src1_wide;
5138 int src2_wide;
5139 int prewiden;
5140 /* prewiden, src1_wide, src2_wide */
5141 static const int neon_3reg_wide[16][3] = {
5142 {1, 0, 0}, /* VADDL */
5143 {1, 1, 0}, /* VADDW */
5144 {1, 0, 0}, /* VSUBL */
5145 {1, 1, 0}, /* VSUBW */
5146 {0, 1, 1}, /* VADDHN */
5147 {0, 0, 0}, /* VABAL */
5148 {0, 1, 1}, /* VSUBHN */
5149 {0, 0, 0}, /* VABDL */
5150 {0, 0, 0}, /* VMLAL */
5151 {0, 0, 0}, /* VQDMLAL */
5152 {0, 0, 0}, /* VMLSL */
5153 {0, 0, 0}, /* VQDMLSL */
5154 {0, 0, 0}, /* Integer VMULL */
5155 {0, 0, 0}, /* VQDMULL */
5156 {0, 0, 0} /* Polynomial VMULL */
5157 };
5158
5159 prewiden = neon_3reg_wide[op][0];
5160 src1_wide = neon_3reg_wide[op][1];
5161 src2_wide = neon_3reg_wide[op][2];
5162
5163 if (size == 0 && (op == 9 || op == 11 || op == 13))
5164 return 1;
5165
5166 /* Avoid overlapping operands. Wide source operands are
5167 always aligned so will never overlap with wide
5168 destinations in problematic ways. */
5169 if (rd == rm && !src2_wide) {
5170 tmp = neon_load_reg(rm, 1);
5171 neon_store_scratch(2, tmp);
5172 } else if (rd == rn && !src1_wide) {
5173 tmp = neon_load_reg(rn, 1);
5174 neon_store_scratch(2, tmp);
5175 }
5176 TCGV_UNUSED(tmp3);
5177 for (pass = 0; pass < 2; pass++) {
5178 if (src1_wide) {
5179 neon_load_reg64(cpu_V0, rn + pass);
5180 TCGV_UNUSED(tmp);
5181 } else {
5182 if (pass == 1 && rd == rn) {
5183 tmp = neon_load_scratch(2);
5184 } else {
5185 tmp = neon_load_reg(rn, pass);
5186 }
5187 if (prewiden) {
5188 gen_neon_widen(cpu_V0, tmp, size, u);
5189 }
5190 }
5191 if (src2_wide) {
5192 neon_load_reg64(cpu_V1, rm + pass);
5193 TCGV_UNUSED(tmp2);
5194 } else {
5195 if (pass == 1 && rd == rm) {
5196 tmp2 = neon_load_scratch(2);
5197 } else {
5198 tmp2 = neon_load_reg(rm, pass);
5199 }
5200 if (prewiden) {
5201 gen_neon_widen(cpu_V1, tmp2, size, u);
5202 }
5203 }
5204 switch (op) {
5205 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5206 gen_neon_addl(size);
5207 break;
5208 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5209 gen_neon_subl(size);
5210 break;
5211 case 5: case 7: /* VABAL, VABDL */
5212 switch ((size << 1) | u) {
5213 case 0:
5214 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5215 break;
5216 case 1:
5217 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5218 break;
5219 case 2:
5220 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5221 break;
5222 case 3:
5223 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5224 break;
5225 case 4:
5226 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5227 break;
5228 case 5:
5229 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5230 break;
5231 default: abort();
5232 }
5233 tcg_temp_free_i32(tmp2);
5234 tcg_temp_free_i32(tmp);
5235 break;
5236 case 8: case 9: case 10: case 11: case 12: case 13:
5237 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5238 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5239 break;
5240 case 14: /* Polynomial VMULL */
5241 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
5242 tcg_temp_free_i32(tmp2);
5243 tcg_temp_free_i32(tmp);
5244 break;
5245 default: /* 15 is RESERVED. */
5246 return 1;
5247 }
5248 if (op == 13) {
5249 /* VQDMULL */
5250 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5251 neon_store_reg64(cpu_V0, rd + pass);
5252 } else if (op == 5 || (op >= 8 && op <= 11)) {
5253 /* Accumulate. */
5254 neon_load_reg64(cpu_V1, rd + pass);
5255 switch (op) {
5256 case 10: /* VMLSL */
5257 gen_neon_negl(cpu_V0, size);
5258 /* Fall through */
5259 case 5: case 8: /* VABAL, VMLAL */
5260 gen_neon_addl(size);
5261 break;
5262 case 9: case 11: /* VQDMLAL, VQDMLSL */
5263 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5264 if (op == 11) {
5265 gen_neon_negl(cpu_V0, size);
5266 }
5267 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5268 break;
5269 default:
5270 abort();
5271 }
5272 neon_store_reg64(cpu_V0, rd + pass);
5273 } else if (op == 4 || op == 6) {
5274 /* Narrowing operation. */
5275 tmp = tcg_temp_new_i32();
5276 if (!u) {
5277 switch (size) {
5278 case 0:
5279 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5280 break;
5281 case 1:
5282 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5283 break;
5284 case 2:
5285 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5286 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5287 break;
5288 default: abort();
5289 }
5290 } else {
5291 switch (size) {
5292 case 0:
5293 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5294 break;
5295 case 1:
5296 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5297 break;
5298 case 2:
5299 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5300 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5301 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5302 break;
5303 default: abort();
5304 }
5305 }
5306 if (pass == 0) {
5307 tmp3 = tmp;
5308 } else {
5309 neon_store_reg(rd, 0, tmp3);
5310 neon_store_reg(rd, 1, tmp);
5311 }
5312 } else {
5313 /* Write back the result. */
5314 neon_store_reg64(cpu_V0, rd + pass);
5315 }
5316 }
5317 } else {
5318 /* Two registers and a scalar. */
5319 switch (op) {
5320 case 0: /* Integer VMLA scalar */
5321 case 1: /* Float VMLA scalar */
5322 case 4: /* Integer VMLS scalar */
5323 case 5: /* Floating point VMLS scalar */
5324 case 8: /* Integer VMUL scalar */
5325 case 9: /* Floating point VMUL scalar */
5326 case 12: /* VQDMULH scalar */
5327 case 13: /* VQRDMULH scalar */
5328 tmp = neon_get_scalar(size, rm);
5329 neon_store_scratch(0, tmp);
5330 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5331 tmp = neon_load_scratch(0);
5332 tmp2 = neon_load_reg(rn, pass);
5333 if (op == 12) {
5334 if (size == 1) {
5335 gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2);
5336 } else {
5337 gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2);
5338 }
5339 } else if (op == 13) {
5340 if (size == 1) {
5341 gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2);
5342 } else {
5343 gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2);
5344 }
5345 } else if (op & 1) {
5346 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5347 } else {
5348 switch (size) {
5349 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5350 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5351 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5352 default: return 1;
5353 }
5354 }
5355 tcg_temp_free_i32(tmp2);
5356 if (op < 8) {
5357 /* Accumulate. */
5358 tmp2 = neon_load_reg(rd, pass);
5359 switch (op) {
5360 case 0:
5361 gen_neon_add(size, tmp, tmp2);
5362 break;
5363 case 1:
5364 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5365 break;
5366 case 4:
5367 gen_neon_rsb(size, tmp, tmp2);
5368 break;
5369 case 5:
5370 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5371 break;
5372 default:
5373 abort();
5374 }
5375 tcg_temp_free_i32(tmp2);
5376 }
5377 neon_store_reg(rd, pass, tmp);
5378 }
5379 break;
5380 case 2: /* VMLAL sclar */
5381 case 3: /* VQDMLAL scalar */
5382 case 6: /* VMLSL scalar */
5383 case 7: /* VQDMLSL scalar */
5384 case 10: /* VMULL scalar */
5385 case 11: /* VQDMULL scalar */
5386 if (size == 0 && (op == 3 || op == 7 || op == 11))
5387 return 1;
5388
5389 tmp2 = neon_get_scalar(size, rm);
5390 /* We need a copy of tmp2 because gen_neon_mull
5391 * deletes it during pass 0. */
5392 tmp4 = tcg_temp_new_i32();
5393 tcg_gen_mov_i32(tmp4, tmp2);
5394 tmp3 = neon_load_reg(rn, 1);
5395
5396 for (pass = 0; pass < 2; pass++) {
5397 if (pass == 0) {
5398 tmp = neon_load_reg(rn, 0);
5399 } else {
5400 tmp = tmp3;
5401 tmp2 = tmp4;
5402 }
5403 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5404 if (op != 11) {
5405 neon_load_reg64(cpu_V1, rd + pass);
5406 }
5407 switch (op) {
5408 case 6:
5409 gen_neon_negl(cpu_V0, size);
5410 /* Fall through */
5411 case 2:
5412 gen_neon_addl(size);
5413 break;
5414 case 3: case 7:
5415 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5416 if (op == 7) {
5417 gen_neon_negl(cpu_V0, size);
5418 }
5419 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5420 break;
5421 case 10:
5422 /* no-op */
5423 break;
5424 case 11:
5425 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5426 break;
5427 default:
5428 abort();
5429 }
5430 neon_store_reg64(cpu_V0, rd + pass);
5431 }
5432
5433
5434 break;
5435 default: /* 14 and 15 are RESERVED */
5436 return 1;
5437 }
5438 }
5439 } else { /* size == 3 */
5440 if (!u) {
5441 /* Extract. */
5442 imm = (insn >> 8) & 0xf;
5443
5444 if (imm > 7 && !q)
5445 return 1;
5446
5447 if (imm == 0) {
5448 neon_load_reg64(cpu_V0, rn);
5449 if (q) {
5450 neon_load_reg64(cpu_V1, rn + 1);
5451 }
5452 } else if (imm == 8) {
5453 neon_load_reg64(cpu_V0, rn + 1);
5454 if (q) {
5455 neon_load_reg64(cpu_V1, rm);
5456 }
5457 } else if (q) {
5458 tmp64 = tcg_temp_new_i64();
5459 if (imm < 8) {
5460 neon_load_reg64(cpu_V0, rn);
5461 neon_load_reg64(tmp64, rn + 1);
5462 } else {
5463 neon_load_reg64(cpu_V0, rn + 1);
5464 neon_load_reg64(tmp64, rm);
5465 }
5466 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5467 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5468 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5469 if (imm < 8) {
5470 neon_load_reg64(cpu_V1, rm);
5471 } else {
5472 neon_load_reg64(cpu_V1, rm + 1);
5473 imm -= 8;
5474 }
5475 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5476 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5477 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5478 tcg_temp_free_i64(tmp64);
5479 } else {
5480 /* BUGFIX */
5481 neon_load_reg64(cpu_V0, rn);
5482 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5483 neon_load_reg64(cpu_V1, rm);
5484 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5485 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5486 }
5487 neon_store_reg64(cpu_V0, rd);
5488 if (q) {
5489 neon_store_reg64(cpu_V1, rd + 1);
5490 }
5491 } else if ((insn & (1 << 11)) == 0) {
5492 /* Two register misc. */
5493 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5494 size = (insn >> 18) & 3;
5495 switch (op) {
5496 case 0: /* VREV64 */
5497 if (size == 3)
5498 return 1;
5499 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5500 tmp = neon_load_reg(rm, pass * 2);
5501 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5502 switch (size) {
5503 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5504 case 1: gen_swap_half(tmp); break;
5505 case 2: /* no-op */ break;
5506 default: abort();
5507 }
5508 neon_store_reg(rd, pass * 2 + 1, tmp);
5509 if (size == 2) {
5510 neon_store_reg(rd, pass * 2, tmp2);
5511 } else {
5512 switch (size) {
5513 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5514 case 1: gen_swap_half(tmp2); break;
5515 default: abort();
5516 }
5517 neon_store_reg(rd, pass * 2, tmp2);
5518 }
5519 }
5520 break;
5521 case 4: case 5: /* VPADDL */
5522 case 12: case 13: /* VPADAL */
5523 if (size == 3)
5524 return 1;
5525 for (pass = 0; pass < q + 1; pass++) {
5526 tmp = neon_load_reg(rm, pass * 2);
5527 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5528 tmp = neon_load_reg(rm, pass * 2 + 1);
5529 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5530 switch (size) {
5531 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5532 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5533 case 2: tcg_gen_add_i64(CPU_V001); break;
5534 default: abort();
5535 }
5536 if (op >= 12) {
5537 /* Accumulate. */
5538 neon_load_reg64(cpu_V1, rd + pass);
5539 gen_neon_addl(size);
5540 }
5541 neon_store_reg64(cpu_V0, rd + pass);
5542 }
5543 break;
5544 case 33: /* VTRN */
5545 if (size == 2) {
5546 for (n = 0; n < (q ? 4 : 2); n += 2) {
5547 tmp = neon_load_reg(rm, n);
5548 tmp2 = neon_load_reg(rd, n + 1);
5549 neon_store_reg(rm, n, tmp2);
5550 neon_store_reg(rd, n + 1, tmp);
5551 }
5552 } else {
5553 goto elementwise;
5554 }
5555 break;
5556 case 34: /* VUZP */
5557 if (gen_neon_unzip(rd, rm, size, q)) {
5558 return 1;
5559 }
5560 break;
5561 case 35: /* VZIP */
5562 if (gen_neon_zip(rd, rm, size, q)) {
5563 return 1;
5564 }
5565 break;
5566 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5567 if (size == 3)
5568 return 1;
5569 TCGV_UNUSED(tmp2);
5570 for (pass = 0; pass < 2; pass++) {
5571 neon_load_reg64(cpu_V0, rm + pass);
5572 tmp = tcg_temp_new_i32();
5573 gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0);
5574 if (pass == 0) {
5575 tmp2 = tmp;
5576 } else {
5577 neon_store_reg(rd, 0, tmp2);
5578 neon_store_reg(rd, 1, tmp);
5579 }
5580 }
5581 break;
5582 case 38: /* VSHLL */
5583 if (q || size == 3)
5584 return 1;
5585 tmp = neon_load_reg(rm, 0);
5586 tmp2 = neon_load_reg(rm, 1);
5587 for (pass = 0; pass < 2; pass++) {
5588 if (pass == 1)
5589 tmp = tmp2;
5590 gen_neon_widen(cpu_V0, tmp, size, 1);
5591 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5592 neon_store_reg64(cpu_V0, rd + pass);
5593 }
5594 break;
5595 case 44: /* VCVT.F16.F32 */
5596 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5597 return 1;
5598 tmp = tcg_temp_new_i32();
5599 tmp2 = tcg_temp_new_i32();
5600 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5601 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5602 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5603 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5604 tcg_gen_shli_i32(tmp2, tmp2, 16);
5605 tcg_gen_or_i32(tmp2, tmp2, tmp);
5606 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5607 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5608 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5609 neon_store_reg(rd, 0, tmp2);
5610 tmp2 = tcg_temp_new_i32();
5611 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5612 tcg_gen_shli_i32(tmp2, tmp2, 16);
5613 tcg_gen_or_i32(tmp2, tmp2, tmp);
5614 neon_store_reg(rd, 1, tmp2);
5615 tcg_temp_free_i32(tmp);
5616 break;
5617 case 46: /* VCVT.F32.F16 */
5618 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5619 return 1;
5620 tmp3 = tcg_temp_new_i32();
5621 tmp = neon_load_reg(rm, 0);
5622 tmp2 = neon_load_reg(rm, 1);
5623 tcg_gen_ext16u_i32(tmp3, tmp);
5624 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5625 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5626 tcg_gen_shri_i32(tmp3, tmp, 16);
5627 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5628 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5629 tcg_temp_free_i32(tmp);
5630 tcg_gen_ext16u_i32(tmp3, tmp2);
5631 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5632 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5633 tcg_gen_shri_i32(tmp3, tmp2, 16);
5634 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5635 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5636 tcg_temp_free_i32(tmp2);
5637 tcg_temp_free_i32(tmp3);
5638 break;
5639 default:
5640 elementwise:
5641 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5642 if (op == 30 || op == 31 || op >= 58) {
5643 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5644 neon_reg_offset(rm, pass));
5645 TCGV_UNUSED(tmp);
5646 } else {
5647 tmp = neon_load_reg(rm, pass);
5648 }
5649 switch (op) {
5650 case 1: /* VREV32 */
5651 switch (size) {
5652 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5653 case 1: gen_swap_half(tmp); break;
5654 default: return 1;
5655 }
5656 break;
5657 case 2: /* VREV16 */
5658 if (size != 0)
5659 return 1;
5660 gen_rev16(tmp);
5661 break;
5662 case 8: /* CLS */
5663 switch (size) {
5664 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5665 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5666 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5667 default: return 1;
5668 }
5669 break;
5670 case 9: /* CLZ */
5671 switch (size) {
5672 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5673 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5674 case 2: gen_helper_clz(tmp, tmp); break;
5675 default: return 1;
5676 }
5677 break;
5678 case 10: /* CNT */
5679 if (size != 0)
5680 return 1;
5681 gen_helper_neon_cnt_u8(tmp, tmp);
5682 break;
5683 case 11: /* VNOT */
5684 if (size != 0)
5685 return 1;
5686 tcg_gen_not_i32(tmp, tmp);
5687 break;
5688 case 14: /* VQABS */
5689 switch (size) {
5690 case 0: gen_helper_neon_qabs_s8(tmp, tmp); break;
5691 case 1: gen_helper_neon_qabs_s16(tmp, tmp); break;
5692 case 2: gen_helper_neon_qabs_s32(tmp, tmp); break;
5693 default: return 1;
5694 }
5695 break;
5696 case 15: /* VQNEG */
5697 switch (size) {
5698 case 0: gen_helper_neon_qneg_s8(tmp, tmp); break;
5699 case 1: gen_helper_neon_qneg_s16(tmp, tmp); break;
5700 case 2: gen_helper_neon_qneg_s32(tmp, tmp); break;
5701 default: return 1;
5702 }
5703 break;
5704 case 16: case 19: /* VCGT #0, VCLE #0 */
5705 tmp2 = tcg_const_i32(0);
5706 switch(size) {
5707 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5708 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5709 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5710 default: return 1;
5711 }
5712 tcg_temp_free(tmp2);
5713 if (op == 19)
5714 tcg_gen_not_i32(tmp, tmp);
5715 break;
5716 case 17: case 20: /* VCGE #0, VCLT #0 */
5717 tmp2 = tcg_const_i32(0);
5718 switch(size) {
5719 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5720 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5721 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5722 default: return 1;
5723 }
5724 tcg_temp_free(tmp2);
5725 if (op == 20)
5726 tcg_gen_not_i32(tmp, tmp);
5727 break;
5728 case 18: /* VCEQ #0 */
5729 tmp2 = tcg_const_i32(0);
5730 switch(size) {
5731 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5732 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5733 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5734 default: return 1;
5735 }
5736 tcg_temp_free(tmp2);
5737 break;
5738 case 22: /* VABS */
5739 switch(size) {
5740 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5741 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5742 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5743 default: return 1;
5744 }
5745 break;
5746 case 23: /* VNEG */
5747 if (size == 3)
5748 return 1;
5749 tmp2 = tcg_const_i32(0);
5750 gen_neon_rsb(size, tmp, tmp2);
5751 tcg_temp_free(tmp2);
5752 break;
5753 case 24: /* Float VCGT #0 */
5754 tmp2 = tcg_const_i32(0);
5755 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5756 tcg_temp_free(tmp2);
5757 break;
5758 case 25: /* Float VCGE #0 */
5759 tmp2 = tcg_const_i32(0);
5760 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5761 tcg_temp_free(tmp2);
5762 break;
5763 case 26: /* Float VCEQ #0 */
5764 tmp2 = tcg_const_i32(0);
5765 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5766 tcg_temp_free(tmp2);
5767 break;
5768 case 27: /* Float VCLE #0 */
5769 tmp2 = tcg_const_i32(0);
5770 gen_helper_neon_cge_f32(tmp, tmp2, tmp);
5771 tcg_temp_free(tmp2);
5772 break;
5773 case 28: /* Float VCLT #0 */
5774 tmp2 = tcg_const_i32(0);
5775 gen_helper_neon_cgt_f32(tmp, tmp2, tmp);
5776 tcg_temp_free(tmp2);
5777 break;
5778 case 30: /* Float VABS */
5779 gen_vfp_abs(0);
5780 break;
5781 case 31: /* Float VNEG */
5782 gen_vfp_neg(0);
5783 break;
5784 case 32: /* VSWP */
5785 tmp2 = neon_load_reg(rd, pass);
5786 neon_store_reg(rm, pass, tmp2);
5787 break;
5788 case 33: /* VTRN */
5789 tmp2 = neon_load_reg(rd, pass);
5790 switch (size) {
5791 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5792 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5793 case 2: abort();
5794 default: return 1;
5795 }
5796 neon_store_reg(rm, pass, tmp2);
5797 break;
5798 case 56: /* Integer VRECPE */
5799 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5800 break;
5801 case 57: /* Integer VRSQRTE */
5802 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5803 break;
5804 case 58: /* Float VRECPE */
5805 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5806 break;
5807 case 59: /* Float VRSQRTE */
5808 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5809 break;
5810 case 60: /* VCVT.F32.S32 */
5811 gen_vfp_sito(0);
5812 break;
5813 case 61: /* VCVT.F32.U32 */
5814 gen_vfp_uito(0);
5815 break;
5816 case 62: /* VCVT.S32.F32 */
5817 gen_vfp_tosiz(0);
5818 break;
5819 case 63: /* VCVT.U32.F32 */
5820 gen_vfp_touiz(0);
5821 break;
5822 default:
5823 /* Reserved: 21, 29, 39-56 */
5824 return 1;
5825 }
5826 if (op == 30 || op == 31 || op >= 58) {
5827 tcg_gen_st_f32(cpu_F0s, cpu_env,
5828 neon_reg_offset(rd, pass));
5829 } else {
5830 neon_store_reg(rd, pass, tmp);
5831 }
5832 }
5833 break;
5834 }
5835 } else if ((insn & (1 << 10)) == 0) {
5836 /* VTBL, VTBX. */
5837 n = ((insn >> 5) & 0x18) + 8;
5838 if (insn & (1 << 6)) {
5839 tmp = neon_load_reg(rd, 0);
5840 } else {
5841 tmp = tcg_temp_new_i32();
5842 tcg_gen_movi_i32(tmp, 0);
5843 }
5844 tmp2 = neon_load_reg(rm, 0);
5845 tmp4 = tcg_const_i32(rn);
5846 tmp5 = tcg_const_i32(n);
5847 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5848 tcg_temp_free_i32(tmp);
5849 if (insn & (1 << 6)) {
5850 tmp = neon_load_reg(rd, 1);
5851 } else {
5852 tmp = tcg_temp_new_i32();
5853 tcg_gen_movi_i32(tmp, 0);
5854 }
5855 tmp3 = neon_load_reg(rm, 1);
5856 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5857 tcg_temp_free_i32(tmp5);
5858 tcg_temp_free_i32(tmp4);
5859 neon_store_reg(rd, 0, tmp2);
5860 neon_store_reg(rd, 1, tmp3);
5861 tcg_temp_free_i32(tmp);
5862 } else if ((insn & 0x380) == 0) {
5863 /* VDUP */
5864 if (insn & (1 << 19)) {
5865 tmp = neon_load_reg(rm, 1);
5866 } else {
5867 tmp = neon_load_reg(rm, 0);
5868 }
5869 if (insn & (1 << 16)) {
5870 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
5871 } else if (insn & (1 << 17)) {
5872 if ((insn >> 18) & 1)
5873 gen_neon_dup_high16(tmp);
5874 else
5875 gen_neon_dup_low16(tmp);
5876 }
5877 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5878 tmp2 = tcg_temp_new_i32();
5879 tcg_gen_mov_i32(tmp2, tmp);
5880 neon_store_reg(rd, pass, tmp2);
5881 }
5882 tcg_temp_free_i32(tmp);
5883 } else {
5884 return 1;
5885 }
5886 }
5887 }
5888 return 0;
5889 }
5890
5891 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5892 {
5893 int crn = (insn >> 16) & 0xf;
5894 int crm = insn & 0xf;
5895 int op1 = (insn >> 21) & 7;
5896 int op2 = (insn >> 5) & 7;
5897 int rt = (insn >> 12) & 0xf;
5898 TCGv tmp;
5899
5900 /* Minimal set of debug registers, since we don't support debug */
5901 if (op1 == 0 && crn == 0 && op2 == 0) {
5902 switch (crm) {
5903 case 0:
5904 /* DBGDIDR: just RAZ. In particular this means the
5905 * "debug architecture version" bits will read as
5906 * a reserved value, which should cause Linux to
5907 * not try to use the debug hardware.
5908 */
5909 tmp = tcg_const_i32(0);
5910 store_reg(s, rt, tmp);
5911 return 0;
5912 case 1:
5913 case 2:
5914 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5915 * don't implement memory mapped debug components
5916 */
5917 if (ENABLE_ARCH_7) {
5918 tmp = tcg_const_i32(0);
5919 store_reg(s, rt, tmp);
5920 return 0;
5921 }
5922 break;
5923 default:
5924 break;
5925 }
5926 }
5927
5928 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5929 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5930 /* TEECR */
5931 if (IS_USER(s))
5932 return 1;
5933 tmp = load_cpu_field(teecr);
5934 store_reg(s, rt, tmp);
5935 return 0;
5936 }
5937 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5938 /* TEEHBR */
5939 if (IS_USER(s) && (env->teecr & 1))
5940 return 1;
5941 tmp = load_cpu_field(teehbr);
5942 store_reg(s, rt, tmp);
5943 return 0;
5944 }
5945 }
5946 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5947 op1, crn, crm, op2);
5948 return 1;
5949 }
5950
5951 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5952 {
5953 int crn = (insn >> 16) & 0xf;
5954 int crm = insn & 0xf;
5955 int op1 = (insn >> 21) & 7;
5956 int op2 = (insn >> 5) & 7;
5957 int rt = (insn >> 12) & 0xf;
5958 TCGv tmp;
5959
5960 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5961 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5962 /* TEECR */
5963 if (IS_USER(s))
5964 return 1;
5965 tmp = load_reg(s, rt);
5966 gen_helper_set_teecr(cpu_env, tmp);
5967 tcg_temp_free_i32(tmp);
5968 return 0;
5969 }
5970 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5971 /* TEEHBR */
5972 if (IS_USER(s) && (env->teecr & 1))
5973 return 1;
5974 tmp = load_reg(s, rt);
5975 store_cpu_field(tmp, teehbr);
5976 return 0;
5977 }
5978 }
5979 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5980 op1, crn, crm, op2);
5981 return 1;
5982 }
5983
5984 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5985 {
5986 int cpnum;
5987
5988 cpnum = (insn >> 8) & 0xf;
5989 if (arm_feature(env, ARM_FEATURE_XSCALE)
5990 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5991 return 1;
5992
5993 switch (cpnum) {
5994 case 0:
5995 case 1:
5996 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5997 return disas_iwmmxt_insn(env, s, insn);
5998 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5999 return disas_dsp_insn(env, s, insn);
6000 }
6001 return 1;
6002 case 10:
6003 case 11:
6004 return disas_vfp_insn (env, s, insn);
6005 case 14:
6006 /* Coprocessors 7-15 are architecturally reserved by ARM.
6007 Unfortunately Intel decided to ignore this. */
6008 if (arm_feature(env, ARM_FEATURE_XSCALE))
6009 goto board;
6010 if (insn & (1 << 20))
6011 return disas_cp14_read(env, s, insn);
6012 else
6013 return disas_cp14_write(env, s, insn);
6014 case 15:
6015 return disas_cp15_insn (env, s, insn);
6016 default:
6017 board:
6018 /* Unknown coprocessor. See if the board has hooked it. */
6019 return disas_cp_insn (env, s, insn);
6020 }
6021 }
6022
6023
6024 /* Store a 64-bit value to a register pair. Clobbers val. */
6025 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
6026 {
6027 TCGv tmp;
6028 tmp = tcg_temp_new_i32();
6029 tcg_gen_trunc_i64_i32(tmp, val);
6030 store_reg(s, rlow, tmp);
6031 tmp = tcg_temp_new_i32();
6032 tcg_gen_shri_i64(val, val, 32);
6033 tcg_gen_trunc_i64_i32(tmp, val);
6034 store_reg(s, rhigh, tmp);
6035 }
6036
6037 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
6038 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
6039 {
6040 TCGv_i64 tmp;
6041 TCGv tmp2;
6042
6043 /* Load value and extend to 64 bits. */
6044 tmp = tcg_temp_new_i64();
6045 tmp2 = load_reg(s, rlow);
6046 tcg_gen_extu_i32_i64(tmp, tmp2);
6047 tcg_temp_free_i32(tmp2);
6048 tcg_gen_add_i64(val, val, tmp);
6049 tcg_temp_free_i64(tmp);
6050 }
6051
6052 /* load and add a 64-bit value from a register pair. */
6053 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
6054 {
6055 TCGv_i64 tmp;
6056 TCGv tmpl;
6057 TCGv tmph;
6058
6059 /* Load 64-bit value rd:rn. */
6060 tmpl = load_reg(s, rlow);
6061 tmph = load_reg(s, rhigh);
6062 tmp = tcg_temp_new_i64();
6063 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
6064 tcg_temp_free_i32(tmpl);
6065 tcg_temp_free_i32(tmph);
6066 tcg_gen_add_i64(val, val, tmp);
6067 tcg_temp_free_i64(tmp);
6068 }
6069
6070 /* Set N and Z flags from a 64-bit value. */
6071 static void gen_logicq_cc(TCGv_i64 val)
6072 {
6073 TCGv tmp = tcg_temp_new_i32();
6074 gen_helper_logicq_cc(tmp, val);
6075 gen_logic_CC(tmp);
6076 tcg_temp_free_i32(tmp);
6077 }
6078
6079 /* Load/Store exclusive instructions are implemented by remembering
6080 the value/address loaded, and seeing if these are the same
6081 when the store is performed. This should be is sufficient to implement
6082 the architecturally mandated semantics, and avoids having to monitor
6083 regular stores.
6084
6085 In system emulation mode only one CPU will be running at once, so
6086 this sequence is effectively atomic. In user emulation mode we
6087 throw an exception and handle the atomic operation elsewhere. */
6088 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
6089 TCGv addr, int size)
6090 {
6091 TCGv tmp;
6092
6093 switch (size) {
6094 case 0:
6095 tmp = gen_ld8u(addr, IS_USER(s));
6096 break;
6097 case 1:
6098 tmp = gen_ld16u(addr, IS_USER(s));
6099 break;
6100 case 2:
6101 case 3:
6102 tmp = gen_ld32(addr, IS_USER(s));
6103 break;
6104 default:
6105 abort();
6106 }
6107 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6108 store_reg(s, rt, tmp);
6109 if (size == 3) {
6110 TCGv tmp2 = tcg_temp_new_i32();
6111 tcg_gen_addi_i32(tmp2, addr, 4);
6112 tmp = gen_ld32(tmp2, IS_USER(s));
6113 tcg_temp_free_i32(tmp2);
6114 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6115 store_reg(s, rt2, tmp);
6116 }
6117 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6118 }
6119
6120 static void gen_clrex(DisasContext *s)
6121 {
6122 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6123 }
6124
6125 #ifdef CONFIG_USER_ONLY
6126 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6127 TCGv addr, int size)
6128 {
6129 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6130 tcg_gen_movi_i32(cpu_exclusive_info,
6131 size | (rd << 4) | (rt << 8) | (rt2 << 12));
6132 gen_exception_insn(s, 4, EXCP_STREX);
6133 }
6134 #else
6135 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6136 TCGv addr, int size)
6137 {
6138 TCGv tmp;
6139 int done_label;
6140 int fail_label;
6141
6142 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6143 [addr] = {Rt};
6144 {Rd} = 0;
6145 } else {
6146 {Rd} = 1;
6147 } */
6148 fail_label = gen_new_label();
6149 done_label = gen_new_label();
6150 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6151 switch (size) {
6152 case 0:
6153 tmp = gen_ld8u(addr, IS_USER(s));
6154 break;
6155 case 1:
6156 tmp = gen_ld16u(addr, IS_USER(s));
6157 break;
6158 case 2:
6159 case 3:
6160 tmp = gen_ld32(addr, IS_USER(s));
6161 break;
6162 default:
6163 abort();
6164 }
6165 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6166 tcg_temp_free_i32(tmp);
6167 if (size == 3) {
6168 TCGv tmp2 = tcg_temp_new_i32();
6169 tcg_gen_addi_i32(tmp2, addr, 4);
6170 tmp = gen_ld32(tmp2, IS_USER(s));
6171 tcg_temp_free_i32(tmp2);
6172 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6173 tcg_temp_free_i32(tmp);
6174 }
6175 tmp = load_reg(s, rt);
6176 switch (size) {
6177 case 0:
6178 gen_st8(tmp, addr, IS_USER(s));
6179 break;
6180 case 1:
6181 gen_st16(tmp, addr, IS_USER(s));
6182 break;
6183 case 2:
6184 case 3:
6185 gen_st32(tmp, addr, IS_USER(s));
6186 break;
6187 default:
6188 abort();
6189 }
6190 if (size == 3) {
6191 tcg_gen_addi_i32(addr, addr, 4);
6192 tmp = load_reg(s, rt2);
6193 gen_st32(tmp, addr, IS_USER(s));
6194 }
6195 tcg_gen_movi_i32(cpu_R[rd], 0);
6196 tcg_gen_br(done_label);
6197 gen_set_label(fail_label);
6198 tcg_gen_movi_i32(cpu_R[rd], 1);
6199 gen_set_label(done_label);
6200 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6201 }
6202 #endif
6203
6204 static void disas_arm_insn(CPUState * env, DisasContext *s)
6205 {
6206 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6207 TCGv tmp;
6208 TCGv tmp2;
6209 TCGv tmp3;
6210 TCGv addr;
6211 TCGv_i64 tmp64;
6212
6213 insn = ldl_code(s->pc);
6214 s->pc += 4;
6215
6216 /* M variants do not implement ARM mode. */
6217 if (IS_M(env))
6218 goto illegal_op;
6219 cond = insn >> 28;
6220 if (cond == 0xf){
6221 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6222 * choose to UNDEF. In ARMv5 and above the space is used
6223 * for miscellaneous unconditional instructions.
6224 */
6225 ARCH(5);
6226
6227 /* Unconditional instructions. */
6228 if (((insn >> 25) & 7) == 1) {
6229 /* NEON Data processing. */
6230 if (!arm_feature(env, ARM_FEATURE_NEON))
6231 goto illegal_op;
6232
6233 if (disas_neon_data_insn(env, s, insn))
6234 goto illegal_op;
6235 return;
6236 }
6237 if ((insn & 0x0f100000) == 0x04000000) {
6238 /* NEON load/store. */
6239 if (!arm_feature(env, ARM_FEATURE_NEON))
6240 goto illegal_op;
6241
6242 if (disas_neon_ls_insn(env, s, insn))
6243 goto illegal_op;
6244 return;
6245 }
6246 if (((insn & 0x0f30f000) == 0x0510f000) ||
6247 ((insn & 0x0f30f010) == 0x0710f000)) {
6248 if ((insn & (1 << 22)) == 0) {
6249 /* PLDW; v7MP */
6250 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6251 goto illegal_op;
6252 }
6253 }
6254 /* Otherwise PLD; v5TE+ */
6255 ARCH(5TE);
6256 return;
6257 }
6258 if (((insn & 0x0f70f000) == 0x0450f000) ||
6259 ((insn & 0x0f70f010) == 0x0650f000)) {
6260 ARCH(7);
6261 return; /* PLI; V7 */
6262 }
6263 if (((insn & 0x0f700000) == 0x04100000) ||
6264 ((insn & 0x0f700010) == 0x06100000)) {
6265 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6266 goto illegal_op;
6267 }
6268 return; /* v7MP: Unallocated memory hint: must NOP */
6269 }
6270
6271 if ((insn & 0x0ffffdff) == 0x01010000) {
6272 ARCH(6);
6273 /* setend */
6274 if (insn & (1 << 9)) {
6275 /* BE8 mode not implemented. */
6276 goto illegal_op;
6277 }
6278 return;
6279 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6280 switch ((insn >> 4) & 0xf) {
6281 case 1: /* clrex */
6282 ARCH(6K);
6283 gen_clrex(s);
6284 return;
6285 case 4: /* dsb */
6286 case 5: /* dmb */
6287 case 6: /* isb */
6288 ARCH(7);
6289 /* We don't emulate caches so these are a no-op. */
6290 return;
6291 default:
6292 goto illegal_op;
6293 }
6294 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6295 /* srs */
6296 int32_t offset;
6297 if (IS_USER(s))
6298 goto illegal_op;
6299 ARCH(6);
6300 op1 = (insn & 0x1f);
6301 addr = tcg_temp_new_i32();
6302 tmp = tcg_const_i32(op1);
6303 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6304 tcg_temp_free_i32(tmp);
6305 i = (insn >> 23) & 3;
6306 switch (i) {
6307 case 0: offset = -4; break; /* DA */
6308 case 1: offset = 0; break; /* IA */
6309 case 2: offset = -8; break; /* DB */
6310 case 3: offset = 4; break; /* IB */
6311 default: abort();
6312 }
6313 if (offset)
6314 tcg_gen_addi_i32(addr, addr, offset);
6315 tmp = load_reg(s, 14);
6316 gen_st32(tmp, addr, 0);
6317 tmp = load_cpu_field(spsr);
6318 tcg_gen_addi_i32(addr, addr, 4);
6319 gen_st32(tmp, addr, 0);
6320 if (insn & (1 << 21)) {
6321 /* Base writeback. */
6322 switch (i) {
6323 case 0: offset = -8; break;
6324 case 1: offset = 4; break;
6325 case 2: offset = -4; break;
6326 case 3: offset = 0; break;
6327 default: abort();
6328 }
6329 if (offset)
6330 tcg_gen_addi_i32(addr, addr, offset);
6331 tmp = tcg_const_i32(op1);
6332 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6333 tcg_temp_free_i32(tmp);
6334 tcg_temp_free_i32(addr);
6335 } else {
6336 tcg_temp_free_i32(addr);
6337 }
6338 return;
6339 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6340 /* rfe */
6341 int32_t offset;
6342 if (IS_USER(s))
6343 goto illegal_op;
6344 ARCH(6);
6345 rn = (insn >> 16) & 0xf;
6346 addr = load_reg(s, rn);
6347 i = (insn >> 23) & 3;
6348 switch (i) {
6349 case 0: offset = -4; break; /* DA */
6350 case 1: offset = 0; break; /* IA */
6351 case 2: offset = -8; break; /* DB */
6352 case 3: offset = 4; break; /* IB */
6353 default: abort();
6354 }
6355 if (offset)
6356 tcg_gen_addi_i32(addr, addr, offset);
6357 /* Load PC into tmp and CPSR into tmp2. */
6358 tmp = gen_ld32(addr, 0);
6359 tcg_gen_addi_i32(addr, addr, 4);
6360 tmp2 = gen_ld32(addr, 0);
6361 if (insn & (1 << 21)) {
6362 /* Base writeback. */
6363 switch (i) {
6364 case 0: offset = -8; break;
6365 case 1: offset = 4; break;
6366 case 2: offset = -4; break;
6367 case 3: offset = 0; break;
6368 default: abort();
6369 }
6370 if (offset)
6371 tcg_gen_addi_i32(addr, addr, offset);
6372 store_reg(s, rn, addr);
6373 } else {
6374 tcg_temp_free_i32(addr);
6375 }
6376 gen_rfe(s, tmp, tmp2);
6377 return;
6378 } else if ((insn & 0x0e000000) == 0x0a000000) {
6379 /* branch link and change to thumb (blx <offset>) */
6380 int32_t offset;
6381
6382 val = (uint32_t)s->pc;
6383 tmp = tcg_temp_new_i32();
6384 tcg_gen_movi_i32(tmp, val);
6385 store_reg(s, 14, tmp);
6386 /* Sign-extend the 24-bit offset */
6387 offset = (((int32_t)insn) << 8) >> 8;
6388 /* offset * 4 + bit24 * 2 + (thumb bit) */
6389 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6390 /* pipeline offset */
6391 val += 4;
6392 /* protected by ARCH(5); above, near the start of uncond block */
6393 gen_bx_im(s, val);
6394 return;
6395 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6396 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6397 /* iWMMXt register transfer. */
6398 if (env->cp15.c15_cpar & (1 << 1))
6399 if (!disas_iwmmxt_insn(env, s, insn))
6400 return;
6401 }
6402 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6403 /* Coprocessor double register transfer. */
6404 ARCH(5TE);
6405 } else if ((insn & 0x0f000010) == 0x0e000010) {
6406 /* Additional coprocessor register transfer. */
6407 } else if ((insn & 0x0ff10020) == 0x01000000) {
6408 uint32_t mask;
6409 uint32_t val;
6410 /* cps (privileged) */
6411 if (IS_USER(s))
6412 return;
6413 mask = val = 0;
6414 if (insn & (1 << 19)) {
6415 if (insn & (1 << 8))
6416 mask |= CPSR_A;
6417 if (insn & (1 << 7))
6418 mask |= CPSR_I;
6419 if (insn & (1 << 6))
6420 mask |= CPSR_F;
6421 if (insn & (1 << 18))
6422 val |= mask;
6423 }
6424 if (insn & (1 << 17)) {
6425 mask |= CPSR_M;
6426 val |= (insn & 0x1f);
6427 }
6428 if (mask) {
6429 gen_set_psr_im(s, mask, 0, val);
6430 }
6431 return;
6432 }
6433 goto illegal_op;
6434 }
6435 if (cond != 0xe) {
6436 /* if not always execute, we generate a conditional jump to
6437 next instruction */
6438 s->condlabel = gen_new_label();
6439 gen_test_cc(cond ^ 1, s->condlabel);
6440 s->condjmp = 1;
6441 }
6442 if ((insn & 0x0f900000) == 0x03000000) {
6443 if ((insn & (1 << 21)) == 0) {
6444 ARCH(6T2);
6445 rd = (insn >> 12) & 0xf;
6446 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6447 if ((insn & (1 << 22)) == 0) {
6448 /* MOVW */
6449 tmp = tcg_temp_new_i32();
6450 tcg_gen_movi_i32(tmp, val);
6451 } else {
6452 /* MOVT */
6453 tmp = load_reg(s, rd);
6454 tcg_gen_ext16u_i32(tmp, tmp);
6455 tcg_gen_ori_i32(tmp, tmp, val << 16);
6456 }
6457 store_reg(s, rd, tmp);
6458 } else {
6459 if (((insn >> 12) & 0xf) != 0xf)
6460 goto illegal_op;
6461 if (((insn >> 16) & 0xf) == 0) {
6462 gen_nop_hint(s, insn & 0xff);
6463 } else {
6464 /* CPSR = immediate */
6465 val = insn & 0xff;
6466 shift = ((insn >> 8) & 0xf) * 2;
6467 if (shift)
6468 val = (val >> shift) | (val << (32 - shift));
6469 i = ((insn & (1 << 22)) != 0);
6470 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6471 goto illegal_op;
6472 }
6473 }
6474 } else if ((insn & 0x0f900000) == 0x01000000
6475 && (insn & 0x00000090) != 0x00000090) {
6476 /* miscellaneous instructions */
6477 op1 = (insn >> 21) & 3;
6478 sh = (insn >> 4) & 0xf;
6479 rm = insn & 0xf;
6480 switch (sh) {
6481 case 0x0: /* move program status register */
6482 if (op1 & 1) {
6483 /* PSR = reg */
6484 tmp = load_reg(s, rm);
6485 i = ((op1 & 2) != 0);
6486 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6487 goto illegal_op;
6488 } else {
6489 /* reg = PSR */
6490 rd = (insn >> 12) & 0xf;
6491 if (op1 & 2) {
6492 if (IS_USER(s))
6493 goto illegal_op;
6494 tmp = load_cpu_field(spsr);
6495 } else {
6496 tmp = tcg_temp_new_i32();
6497 gen_helper_cpsr_read(tmp);
6498 }
6499 store_reg(s, rd, tmp);
6500 }
6501 break;
6502 case 0x1:
6503 if (op1 == 1) {
6504 /* branch/exchange thumb (bx). */
6505 ARCH(4T);
6506 tmp = load_reg(s, rm);
6507 gen_bx(s, tmp);
6508 } else if (op1 == 3) {
6509 /* clz */
6510 ARCH(5);
6511 rd = (insn >> 12) & 0xf;
6512 tmp = load_reg(s, rm);
6513 gen_helper_clz(tmp, tmp);
6514 store_reg(s, rd, tmp);
6515 } else {
6516 goto illegal_op;
6517 }
6518 break;
6519 case 0x2:
6520 if (op1 == 1) {
6521 ARCH(5J); /* bxj */
6522 /* Trivial implementation equivalent to bx. */
6523 tmp = load_reg(s, rm);
6524 gen_bx(s, tmp);
6525 } else {
6526 goto illegal_op;
6527 }
6528 break;
6529 case 0x3:
6530 if (op1 != 1)
6531 goto illegal_op;
6532
6533 ARCH(5);
6534 /* branch link/exchange thumb (blx) */
6535 tmp = load_reg(s, rm);
6536 tmp2 = tcg_temp_new_i32();
6537 tcg_gen_movi_i32(tmp2, s->pc);
6538 store_reg(s, 14, tmp2);
6539 gen_bx(s, tmp);
6540 break;
6541 case 0x5: /* saturating add/subtract */
6542 ARCH(5TE);
6543 rd = (insn >> 12) & 0xf;
6544 rn = (insn >> 16) & 0xf;
6545 tmp = load_reg(s, rm);
6546 tmp2 = load_reg(s, rn);
6547 if (op1 & 2)
6548 gen_helper_double_saturate(tmp2, tmp2);
6549 if (op1 & 1)
6550 gen_helper_sub_saturate(tmp, tmp, tmp2);
6551 else
6552 gen_helper_add_saturate(tmp, tmp, tmp2);
6553 tcg_temp_free_i32(tmp2);
6554 store_reg(s, rd, tmp);
6555 break;
6556 case 7:
6557 /* SMC instruction (op1 == 3)
6558 and undefined instructions (op1 == 0 || op1 == 2)
6559 will trap */
6560 if (op1 != 1) {
6561 goto illegal_op;
6562 }
6563 /* bkpt */
6564 ARCH(5);
6565 gen_exception_insn(s, 4, EXCP_BKPT);
6566 break;
6567 case 0x8: /* signed multiply */
6568 case 0xa:
6569 case 0xc:
6570 case 0xe:
6571 ARCH(5TE);
6572 rs = (insn >> 8) & 0xf;
6573 rn = (insn >> 12) & 0xf;
6574 rd = (insn >> 16) & 0xf;
6575 if (op1 == 1) {
6576 /* (32 * 16) >> 16 */
6577 tmp = load_reg(s, rm);
6578 tmp2 = load_reg(s, rs);
6579 if (sh & 4)
6580 tcg_gen_sari_i32(tmp2, tmp2, 16);
6581 else
6582 gen_sxth(tmp2);
6583 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6584 tcg_gen_shri_i64(tmp64, tmp64, 16);
6585 tmp = tcg_temp_new_i32();
6586 tcg_gen_trunc_i64_i32(tmp, tmp64);
6587 tcg_temp_free_i64(tmp64);
6588 if ((sh & 2) == 0) {
6589 tmp2 = load_reg(s, rn);
6590 gen_helper_add_setq(tmp, tmp, tmp2);
6591 tcg_temp_free_i32(tmp2);
6592 }
6593 store_reg(s, rd, tmp);
6594 } else {
6595 /* 16 * 16 */
6596 tmp = load_reg(s, rm);
6597 tmp2 = load_reg(s, rs);
6598 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6599 tcg_temp_free_i32(tmp2);
6600 if (op1 == 2) {
6601 tmp64 = tcg_temp_new_i64();
6602 tcg_gen_ext_i32_i64(tmp64, tmp);
6603 tcg_temp_free_i32(tmp);
6604 gen_addq(s, tmp64, rn, rd);
6605 gen_storeq_reg(s, rn, rd, tmp64);
6606 tcg_temp_free_i64(tmp64);
6607 } else {
6608 if (op1 == 0) {
6609 tmp2 = load_reg(s, rn);
6610 gen_helper_add_setq(tmp, tmp, tmp2);
6611 tcg_temp_free_i32(tmp2);
6612 }
6613 store_reg(s, rd, tmp);
6614 }
6615 }
6616 break;
6617 default:
6618 goto illegal_op;
6619 }
6620 } else if (((insn & 0x0e000000) == 0 &&
6621 (insn & 0x00000090) != 0x90) ||
6622 ((insn & 0x0e000000) == (1 << 25))) {
6623 int set_cc, logic_cc, shiftop;
6624
6625 op1 = (insn >> 21) & 0xf;
6626 set_cc = (insn >> 20) & 1;
6627 logic_cc = table_logic_cc[op1] & set_cc;
6628
6629 /* data processing instruction */
6630 if (insn & (1 << 25)) {
6631 /* immediate operand */
6632 val = insn & 0xff;
6633 shift = ((insn >> 8) & 0xf) * 2;
6634 if (shift) {
6635 val = (val >> shift) | (val << (32 - shift));
6636 }
6637 tmp2 = tcg_temp_new_i32();
6638 tcg_gen_movi_i32(tmp2, val);
6639 if (logic_cc && shift) {
6640 gen_set_CF_bit31(tmp2);
6641 }
6642 } else {
6643 /* register */
6644 rm = (insn) & 0xf;
6645 tmp2 = load_reg(s, rm);
6646 shiftop = (insn >> 5) & 3;
6647 if (!(insn & (1 << 4))) {
6648 shift = (insn >> 7) & 0x1f;
6649 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6650 } else {
6651 rs = (insn >> 8) & 0xf;
6652 tmp = load_reg(s, rs);
6653 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6654 }
6655 }
6656 if (op1 != 0x0f && op1 != 0x0d) {
6657 rn = (insn >> 16) & 0xf;
6658 tmp = load_reg(s, rn);
6659 } else {
6660 TCGV_UNUSED(tmp);
6661 }
6662 rd = (insn >> 12) & 0xf;
6663 switch(op1) {
6664 case 0x00:
6665 tcg_gen_and_i32(tmp, tmp, tmp2);
6666 if (logic_cc) {
6667 gen_logic_CC(tmp);
6668 }
6669 store_reg_bx(env, s, rd, tmp);
6670 break;
6671 case 0x01:
6672 tcg_gen_xor_i32(tmp, tmp, tmp2);
6673 if (logic_cc) {
6674 gen_logic_CC(tmp);
6675 }
6676 store_reg_bx(env, s, rd, tmp);
6677 break;
6678 case 0x02:
6679 if (set_cc && rd == 15) {
6680 /* SUBS r15, ... is used for exception return. */
6681 if (IS_USER(s)) {
6682 goto illegal_op;
6683 }
6684 gen_helper_sub_cc(tmp, tmp, tmp2);
6685 gen_exception_return(s, tmp);
6686 } else {
6687 if (set_cc) {
6688 gen_helper_sub_cc(tmp, tmp, tmp2);
6689 } else {
6690 tcg_gen_sub_i32(tmp, tmp, tmp2);
6691 }
6692 store_reg_bx(env, s, rd, tmp);
6693 }
6694 break;
6695 case 0x03:
6696 if (set_cc) {
6697 gen_helper_sub_cc(tmp, tmp2, tmp);
6698 } else {
6699 tcg_gen_sub_i32(tmp, tmp2, tmp);
6700 }
6701 store_reg_bx(env, s, rd, tmp);
6702 break;
6703 case 0x04:
6704 if (set_cc) {
6705 gen_helper_add_cc(tmp, tmp, tmp2);
6706 } else {
6707 tcg_gen_add_i32(tmp, tmp, tmp2);
6708 }
6709 store_reg_bx(env, s, rd, tmp);
6710 break;
6711 case 0x05:
6712 if (set_cc) {
6713 gen_helper_adc_cc(tmp, tmp, tmp2);
6714 } else {
6715 gen_add_carry(tmp, tmp, tmp2);
6716 }
6717 store_reg_bx(env, s, rd, tmp);
6718 break;
6719 case 0x06:
6720 if (set_cc) {
6721 gen_helper_sbc_cc(tmp, tmp, tmp2);
6722 } else {
6723 gen_sub_carry(tmp, tmp, tmp2);
6724 }
6725 store_reg_bx(env, s, rd, tmp);
6726 break;
6727 case 0x07:
6728 if (set_cc) {
6729 gen_helper_sbc_cc(tmp, tmp2, tmp);
6730 } else {
6731 gen_sub_carry(tmp, tmp2, tmp);
6732 }
6733 store_reg_bx(env, s, rd, tmp);
6734 break;
6735 case 0x08:
6736 if (set_cc) {
6737 tcg_gen_and_i32(tmp, tmp, tmp2);
6738 gen_logic_CC(tmp);
6739 }
6740 tcg_temp_free_i32(tmp);
6741 break;
6742 case 0x09:
6743 if (set_cc) {
6744 tcg_gen_xor_i32(tmp, tmp, tmp2);
6745 gen_logic_CC(tmp);
6746 }
6747 tcg_temp_free_i32(tmp);
6748 break;
6749 case 0x0a:
6750 if (set_cc) {
6751 gen_helper_sub_cc(tmp, tmp, tmp2);
6752 }
6753 tcg_temp_free_i32(tmp);
6754 break;
6755 case 0x0b:
6756 if (set_cc) {
6757 gen_helper_add_cc(tmp, tmp, tmp2);
6758 }
6759 tcg_temp_free_i32(tmp);
6760 break;
6761 case 0x0c:
6762 tcg_gen_or_i32(tmp, tmp, tmp2);
6763 if (logic_cc) {
6764 gen_logic_CC(tmp);
6765 }
6766 store_reg_bx(env, s, rd, tmp);
6767 break;
6768 case 0x0d:
6769 if (logic_cc && rd == 15) {
6770 /* MOVS r15, ... is used for exception return. */
6771 if (IS_USER(s)) {
6772 goto illegal_op;
6773 }
6774 gen_exception_return(s, tmp2);
6775 } else {
6776 if (logic_cc) {
6777 gen_logic_CC(tmp2);
6778 }
6779 store_reg_bx(env, s, rd, tmp2);
6780 }
6781 break;
6782 case 0x0e:
6783 tcg_gen_andc_i32(tmp, tmp, tmp2);
6784 if (logic_cc) {
6785 gen_logic_CC(tmp);
6786 }
6787 store_reg_bx(env, s, rd, tmp);
6788 break;
6789 default:
6790 case 0x0f:
6791 tcg_gen_not_i32(tmp2, tmp2);
6792 if (logic_cc) {
6793 gen_logic_CC(tmp2);
6794 }
6795 store_reg_bx(env, s, rd, tmp2);
6796 break;
6797 }
6798 if (op1 != 0x0f && op1 != 0x0d) {
6799 tcg_temp_free_i32(tmp2);
6800 }
6801 } else {
6802 /* other instructions */
6803 op1 = (insn >> 24) & 0xf;
6804 switch(op1) {
6805 case 0x0:
6806 case 0x1:
6807 /* multiplies, extra load/stores */
6808 sh = (insn >> 5) & 3;
6809 if (sh == 0) {
6810 if (op1 == 0x0) {
6811 rd = (insn >> 16) & 0xf;
6812 rn = (insn >> 12) & 0xf;
6813 rs = (insn >> 8) & 0xf;
6814 rm = (insn) & 0xf;
6815 op1 = (insn >> 20) & 0xf;
6816 switch (op1) {
6817 case 0: case 1: case 2: case 3: case 6:
6818 /* 32 bit mul */
6819 tmp = load_reg(s, rs);
6820 tmp2 = load_reg(s, rm);
6821 tcg_gen_mul_i32(tmp, tmp, tmp2);
6822 tcg_temp_free_i32(tmp2);
6823 if (insn & (1 << 22)) {
6824 /* Subtract (mls) */
6825 ARCH(6T2);
6826 tmp2 = load_reg(s, rn);
6827 tcg_gen_sub_i32(tmp, tmp2, tmp);
6828 tcg_temp_free_i32(tmp2);
6829 } else if (insn & (1 << 21)) {
6830 /* Add */
6831 tmp2 = load_reg(s, rn);
6832 tcg_gen_add_i32(tmp, tmp, tmp2);
6833 tcg_temp_free_i32(tmp2);
6834 }
6835 if (insn & (1 << 20))
6836 gen_logic_CC(tmp);
6837 store_reg(s, rd, tmp);
6838 break;
6839 case 4:
6840 /* 64 bit mul double accumulate (UMAAL) */
6841 ARCH(6);
6842 tmp = load_reg(s, rs);
6843 tmp2 = load_reg(s, rm);
6844 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6845 gen_addq_lo(s, tmp64, rn);
6846 gen_addq_lo(s, tmp64, rd);
6847 gen_storeq_reg(s, rn, rd, tmp64);
6848 tcg_temp_free_i64(tmp64);
6849 break;
6850 case 8: case 9: case 10: case 11:
6851 case 12: case 13: case 14: case 15:
6852 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6853 tmp = load_reg(s, rs);
6854 tmp2 = load_reg(s, rm);
6855 if (insn & (1 << 22)) {
6856 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6857 } else {
6858 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6859 }
6860 if (insn & (1 << 21)) { /* mult accumulate */
6861 gen_addq(s, tmp64, rn, rd);
6862 }
6863 if (insn & (1 << 20)) {
6864 gen_logicq_cc(tmp64);
6865 }
6866 gen_storeq_reg(s, rn, rd, tmp64);
6867 tcg_temp_free_i64(tmp64);
6868 break;
6869 default:
6870 goto illegal_op;
6871 }
6872 } else {
6873 rn = (insn >> 16) & 0xf;
6874 rd = (insn >> 12) & 0xf;
6875 if (insn & (1 << 23)) {
6876 /* load/store exclusive */
6877 op1 = (insn >> 21) & 0x3;
6878 if (op1)
6879 ARCH(6K);
6880 else
6881 ARCH(6);
6882 addr = tcg_temp_local_new_i32();
6883 load_reg_var(s, addr, rn);
6884 if (insn & (1 << 20)) {
6885 switch (op1) {
6886 case 0: /* ldrex */
6887 gen_load_exclusive(s, rd, 15, addr, 2);
6888 break;
6889 case 1: /* ldrexd */
6890 gen_load_exclusive(s, rd, rd + 1, addr, 3);
6891 break;
6892 case 2: /* ldrexb */
6893 gen_load_exclusive(s, rd, 15, addr, 0);
6894 break;
6895 case 3: /* ldrexh */
6896 gen_load_exclusive(s, rd, 15, addr, 1);
6897 break;
6898 default:
6899 abort();
6900 }
6901 } else {
6902 rm = insn & 0xf;
6903 switch (op1) {
6904 case 0: /* strex */
6905 gen_store_exclusive(s, rd, rm, 15, addr, 2);
6906 break;
6907 case 1: /* strexd */
6908 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
6909 break;
6910 case 2: /* strexb */
6911 gen_store_exclusive(s, rd, rm, 15, addr, 0);
6912 break;
6913 case 3: /* strexh */
6914 gen_store_exclusive(s, rd, rm, 15, addr, 1);
6915 break;
6916 default:
6917 abort();
6918 }
6919 }
6920 tcg_temp_free(addr);
6921 } else {
6922 /* SWP instruction */
6923 rm = (insn) & 0xf;
6924
6925 /* ??? This is not really atomic. However we know
6926 we never have multiple CPUs running in parallel,
6927 so it is good enough. */
6928 addr = load_reg(s, rn);
6929 tmp = load_reg(s, rm);
6930 if (insn & (1 << 22)) {
6931 tmp2 = gen_ld8u(addr, IS_USER(s));
6932 gen_st8(tmp, addr, IS_USER(s));
6933 } else {
6934 tmp2 = gen_ld32(addr, IS_USER(s));
6935 gen_st32(tmp, addr, IS_USER(s));
6936 }
6937 tcg_temp_free_i32(addr);
6938 store_reg(s, rd, tmp2);
6939 }
6940 }
6941 } else {
6942 int address_offset;
6943 int load;
6944 /* Misc load/store */
6945 rn = (insn >> 16) & 0xf;
6946 rd = (insn >> 12) & 0xf;
6947 addr = load_reg(s, rn);
6948 if (insn & (1 << 24))
6949 gen_add_datah_offset(s, insn, 0, addr);
6950 address_offset = 0;
6951 if (insn & (1 << 20)) {
6952 /* load */
6953 switch(sh) {
6954 case 1:
6955 tmp = gen_ld16u(addr, IS_USER(s));
6956 break;
6957 case 2:
6958 tmp = gen_ld8s(addr, IS_USER(s));
6959 break;
6960 default:
6961 case 3:
6962 tmp = gen_ld16s(addr, IS_USER(s));
6963 break;
6964 }
6965 load = 1;
6966 } else if (sh & 2) {
6967 ARCH(5TE);
6968 /* doubleword */
6969 if (sh & 1) {
6970 /* store */
6971 tmp = load_reg(s, rd);
6972 gen_st32(tmp, addr, IS_USER(s));
6973 tcg_gen_addi_i32(addr, addr, 4);
6974 tmp = load_reg(s, rd + 1);
6975 gen_st32(tmp, addr, IS_USER(s));
6976 load = 0;
6977 } else {
6978 /* load */
6979 tmp = gen_ld32(addr, IS_USER(s));
6980 store_reg(s, rd, tmp);
6981 tcg_gen_addi_i32(addr, addr, 4);
6982 tmp = gen_ld32(addr, IS_USER(s));
6983 rd++;
6984 load = 1;
6985 }
6986 address_offset = -4;
6987 } else {
6988 /* store */
6989 tmp = load_reg(s, rd);
6990 gen_st16(tmp, addr, IS_USER(s));
6991 load = 0;
6992 }
6993 /* Perform base writeback before the loaded value to
6994 ensure correct behavior with overlapping index registers.
6995 ldrd with base writeback is is undefined if the
6996 destination and index registers overlap. */
6997 if (!(insn & (1 << 24))) {
6998 gen_add_datah_offset(s, insn, address_offset, addr);
6999 store_reg(s, rn, addr);
7000 } else if (insn & (1 << 21)) {
7001 if (address_offset)
7002 tcg_gen_addi_i32(addr, addr, address_offset);
7003 store_reg(s, rn, addr);
7004 } else {
7005 tcg_temp_free_i32(addr);
7006 }
7007 if (load) {
7008 /* Complete the load. */
7009 store_reg(s, rd, tmp);
7010 }
7011 }
7012 break;
7013 case 0x4:
7014 case 0x5:
7015 goto do_ldst;
7016 case 0x6:
7017 case 0x7:
7018 if (insn & (1 << 4)) {
7019 ARCH(6);
7020 /* Armv6 Media instructions. */
7021 rm = insn & 0xf;
7022 rn = (insn >> 16) & 0xf;
7023 rd = (insn >> 12) & 0xf;
7024 rs = (insn >> 8) & 0xf;
7025 switch ((insn >> 23) & 3) {
7026 case 0: /* Parallel add/subtract. */
7027 op1 = (insn >> 20) & 7;
7028 tmp = load_reg(s, rn);
7029 tmp2 = load_reg(s, rm);
7030 sh = (insn >> 5) & 7;
7031 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
7032 goto illegal_op;
7033 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
7034 tcg_temp_free_i32(tmp2);
7035 store_reg(s, rd, tmp);
7036 break;
7037 case 1:
7038 if ((insn & 0x00700020) == 0) {
7039 /* Halfword pack. */
7040 tmp = load_reg(s, rn);
7041 tmp2 = load_reg(s, rm);
7042 shift = (insn >> 7) & 0x1f;
7043 if (insn & (1 << 6)) {
7044 /* pkhtb */
7045 if (shift == 0)
7046 shift = 31;
7047 tcg_gen_sari_i32(tmp2, tmp2, shift);
7048 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7049 tcg_gen_ext16u_i32(tmp2, tmp2);
7050 } else {
7051 /* pkhbt */
7052 if (shift)
7053 tcg_gen_shli_i32(tmp2, tmp2, shift);
7054 tcg_gen_ext16u_i32(tmp, tmp);
7055 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7056 }
7057 tcg_gen_or_i32(tmp, tmp, tmp2);
7058 tcg_temp_free_i32(tmp2);
7059 store_reg(s, rd, tmp);
7060 } else if ((insn & 0x00200020) == 0x00200000) {
7061 /* [us]sat */
7062 tmp = load_reg(s, rm);
7063 shift = (insn >> 7) & 0x1f;
7064 if (insn & (1 << 6)) {
7065 if (shift == 0)
7066 shift = 31;
7067 tcg_gen_sari_i32(tmp, tmp, shift);
7068 } else {
7069 tcg_gen_shli_i32(tmp, tmp, shift);
7070 }
7071 sh = (insn >> 16) & 0x1f;
7072 tmp2 = tcg_const_i32(sh);
7073 if (insn & (1 << 22))
7074 gen_helper_usat(tmp, tmp, tmp2);
7075 else
7076 gen_helper_ssat(tmp, tmp, tmp2);
7077 tcg_temp_free_i32(tmp2);
7078 store_reg(s, rd, tmp);
7079 } else if ((insn & 0x00300fe0) == 0x00200f20) {
7080 /* [us]sat16 */
7081 tmp = load_reg(s, rm);
7082 sh = (insn >> 16) & 0x1f;
7083 tmp2 = tcg_const_i32(sh);
7084 if (insn & (1 << 22))
7085 gen_helper_usat16(tmp, tmp, tmp2);
7086 else
7087 gen_helper_ssat16(tmp, tmp, tmp2);
7088 tcg_temp_free_i32(tmp2);
7089 store_reg(s, rd, tmp);
7090 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
7091 /* Select bytes. */
7092 tmp = load_reg(s, rn);
7093 tmp2 = load_reg(s, rm);
7094 tmp3 = tcg_temp_new_i32();
7095 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7096 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7097 tcg_temp_free_i32(tmp3);
7098 tcg_temp_free_i32(tmp2);
7099 store_reg(s, rd, tmp);
7100 } else if ((insn & 0x000003e0) == 0x00000060) {
7101 tmp = load_reg(s, rm);
7102 shift = (insn >> 10) & 3;
7103 /* ??? In many cases it's not neccessary to do a
7104 rotate, a shift is sufficient. */
7105 if (shift != 0)
7106 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7107 op1 = (insn >> 20) & 7;
7108 switch (op1) {
7109 case 0: gen_sxtb16(tmp); break;
7110 case 2: gen_sxtb(tmp); break;
7111 case 3: gen_sxth(tmp); break;
7112 case 4: gen_uxtb16(tmp); break;
7113 case 6: gen_uxtb(tmp); break;
7114 case 7: gen_uxth(tmp); break;
7115 default: goto illegal_op;
7116 }
7117 if (rn != 15) {
7118 tmp2 = load_reg(s, rn);
7119 if ((op1 & 3) == 0) {
7120 gen_add16(tmp, tmp2);
7121 } else {
7122 tcg_gen_add_i32(tmp, tmp, tmp2);
7123 tcg_temp_free_i32(tmp2);
7124 }
7125 }
7126 store_reg(s, rd, tmp);
7127 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7128 /* rev */
7129 tmp = load_reg(s, rm);
7130 if (insn & (1 << 22)) {
7131 if (insn & (1 << 7)) {
7132 gen_revsh(tmp);
7133 } else {
7134 ARCH(6T2);
7135 gen_helper_rbit(tmp, tmp);
7136 }
7137 } else {
7138 if (insn & (1 << 7))
7139 gen_rev16(tmp);
7140 else
7141 tcg_gen_bswap32_i32(tmp, tmp);
7142 }
7143 store_reg(s, rd, tmp);
7144 } else {
7145 goto illegal_op;
7146 }
7147 break;
7148 case 2: /* Multiplies (Type 3). */
7149 tmp = load_reg(s, rm);
7150 tmp2 = load_reg(s, rs);
7151 if (insn & (1 << 20)) {
7152 /* Signed multiply most significant [accumulate].
7153 (SMMUL, SMMLA, SMMLS) */
7154 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7155
7156 if (rd != 15) {
7157 tmp = load_reg(s, rd);
7158 if (insn & (1 << 6)) {
7159 tmp64 = gen_subq_msw(tmp64, tmp);
7160 } else {
7161 tmp64 = gen_addq_msw(tmp64, tmp);
7162 }
7163 }
7164 if (insn & (1 << 5)) {
7165 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7166 }
7167 tcg_gen_shri_i64(tmp64, tmp64, 32);
7168 tmp = tcg_temp_new_i32();
7169 tcg_gen_trunc_i64_i32(tmp, tmp64);
7170 tcg_temp_free_i64(tmp64);
7171 store_reg(s, rn, tmp);
7172 } else {
7173 if (insn & (1 << 5))
7174 gen_swap_half(tmp2);
7175 gen_smul_dual(tmp, tmp2);
7176 if (insn & (1 << 6)) {
7177 /* This subtraction cannot overflow. */
7178 tcg_gen_sub_i32(tmp, tmp, tmp2);
7179 } else {
7180 /* This addition cannot overflow 32 bits;
7181 * however it may overflow considered as a signed
7182 * operation, in which case we must set the Q flag.
7183 */
7184 gen_helper_add_setq(tmp, tmp, tmp2);
7185 }
7186 tcg_temp_free_i32(tmp2);
7187 if (insn & (1 << 22)) {
7188 /* smlald, smlsld */
7189 tmp64 = tcg_temp_new_i64();
7190 tcg_gen_ext_i32_i64(tmp64, tmp);
7191 tcg_temp_free_i32(tmp);
7192 gen_addq(s, tmp64, rd, rn);
7193 gen_storeq_reg(s, rd, rn, tmp64);
7194 tcg_temp_free_i64(tmp64);
7195 } else {
7196 /* smuad, smusd, smlad, smlsd */
7197 if (rd != 15)
7198 {
7199 tmp2 = load_reg(s, rd);
7200 gen_helper_add_setq(tmp, tmp, tmp2);
7201 tcg_temp_free_i32(tmp2);
7202 }
7203 store_reg(s, rn, tmp);
7204 }
7205 }
7206 break;
7207 case 3:
7208 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7209 switch (op1) {
7210 case 0: /* Unsigned sum of absolute differences. */
7211 ARCH(6);
7212 tmp = load_reg(s, rm);
7213 tmp2 = load_reg(s, rs);
7214 gen_helper_usad8(tmp, tmp, tmp2);
7215 tcg_temp_free_i32(tmp2);
7216 if (rd != 15) {
7217 tmp2 = load_reg(s, rd);
7218 tcg_gen_add_i32(tmp, tmp, tmp2);
7219 tcg_temp_free_i32(tmp2);
7220 }
7221 store_reg(s, rn, tmp);
7222 break;
7223 case 0x20: case 0x24: case 0x28: case 0x2c:
7224 /* Bitfield insert/clear. */
7225 ARCH(6T2);
7226 shift = (insn >> 7) & 0x1f;
7227 i = (insn >> 16) & 0x1f;
7228 i = i + 1 - shift;
7229 if (rm == 15) {
7230 tmp = tcg_temp_new_i32();
7231 tcg_gen_movi_i32(tmp, 0);
7232 } else {
7233 tmp = load_reg(s, rm);
7234 }
7235 if (i != 32) {
7236 tmp2 = load_reg(s, rd);
7237 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7238 tcg_temp_free_i32(tmp2);
7239 }
7240 store_reg(s, rd, tmp);
7241 break;
7242 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7243 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7244 ARCH(6T2);
7245 tmp = load_reg(s, rm);
7246 shift = (insn >> 7) & 0x1f;
7247 i = ((insn >> 16) & 0x1f) + 1;
7248 if (shift + i > 32)
7249 goto illegal_op;
7250 if (i < 32) {
7251 if (op1 & 0x20) {
7252 gen_ubfx(tmp, shift, (1u << i) - 1);
7253 } else {
7254 gen_sbfx(tmp, shift, i);
7255 }
7256 }
7257 store_reg(s, rd, tmp);
7258 break;
7259 default:
7260 goto illegal_op;
7261 }
7262 break;
7263 }
7264 break;
7265 }
7266 do_ldst:
7267 /* Check for undefined extension instructions
7268 * per the ARM Bible IE:
7269 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7270 */
7271 sh = (0xf << 20) | (0xf << 4);
7272 if (op1 == 0x7 && ((insn & sh) == sh))
7273 {
7274 goto illegal_op;
7275 }
7276 /* load/store byte/word */
7277 rn = (insn >> 16) & 0xf;
7278 rd = (insn >> 12) & 0xf;
7279 tmp2 = load_reg(s, rn);
7280 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7281 if (insn & (1 << 24))
7282 gen_add_data_offset(s, insn, tmp2);
7283 if (insn & (1 << 20)) {
7284 /* load */
7285 if (insn & (1 << 22)) {
7286 tmp = gen_ld8u(tmp2, i);
7287 } else {
7288 tmp = gen_ld32(tmp2, i);
7289 }
7290 } else {
7291 /* store */
7292 tmp = load_reg(s, rd);
7293 if (insn & (1 << 22))
7294 gen_st8(tmp, tmp2, i);
7295 else
7296 gen_st32(tmp, tmp2, i);
7297 }
7298 if (!(insn & (1 << 24))) {
7299 gen_add_data_offset(s, insn, tmp2);
7300 store_reg(s, rn, tmp2);
7301 } else if (insn & (1 << 21)) {
7302 store_reg(s, rn, tmp2);
7303 } else {
7304 tcg_temp_free_i32(tmp2);
7305 }
7306 if (insn & (1 << 20)) {
7307 /* Complete the load. */
7308 store_reg_from_load(env, s, rd, tmp);
7309 }
7310 break;
7311 case 0x08:
7312 case 0x09:
7313 {
7314 int j, n, user, loaded_base;
7315 TCGv loaded_var;
7316 /* load/store multiple words */
7317 /* XXX: store correct base if write back */
7318 user = 0;
7319 if (insn & (1 << 22)) {
7320 if (IS_USER(s))
7321 goto illegal_op; /* only usable in supervisor mode */
7322
7323 if ((insn & (1 << 15)) == 0)
7324 user = 1;
7325 }
7326 rn = (insn >> 16) & 0xf;
7327 addr = load_reg(s, rn);
7328
7329 /* compute total size */
7330 loaded_base = 0;
7331 TCGV_UNUSED(loaded_var);
7332 n = 0;
7333 for(i=0;i<16;i++) {
7334 if (insn & (1 << i))
7335 n++;
7336 }
7337 /* XXX: test invalid n == 0 case ? */
7338 if (insn & (1 << 23)) {
7339 if (insn & (1 << 24)) {
7340 /* pre increment */
7341 tcg_gen_addi_i32(addr, addr, 4);
7342 } else {
7343 /* post increment */
7344 }
7345 } else {
7346 if (insn & (1 << 24)) {
7347 /* pre decrement */
7348 tcg_gen_addi_i32(addr, addr, -(n * 4));
7349 } else {
7350 /* post decrement */
7351 if (n != 1)
7352 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7353 }
7354 }
7355 j = 0;
7356 for(i=0;i<16;i++) {
7357 if (insn & (1 << i)) {
7358 if (insn & (1 << 20)) {
7359 /* load */
7360 tmp = gen_ld32(addr, IS_USER(s));
7361 if (user) {
7362 tmp2 = tcg_const_i32(i);
7363 gen_helper_set_user_reg(tmp2, tmp);
7364 tcg_temp_free_i32(tmp2);
7365 tcg_temp_free_i32(tmp);
7366 } else if (i == rn) {
7367 loaded_var = tmp;
7368 loaded_base = 1;
7369 } else {
7370 store_reg_from_load(env, s, i, tmp);
7371 }
7372 } else {
7373 /* store */
7374 if (i == 15) {
7375 /* special case: r15 = PC + 8 */
7376 val = (long)s->pc + 4;
7377 tmp = tcg_temp_new_i32();
7378 tcg_gen_movi_i32(tmp, val);
7379 } else if (user) {
7380 tmp = tcg_temp_new_i32();
7381 tmp2 = tcg_const_i32(i);
7382 gen_helper_get_user_reg(tmp, tmp2);
7383 tcg_temp_free_i32(tmp2);
7384 } else {
7385 tmp = load_reg(s, i);
7386 }
7387 gen_st32(tmp, addr, IS_USER(s));
7388 }
7389 j++;
7390 /* no need to add after the last transfer */
7391 if (j != n)
7392 tcg_gen_addi_i32(addr, addr, 4);
7393 }
7394 }
7395 if (insn & (1 << 21)) {
7396 /* write back */
7397 if (insn & (1 << 23)) {
7398 if (insn & (1 << 24)) {
7399 /* pre increment */
7400 } else {
7401 /* post increment */
7402 tcg_gen_addi_i32(addr, addr, 4);
7403 }
7404 } else {
7405 if (insn & (1 << 24)) {
7406 /* pre decrement */
7407 if (n != 1)
7408 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7409 } else {
7410 /* post decrement */
7411 tcg_gen_addi_i32(addr, addr, -(n * 4));
7412 }
7413 }
7414 store_reg(s, rn, addr);
7415 } else {
7416 tcg_temp_free_i32(addr);
7417 }
7418 if (loaded_base) {
7419 store_reg(s, rn, loaded_var);
7420 }
7421 if ((insn & (1 << 22)) && !user) {
7422 /* Restore CPSR from SPSR. */
7423 tmp = load_cpu_field(spsr);
7424 gen_set_cpsr(tmp, 0xffffffff);
7425 tcg_temp_free_i32(tmp);
7426 s->is_jmp = DISAS_UPDATE;
7427 }
7428 }
7429 break;
7430 case 0xa:
7431 case 0xb:
7432 {
7433 int32_t offset;
7434
7435 /* branch (and link) */
7436 val = (int32_t)s->pc;
7437 if (insn & (1 << 24)) {
7438 tmp = tcg_temp_new_i32();
7439 tcg_gen_movi_i32(tmp, val);
7440 store_reg(s, 14, tmp);
7441 }
7442 offset = (((int32_t)insn << 8) >> 8);
7443 val += (offset << 2) + 4;
7444 gen_jmp(s, val);
7445 }
7446 break;
7447 case 0xc:
7448 case 0xd:
7449 case 0xe:
7450 /* Coprocessor. */
7451 if (disas_coproc_insn(env, s, insn))
7452 goto illegal_op;
7453 break;
7454 case 0xf:
7455 /* swi */
7456 gen_set_pc_im(s->pc);
7457 s->is_jmp = DISAS_SWI;
7458 break;
7459 default:
7460 illegal_op:
7461 gen_exception_insn(s, 4, EXCP_UDEF);
7462 break;
7463 }
7464 }
7465 }
7466
7467 /* Return true if this is a Thumb-2 logical op. */
7468 static int
7469 thumb2_logic_op(int op)
7470 {
7471 return (op < 8);
7472 }
7473
7474 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7475 then set condition code flags based on the result of the operation.
7476 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7477 to the high bit of T1.
7478 Returns zero if the opcode is valid. */
7479
7480 static int
7481 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7482 {
7483 int logic_cc;
7484
7485 logic_cc = 0;
7486 switch (op) {
7487 case 0: /* and */
7488 tcg_gen_and_i32(t0, t0, t1);
7489 logic_cc = conds;
7490 break;
7491 case 1: /* bic */
7492 tcg_gen_andc_i32(t0, t0, t1);
7493 logic_cc = conds;
7494 break;
7495 case 2: /* orr */
7496 tcg_gen_or_i32(t0, t0, t1);
7497 logic_cc = conds;
7498 break;
7499 case 3: /* orn */
7500 tcg_gen_orc_i32(t0, t0, t1);
7501 logic_cc = conds;
7502 break;
7503 case 4: /* eor */
7504 tcg_gen_xor_i32(t0, t0, t1);
7505 logic_cc = conds;
7506 break;
7507 case 8: /* add */
7508 if (conds)
7509 gen_helper_add_cc(t0, t0, t1);
7510 else
7511 tcg_gen_add_i32(t0, t0, t1);
7512 break;
7513 case 10: /* adc */
7514 if (conds)
7515 gen_helper_adc_cc(t0, t0, t1);
7516 else
7517 gen_adc(t0, t1);
7518 break;
7519 case 11: /* sbc */
7520 if (conds)
7521 gen_helper_sbc_cc(t0, t0, t1);
7522 else
7523 gen_sub_carry(t0, t0, t1);
7524 break;
7525 case 13: /* sub */
7526 if (conds)
7527 gen_helper_sub_cc(t0, t0, t1);
7528 else
7529 tcg_gen_sub_i32(t0, t0, t1);
7530 break;
7531 case 14: /* rsb */
7532 if (conds)
7533 gen_helper_sub_cc(t0, t1, t0);
7534 else
7535 tcg_gen_sub_i32(t0, t1, t0);
7536 break;
7537 default: /* 5, 6, 7, 9, 12, 15. */
7538 return 1;
7539 }
7540 if (logic_cc) {
7541 gen_logic_CC(t0);
7542 if (shifter_out)
7543 gen_set_CF_bit31(t1);
7544 }
7545 return 0;
7546 }
7547
7548 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7549 is not legal. */
7550 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7551 {
7552 uint32_t insn, imm, shift, offset;
7553 uint32_t rd, rn, rm, rs;
7554 TCGv tmp;
7555 TCGv tmp2;
7556 TCGv tmp3;
7557 TCGv addr;
7558 TCGv_i64 tmp64;
7559 int op;
7560 int shiftop;
7561 int conds;
7562 int logic_cc;
7563
7564 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7565 || arm_feature (env, ARM_FEATURE_M))) {
7566 /* Thumb-1 cores may need to treat bl and blx as a pair of
7567 16-bit instructions to get correct prefetch abort behavior. */
7568 insn = insn_hw1;
7569 if ((insn & (1 << 12)) == 0) {
7570 ARCH(5);
7571 /* Second half of blx. */
7572 offset = ((insn & 0x7ff) << 1);
7573 tmp = load_reg(s, 14);
7574 tcg_gen_addi_i32(tmp, tmp, offset);
7575 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7576
7577 tmp2 = tcg_temp_new_i32();
7578 tcg_gen_movi_i32(tmp2, s->pc | 1);
7579 store_reg(s, 14, tmp2);
7580 gen_bx(s, tmp);
7581 return 0;
7582 }
7583 if (insn & (1 << 11)) {
7584 /* Second half of bl. */
7585 offset = ((insn & 0x7ff) << 1) | 1;
7586 tmp = load_reg(s, 14);
7587 tcg_gen_addi_i32(tmp, tmp, offset);
7588
7589 tmp2 = tcg_temp_new_i32();
7590 tcg_gen_movi_i32(tmp2, s->pc | 1);
7591 store_reg(s, 14, tmp2);
7592 gen_bx(s, tmp);
7593 return 0;
7594 }
7595 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7596 /* Instruction spans a page boundary. Implement it as two
7597 16-bit instructions in case the second half causes an
7598 prefetch abort. */
7599 offset = ((int32_t)insn << 21) >> 9;
7600 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7601 return 0;
7602 }
7603 /* Fall through to 32-bit decode. */
7604 }
7605
7606 insn = lduw_code(s->pc);
7607 s->pc += 2;
7608 insn |= (uint32_t)insn_hw1 << 16;
7609
7610 if ((insn & 0xf800e800) != 0xf000e800) {
7611 ARCH(6T2);
7612 }
7613
7614 rn = (insn >> 16) & 0xf;
7615 rs = (insn >> 12) & 0xf;
7616 rd = (insn >> 8) & 0xf;
7617 rm = insn & 0xf;
7618 switch ((insn >> 25) & 0xf) {
7619 case 0: case 1: case 2: case 3:
7620 /* 16-bit instructions. Should never happen. */
7621 abort();
7622 case 4:
7623 if (insn & (1 << 22)) {
7624 /* Other load/store, table branch. */
7625 if (insn & 0x01200000) {
7626 /* Load/store doubleword. */
7627 if (rn == 15) {
7628 addr = tcg_temp_new_i32();
7629 tcg_gen_movi_i32(addr, s->pc & ~3);
7630 } else {
7631 addr = load_reg(s, rn);
7632 }
7633 offset = (insn & 0xff) * 4;
7634 if ((insn & (1 << 23)) == 0)
7635 offset = -offset;
7636 if (insn & (1 << 24)) {
7637 tcg_gen_addi_i32(addr, addr, offset);
7638 offset = 0;
7639 }
7640 if (insn & (1 << 20)) {
7641 /* ldrd */
7642 tmp = gen_ld32(addr, IS_USER(s));
7643 store_reg(s, rs, tmp);
7644 tcg_gen_addi_i32(addr, addr, 4);
7645 tmp = gen_ld32(addr, IS_USER(s));
7646 store_reg(s, rd, tmp);
7647 } else {
7648 /* strd */
7649 tmp = load_reg(s, rs);
7650 gen_st32(tmp, addr, IS_USER(s));
7651 tcg_gen_addi_i32(addr, addr, 4);
7652 tmp = load_reg(s, rd);
7653 gen_st32(tmp, addr, IS_USER(s));
7654 }
7655 if (insn & (1 << 21)) {
7656 /* Base writeback. */
7657 if (rn == 15)
7658 goto illegal_op;
7659 tcg_gen_addi_i32(addr, addr, offset - 4);
7660 store_reg(s, rn, addr);
7661 } else {
7662 tcg_temp_free_i32(addr);
7663 }
7664 } else if ((insn & (1 << 23)) == 0) {
7665 /* Load/store exclusive word. */
7666 addr = tcg_temp_local_new();
7667 load_reg_var(s, addr, rn);
7668 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7669 if (insn & (1 << 20)) {
7670 gen_load_exclusive(s, rs, 15, addr, 2);
7671 } else {
7672 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7673 }
7674 tcg_temp_free(addr);
7675 } else if ((insn & (1 << 6)) == 0) {
7676 /* Table Branch. */
7677 if (rn == 15) {
7678 addr = tcg_temp_new_i32();
7679 tcg_gen_movi_i32(addr, s->pc);
7680 } else {
7681 addr = load_reg(s, rn);
7682 }
7683 tmp = load_reg(s, rm);
7684 tcg_gen_add_i32(addr, addr, tmp);
7685 if (insn & (1 << 4)) {
7686 /* tbh */
7687 tcg_gen_add_i32(addr, addr, tmp);
7688 tcg_temp_free_i32(tmp);
7689 tmp = gen_ld16u(addr, IS_USER(s));
7690 } else { /* tbb */
7691 tcg_temp_free_i32(tmp);
7692 tmp = gen_ld8u(addr, IS_USER(s));
7693 }
7694 tcg_temp_free_i32(addr);
7695 tcg_gen_shli_i32(tmp, tmp, 1);
7696 tcg_gen_addi_i32(tmp, tmp, s->pc);
7697 store_reg(s, 15, tmp);
7698 } else {
7699 /* Load/store exclusive byte/halfword/doubleword. */
7700 ARCH(7);
7701 op = (insn >> 4) & 0x3;
7702 if (op == 2) {
7703 goto illegal_op;
7704 }
7705 addr = tcg_temp_local_new();
7706 load_reg_var(s, addr, rn);
7707 if (insn & (1 << 20)) {
7708 gen_load_exclusive(s, rs, rd, addr, op);
7709 } else {
7710 gen_store_exclusive(s, rm, rs, rd, addr, op);
7711 }
7712 tcg_temp_free(addr);
7713 }
7714 } else {
7715 /* Load/store multiple, RFE, SRS. */
7716 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7717 /* Not available in user mode. */
7718 if (IS_USER(s))
7719 goto illegal_op;
7720 if (insn & (1 << 20)) {
7721 /* rfe */
7722 addr = load_reg(s, rn);
7723 if ((insn & (1 << 24)) == 0)
7724 tcg_gen_addi_i32(addr, addr, -8);
7725 /* Load PC into tmp and CPSR into tmp2. */
7726 tmp = gen_ld32(addr, 0);
7727 tcg_gen_addi_i32(addr, addr, 4);
7728 tmp2 = gen_ld32(addr, 0);
7729 if (insn & (1 << 21)) {
7730 /* Base writeback. */
7731 if (insn & (1 << 24)) {
7732 tcg_gen_addi_i32(addr, addr, 4);
7733 } else {
7734 tcg_gen_addi_i32(addr, addr, -4);
7735 }
7736 store_reg(s, rn, addr);
7737 } else {
7738 tcg_temp_free_i32(addr);
7739 }
7740 gen_rfe(s, tmp, tmp2);
7741 } else {
7742 /* srs */
7743 op = (insn & 0x1f);
7744 addr = tcg_temp_new_i32();
7745 tmp = tcg_const_i32(op);
7746 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7747 tcg_temp_free_i32(tmp);
7748 if ((insn & (1 << 24)) == 0) {
7749 tcg_gen_addi_i32(addr, addr, -8);
7750 }
7751 tmp = load_reg(s, 14);
7752 gen_st32(tmp, addr, 0);
7753 tcg_gen_addi_i32(addr, addr, 4);
7754 tmp = tcg_temp_new_i32();
7755 gen_helper_cpsr_read(tmp);
7756 gen_st32(tmp, addr, 0);
7757 if (insn & (1 << 21)) {
7758 if ((insn & (1 << 24)) == 0) {
7759 tcg_gen_addi_i32(addr, addr, -4);
7760 } else {
7761 tcg_gen_addi_i32(addr, addr, 4);
7762 }
7763 tmp = tcg_const_i32(op);
7764 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7765 tcg_temp_free_i32(tmp);
7766 } else {
7767 tcg_temp_free_i32(addr);
7768 }
7769 }
7770 } else {
7771 int i;
7772 /* Load/store multiple. */
7773 addr = load_reg(s, rn);
7774 offset = 0;
7775 for (i = 0; i < 16; i++) {
7776 if (insn & (1 << i))
7777 offset += 4;
7778 }
7779 if (insn & (1 << 24)) {
7780 tcg_gen_addi_i32(addr, addr, -offset);
7781 }
7782
7783 for (i = 0; i < 16; i++) {
7784 if ((insn & (1 << i)) == 0)
7785 continue;
7786 if (insn & (1 << 20)) {
7787 /* Load. */
7788 tmp = gen_ld32(addr, IS_USER(s));
7789 if (i == 15) {
7790 gen_bx(s, tmp);
7791 } else {
7792 store_reg(s, i, tmp);
7793 }
7794 } else {
7795 /* Store. */
7796 tmp = load_reg(s, i);
7797 gen_st32(tmp, addr, IS_USER(s));
7798 }
7799 tcg_gen_addi_i32(addr, addr, 4);
7800 }
7801 if (insn & (1 << 21)) {
7802 /* Base register writeback. */
7803 if (insn & (1 << 24)) {
7804 tcg_gen_addi_i32(addr, addr, -offset);
7805 }
7806 /* Fault if writeback register is in register list. */
7807 if (insn & (1 << rn))
7808 goto illegal_op;
7809 store_reg(s, rn, addr);
7810 } else {
7811 tcg_temp_free_i32(addr);
7812 }
7813 }
7814 }
7815 break;
7816 case 5:
7817
7818 op = (insn >> 21) & 0xf;
7819 if (op == 6) {
7820 /* Halfword pack. */
7821 tmp = load_reg(s, rn);
7822 tmp2 = load_reg(s, rm);
7823 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7824 if (insn & (1 << 5)) {
7825 /* pkhtb */
7826 if (shift == 0)
7827 shift = 31;
7828 tcg_gen_sari_i32(tmp2, tmp2, shift);
7829 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7830 tcg_gen_ext16u_i32(tmp2, tmp2);
7831 } else {
7832 /* pkhbt */
7833 if (shift)
7834 tcg_gen_shli_i32(tmp2, tmp2, shift);
7835 tcg_gen_ext16u_i32(tmp, tmp);
7836 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7837 }
7838 tcg_gen_or_i32(tmp, tmp, tmp2);
7839 tcg_temp_free_i32(tmp2);
7840 store_reg(s, rd, tmp);
7841 } else {
7842 /* Data processing register constant shift. */
7843 if (rn == 15) {
7844 tmp = tcg_temp_new_i32();
7845 tcg_gen_movi_i32(tmp, 0);
7846 } else {
7847 tmp = load_reg(s, rn);
7848 }
7849 tmp2 = load_reg(s, rm);
7850
7851 shiftop = (insn >> 4) & 3;
7852 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7853 conds = (insn & (1 << 20)) != 0;
7854 logic_cc = (conds && thumb2_logic_op(op));
7855 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7856 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7857 goto illegal_op;
7858 tcg_temp_free_i32(tmp2);
7859 if (rd != 15) {
7860 store_reg(s, rd, tmp);
7861 } else {
7862 tcg_temp_free_i32(tmp);
7863 }
7864 }
7865 break;
7866 case 13: /* Misc data processing. */
7867 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7868 if (op < 4 && (insn & 0xf000) != 0xf000)
7869 goto illegal_op;
7870 switch (op) {
7871 case 0: /* Register controlled shift. */
7872 tmp = load_reg(s, rn);
7873 tmp2 = load_reg(s, rm);
7874 if ((insn & 0x70) != 0)
7875 goto illegal_op;
7876 op = (insn >> 21) & 3;
7877 logic_cc = (insn & (1 << 20)) != 0;
7878 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7879 if (logic_cc)
7880 gen_logic_CC(tmp);
7881 store_reg_bx(env, s, rd, tmp);
7882 break;
7883 case 1: /* Sign/zero extend. */
7884 tmp = load_reg(s, rm);
7885 shift = (insn >> 4) & 3;
7886 /* ??? In many cases it's not neccessary to do a
7887 rotate, a shift is sufficient. */
7888 if (shift != 0)
7889 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7890 op = (insn >> 20) & 7;
7891 switch (op) {
7892 case 0: gen_sxth(tmp); break;
7893 case 1: gen_uxth(tmp); break;
7894 case 2: gen_sxtb16(tmp); break;
7895 case 3: gen_uxtb16(tmp); break;
7896 case 4: gen_sxtb(tmp); break;
7897 case 5: gen_uxtb(tmp); break;
7898 default: goto illegal_op;
7899 }
7900 if (rn != 15) {
7901 tmp2 = load_reg(s, rn);
7902 if ((op >> 1) == 1) {
7903 gen_add16(tmp, tmp2);
7904 } else {
7905 tcg_gen_add_i32(tmp, tmp, tmp2);
7906 tcg_temp_free_i32(tmp2);
7907 }
7908 }
7909 store_reg(s, rd, tmp);
7910 break;
7911 case 2: /* SIMD add/subtract. */
7912 op = (insn >> 20) & 7;
7913 shift = (insn >> 4) & 7;
7914 if ((op & 3) == 3 || (shift & 3) == 3)
7915 goto illegal_op;
7916 tmp = load_reg(s, rn);
7917 tmp2 = load_reg(s, rm);
7918 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7919 tcg_temp_free_i32(tmp2);
7920 store_reg(s, rd, tmp);
7921 break;
7922 case 3: /* Other data processing. */
7923 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7924 if (op < 4) {
7925 /* Saturating add/subtract. */
7926 tmp = load_reg(s, rn);
7927 tmp2 = load_reg(s, rm);
7928 if (op & 1)
7929 gen_helper_double_saturate(tmp, tmp);
7930 if (op & 2)
7931 gen_helper_sub_saturate(tmp, tmp2, tmp);
7932 else
7933 gen_helper_add_saturate(tmp, tmp, tmp2);
7934 tcg_temp_free_i32(tmp2);
7935 } else {
7936 tmp = load_reg(s, rn);
7937 switch (op) {
7938 case 0x0a: /* rbit */
7939 gen_helper_rbit(tmp, tmp);
7940 break;
7941 case 0x08: /* rev */
7942 tcg_gen_bswap32_i32(tmp, tmp);
7943 break;
7944 case 0x09: /* rev16 */
7945 gen_rev16(tmp);
7946 break;
7947 case 0x0b: /* revsh */
7948 gen_revsh(tmp);
7949 break;
7950 case 0x10: /* sel */
7951 tmp2 = load_reg(s, rm);
7952 tmp3 = tcg_temp_new_i32();
7953 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7954 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7955 tcg_temp_free_i32(tmp3);
7956 tcg_temp_free_i32(tmp2);
7957 break;
7958 case 0x18: /* clz */
7959 gen_helper_clz(tmp, tmp);
7960 break;
7961 default:
7962 goto illegal_op;
7963 }
7964 }
7965 store_reg(s, rd, tmp);
7966 break;
7967 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7968 op = (insn >> 4) & 0xf;
7969 tmp = load_reg(s, rn);
7970 tmp2 = load_reg(s, rm);
7971 switch ((insn >> 20) & 7) {
7972 case 0: /* 32 x 32 -> 32 */
7973 tcg_gen_mul_i32(tmp, tmp, tmp2);
7974 tcg_temp_free_i32(tmp2);
7975 if (rs != 15) {
7976 tmp2 = load_reg(s, rs);
7977 if (op)
7978 tcg_gen_sub_i32(tmp, tmp2, tmp);
7979 else
7980 tcg_gen_add_i32(tmp, tmp, tmp2);
7981 tcg_temp_free_i32(tmp2);
7982 }
7983 break;
7984 case 1: /* 16 x 16 -> 32 */
7985 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7986 tcg_temp_free_i32(tmp2);
7987 if (rs != 15) {
7988 tmp2 = load_reg(s, rs);
7989 gen_helper_add_setq(tmp, tmp, tmp2);
7990 tcg_temp_free_i32(tmp2);
7991 }
7992 break;
7993 case 2: /* Dual multiply add. */
7994 case 4: /* Dual multiply subtract. */
7995 if (op)
7996 gen_swap_half(tmp2);
7997 gen_smul_dual(tmp, tmp2);
7998 if (insn & (1 << 22)) {
7999 /* This subtraction cannot overflow. */
8000 tcg_gen_sub_i32(tmp, tmp, tmp2);
8001 } else {
8002 /* This addition cannot overflow 32 bits;
8003 * however it may overflow considered as a signed
8004 * operation, in which case we must set the Q flag.
8005 */
8006 gen_helper_add_setq(tmp, tmp, tmp2);
8007 }
8008 tcg_temp_free_i32(tmp2);
8009 if (rs != 15)
8010 {
8011 tmp2 = load_reg(s, rs);
8012 gen_helper_add_setq(tmp, tmp, tmp2);
8013 tcg_temp_free_i32(tmp2);
8014 }
8015 break;
8016 case 3: /* 32 * 16 -> 32msb */
8017 if (op)
8018 tcg_gen_sari_i32(tmp2, tmp2, 16);
8019 else
8020 gen_sxth(tmp2);
8021 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8022 tcg_gen_shri_i64(tmp64, tmp64, 16);
8023 tmp = tcg_temp_new_i32();
8024 tcg_gen_trunc_i64_i32(tmp, tmp64);
8025 tcg_temp_free_i64(tmp64);
8026 if (rs != 15)
8027 {
8028 tmp2 = load_reg(s, rs);
8029 gen_helper_add_setq(tmp, tmp, tmp2);
8030 tcg_temp_free_i32(tmp2);
8031 }
8032 break;
8033 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
8034 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8035 if (rs != 15) {
8036 tmp = load_reg(s, rs);
8037 if (insn & (1 << 20)) {
8038 tmp64 = gen_addq_msw(tmp64, tmp);
8039 } else {
8040 tmp64 = gen_subq_msw(tmp64, tmp);
8041 }
8042 }
8043 if (insn & (1 << 4)) {
8044 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8045 }
8046 tcg_gen_shri_i64(tmp64, tmp64, 32);
8047 tmp = tcg_temp_new_i32();
8048 tcg_gen_trunc_i64_i32(tmp, tmp64);
8049 tcg_temp_free_i64(tmp64);
8050 break;
8051 case 7: /* Unsigned sum of absolute differences. */
8052 gen_helper_usad8(tmp, tmp, tmp2);
8053 tcg_temp_free_i32(tmp2);
8054 if (rs != 15) {
8055 tmp2 = load_reg(s, rs);
8056 tcg_gen_add_i32(tmp, tmp, tmp2);
8057 tcg_temp_free_i32(tmp2);
8058 }
8059 break;
8060 }
8061 store_reg(s, rd, tmp);
8062 break;
8063 case 6: case 7: /* 64-bit multiply, Divide. */
8064 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
8065 tmp = load_reg(s, rn);
8066 tmp2 = load_reg(s, rm);
8067 if ((op & 0x50) == 0x10) {
8068 /* sdiv, udiv */
8069 if (!arm_feature(env, ARM_FEATURE_DIV))
8070 goto illegal_op;
8071 if (op & 0x20)
8072 gen_helper_udiv(tmp, tmp, tmp2);
8073 else
8074 gen_helper_sdiv(tmp, tmp, tmp2);
8075 tcg_temp_free_i32(tmp2);
8076 store_reg(s, rd, tmp);
8077 } else if ((op & 0xe) == 0xc) {
8078 /* Dual multiply accumulate long. */
8079 if (op & 1)
8080 gen_swap_half(tmp2);
8081 gen_smul_dual(tmp, tmp2);
8082 if (op & 0x10) {
8083 tcg_gen_sub_i32(tmp, tmp, tmp2);
8084 } else {
8085 tcg_gen_add_i32(tmp, tmp, tmp2);
8086 }
8087 tcg_temp_free_i32(tmp2);
8088 /* BUGFIX */
8089 tmp64 = tcg_temp_new_i64();
8090 tcg_gen_ext_i32_i64(tmp64, tmp);
8091 tcg_temp_free_i32(tmp);
8092 gen_addq(s, tmp64, rs, rd);
8093 gen_storeq_reg(s, rs, rd, tmp64);
8094 tcg_temp_free_i64(tmp64);
8095 } else {
8096 if (op & 0x20) {
8097 /* Unsigned 64-bit multiply */
8098 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8099 } else {
8100 if (op & 8) {
8101 /* smlalxy */
8102 gen_mulxy(tmp, tmp2, op & 2, op & 1);
8103 tcg_temp_free_i32(tmp2);
8104 tmp64 = tcg_temp_new_i64();
8105 tcg_gen_ext_i32_i64(tmp64, tmp);
8106 tcg_temp_free_i32(tmp);
8107 } else {
8108 /* Signed 64-bit multiply */
8109 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8110 }
8111 }
8112 if (op & 4) {
8113 /* umaal */
8114 gen_addq_lo(s, tmp64, rs);
8115 gen_addq_lo(s, tmp64, rd);
8116 } else if (op & 0x40) {
8117 /* 64-bit accumulate. */
8118 gen_addq(s, tmp64, rs, rd);
8119 }
8120 gen_storeq_reg(s, rs, rd, tmp64);
8121 tcg_temp_free_i64(tmp64);
8122 }
8123 break;
8124 }
8125 break;
8126 case 6: case 7: case 14: case 15:
8127 /* Coprocessor. */
8128 if (((insn >> 24) & 3) == 3) {
8129 /* Translate into the equivalent ARM encoding. */
8130 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
8131 if (disas_neon_data_insn(env, s, insn))
8132 goto illegal_op;
8133 } else {
8134 if (insn & (1 << 28))
8135 goto illegal_op;
8136 if (disas_coproc_insn (env, s, insn))
8137 goto illegal_op;
8138 }
8139 break;
8140 case 8: case 9: case 10: case 11:
8141 if (insn & (1 << 15)) {
8142 /* Branches, misc control. */
8143 if (insn & 0x5000) {
8144 /* Unconditional branch. */
8145 /* signextend(hw1[10:0]) -> offset[:12]. */
8146 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8147 /* hw1[10:0] -> offset[11:1]. */
8148 offset |= (insn & 0x7ff) << 1;
8149 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8150 offset[24:22] already have the same value because of the
8151 sign extension above. */
8152 offset ^= ((~insn) & (1 << 13)) << 10;
8153 offset ^= ((~insn) & (1 << 11)) << 11;
8154
8155 if (insn & (1 << 14)) {
8156 /* Branch and link. */
8157 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
8158 }
8159
8160 offset += s->pc;
8161 if (insn & (1 << 12)) {
8162 /* b/bl */
8163 gen_jmp(s, offset);
8164 } else {
8165 /* blx */
8166 offset &= ~(uint32_t)2;
8167 /* thumb2 bx, no need to check */
8168 gen_bx_im(s, offset);
8169 }
8170 } else if (((insn >> 23) & 7) == 7) {
8171 /* Misc control */
8172 if (insn & (1 << 13))
8173 goto illegal_op;
8174
8175 if (insn & (1 << 26)) {
8176 /* Secure monitor call (v6Z) */
8177 goto illegal_op; /* not implemented. */
8178 } else {
8179 op = (insn >> 20) & 7;
8180 switch (op) {
8181 case 0: /* msr cpsr. */
8182 if (IS_M(env)) {
8183 tmp = load_reg(s, rn);
8184 addr = tcg_const_i32(insn & 0xff);
8185 gen_helper_v7m_msr(cpu_env, addr, tmp);
8186 tcg_temp_free_i32(addr);
8187 tcg_temp_free_i32(tmp);
8188 gen_lookup_tb(s);
8189 break;
8190 }
8191 /* fall through */
8192 case 1: /* msr spsr. */
8193 if (IS_M(env))
8194 goto illegal_op;
8195 tmp = load_reg(s, rn);
8196 if (gen_set_psr(s,
8197 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8198 op == 1, tmp))
8199 goto illegal_op;
8200 break;
8201 case 2: /* cps, nop-hint. */
8202 if (((insn >> 8) & 7) == 0) {
8203 gen_nop_hint(s, insn & 0xff);
8204 }
8205 /* Implemented as NOP in user mode. */
8206 if (IS_USER(s))
8207 break;
8208 offset = 0;
8209 imm = 0;
8210 if (insn & (1 << 10)) {
8211 if (insn & (1 << 7))
8212 offset |= CPSR_A;
8213 if (insn & (1 << 6))
8214 offset |= CPSR_I;
8215 if (insn & (1 << 5))
8216 offset |= CPSR_F;
8217 if (insn & (1 << 9))
8218 imm = CPSR_A | CPSR_I | CPSR_F;
8219 }
8220 if (insn & (1 << 8)) {
8221 offset |= 0x1f;
8222 imm |= (insn & 0x1f);
8223 }
8224 if (offset) {
8225 gen_set_psr_im(s, offset, 0, imm);
8226 }
8227 break;
8228 case 3: /* Special control operations. */
8229 ARCH(7);
8230 op = (insn >> 4) & 0xf;
8231 switch (op) {
8232 case 2: /* clrex */
8233 gen_clrex(s);
8234 break;
8235 case 4: /* dsb */
8236 case 5: /* dmb */
8237 case 6: /* isb */
8238 /* These execute as NOPs. */
8239 break;
8240 default:
8241 goto illegal_op;
8242 }
8243 break;
8244 case 4: /* bxj */
8245 /* Trivial implementation equivalent to bx. */
8246 tmp = load_reg(s, rn);
8247 gen_bx(s, tmp);
8248 break;
8249 case 5: /* Exception return. */
8250 if (IS_USER(s)) {
8251 goto illegal_op;
8252 }
8253 if (rn != 14 || rd != 15) {
8254 goto illegal_op;
8255 }
8256 tmp = load_reg(s, rn);
8257 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8258 gen_exception_return(s, tmp);
8259 break;
8260 case 6: /* mrs cpsr. */
8261 tmp = tcg_temp_new_i32();
8262 if (IS_M(env)) {
8263 addr = tcg_const_i32(insn & 0xff);
8264 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8265 tcg_temp_free_i32(addr);
8266 } else {
8267 gen_helper_cpsr_read(tmp);
8268 }
8269 store_reg(s, rd, tmp);
8270 break;
8271 case 7: /* mrs spsr. */
8272 /* Not accessible in user mode. */
8273 if (IS_USER(s) || IS_M(env))
8274 goto illegal_op;
8275 tmp = load_cpu_field(spsr);
8276 store_reg(s, rd, tmp);
8277 break;
8278 }
8279 }
8280 } else {
8281 /* Conditional branch. */
8282 op = (insn >> 22) & 0xf;
8283 /* Generate a conditional jump to next instruction. */
8284 s->condlabel = gen_new_label();
8285 gen_test_cc(op ^ 1, s->condlabel);
8286 s->condjmp = 1;
8287
8288 /* offset[11:1] = insn[10:0] */
8289 offset = (insn & 0x7ff) << 1;
8290 /* offset[17:12] = insn[21:16]. */
8291 offset |= (insn & 0x003f0000) >> 4;
8292 /* offset[31:20] = insn[26]. */
8293 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8294 /* offset[18] = insn[13]. */
8295 offset |= (insn & (1 << 13)) << 5;
8296 /* offset[19] = insn[11]. */
8297 offset |= (insn & (1 << 11)) << 8;
8298
8299 /* jump to the offset */
8300 gen_jmp(s, s->pc + offset);
8301 }
8302 } else {
8303 /* Data processing immediate. */
8304 if (insn & (1 << 25)) {
8305 if (insn & (1 << 24)) {
8306 if (insn & (1 << 20))
8307 goto illegal_op;
8308 /* Bitfield/Saturate. */
8309 op = (insn >> 21) & 7;
8310 imm = insn & 0x1f;
8311 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8312 if (rn == 15) {
8313 tmp = tcg_temp_new_i32();
8314 tcg_gen_movi_i32(tmp, 0);
8315 } else {
8316 tmp = load_reg(s, rn);
8317 }
8318 switch (op) {
8319 case 2: /* Signed bitfield extract. */
8320 imm++;
8321 if (shift + imm > 32)
8322 goto illegal_op;
8323 if (imm < 32)
8324 gen_sbfx(tmp, shift, imm);
8325 break;
8326 case 6: /* Unsigned bitfield extract. */
8327 imm++;
8328 if (shift + imm > 32)
8329 goto illegal_op;
8330 if (imm < 32)
8331 gen_ubfx(tmp, shift, (1u << imm) - 1);
8332 break;
8333 case 3: /* Bitfield insert/clear. */
8334 if (imm < shift)
8335 goto illegal_op;
8336 imm = imm + 1 - shift;
8337 if (imm != 32) {
8338 tmp2 = load_reg(s, rd);
8339 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8340 tcg_temp_free_i32(tmp2);
8341 }
8342 break;
8343 case 7:
8344 goto illegal_op;
8345 default: /* Saturate. */
8346 if (shift) {
8347 if (op & 1)
8348 tcg_gen_sari_i32(tmp, tmp, shift);
8349 else
8350 tcg_gen_shli_i32(tmp, tmp, shift);
8351 }
8352 tmp2 = tcg_const_i32(imm);
8353 if (op & 4) {
8354 /* Unsigned. */
8355 if ((op & 1) && shift == 0)
8356 gen_helper_usat16(tmp, tmp, tmp2);
8357 else
8358 gen_helper_usat(tmp, tmp, tmp2);
8359 } else {
8360 /* Signed. */
8361 if ((op & 1) && shift == 0)
8362 gen_helper_ssat16(tmp, tmp, tmp2);
8363 else
8364 gen_helper_ssat(tmp, tmp, tmp2);
8365 }
8366 tcg_temp_free_i32(tmp2);
8367 break;
8368 }
8369 store_reg(s, rd, tmp);
8370 } else {
8371 imm = ((insn & 0x04000000) >> 15)
8372 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8373 if (insn & (1 << 22)) {
8374 /* 16-bit immediate. */
8375 imm |= (insn >> 4) & 0xf000;
8376 if (insn & (1 << 23)) {
8377 /* movt */
8378 tmp = load_reg(s, rd);
8379 tcg_gen_ext16u_i32(tmp, tmp);
8380 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8381 } else {
8382 /* movw */
8383 tmp = tcg_temp_new_i32();
8384 tcg_gen_movi_i32(tmp, imm);
8385 }
8386 } else {
8387 /* Add/sub 12-bit immediate. */
8388 if (rn == 15) {
8389 offset = s->pc & ~(uint32_t)3;
8390 if (insn & (1 << 23))
8391 offset -= imm;
8392 else
8393 offset += imm;
8394 tmp = tcg_temp_new_i32();
8395 tcg_gen_movi_i32(tmp, offset);
8396 } else {
8397 tmp = load_reg(s, rn);
8398 if (insn & (1 << 23))
8399 tcg_gen_subi_i32(tmp, tmp, imm);
8400 else
8401 tcg_gen_addi_i32(tmp, tmp, imm);
8402 }
8403 }
8404 store_reg(s, rd, tmp);
8405 }
8406 } else {
8407 int shifter_out = 0;
8408 /* modified 12-bit immediate. */
8409 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8410 imm = (insn & 0xff);
8411 switch (shift) {
8412 case 0: /* XY */
8413 /* Nothing to do. */
8414 break;
8415 case 1: /* 00XY00XY */
8416 imm |= imm << 16;
8417 break;
8418 case 2: /* XY00XY00 */
8419 imm |= imm << 16;
8420 imm <<= 8;
8421 break;
8422 case 3: /* XYXYXYXY */
8423 imm |= imm << 16;
8424 imm |= imm << 8;
8425 break;
8426 default: /* Rotated constant. */
8427 shift = (shift << 1) | (imm >> 7);
8428 imm |= 0x80;
8429 imm = imm << (32 - shift);
8430 shifter_out = 1;
8431 break;
8432 }
8433 tmp2 = tcg_temp_new_i32();
8434 tcg_gen_movi_i32(tmp2, imm);
8435 rn = (insn >> 16) & 0xf;
8436 if (rn == 15) {
8437 tmp = tcg_temp_new_i32();
8438 tcg_gen_movi_i32(tmp, 0);
8439 } else {
8440 tmp = load_reg(s, rn);
8441 }
8442 op = (insn >> 21) & 0xf;
8443 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8444 shifter_out, tmp, tmp2))
8445 goto illegal_op;
8446 tcg_temp_free_i32(tmp2);
8447 rd = (insn >> 8) & 0xf;
8448 if (rd != 15) {
8449 store_reg(s, rd, tmp);
8450 } else {
8451 tcg_temp_free_i32(tmp);
8452 }
8453 }
8454 }
8455 break;
8456 case 12: /* Load/store single data item. */
8457 {
8458 int postinc = 0;
8459 int writeback = 0;
8460 int user;
8461 if ((insn & 0x01100000) == 0x01000000) {
8462 if (disas_neon_ls_insn(env, s, insn))
8463 goto illegal_op;
8464 break;
8465 }
8466 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8467 if (rs == 15) {
8468 if (!(insn & (1 << 20))) {
8469 goto illegal_op;
8470 }
8471 if (op != 2) {
8472 /* Byte or halfword load space with dest == r15 : memory hints.
8473 * Catch them early so we don't emit pointless addressing code.
8474 * This space is a mix of:
8475 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8476 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8477 * cores)
8478 * unallocated hints, which must be treated as NOPs
8479 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8480 * which is easiest for the decoding logic
8481 * Some space which must UNDEF
8482 */
8483 int op1 = (insn >> 23) & 3;
8484 int op2 = (insn >> 6) & 0x3f;
8485 if (op & 2) {
8486 goto illegal_op;
8487 }
8488 if (rn == 15) {
8489 /* UNPREDICTABLE or unallocated hint */
8490 return 0;
8491 }
8492 if (op1 & 1) {
8493 return 0; /* PLD* or unallocated hint */
8494 }
8495 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8496 return 0; /* PLD* or unallocated hint */
8497 }
8498 /* UNDEF space, or an UNPREDICTABLE */
8499 return 1;
8500 }
8501 }
8502 user = IS_USER(s);
8503 if (rn == 15) {
8504 addr = tcg_temp_new_i32();
8505 /* PC relative. */
8506 /* s->pc has already been incremented by 4. */
8507 imm = s->pc & 0xfffffffc;
8508 if (insn & (1 << 23))
8509 imm += insn & 0xfff;
8510 else
8511 imm -= insn & 0xfff;
8512 tcg_gen_movi_i32(addr, imm);
8513 } else {
8514 addr = load_reg(s, rn);
8515 if (insn & (1 << 23)) {
8516 /* Positive offset. */
8517 imm = insn & 0xfff;
8518 tcg_gen_addi_i32(addr, addr, imm);
8519 } else {
8520 imm = insn & 0xff;
8521 switch ((insn >> 8) & 0xf) {
8522 case 0x0: /* Shifted Register. */
8523 shift = (insn >> 4) & 0xf;
8524 if (shift > 3) {
8525 tcg_temp_free_i32(addr);
8526 goto illegal_op;
8527 }
8528 tmp = load_reg(s, rm);
8529 if (shift)
8530 tcg_gen_shli_i32(tmp, tmp, shift);
8531 tcg_gen_add_i32(addr, addr, tmp);
8532 tcg_temp_free_i32(tmp);
8533 break;
8534 case 0xc: /* Negative offset. */
8535 tcg_gen_addi_i32(addr, addr, -imm);
8536 break;
8537 case 0xe: /* User privilege. */
8538 tcg_gen_addi_i32(addr, addr, imm);
8539 user = 1;
8540 break;
8541 case 0x9: /* Post-decrement. */
8542 imm = -imm;
8543 /* Fall through. */
8544 case 0xb: /* Post-increment. */
8545 postinc = 1;
8546 writeback = 1;
8547 break;
8548 case 0xd: /* Pre-decrement. */
8549 imm = -imm;
8550 /* Fall through. */
8551 case 0xf: /* Pre-increment. */
8552 tcg_gen_addi_i32(addr, addr, imm);
8553 writeback = 1;
8554 break;
8555 default:
8556 tcg_temp_free_i32(addr);
8557 goto illegal_op;
8558 }
8559 }
8560 }
8561 if (insn & (1 << 20)) {
8562 /* Load. */
8563 switch (op) {
8564 case 0: tmp = gen_ld8u(addr, user); break;
8565 case 4: tmp = gen_ld8s(addr, user); break;
8566 case 1: tmp = gen_ld16u(addr, user); break;
8567 case 5: tmp = gen_ld16s(addr, user); break;
8568 case 2: tmp = gen_ld32(addr, user); break;
8569 default:
8570 tcg_temp_free_i32(addr);
8571 goto illegal_op;
8572 }
8573 if (rs == 15) {
8574 gen_bx(s, tmp);
8575 } else {
8576 store_reg(s, rs, tmp);
8577 }
8578 } else {
8579 /* Store. */
8580 tmp = load_reg(s, rs);
8581 switch (op) {
8582 case 0: gen_st8(tmp, addr, user); break;
8583 case 1: gen_st16(tmp, addr, user); break;
8584 case 2: gen_st32(tmp, addr, user); break;
8585 default:
8586 tcg_temp_free_i32(addr);
8587 goto illegal_op;
8588 }
8589 }
8590 if (postinc)
8591 tcg_gen_addi_i32(addr, addr, imm);
8592 if (writeback) {
8593 store_reg(s, rn, addr);
8594 } else {
8595 tcg_temp_free_i32(addr);
8596 }
8597 }
8598 break;
8599 default:
8600 goto illegal_op;
8601 }
8602 return 0;
8603 illegal_op:
8604 return 1;
8605 }
8606
8607 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8608 {
8609 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8610 int32_t offset;
8611 int i;
8612 TCGv tmp;
8613 TCGv tmp2;
8614 TCGv addr;
8615
8616 if (s->condexec_mask) {
8617 cond = s->condexec_cond;
8618 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8619 s->condlabel = gen_new_label();
8620 gen_test_cc(cond ^ 1, s->condlabel);
8621 s->condjmp = 1;
8622 }
8623 }
8624
8625 insn = lduw_code(s->pc);
8626 s->pc += 2;
8627
8628 switch (insn >> 12) {
8629 case 0: case 1:
8630
8631 rd = insn & 7;
8632 op = (insn >> 11) & 3;
8633 if (op == 3) {
8634 /* add/subtract */
8635 rn = (insn >> 3) & 7;
8636 tmp = load_reg(s, rn);
8637 if (insn & (1 << 10)) {
8638 /* immediate */
8639 tmp2 = tcg_temp_new_i32();
8640 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8641 } else {
8642 /* reg */
8643 rm = (insn >> 6) & 7;
8644 tmp2 = load_reg(s, rm);
8645 }
8646 if (insn & (1 << 9)) {
8647 if (s->condexec_mask)
8648 tcg_gen_sub_i32(tmp, tmp, tmp2);
8649 else
8650 gen_helper_sub_cc(tmp, tmp, tmp2);
8651 } else {
8652 if (s->condexec_mask)
8653 tcg_gen_add_i32(tmp, tmp, tmp2);
8654 else
8655 gen_helper_add_cc(tmp, tmp, tmp2);
8656 }
8657 tcg_temp_free_i32(tmp2);
8658 store_reg(s, rd, tmp);
8659 } else {
8660 /* shift immediate */
8661 rm = (insn >> 3) & 7;
8662 shift = (insn >> 6) & 0x1f;
8663 tmp = load_reg(s, rm);
8664 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8665 if (!s->condexec_mask)
8666 gen_logic_CC(tmp);
8667 store_reg(s, rd, tmp);
8668 }
8669 break;
8670 case 2: case 3:
8671 /* arithmetic large immediate */
8672 op = (insn >> 11) & 3;
8673 rd = (insn >> 8) & 0x7;
8674 if (op == 0) { /* mov */
8675 tmp = tcg_temp_new_i32();
8676 tcg_gen_movi_i32(tmp, insn & 0xff);
8677 if (!s->condexec_mask)
8678 gen_logic_CC(tmp);
8679 store_reg(s, rd, tmp);
8680 } else {
8681 tmp = load_reg(s, rd);
8682 tmp2 = tcg_temp_new_i32();
8683 tcg_gen_movi_i32(tmp2, insn & 0xff);
8684 switch (op) {
8685 case 1: /* cmp */
8686 gen_helper_sub_cc(tmp, tmp, tmp2);
8687 tcg_temp_free_i32(tmp);
8688 tcg_temp_free_i32(tmp2);
8689 break;
8690 case 2: /* add */
8691 if (s->condexec_mask)
8692 tcg_gen_add_i32(tmp, tmp, tmp2);
8693 else
8694 gen_helper_add_cc(tmp, tmp, tmp2);
8695 tcg_temp_free_i32(tmp2);
8696 store_reg(s, rd, tmp);
8697 break;
8698 case 3: /* sub */
8699 if (s->condexec_mask)
8700 tcg_gen_sub_i32(tmp, tmp, tmp2);
8701 else
8702 gen_helper_sub_cc(tmp, tmp, tmp2);
8703 tcg_temp_free_i32(tmp2);
8704 store_reg(s, rd, tmp);
8705 break;
8706 }
8707 }
8708 break;
8709 case 4:
8710 if (insn & (1 << 11)) {
8711 rd = (insn >> 8) & 7;
8712 /* load pc-relative. Bit 1 of PC is ignored. */
8713 val = s->pc + 2 + ((insn & 0xff) * 4);
8714 val &= ~(uint32_t)2;
8715 addr = tcg_temp_new_i32();
8716 tcg_gen_movi_i32(addr, val);
8717 tmp = gen_ld32(addr, IS_USER(s));
8718 tcg_temp_free_i32(addr);
8719 store_reg(s, rd, tmp);
8720 break;
8721 }
8722 if (insn & (1 << 10)) {
8723 /* data processing extended or blx */
8724 rd = (insn & 7) | ((insn >> 4) & 8);
8725 rm = (insn >> 3) & 0xf;
8726 op = (insn >> 8) & 3;
8727 switch (op) {
8728 case 0: /* add */
8729 tmp = load_reg(s, rd);
8730 tmp2 = load_reg(s, rm);
8731 tcg_gen_add_i32(tmp, tmp, tmp2);
8732 tcg_temp_free_i32(tmp2);
8733 store_reg(s, rd, tmp);
8734 break;
8735 case 1: /* cmp */
8736 tmp = load_reg(s, rd);
8737 tmp2 = load_reg(s, rm);
8738 gen_helper_sub_cc(tmp, tmp, tmp2);
8739 tcg_temp_free_i32(tmp2);
8740 tcg_temp_free_i32(tmp);
8741 break;
8742 case 2: /* mov/cpy */
8743 tmp = load_reg(s, rm);
8744 store_reg(s, rd, tmp);
8745 break;
8746 case 3:/* branch [and link] exchange thumb register */
8747 tmp = load_reg(s, rm);
8748 if (insn & (1 << 7)) {
8749 ARCH(5);
8750 val = (uint32_t)s->pc | 1;
8751 tmp2 = tcg_temp_new_i32();
8752 tcg_gen_movi_i32(tmp2, val);
8753 store_reg(s, 14, tmp2);
8754 }
8755 /* already thumb, no need to check */
8756 gen_bx(s, tmp);
8757 break;
8758 }
8759 break;
8760 }
8761
8762 /* data processing register */
8763 rd = insn & 7;
8764 rm = (insn >> 3) & 7;
8765 op = (insn >> 6) & 0xf;
8766 if (op == 2 || op == 3 || op == 4 || op == 7) {
8767 /* the shift/rotate ops want the operands backwards */
8768 val = rm;
8769 rm = rd;
8770 rd = val;
8771 val = 1;
8772 } else {
8773 val = 0;
8774 }
8775
8776 if (op == 9) { /* neg */
8777 tmp = tcg_temp_new_i32();
8778 tcg_gen_movi_i32(tmp, 0);
8779 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8780 tmp = load_reg(s, rd);
8781 } else {
8782 TCGV_UNUSED(tmp);
8783 }
8784
8785 tmp2 = load_reg(s, rm);
8786 switch (op) {
8787 case 0x0: /* and */
8788 tcg_gen_and_i32(tmp, tmp, tmp2);
8789 if (!s->condexec_mask)
8790 gen_logic_CC(tmp);
8791 break;
8792 case 0x1: /* eor */
8793 tcg_gen_xor_i32(tmp, tmp, tmp2);
8794 if (!s->condexec_mask)
8795 gen_logic_CC(tmp);
8796 break;
8797 case 0x2: /* lsl */
8798 if (s->condexec_mask) {
8799 gen_helper_shl(tmp2, tmp2, tmp);
8800 } else {
8801 gen_helper_shl_cc(tmp2, tmp2, tmp);
8802 gen_logic_CC(tmp2);
8803 }
8804 break;
8805 case 0x3: /* lsr */
8806 if (s->condexec_mask) {
8807 gen_helper_shr(tmp2, tmp2, tmp);
8808 } else {
8809 gen_helper_shr_cc(tmp2, tmp2, tmp);
8810 gen_logic_CC(tmp2);
8811 }
8812 break;
8813 case 0x4: /* asr */
8814 if (s->condexec_mask) {
8815 gen_helper_sar(tmp2, tmp2, tmp);
8816 } else {
8817 gen_helper_sar_cc(tmp2, tmp2, tmp);
8818 gen_logic_CC(tmp2);
8819 }
8820 break;
8821 case 0x5: /* adc */
8822 if (s->condexec_mask)
8823 gen_adc(tmp, tmp2);
8824 else
8825 gen_helper_adc_cc(tmp, tmp, tmp2);
8826 break;
8827 case 0x6: /* sbc */
8828 if (s->condexec_mask)
8829 gen_sub_carry(tmp, tmp, tmp2);
8830 else
8831 gen_helper_sbc_cc(tmp, tmp, tmp2);
8832 break;
8833 case 0x7: /* ror */
8834 if (s->condexec_mask) {
8835 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8836 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
8837 } else {
8838 gen_helper_ror_cc(tmp2, tmp2, tmp);
8839 gen_logic_CC(tmp2);
8840 }
8841 break;
8842 case 0x8: /* tst */
8843 tcg_gen_and_i32(tmp, tmp, tmp2);
8844 gen_logic_CC(tmp);
8845 rd = 16;
8846 break;
8847 case 0x9: /* neg */
8848 if (s->condexec_mask)
8849 tcg_gen_neg_i32(tmp, tmp2);
8850 else
8851 gen_helper_sub_cc(tmp, tmp, tmp2);
8852 break;
8853 case 0xa: /* cmp */
8854 gen_helper_sub_cc(tmp, tmp, tmp2);
8855 rd = 16;
8856 break;
8857 case 0xb: /* cmn */
8858 gen_helper_add_cc(tmp, tmp, tmp2);
8859 rd = 16;
8860 break;
8861 case 0xc: /* orr */
8862 tcg_gen_or_i32(tmp, tmp, tmp2);
8863 if (!s->condexec_mask)
8864 gen_logic_CC(tmp);
8865 break;
8866 case 0xd: /* mul */
8867 tcg_gen_mul_i32(tmp, tmp, tmp2);
8868 if (!s->condexec_mask)
8869 gen_logic_CC(tmp);
8870 break;
8871 case 0xe: /* bic */
8872 tcg_gen_andc_i32(tmp, tmp, tmp2);
8873 if (!s->condexec_mask)
8874 gen_logic_CC(tmp);
8875 break;
8876 case 0xf: /* mvn */
8877 tcg_gen_not_i32(tmp2, tmp2);
8878 if (!s->condexec_mask)
8879 gen_logic_CC(tmp2);
8880 val = 1;
8881 rm = rd;
8882 break;
8883 }
8884 if (rd != 16) {
8885 if (val) {
8886 store_reg(s, rm, tmp2);
8887 if (op != 0xf)
8888 tcg_temp_free_i32(tmp);
8889 } else {
8890 store_reg(s, rd, tmp);
8891 tcg_temp_free_i32(tmp2);
8892 }
8893 } else {
8894 tcg_temp_free_i32(tmp);
8895 tcg_temp_free_i32(tmp2);
8896 }
8897 break;
8898
8899 case 5:
8900 /* load/store register offset. */
8901 rd = insn & 7;
8902 rn = (insn >> 3) & 7;
8903 rm = (insn >> 6) & 7;
8904 op = (insn >> 9) & 7;
8905 addr = load_reg(s, rn);
8906 tmp = load_reg(s, rm);
8907 tcg_gen_add_i32(addr, addr, tmp);
8908 tcg_temp_free_i32(tmp);
8909
8910 if (op < 3) /* store */
8911 tmp = load_reg(s, rd);
8912
8913 switch (op) {
8914 case 0: /* str */
8915 gen_st32(tmp, addr, IS_USER(s));
8916 break;
8917 case 1: /* strh */
8918 gen_st16(tmp, addr, IS_USER(s));
8919 break;
8920 case 2: /* strb */
8921 gen_st8(tmp, addr, IS_USER(s));
8922 break;
8923 case 3: /* ldrsb */
8924 tmp = gen_ld8s(addr, IS_USER(s));
8925 break;
8926 case 4: /* ldr */
8927 tmp = gen_ld32(addr, IS_USER(s));
8928 break;
8929 case 5: /* ldrh */
8930 tmp = gen_ld16u(addr, IS_USER(s));
8931 break;
8932 case 6: /* ldrb */
8933 tmp = gen_ld8u(addr, IS_USER(s));
8934 break;
8935 case 7: /* ldrsh */
8936 tmp = gen_ld16s(addr, IS_USER(s));
8937 break;
8938 }
8939 if (op >= 3) /* load */
8940 store_reg(s, rd, tmp);
8941 tcg_temp_free_i32(addr);
8942 break;
8943
8944 case 6:
8945 /* load/store word immediate offset */
8946 rd = insn & 7;
8947 rn = (insn >> 3) & 7;
8948 addr = load_reg(s, rn);
8949 val = (insn >> 4) & 0x7c;
8950 tcg_gen_addi_i32(addr, addr, val);
8951
8952 if (insn & (1 << 11)) {
8953 /* load */
8954 tmp = gen_ld32(addr, IS_USER(s));
8955 store_reg(s, rd, tmp);
8956 } else {
8957 /* store */
8958 tmp = load_reg(s, rd);
8959 gen_st32(tmp, addr, IS_USER(s));
8960 }
8961 tcg_temp_free_i32(addr);
8962 break;
8963
8964 case 7:
8965 /* load/store byte immediate offset */
8966 rd = insn & 7;
8967 rn = (insn >> 3) & 7;
8968 addr = load_reg(s, rn);
8969 val = (insn >> 6) & 0x1f;
8970 tcg_gen_addi_i32(addr, addr, val);
8971
8972 if (insn & (1 << 11)) {
8973 /* load */
8974 tmp = gen_ld8u(addr, IS_USER(s));
8975 store_reg(s, rd, tmp);
8976 } else {
8977 /* store */
8978 tmp = load_reg(s, rd);
8979 gen_st8(tmp, addr, IS_USER(s));
8980 }
8981 tcg_temp_free_i32(addr);
8982 break;
8983
8984 case 8:
8985 /* load/store halfword immediate offset */
8986 rd = insn & 7;
8987 rn = (insn >> 3) & 7;
8988 addr = load_reg(s, rn);
8989 val = (insn >> 5) & 0x3e;
8990 tcg_gen_addi_i32(addr, addr, val);
8991
8992 if (insn & (1 << 11)) {
8993 /* load */
8994 tmp = gen_ld16u(addr, IS_USER(s));
8995 store_reg(s, rd, tmp);
8996 } else {
8997 /* store */
8998 tmp = load_reg(s, rd);
8999 gen_st16(tmp, addr, IS_USER(s));
9000 }
9001 tcg_temp_free_i32(addr);
9002 break;
9003
9004 case 9:
9005 /* load/store from stack */
9006 rd = (insn >> 8) & 7;
9007 addr = load_reg(s, 13);
9008 val = (insn & 0xff) * 4;
9009 tcg_gen_addi_i32(addr, addr, val);
9010
9011 if (insn & (1 << 11)) {
9012 /* load */
9013 tmp = gen_ld32(addr, IS_USER(s));
9014 store_reg(s, rd, tmp);
9015 } else {
9016 /* store */
9017 tmp = load_reg(s, rd);
9018 gen_st32(tmp, addr, IS_USER(s));
9019 }
9020 tcg_temp_free_i32(addr);
9021 break;
9022
9023 case 10:
9024 /* add to high reg */
9025 rd = (insn >> 8) & 7;
9026 if (insn & (1 << 11)) {
9027 /* SP */
9028 tmp = load_reg(s, 13);
9029 } else {
9030 /* PC. bit 1 is ignored. */
9031 tmp = tcg_temp_new_i32();
9032 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
9033 }
9034 val = (insn & 0xff) * 4;
9035 tcg_gen_addi_i32(tmp, tmp, val);
9036 store_reg(s, rd, tmp);
9037 break;
9038
9039 case 11:
9040 /* misc */
9041 op = (insn >> 8) & 0xf;
9042 switch (op) {
9043 case 0:
9044 /* adjust stack pointer */
9045 tmp = load_reg(s, 13);
9046 val = (insn & 0x7f) * 4;
9047 if (insn & (1 << 7))
9048 val = -(int32_t)val;
9049 tcg_gen_addi_i32(tmp, tmp, val);
9050 store_reg(s, 13, tmp);
9051 break;
9052
9053 case 2: /* sign/zero extend. */
9054 ARCH(6);
9055 rd = insn & 7;
9056 rm = (insn >> 3) & 7;
9057 tmp = load_reg(s, rm);
9058 switch ((insn >> 6) & 3) {
9059 case 0: gen_sxth(tmp); break;
9060 case 1: gen_sxtb(tmp); break;
9061 case 2: gen_uxth(tmp); break;
9062 case 3: gen_uxtb(tmp); break;
9063 }
9064 store_reg(s, rd, tmp);
9065 break;
9066 case 4: case 5: case 0xc: case 0xd:
9067 /* push/pop */
9068 addr = load_reg(s, 13);
9069 if (insn & (1 << 8))
9070 offset = 4;
9071 else
9072 offset = 0;
9073 for (i = 0; i < 8; i++) {
9074 if (insn & (1 << i))
9075 offset += 4;
9076 }
9077 if ((insn & (1 << 11)) == 0) {
9078 tcg_gen_addi_i32(addr, addr, -offset);
9079 }
9080 for (i = 0; i < 8; i++) {
9081 if (insn & (1 << i)) {
9082 if (insn & (1 << 11)) {
9083 /* pop */
9084 tmp = gen_ld32(addr, IS_USER(s));
9085 store_reg(s, i, tmp);
9086 } else {
9087 /* push */
9088 tmp = load_reg(s, i);
9089 gen_st32(tmp, addr, IS_USER(s));
9090 }
9091 /* advance to the next address. */
9092 tcg_gen_addi_i32(addr, addr, 4);
9093 }
9094 }
9095 TCGV_UNUSED(tmp);
9096 if (insn & (1 << 8)) {
9097 if (insn & (1 << 11)) {
9098 /* pop pc */
9099 tmp = gen_ld32(addr, IS_USER(s));
9100 /* don't set the pc until the rest of the instruction
9101 has completed */
9102 } else {
9103 /* push lr */
9104 tmp = load_reg(s, 14);
9105 gen_st32(tmp, addr, IS_USER(s));
9106 }
9107 tcg_gen_addi_i32(addr, addr, 4);
9108 }
9109 if ((insn & (1 << 11)) == 0) {
9110 tcg_gen_addi_i32(addr, addr, -offset);
9111 }
9112 /* write back the new stack pointer */
9113 store_reg(s, 13, addr);
9114 /* set the new PC value */
9115 if ((insn & 0x0900) == 0x0900) {
9116 store_reg_from_load(env, s, 15, tmp);
9117 }
9118 break;
9119
9120 case 1: case 3: case 9: case 11: /* czb */
9121 rm = insn & 7;
9122 tmp = load_reg(s, rm);
9123 s->condlabel = gen_new_label();
9124 s->condjmp = 1;
9125 if (insn & (1 << 11))
9126 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9127 else
9128 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
9129 tcg_temp_free_i32(tmp);
9130 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9131 val = (uint32_t)s->pc + 2;
9132 val += offset;
9133 gen_jmp(s, val);
9134 break;
9135
9136 case 15: /* IT, nop-hint. */
9137 if ((insn & 0xf) == 0) {
9138 gen_nop_hint(s, (insn >> 4) & 0xf);
9139 break;
9140 }
9141 /* If Then. */
9142 s->condexec_cond = (insn >> 4) & 0xe;
9143 s->condexec_mask = insn & 0x1f;
9144 /* No actual code generated for this insn, just setup state. */
9145 break;
9146
9147 case 0xe: /* bkpt */
9148 ARCH(5);
9149 gen_exception_insn(s, 2, EXCP_BKPT);
9150 break;
9151
9152 case 0xa: /* rev */
9153 ARCH(6);
9154 rn = (insn >> 3) & 0x7;
9155 rd = insn & 0x7;
9156 tmp = load_reg(s, rn);
9157 switch ((insn >> 6) & 3) {
9158 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
9159 case 1: gen_rev16(tmp); break;
9160 case 3: gen_revsh(tmp); break;
9161 default: goto illegal_op;
9162 }
9163 store_reg(s, rd, tmp);
9164 break;
9165
9166 case 6: /* cps */
9167 ARCH(6);
9168 if (IS_USER(s))
9169 break;
9170 if (IS_M(env)) {
9171 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9172 /* PRIMASK */
9173 if (insn & 1) {
9174 addr = tcg_const_i32(16);
9175 gen_helper_v7m_msr(cpu_env, addr, tmp);
9176 tcg_temp_free_i32(addr);
9177 }
9178 /* FAULTMASK */
9179 if (insn & 2) {
9180 addr = tcg_const_i32(17);
9181 gen_helper_v7m_msr(cpu_env, addr, tmp);
9182 tcg_temp_free_i32(addr);
9183 }
9184 tcg_temp_free_i32(tmp);
9185 gen_lookup_tb(s);
9186 } else {
9187 if (insn & (1 << 4))
9188 shift = CPSR_A | CPSR_I | CPSR_F;
9189 else
9190 shift = 0;
9191 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9192 }
9193 break;
9194
9195 default:
9196 goto undef;
9197 }
9198 break;
9199
9200 case 12:
9201 /* load/store multiple */
9202 rn = (insn >> 8) & 0x7;
9203 addr = load_reg(s, rn);
9204 for (i = 0; i < 8; i++) {
9205 if (insn & (1 << i)) {
9206 if (insn & (1 << 11)) {
9207 /* load */
9208 tmp = gen_ld32(addr, IS_USER(s));
9209 store_reg(s, i, tmp);
9210 } else {
9211 /* store */
9212 tmp = load_reg(s, i);
9213 gen_st32(tmp, addr, IS_USER(s));
9214 }
9215 /* advance to the next address */
9216 tcg_gen_addi_i32(addr, addr, 4);
9217 }
9218 }
9219 /* Base register writeback. */
9220 if ((insn & (1 << rn)) == 0) {
9221 store_reg(s, rn, addr);
9222 } else {
9223 tcg_temp_free_i32(addr);
9224 }
9225 break;
9226
9227 case 13:
9228 /* conditional branch or swi */
9229 cond = (insn >> 8) & 0xf;
9230 if (cond == 0xe)
9231 goto undef;
9232
9233 if (cond == 0xf) {
9234 /* swi */
9235 gen_set_pc_im(s->pc);
9236 s->is_jmp = DISAS_SWI;
9237 break;
9238 }
9239 /* generate a conditional jump to next instruction */
9240 s->condlabel = gen_new_label();
9241 gen_test_cc(cond ^ 1, s->condlabel);
9242 s->condjmp = 1;
9243
9244 /* jump to the offset */
9245 val = (uint32_t)s->pc + 2;
9246 offset = ((int32_t)insn << 24) >> 24;
9247 val += offset << 1;
9248 gen_jmp(s, val);
9249 break;
9250
9251 case 14:
9252 if (insn & (1 << 11)) {
9253 if (disas_thumb2_insn(env, s, insn))
9254 goto undef32;
9255 break;
9256 }
9257 /* unconditional branch */
9258 val = (uint32_t)s->pc;
9259 offset = ((int32_t)insn << 21) >> 21;
9260 val += (offset << 1) + 2;
9261 gen_jmp(s, val);
9262 break;
9263
9264 case 15:
9265 if (disas_thumb2_insn(env, s, insn))
9266 goto undef32;
9267 break;
9268 }
9269 return;
9270 undef32:
9271 gen_exception_insn(s, 4, EXCP_UDEF);
9272 return;
9273 illegal_op:
9274 undef:
9275 gen_exception_insn(s, 2, EXCP_UDEF);
9276 }
9277
9278 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9279 basic block 'tb'. If search_pc is TRUE, also generate PC
9280 information for each intermediate instruction. */
9281 static inline void gen_intermediate_code_internal(CPUState *env,
9282 TranslationBlock *tb,
9283 int search_pc)
9284 {
9285 DisasContext dc1, *dc = &dc1;
9286 CPUBreakpoint *bp;
9287 uint16_t *gen_opc_end;
9288 int j, lj;
9289 target_ulong pc_start;
9290 uint32_t next_page_start;
9291 int num_insns;
9292 int max_insns;
9293
9294 /* generate intermediate code */
9295 pc_start = tb->pc;
9296
9297 dc->tb = tb;
9298
9299 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9300
9301 dc->is_jmp = DISAS_NEXT;
9302 dc->pc = pc_start;
9303 dc->singlestep_enabled = env->singlestep_enabled;
9304 dc->condjmp = 0;
9305 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9306 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9307 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9308 #if !defined(CONFIG_USER_ONLY)
9309 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9310 #endif
9311 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9312 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9313 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9314 cpu_F0s = tcg_temp_new_i32();
9315 cpu_F1s = tcg_temp_new_i32();
9316 cpu_F0d = tcg_temp_new_i64();
9317 cpu_F1d = tcg_temp_new_i64();
9318 cpu_V0 = cpu_F0d;
9319 cpu_V1 = cpu_F1d;
9320 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9321 cpu_M0 = tcg_temp_new_i64();
9322 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9323 lj = -1;
9324 num_insns = 0;
9325 max_insns = tb->cflags & CF_COUNT_MASK;
9326 if (max_insns == 0)
9327 max_insns = CF_COUNT_MASK;
9328
9329 gen_icount_start();
9330
9331 tcg_clear_temp_count();
9332
9333 /* A note on handling of the condexec (IT) bits:
9334 *
9335 * We want to avoid the overhead of having to write the updated condexec
9336 * bits back to the CPUState for every instruction in an IT block. So:
9337 * (1) if the condexec bits are not already zero then we write
9338 * zero back into the CPUState now. This avoids complications trying
9339 * to do it at the end of the block. (For example if we don't do this
9340 * it's hard to identify whether we can safely skip writing condexec
9341 * at the end of the TB, which we definitely want to do for the case
9342 * where a TB doesn't do anything with the IT state at all.)
9343 * (2) if we are going to leave the TB then we call gen_set_condexec()
9344 * which will write the correct value into CPUState if zero is wrong.
9345 * This is done both for leaving the TB at the end, and for leaving
9346 * it because of an exception we know will happen, which is done in
9347 * gen_exception_insn(). The latter is necessary because we need to
9348 * leave the TB with the PC/IT state just prior to execution of the
9349 * instruction which caused the exception.
9350 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9351 * then the CPUState will be wrong and we need to reset it.
9352 * This is handled in the same way as restoration of the
9353 * PC in these situations: we will be called again with search_pc=1
9354 * and generate a mapping of the condexec bits for each PC in
9355 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9356 * the condexec bits.
9357 *
9358 * Note that there are no instructions which can read the condexec
9359 * bits, and none which can write non-static values to them, so
9360 * we don't need to care about whether CPUState is correct in the
9361 * middle of a TB.
9362 */
9363
9364 /* Reset the conditional execution bits immediately. This avoids
9365 complications trying to do it at the end of the block. */
9366 if (dc->condexec_mask || dc->condexec_cond)
9367 {
9368 TCGv tmp = tcg_temp_new_i32();
9369 tcg_gen_movi_i32(tmp, 0);
9370 store_cpu_field(tmp, condexec_bits);
9371 }
9372 do {
9373 #ifdef CONFIG_USER_ONLY
9374 /* Intercept jump to the magic kernel page. */
9375 if (dc->pc >= 0xffff0000) {
9376 /* We always get here via a jump, so know we are not in a
9377 conditional execution block. */
9378 gen_exception(EXCP_KERNEL_TRAP);
9379 dc->is_jmp = DISAS_UPDATE;
9380 break;
9381 }
9382 #else
9383 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9384 /* We always get here via a jump, so know we are not in a
9385 conditional execution block. */
9386 gen_exception(EXCP_EXCEPTION_EXIT);
9387 dc->is_jmp = DISAS_UPDATE;
9388 break;
9389 }
9390 #endif
9391
9392 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9393 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9394 if (bp->pc == dc->pc) {
9395 gen_exception_insn(dc, 0, EXCP_DEBUG);
9396 /* Advance PC so that clearing the breakpoint will
9397 invalidate this TB. */
9398 dc->pc += 2;
9399 goto done_generating;
9400 break;
9401 }
9402 }
9403 }
9404 if (search_pc) {
9405 j = gen_opc_ptr - gen_opc_buf;
9406 if (lj < j) {
9407 lj++;
9408 while (lj < j)
9409 gen_opc_instr_start[lj++] = 0;
9410 }
9411 gen_opc_pc[lj] = dc->pc;
9412 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9413 gen_opc_instr_start[lj] = 1;
9414 gen_opc_icount[lj] = num_insns;
9415 }
9416
9417 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9418 gen_io_start();
9419
9420 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9421 tcg_gen_debug_insn_start(dc->pc);
9422 }
9423
9424 if (dc->thumb) {
9425 disas_thumb_insn(env, dc);
9426 if (dc->condexec_mask) {
9427 dc->condexec_cond = (dc->condexec_cond & 0xe)
9428 | ((dc->condexec_mask >> 4) & 1);
9429 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9430 if (dc->condexec_mask == 0) {
9431 dc->condexec_cond = 0;
9432 }
9433 }
9434 } else {
9435 disas_arm_insn(env, dc);
9436 }
9437
9438 if (dc->condjmp && !dc->is_jmp) {
9439 gen_set_label(dc->condlabel);
9440 dc->condjmp = 0;
9441 }
9442
9443 if (tcg_check_temp_count()) {
9444 fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
9445 }
9446
9447 /* Translation stops when a conditional branch is encountered.
9448 * Otherwise the subsequent code could get translated several times.
9449 * Also stop translation when a page boundary is reached. This
9450 * ensures prefetch aborts occur at the right place. */
9451 num_insns ++;
9452 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9453 !env->singlestep_enabled &&
9454 !singlestep &&
9455 dc->pc < next_page_start &&
9456 num_insns < max_insns);
9457
9458 if (tb->cflags & CF_LAST_IO) {
9459 if (dc->condjmp) {
9460 /* FIXME: This can theoretically happen with self-modifying
9461 code. */
9462 cpu_abort(env, "IO on conditional branch instruction");
9463 }
9464 gen_io_end();
9465 }
9466
9467 /* At this stage dc->condjmp will only be set when the skipped
9468 instruction was a conditional branch or trap, and the PC has
9469 already been written. */
9470 if (unlikely(env->singlestep_enabled)) {
9471 /* Make sure the pc is updated, and raise a debug exception. */
9472 if (dc->condjmp) {
9473 gen_set_condexec(dc);
9474 if (dc->is_jmp == DISAS_SWI) {
9475 gen_exception(EXCP_SWI);
9476 } else {
9477 gen_exception(EXCP_DEBUG);
9478 }
9479 gen_set_label(dc->condlabel);
9480 }
9481 if (dc->condjmp || !dc->is_jmp) {
9482 gen_set_pc_im(dc->pc);
9483 dc->condjmp = 0;
9484 }
9485 gen_set_condexec(dc);
9486 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9487 gen_exception(EXCP_SWI);
9488 } else {
9489 /* FIXME: Single stepping a WFI insn will not halt
9490 the CPU. */
9491 gen_exception(EXCP_DEBUG);
9492 }
9493 } else {
9494 /* While branches must always occur at the end of an IT block,
9495 there are a few other things that can cause us to terminate
9496 the TB in the middel of an IT block:
9497 - Exception generating instructions (bkpt, swi, undefined).
9498 - Page boundaries.
9499 - Hardware watchpoints.
9500 Hardware breakpoints have already been handled and skip this code.
9501 */
9502 gen_set_condexec(dc);
9503 switch(dc->is_jmp) {
9504 case DISAS_NEXT:
9505 gen_goto_tb(dc, 1, dc->pc);
9506 break;
9507 default:
9508 case DISAS_JUMP:
9509 case DISAS_UPDATE:
9510 /* indicate that the hash table must be used to find the next TB */
9511 tcg_gen_exit_tb(0);
9512 break;
9513 case DISAS_TB_JUMP:
9514 /* nothing more to generate */
9515 break;
9516 case DISAS_WFI:
9517 gen_helper_wfi();
9518 break;
9519 case DISAS_SWI:
9520 gen_exception(EXCP_SWI);
9521 break;
9522 }
9523 if (dc->condjmp) {
9524 gen_set_label(dc->condlabel);
9525 gen_set_condexec(dc);
9526 gen_goto_tb(dc, 1, dc->pc);
9527 dc->condjmp = 0;
9528 }
9529 }
9530
9531 done_generating:
9532 gen_icount_end(tb, num_insns);
9533 *gen_opc_ptr = INDEX_op_end;
9534
9535 #ifdef DEBUG_DISAS
9536 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9537 qemu_log("----------------\n");
9538 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9539 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9540 qemu_log("\n");
9541 }
9542 #endif
9543 if (search_pc) {
9544 j = gen_opc_ptr - gen_opc_buf;
9545 lj++;
9546 while (lj <= j)
9547 gen_opc_instr_start[lj++] = 0;
9548 } else {
9549 tb->size = dc->pc - pc_start;
9550 tb->icount = num_insns;
9551 }
9552 }
9553
9554 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9555 {
9556 gen_intermediate_code_internal(env, tb, 0);
9557 }
9558
9559 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9560 {
9561 gen_intermediate_code_internal(env, tb, 1);
9562 }
9563
9564 static const char *cpu_mode_names[16] = {
9565 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9566 "???", "???", "???", "und", "???", "???", "???", "sys"
9567 };
9568
9569 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9570 int flags)
9571 {
9572 int i;
9573 #if 0
9574 union {
9575 uint32_t i;
9576 float s;
9577 } s0, s1;
9578 CPU_DoubleU d;
9579 /* ??? This assumes float64 and double have the same layout.
9580 Oh well, it's only debug dumps. */
9581 union {
9582 float64 f64;
9583 double d;
9584 } d0;
9585 #endif
9586 uint32_t psr;
9587
9588 for(i=0;i<16;i++) {
9589 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9590 if ((i % 4) == 3)
9591 cpu_fprintf(f, "\n");
9592 else
9593 cpu_fprintf(f, " ");
9594 }
9595 psr = cpsr_read(env);
9596 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9597 psr,
9598 psr & (1 << 31) ? 'N' : '-',
9599 psr & (1 << 30) ? 'Z' : '-',
9600 psr & (1 << 29) ? 'C' : '-',
9601 psr & (1 << 28) ? 'V' : '-',
9602 psr & CPSR_T ? 'T' : 'A',
9603 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9604
9605 #if 0
9606 for (i = 0; i < 16; i++) {
9607 d.d = env->vfp.regs[i];
9608 s0.i = d.l.lower;
9609 s1.i = d.l.upper;
9610 d0.f64 = d.d;
9611 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9612 i * 2, (int)s0.i, s0.s,
9613 i * 2 + 1, (int)s1.i, s1.s,
9614 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9615 d0.d);
9616 }
9617 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9618 #endif
9619 }
9620
9621 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9622 unsigned long searched_pc, int pc_pos, void *puc)
9623 {
9624 env->regs[15] = gen_opc_pc[pc_pos];
9625 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9626 }
Qemu copy for testing