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Merge remote branch 'spice/spice.v29.pull' into staging
[qemu.git] / target-arm / translate.c
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
42
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
44
45 /* internal defines */
46 typedef struct DisasContext {
47 target_ulong pc;
48 int is_jmp;
49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
56 struct TranslationBlock *tb;
57 int singlestep_enabled;
58 int thumb;
59 #if !defined(CONFIG_USER_ONLY)
60 int user;
61 #endif
62 int vfp_enabled;
63 int vec_len;
64 int vec_stride;
65 } DisasContext;
66
67 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
69 #if defined(CONFIG_USER_ONLY)
70 #define IS_USER(s) 1
71 #else
72 #define IS_USER(s) (s->user)
73 #endif
74
75 /* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77 #define DISAS_WFI 4
78 #define DISAS_SWI 5
79
80 static TCGv_ptr cpu_env;
81 /* We reuse the same 64-bit temporaries for efficiency. */
82 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
83 static TCGv_i32 cpu_R[16];
84 static TCGv_i32 cpu_exclusive_addr;
85 static TCGv_i32 cpu_exclusive_val;
86 static TCGv_i32 cpu_exclusive_high;
87 #ifdef CONFIG_USER_ONLY
88 static TCGv_i32 cpu_exclusive_test;
89 static TCGv_i32 cpu_exclusive_info;
90 #endif
91
92 /* FIXME: These should be removed. */
93 static TCGv cpu_F0s, cpu_F1s;
94 static TCGv_i64 cpu_F0d, cpu_F1d;
95
96 #include "gen-icount.h"
97
98 static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
102 /* initialize TCG globals. */
103 void arm_translate_init(void)
104 {
105 int i;
106
107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120 #ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125 #endif
126
127 #define GEN_HELPER 2
128 #include "helpers.h"
129 }
130
131 static int num_temps;
132
133 /* Allocate a temporary variable. */
134 static TCGv_i32 new_tmp(void)
135 {
136 num_temps++;
137 return tcg_temp_new_i32();
138 }
139
140 /* Release a temporary variable. */
141 static void dead_tmp(TCGv tmp)
142 {
143 tcg_temp_free(tmp);
144 num_temps--;
145 }
146
147 static inline TCGv load_cpu_offset(int offset)
148 {
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152 }
153
154 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156 static inline void store_cpu_offset(TCGv var, int offset)
157 {
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160 }
161
162 #define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
165 /* Set a variable to the value of a CPU register. */
166 static void load_reg_var(DisasContext *s, TCGv var, int reg)
167 {
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
177 tcg_gen_mov_i32(var, cpu_R[reg]);
178 }
179 }
180
181 /* Create a new temporary and set it to the value of a CPU register. */
182 static inline TCGv load_reg(DisasContext *s, int reg)
183 {
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187 }
188
189 /* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191 static void store_reg(DisasContext *s, int reg, TCGv var)
192 {
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
197 tcg_gen_mov_i32(cpu_R[reg], var);
198 dead_tmp(var);
199 }
200
201 /* Value extensions. */
202 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
204 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
207 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
209
210
211 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212 {
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216 }
217 /* Set NZCV flags from the high 4 bits of var. */
218 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220 static void gen_exception(int excp)
221 {
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226 }
227
228 static void gen_smul_dual(TCGv a, TCGv b)
229 {
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241 }
242
243 /* Byteswap each halfword. */
244 static void gen_rev16(TCGv var)
245 {
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253 }
254
255 /* Byteswap low halfword and sign extend. */
256 static void gen_revsh(TCGv var)
257 {
258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
261 }
262
263 /* Unsigned bitfield extract. */
264 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265 {
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269 }
270
271 /* Signed bitfield extract. */
272 static void gen_sbfx(TCGv var, int shift, int width)
273 {
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284 }
285
286 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
287 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288 {
289 tcg_gen_andi_i32(val, val, mask);
290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
292 tcg_gen_or_i32(dest, base, val);
293 }
294
295 /* Return (b << 32) + a. Mark inputs as dead */
296 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
297 {
298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307 }
308
309 /* Return (b << 32) - a. Mark inputs as dead. */
310 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311 {
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
321 }
322
323 /* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
325 /* 32x32->64 multiply. Marks inputs as dead. */
326 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
327 {
328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
336 tcg_temp_free_i64(tmp2);
337 return tmp1;
338 }
339
340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
341 {
342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 tcg_temp_free_i64(tmp2);
351 return tmp1;
352 }
353
354 /* Swap low and high halfwords. */
355 static void gen_swap_half(TCGv var)
356 {
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
361 dead_tmp(tmp);
362 }
363
364 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371 static void gen_add16(TCGv t0, TCGv t1)
372 {
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382 }
383
384 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
386 /* Set CF to the top bit of var. */
387 static void gen_set_CF_bit31(TCGv var)
388 {
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
391 gen_set_CF(tmp);
392 dead_tmp(tmp);
393 }
394
395 /* Set N and Z flags from var. */
396 static inline void gen_logic_CC(TCGv var)
397 {
398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
400 }
401
402 /* T0 += T1 + CF. */
403 static void gen_adc(TCGv t0, TCGv t1)
404 {
405 TCGv tmp;
406 tcg_gen_add_i32(t0, t0, t1);
407 tmp = load_cpu_field(CF);
408 tcg_gen_add_i32(t0, t0, tmp);
409 dead_tmp(tmp);
410 }
411
412 /* dest = T0 + T1 + CF. */
413 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414 {
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420 }
421
422 /* dest = T0 - T1 + CF - 1. */
423 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424 {
425 TCGv tmp;
426 tcg_gen_sub_i32(dest, t0, t1);
427 tmp = load_cpu_field(CF);
428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431 }
432
433 /* FIXME: Implement this natively. */
434 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
436 static void shifter_out_im(TCGv var, int shift)
437 {
438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
441 } else {
442 tcg_gen_shri_i32(tmp, var, shift);
443 if (shift != 31)
444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448 }
449
450 /* Shift by immediate. Includes special handling for shift == 0. */
451 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452 {
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
487 tcg_gen_rotri_i32(var, var, shift); break;
488 } else {
489 TCGv tmp = load_cpu_field(CF);
490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
496 }
497 }
498 };
499
500 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502 {
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
517 }
518 }
519 dead_tmp(shift);
520 }
521
522 #define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
531 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
532 {
533 TCGv_ptr tmp;
534
535 switch (op1) {
536 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
538 tmp = tcg_temp_new_ptr();
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
541 tcg_temp_free_ptr(tmp);
542 break;
543 case 5:
544 tmp = tcg_temp_new_ptr();
545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
547 tcg_temp_free_ptr(tmp);
548 break;
549 #undef gen_pas_helper
550 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563 #undef gen_pas_helper
564 }
565 }
566 #undef PAS_OP
567
568 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569 #define PAS_OP(pfx) \
570 switch (op1) { \
571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
578 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
579 {
580 TCGv_ptr tmp;
581
582 switch (op2) {
583 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
585 tmp = tcg_temp_new_ptr();
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
588 tcg_temp_free_ptr(tmp);
589 break;
590 case 4:
591 tmp = tcg_temp_new_ptr();
592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
594 tcg_temp_free_ptr(tmp);
595 break;
596 #undef gen_pas_helper
597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610 #undef gen_pas_helper
611 }
612 }
613 #undef PAS_OP
614
615 static void gen_test_cc(int cc, int label)
616 {
617 TCGv tmp;
618 TCGv tmp2;
619 int inv;
620
621 switch (cc) {
622 case 0: /* eq: Z */
623 tmp = load_cpu_field(ZF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 1: /* ne: !Z */
627 tmp = load_cpu_field(ZF);
628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
637 break;
638 case 4: /* mi: N */
639 tmp = load_cpu_field(NF);
640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
641 break;
642 case 5: /* pl: !N */
643 tmp = load_cpu_field(NF);
644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
658 dead_tmp(tmp);
659 tmp = load_cpu_field(ZF);
660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
666 dead_tmp(tmp);
667 tmp = load_cpu_field(ZF);
668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
672 tmp2 = load_cpu_field(NF);
673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
679 tmp2 = load_cpu_field(NF);
680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
686 tmp = load_cpu_field(ZF);
687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
690 tmp2 = load_cpu_field(NF);
691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
697 tmp = load_cpu_field(ZF);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
701 tmp2 = load_cpu_field(NF);
702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711 }
712
713 static const uint8_t table_logic_cc[16] = {
714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730 };
731
732 /* Set PC and Thumb state from an immediate address. */
733 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
734 {
735 TCGv tmp;
736
737 s->is_jmp = DISAS_UPDATE;
738 if (s->thumb != (addr & 1)) {
739 tmp = new_tmp();
740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
742 dead_tmp(tmp);
743 }
744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
745 }
746
747 /* Set PC and Thumb state from var. var is marked as dead. */
748 static inline void gen_bx(DisasContext *s, TCGv var)
749 {
750 s->is_jmp = DISAS_UPDATE;
751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
754 }
755
756 /* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759 static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761 {
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767 }
768
769 static inline TCGv gen_ld8s(TCGv addr, int index)
770 {
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774 }
775 static inline TCGv gen_ld8u(TCGv addr, int index)
776 {
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780 }
781 static inline TCGv gen_ld16s(TCGv addr, int index)
782 {
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786 }
787 static inline TCGv gen_ld16u(TCGv addr, int index)
788 {
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792 }
793 static inline TCGv gen_ld32(TCGv addr, int index)
794 {
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798 }
799 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800 {
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804 }
805 static inline void gen_st8(TCGv val, TCGv addr, int index)
806 {
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809 }
810 static inline void gen_st16(TCGv val, TCGv addr, int index)
811 {
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814 }
815 static inline void gen_st32(TCGv val, TCGv addr, int index)
816 {
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819 }
820 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821 {
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824 }
825
826 static inline void gen_set_pc_im(uint32_t val)
827 {
828 tcg_gen_movi_i32(cpu_R[15], val);
829 }
830
831 /* Force a TB lookup after an instruction that changes the CPU state. */
832 static inline void gen_lookup_tb(DisasContext *s)
833 {
834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
835 s->is_jmp = DISAS_UPDATE;
836 }
837
838 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
840 {
841 int val, rm, shift, shiftop;
842 TCGv offset;
843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
849 if (val != 0)
850 tcg_gen_addi_i32(var, var, val);
851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
855 shiftop = (insn >> 5) & 3;
856 offset = load_reg(s, rm);
857 gen_arm_shift_im(offset, shiftop, shift, 0);
858 if (!(insn & (1 << 23)))
859 tcg_gen_sub_i32(var, var, offset);
860 else
861 tcg_gen_add_i32(var, var, offset);
862 dead_tmp(offset);
863 }
864 }
865
866 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
867 int extra, TCGv var)
868 {
869 int val, rm;
870 TCGv offset;
871
872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
877 val += extra;
878 if (val != 0)
879 tcg_gen_addi_i32(var, var, val);
880 } else {
881 /* register */
882 if (extra)
883 tcg_gen_addi_i32(var, var, extra);
884 rm = (insn) & 0xf;
885 offset = load_reg(s, rm);
886 if (!(insn & (1 << 23)))
887 tcg_gen_sub_i32(var, var, offset);
888 else
889 tcg_gen_add_i32(var, var, offset);
890 dead_tmp(offset);
891 }
892 }
893
894 #define VFP_OP2(name) \
895 static inline void gen_vfp_##name(int dp) \
896 { \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
901 }
902
903 VFP_OP2(add)
904 VFP_OP2(sub)
905 VFP_OP2(mul)
906 VFP_OP2(div)
907
908 #undef VFP_OP2
909
910 static inline void gen_vfp_abs(int dp)
911 {
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916 }
917
918 static inline void gen_vfp_neg(int dp)
919 {
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924 }
925
926 static inline void gen_vfp_sqrt(int dp)
927 {
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932 }
933
934 static inline void gen_vfp_cmp(int dp)
935 {
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940 }
941
942 static inline void gen_vfp_cmpe(int dp)
943 {
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948 }
949
950 static inline void gen_vfp_F1_ld0(int dp)
951 {
952 if (dp)
953 tcg_gen_movi_i64(cpu_F1d, 0);
954 else
955 tcg_gen_movi_i32(cpu_F1s, 0);
956 }
957
958 static inline void gen_vfp_uito(int dp)
959 {
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964 }
965
966 static inline void gen_vfp_sito(int dp)
967 {
968 if (dp)
969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
970 else
971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
972 }
973
974 static inline void gen_vfp_toui(int dp)
975 {
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980 }
981
982 static inline void gen_vfp_touiz(int dp)
983 {
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988 }
989
990 static inline void gen_vfp_tosi(int dp)
991 {
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996 }
997
998 static inline void gen_vfp_tosiz(int dp)
999 {
1000 if (dp)
1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1002 else
1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004 }
1005
1006 #define VFP_GEN_FIX(name) \
1007 static inline void gen_vfp_##name(int dp, int shift) \
1008 { \
1009 TCGv tmp_shift = tcg_const_i32(shift); \
1010 if (dp) \
1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1012 else \
1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
1015 }
1016 VFP_GEN_FIX(tosh)
1017 VFP_GEN_FIX(tosl)
1018 VFP_GEN_FIX(touh)
1019 VFP_GEN_FIX(toul)
1020 VFP_GEN_FIX(shto)
1021 VFP_GEN_FIX(slto)
1022 VFP_GEN_FIX(uhto)
1023 VFP_GEN_FIX(ulto)
1024 #undef VFP_GEN_FIX
1025
1026 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1027 {
1028 if (dp)
1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1030 else
1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1032 }
1033
1034 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1035 {
1036 if (dp)
1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1038 else
1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1040 }
1041
1042 static inline long
1043 vfp_reg_offset (int dp, int reg)
1044 {
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054 }
1055
1056 /* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058 static inline long
1059 neon_reg_offset (int reg, int n)
1060 {
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064 }
1065
1066 static TCGv neon_load_reg(int reg, int pass)
1067 {
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071 }
1072
1073 static void neon_store_reg(int reg, int pass, TCGv var)
1074 {
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077 }
1078
1079 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1080 {
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082 }
1083
1084 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1085 {
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087 }
1088
1089 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1090 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1091 #define tcg_gen_st_f32 tcg_gen_st_i32
1092 #define tcg_gen_st_f64 tcg_gen_st_i64
1093
1094 static inline void gen_mov_F0_vreg(int dp, int reg)
1095 {
1096 if (dp)
1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1098 else
1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1100 }
1101
1102 static inline void gen_mov_F1_vreg(int dp, int reg)
1103 {
1104 if (dp)
1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1106 else
1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1108 }
1109
1110 static inline void gen_mov_vreg_F0(int dp, int reg)
1111 {
1112 if (dp)
1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1114 else
1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1116 }
1117
1118 #define ARM_CP_RW_BIT (1 << 20)
1119
1120 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1121 {
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123 }
1124
1125 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1126 {
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128 }
1129
1130 static inline TCGv iwmmxt_load_creg(int reg)
1131 {
1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
1135 }
1136
1137 static inline void iwmmxt_store_creg(int reg, TCGv var)
1138 {
1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1140 dead_tmp(var);
1141 }
1142
1143 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144 {
1145 iwmmxt_store_reg(cpu_M0, rn);
1146 }
1147
1148 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149 {
1150 iwmmxt_load_reg(cpu_M0, rn);
1151 }
1152
1153 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154 {
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157 }
1158
1159 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160 {
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163 }
1164
1165 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166 {
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169 }
1170
1171 #define IWMMXT_OP(name) \
1172 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173 { \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176 }
1177
1178 #define IWMMXT_OP_ENV(name) \
1179 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180 { \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183 }
1184
1185 #define IWMMXT_OP_ENV_SIZE(name) \
1186 IWMMXT_OP_ENV(name##b) \
1187 IWMMXT_OP_ENV(name##w) \
1188 IWMMXT_OP_ENV(name##l)
1189
1190 #define IWMMXT_OP_ENV1(name) \
1191 static inline void gen_op_iwmmxt_##name##_M0(void) \
1192 { \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194 }
1195
1196 IWMMXT_OP(maddsq)
1197 IWMMXT_OP(madduq)
1198 IWMMXT_OP(sadb)
1199 IWMMXT_OP(sadw)
1200 IWMMXT_OP(mulslw)
1201 IWMMXT_OP(mulshw)
1202 IWMMXT_OP(mululw)
1203 IWMMXT_OP(muluhw)
1204 IWMMXT_OP(macsw)
1205 IWMMXT_OP(macuw)
1206
1207 IWMMXT_OP_ENV_SIZE(unpackl)
1208 IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210 IWMMXT_OP_ENV1(unpacklub)
1211 IWMMXT_OP_ENV1(unpackluw)
1212 IWMMXT_OP_ENV1(unpacklul)
1213 IWMMXT_OP_ENV1(unpackhub)
1214 IWMMXT_OP_ENV1(unpackhuw)
1215 IWMMXT_OP_ENV1(unpackhul)
1216 IWMMXT_OP_ENV1(unpacklsb)
1217 IWMMXT_OP_ENV1(unpacklsw)
1218 IWMMXT_OP_ENV1(unpacklsl)
1219 IWMMXT_OP_ENV1(unpackhsb)
1220 IWMMXT_OP_ENV1(unpackhsw)
1221 IWMMXT_OP_ENV1(unpackhsl)
1222
1223 IWMMXT_OP_ENV_SIZE(cmpeq)
1224 IWMMXT_OP_ENV_SIZE(cmpgtu)
1225 IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227 IWMMXT_OP_ENV_SIZE(mins)
1228 IWMMXT_OP_ENV_SIZE(minu)
1229 IWMMXT_OP_ENV_SIZE(maxs)
1230 IWMMXT_OP_ENV_SIZE(maxu)
1231
1232 IWMMXT_OP_ENV_SIZE(subn)
1233 IWMMXT_OP_ENV_SIZE(addn)
1234 IWMMXT_OP_ENV_SIZE(subu)
1235 IWMMXT_OP_ENV_SIZE(addu)
1236 IWMMXT_OP_ENV_SIZE(subs)
1237 IWMMXT_OP_ENV_SIZE(adds)
1238
1239 IWMMXT_OP_ENV(avgb0)
1240 IWMMXT_OP_ENV(avgb1)
1241 IWMMXT_OP_ENV(avgw0)
1242 IWMMXT_OP_ENV(avgw1)
1243
1244 IWMMXT_OP(msadb)
1245
1246 IWMMXT_OP_ENV(packuw)
1247 IWMMXT_OP_ENV(packul)
1248 IWMMXT_OP_ENV(packuq)
1249 IWMMXT_OP_ENV(packsw)
1250 IWMMXT_OP_ENV(packsl)
1251 IWMMXT_OP_ENV(packsq)
1252
1253 static void gen_op_iwmmxt_set_mup(void)
1254 {
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 }
1260
1261 static void gen_op_iwmmxt_set_cup(void)
1262 {
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267 }
1268
1269 static void gen_op_iwmmxt_setpsr_nz(void)
1270 {
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274 }
1275
1276 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277 {
1278 iwmmxt_load_reg(cpu_V1, rn);
1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281 }
1282
1283 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1284 {
1285 int rd;
1286 uint32_t offset;
1287 TCGv tmp;
1288
1289 rd = (insn >> 16) & 0xf;
1290 tmp = load_reg(s, rd);
1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
1296 tcg_gen_addi_i32(tmp, tmp, offset);
1297 else
1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
1300 if (insn & (1 << 21))
1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
1306 tcg_gen_mov_i32(dest, tmp);
1307 if (insn & (1 << 23))
1308 tcg_gen_addi_i32(tmp, tmp, offset);
1309 else
1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315 }
1316
1317 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1318 {
1319 int rd = (insn >> 0) & 0xf;
1320 TCGv tmp;
1321
1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1324 return 1;
1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
1336 return 0;
1337 }
1338
1339 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342 {
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1358 } else { /* TMCRR */
1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
1370 return 1;
1371 }
1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
1377 } else {
1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1382 i = 0;
1383 } else { /* WLDRW wRd */
1384 tmp = gen_ld32(addr, IS_USER(s));
1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
1388 tmp = gen_ld16u(addr, IS_USER(s));
1389 } else { /* WLDRB */
1390 tmp = gen_ld8u(addr, IS_USER(s));
1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st32(tmp, addr, IS_USER(s));
1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1417 gen_st16(tmp, addr, IS_USER(s));
1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1420 gen_st8(tmp, addr, IS_USER(s));
1421 }
1422 }
1423 }
1424 }
1425 dead_tmp(addr);
1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
1682 tmp = load_reg(s, rd);
1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
1688 break;
1689 case 1:
1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
1692 break;
1693 case 2:
1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
1696 break;
1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
1700 }
1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
1714 tmp = new_tmp();
1715 switch ((insn >> 22) & 3) {
1716 case 0:
1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
1723 }
1724 break;
1725 case 1:
1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1732 }
1733 break;
1734 case 2:
1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1737 break;
1738 }
1739 store_reg(s, rd, tmp);
1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1743 return 1;
1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1745 switch ((insn >> 22) & 3) {
1746 case 0:
1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1748 break;
1749 case 1:
1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1751 break;
1752 case 2:
1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1754 break;
1755 }
1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
1765 tmp = load_reg(s, rd);
1766 switch ((insn >> 6) & 3) {
1767 case 0:
1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1769 break;
1770 case 1:
1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1772 break;
1773 case 2:
1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1775 break;
1776 }
1777 dead_tmp(tmp);
1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1783 return 1;
1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 }
1799 break;
1800 case 2:
1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
1803 break;
1804 }
1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1816 break;
1817 case 1:
1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1819 break;
1820 case 2:
1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1831 return 1;
1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 }
1847 break;
1848 case 2:
1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
1851 break;
1852 }
1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
1863 tmp = new_tmp();
1864 switch ((insn >> 22) & 3) {
1865 case 0:
1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1867 break;
1868 case 1:
1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1870 break;
1871 case 2:
1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1873 break;
1874 }
1875 store_reg(s, rd, tmp);
1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
1981 return 1;
1982 }
1983 switch ((insn >> 22) & 3) {
1984 case 1:
1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
1986 break;
1987 case 2:
1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
1989 break;
1990 case 3:
1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
1992 break;
1993 }
1994 dead_tmp(tmp);
1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
2009 return 1;
2010 }
2011 switch ((insn >> 22) & 3) {
2012 case 1:
2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2014 break;
2015 case 2:
2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2017 break;
2018 case 3:
2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2020 break;
2021 }
2022 dead_tmp(tmp);
2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
2037 return 1;
2038 }
2039 switch ((insn >> 22) & 3) {
2040 case 1:
2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2042 break;
2043 case 2:
2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2045 break;
2046 case 3:
2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2048 break;
2049 }
2050 dead_tmp(tmp);
2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
2062 tmp = new_tmp();
2063 switch ((insn >> 22) & 3) {
2064 case 1:
2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
2067 return 1;
2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2070 break;
2071 case 2:
2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
2074 return 1;
2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2077 break;
2078 case 3:
2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
2081 return 1;
2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2084 break;
2085 }
2086 dead_tmp(tmp);
2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
2276 switch ((insn >> 22) & 3) {
2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2315 break;
2316 case 0x8: /* TMIAPH */
2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2320 if (insn & (1 << 16))
2321 tcg_gen_shri_i32(tmp, tmp, 16);
2322 if (insn & (1 << 17))
2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2325 break;
2326 default:
2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
2329 return 1;
2330 }
2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341 }
2342
2343 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346 {
2347 int acc, rd0, rd1, rdhi, rdlo;
2348 TCGv tmp, tmp2;
2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2364 break;
2365 case 0x8: /* MIAPH */
2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
2372 if (insn & (1 << 16))
2373 tcg_gen_shri_i32(tmp, tmp, 16);
2374 if (insn & (1 << 17))
2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2377 break;
2378 default:
2379 return 1;
2380 }
2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2403 } else { /* MAR */
2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411 }
2412
2413 /* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416 {
2417 TCGv tmp, tmp2;
2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
2424 if (insn & ARM_CP_RW_BIT) {
2425 if (!env->cp[cp].cp_read)
2426 return 1;
2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
2432 store_reg(s, rd, tmp);
2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
2441 dead_tmp(tmp);
2442 }
2443 return 0;
2444 }
2445
2446 static int cp15_user_ok(uint32_t insn)
2447 {
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464 }
2465
2466 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467 {
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
2480 switch (op) {
2481 case 2:
2482 tmp = load_cpu_field(cp15.c13_tls1);
2483 break;
2484 case 3:
2485 tmp = load_cpu_field(cp15.c13_tls2);
2486 break;
2487 case 4:
2488 tmp = load_cpu_field(cp15.c13_tls3);
2489 break;
2490 default:
2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
2499 store_cpu_field(tmp, cp15.c13_tls1);
2500 break;
2501 case 3:
2502 store_cpu_field(tmp, cp15.c13_tls2);
2503 break;
2504 case 4:
2505 store_cpu_field(tmp, cp15.c13_tls3);
2506 break;
2507 default:
2508 dead_tmp(tmp);
2509 return 0;
2510 }
2511 }
2512 return 1;
2513 }
2514
2515 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
2517 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2518 {
2519 uint32_t rd;
2520 TCGv tmp, tmp2;
2521
2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
2539 return 1;
2540 }
2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
2544 gen_set_pc_im(s->pc);
2545 s->is_jmp = DISAS_WFI;
2546 return 0;
2547 }
2548 rd = (insn >> 12) & 0xf;
2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
2553 tmp2 = tcg_const_i32(insn);
2554 if (insn & ARM_CP_RW_BIT) {
2555 tmp = new_tmp();
2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
2562 } else {
2563 tmp = load_reg(s, rd);
2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2565 dead_tmp(tmp);
2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
2572 }
2573 tcg_temp_free_i32(tmp2);
2574 return 0;
2575 }
2576
2577 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578 #define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
2597 /* Move between integer and VFP cores. */
2598 static TCGv gen_vfp_mrs(void)
2599 {
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603 }
2604
2605 static void gen_vfp_msr(TCGv tmp)
2606 {
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609 }
2610
2611 static void gen_neon_dup_u8(TCGv var, int shift)
2612 {
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
2616 tcg_gen_ext8u_i32(var, var);
2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622 }
2623
2624 static void gen_neon_dup_low16(TCGv var)
2625 {
2626 TCGv tmp = new_tmp();
2627 tcg_gen_ext16u_i32(var, var);
2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631 }
2632
2633 static void gen_neon_dup_high16(TCGv var)
2634 {
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640 }
2641
2642 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645 {
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
2648 TCGv addr;
2649 TCGv tmp;
2650 TCGv tmp2;
2651
2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
2655 if (!s->vfp_enabled) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2662 return 1;
2663 }
2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
2676 return 1;
2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
2692 if (insn & ARM_CP_RW_BIT) {
2693 /* vfp->arm */
2694 tmp = neon_load_reg(rn, pass);
2695 switch (size) {
2696 case 0:
2697 if (offset)
2698 tcg_gen_shri_i32(tmp, tmp, offset);
2699 if (insn & (1 << 23))
2700 gen_uxtb(tmp);
2701 else
2702 gen_sxtb(tmp);
2703 break;
2704 case 1:
2705 if (insn & (1 << 23)) {
2706 if (offset) {
2707 tcg_gen_shri_i32(tmp, tmp, 16);
2708 } else {
2709 gen_uxth(tmp);
2710 }
2711 } else {
2712 if (offset) {
2713 tcg_gen_sari_i32(tmp, tmp, 16);
2714 } else {
2715 gen_sxth(tmp);
2716 }
2717 }
2718 break;
2719 case 2:
2720 break;
2721 }
2722 store_reg(s, rd, tmp);
2723 } else {
2724 /* arm->vfp */
2725 tmp = load_reg(s, rd);
2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
2729 gen_neon_dup_u8(tmp, 0);
2730 } else if (size == 1) {
2731 gen_neon_dup_low16(tmp);
2732 }
2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
2746 break;
2747 case 1:
2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
2751 break;
2752 case 2:
2753 break;
2754 }
2755 neon_store_reg(rn, pass, tmp);
2756 }
2757 }
2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
2762 if (insn & ARM_CP_RW_BIT) {
2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
2766 rn >>= 1;
2767
2768 switch (rn) {
2769 case ARM_VFP_FPSID:
2770 /* VFP2 allows access to FSID from userspace.
2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
2776 tmp = load_cpu_field(vfp.xregs[rn]);
2777 break;
2778 case ARM_VFP_FPEXC:
2779 if (IS_USER(s))
2780 return 1;
2781 tmp = load_cpu_field(vfp.xregs[rn]);
2782 break;
2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
2789 tmp = load_cpu_field(vfp.xregs[rn]);
2790 break;
2791 case ARM_VFP_FPSCR:
2792 if (rd == 15) {
2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
2799 break;
2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
2805 tmp = load_cpu_field(vfp.xregs[rn]);
2806 break;
2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
2812 tmp = gen_vfp_mrs();
2813 }
2814 if (rd == 15) {
2815 /* Set the 4 flag bits in the CPSR. */
2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
2821 } else {
2822 /* arm->vfp */
2823 tmp = load_reg(s, rd);
2824 if (insn & (1 << 21)) {
2825 rn >>= 1;
2826 /* system register */
2827 switch (rn) {
2828 case ARM_VFP_FPSID:
2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
2831 /* Writes are ignored. */
2832 break;
2833 case ARM_VFP_FPSCR:
2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
2836 gen_lookup_tb(s);
2837 break;
2838 case ARM_VFP_FPEXC:
2839 if (IS_USER(s))
2840 return 1;
2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2844 store_cpu_field(tmp, vfp.xregs[rn]);
2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
2849 store_cpu_field(tmp, vfp.xregs[rn]);
2850 break;
2851 default:
2852 return 1;
2853 }
2854 } else {
2855 gen_vfp_msr(tmp);
2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
2870 VFP_DREG_N(rn, insn);
2871 }
2872
2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2874 /* Integer or single precision destination. */
2875 rd = VFP_SREG_D(insn);
2876 } else {
2877 VFP_DREG_D(rd, insn);
2878 }
2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
2885 } else {
2886 VFP_DREG_M(rm, insn);
2887 }
2888 } else {
2889 rn = VFP_SREG_N(insn);
2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
2899 rm = VFP_SREG_M(insn);
2900 }
2901
2902 veclen = s->vec_len;
2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
2910
2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
2923 delta_d = (s->vec_stride >> 1) + 1;
2924 else
2925 delta_d = s->vec_stride + 1;
2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
2971 break;
2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
3000 gen_vfp_neg(dp);
3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
3039 tcg_gen_movi_i32(cpu_F0s, n);
3040 }
3041 break;
3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3113 else
3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
3125 gen_vfp_shto(dp, 16 - rm);
3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
3130 gen_vfp_slto(dp, 32 - rm);
3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
3135 gen_vfp_uhto(dp, 16 - rm);
3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
3140 gen_vfp_ulto(dp, 32 - rm);
3141 break;
3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
3157 gen_vfp_tosh(dp, 16 - rm);
3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
3162 gen_vfp_tosl(dp, 32 - rm);
3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_touh(dp, 16 - rm);
3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_toul(dp, 32 - rm);
3173 break;
3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
3244
3245 if (insn & ARM_CP_RW_BIT) {
3246 /* vfp->arm */
3247 if (dp) {
3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
3254 } else {
3255 gen_mov_F0_vreg(0, rm);
3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
3258 gen_mov_F0_vreg(0, rm + 1);
3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
3271 } else {
3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
3274 gen_mov_vreg_F0(0, rm);
3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
3284 VFP_DREG_D(rd, insn);
3285 else
3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
3290 } else {
3291 addr = load_reg(s, rn);
3292 }
3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
3298 tcg_gen_addi_i32(addr, addr, offset);
3299 if (insn & (1 << 20)) {
3300 gen_vfp_ld(s, dp, addr);
3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
3304 gen_vfp_st(s, dp, addr);
3305 }
3306 dead_tmp(addr);
3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
3322 if (insn & ARM_CP_RW_BIT) {
3323 /* load */
3324 gen_vfp_ld(s, dp, addr);
3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
3329 gen_vfp_st(s, dp, addr);
3330 }
3331 tcg_gen_addi_i32(addr, addr, offset);
3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356 }
3357
3358 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3359 {
3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3364 tcg_gen_goto_tb(n);
3365 gen_set_pc_im(dest);
3366 tcg_gen_exit_tb((long)tb + n);
3367 } else {
3368 gen_set_pc_im(dest);
3369 tcg_gen_exit_tb(0);
3370 }
3371 }
3372
3373 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374 {
3375 if (unlikely(s->singlestep_enabled)) {
3376 /* An indirect jump so that we still trigger the debug exception. */
3377 if (s->thumb)
3378 dest |= 1;
3379 gen_bx_im(s, dest);
3380 } else {
3381 gen_goto_tb(s, 0, dest);
3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384 }
3385
3386 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3387 {
3388 if (x)
3389 tcg_gen_sari_i32(t0, t0, 16);
3390 else
3391 gen_sxth(t0);
3392 if (y)
3393 tcg_gen_sari_i32(t1, t1, 16);
3394 else
3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
3397 }
3398
3399 /* Return the mask of PSR bits set by a MSR instruction. */
3400 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
3412
3413 /* Mask out undefined bits. */
3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
3416 mask &= ~(CPSR_E | CPSR_GE);
3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3418 mask &= ~CPSR_IT;
3419 /* Mask out execution state bits. */
3420 if (!spsr)
3421 mask &= ~CPSR_EXEC;
3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
3424 mask &= CPSR_USER;
3425 return mask;
3426 }
3427
3428 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3430 {
3431 TCGv tmp;
3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
3441 store_cpu_field(tmp, spsr);
3442 } else {
3443 gen_set_cpsr(t0, mask);
3444 }
3445 dead_tmp(t0);
3446 gen_lookup_tb(s);
3447 return 0;
3448 }
3449
3450 /* Returns nonzero if access to the PSR is not permitted. */
3451 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452 {
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457 }
3458
3459 /* Generate an old-style exception return. Marks pc as dead. */
3460 static void gen_exception_return(DisasContext *s, TCGv pc)
3461 {
3462 TCGv tmp;
3463 store_reg(s, 15, pc);
3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
3467 s->is_jmp = DISAS_UPDATE;
3468 }
3469
3470 /* Generate a v6 exception return. Marks both values as dead. */
3471 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3472 {
3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
3476 s->is_jmp = DISAS_UPDATE;
3477 }
3478
3479 static inline void
3480 gen_set_condexec (DisasContext *s)
3481 {
3482 if (s->condexec_mask) {
3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
3486 store_cpu_field(tmp, condexec_bits);
3487 }
3488 }
3489
3490 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491 {
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496 }
3497
3498 static void gen_nop_hint(DisasContext *s, int val)
3499 {
3500 switch (val) {
3501 case 3: /* wfi */
3502 gen_set_pc_im(s->pc);
3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511 }
3512
3513 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3514
3515 static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
3516 {
3517 switch (size) {
3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3521 default: return 1;
3522 }
3523 return 0;
3524 }
3525
3526 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3527 {
3528 switch (size) {
3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3532 default: return;
3533 }
3534 }
3535
3536 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3537 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
3542 /* FIXME: This is wrong. They set the wrong overflow bit. */
3543 #define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3544 #define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3545 #define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3546 #define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3547
3548 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3549 switch ((size << 1) | u) { \
3550 case 0: \
3551 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3552 break; \
3553 case 1: \
3554 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3555 break; \
3556 case 2: \
3557 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3558 break; \
3559 case 3: \
3560 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3561 break; \
3562 case 4: \
3563 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3564 break; \
3565 case 5: \
3566 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3567 break; \
3568 default: return 1; \
3569 }} while (0)
3570
3571 #define GEN_NEON_INTEGER_OP(name) do { \
3572 switch ((size << 1) | u) { \
3573 case 0: \
3574 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3575 break; \
3576 case 1: \
3577 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3578 break; \
3579 case 2: \
3580 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3581 break; \
3582 case 3: \
3583 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3584 break; \
3585 case 4: \
3586 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3587 break; \
3588 case 5: \
3589 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3590 break; \
3591 default: return 1; \
3592 }} while (0)
3593
3594 static TCGv neon_load_scratch(int scratch)
3595 {
3596 TCGv tmp = new_tmp();
3597 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 return tmp;
3599 }
3600
3601 static void neon_store_scratch(int scratch, TCGv var)
3602 {
3603 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3604 dead_tmp(var);
3605 }
3606
3607 static inline TCGv neon_get_scalar(int size, int reg)
3608 {
3609 TCGv tmp;
3610 if (size == 1) {
3611 tmp = neon_load_reg(reg & 7, reg >> 4);
3612 if (reg & 8) {
3613 gen_neon_dup_high16(tmp);
3614 } else {
3615 gen_neon_dup_low16(tmp);
3616 }
3617 } else {
3618 tmp = neon_load_reg(reg & 15, reg >> 4);
3619 }
3620 return tmp;
3621 }
3622
3623 static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3624 {
3625 TCGv rd, rm, tmp;
3626
3627 rd = new_tmp();
3628 rm = new_tmp();
3629 tmp = new_tmp();
3630
3631 tcg_gen_andi_i32(rd, t0, 0xff);
3632 tcg_gen_shri_i32(tmp, t0, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3634 tcg_gen_or_i32(rd, rd, tmp);
3635 tcg_gen_shli_i32(tmp, t1, 16);
3636 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3637 tcg_gen_or_i32(rd, rd, tmp);
3638 tcg_gen_shli_i32(tmp, t1, 8);
3639 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3640 tcg_gen_or_i32(rd, rd, tmp);
3641
3642 tcg_gen_shri_i32(rm, t0, 8);
3643 tcg_gen_andi_i32(rm, rm, 0xff);
3644 tcg_gen_shri_i32(tmp, t0, 16);
3645 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3646 tcg_gen_or_i32(rm, rm, tmp);
3647 tcg_gen_shli_i32(tmp, t1, 8);
3648 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3649 tcg_gen_or_i32(rm, rm, tmp);
3650 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3651 tcg_gen_or_i32(t1, rm, tmp);
3652 tcg_gen_mov_i32(t0, rd);
3653
3654 dead_tmp(tmp);
3655 dead_tmp(rm);
3656 dead_tmp(rd);
3657 }
3658
3659 static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3660 {
3661 TCGv rd, rm, tmp;
3662
3663 rd = new_tmp();
3664 rm = new_tmp();
3665 tmp = new_tmp();
3666
3667 tcg_gen_andi_i32(rd, t0, 0xff);
3668 tcg_gen_shli_i32(tmp, t1, 8);
3669 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3670 tcg_gen_or_i32(rd, rd, tmp);
3671 tcg_gen_shli_i32(tmp, t0, 16);
3672 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3673 tcg_gen_or_i32(rd, rd, tmp);
3674 tcg_gen_shli_i32(tmp, t1, 24);
3675 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3676 tcg_gen_or_i32(rd, rd, tmp);
3677
3678 tcg_gen_andi_i32(rm, t1, 0xff000000);
3679 tcg_gen_shri_i32(tmp, t0, 8);
3680 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3681 tcg_gen_or_i32(rm, rm, tmp);
3682 tcg_gen_shri_i32(tmp, t1, 8);
3683 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3684 tcg_gen_or_i32(rm, rm, tmp);
3685 tcg_gen_shri_i32(tmp, t0, 16);
3686 tcg_gen_andi_i32(tmp, tmp, 0xff);
3687 tcg_gen_or_i32(t1, rm, tmp);
3688 tcg_gen_mov_i32(t0, rd);
3689
3690 dead_tmp(tmp);
3691 dead_tmp(rm);
3692 dead_tmp(rd);
3693 }
3694
3695 static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3696 {
3697 TCGv tmp, tmp2;
3698
3699 tmp = new_tmp();
3700 tmp2 = new_tmp();
3701
3702 tcg_gen_andi_i32(tmp, t0, 0xffff);
3703 tcg_gen_shli_i32(tmp2, t1, 16);
3704 tcg_gen_or_i32(tmp, tmp, tmp2);
3705 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3706 tcg_gen_shri_i32(tmp2, t0, 16);
3707 tcg_gen_or_i32(t1, t1, tmp2);
3708 tcg_gen_mov_i32(t0, tmp);
3709
3710 dead_tmp(tmp2);
3711 dead_tmp(tmp);
3712 }
3713
3714 static void gen_neon_unzip(int reg, int q, int tmp, int size)
3715 {
3716 int n;
3717 TCGv t0, t1;
3718
3719 for (n = 0; n < q + 1; n += 2) {
3720 t0 = neon_load_reg(reg, n);
3721 t1 = neon_load_reg(reg, n + 1);
3722 switch (size) {
3723 case 0: gen_neon_unzip_u8(t0, t1); break;
3724 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
3725 case 2: /* no-op */; break;
3726 default: abort();
3727 }
3728 neon_store_scratch(tmp + n, t0);
3729 neon_store_scratch(tmp + n + 1, t1);
3730 }
3731 }
3732
3733 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3734 {
3735 TCGv rd, tmp;
3736
3737 rd = new_tmp();
3738 tmp = new_tmp();
3739
3740 tcg_gen_shli_i32(rd, t0, 8);
3741 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3742 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3743 tcg_gen_or_i32(rd, rd, tmp);
3744
3745 tcg_gen_shri_i32(t1, t1, 8);
3746 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3747 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3748 tcg_gen_or_i32(t1, t1, tmp);
3749 tcg_gen_mov_i32(t0, rd);
3750
3751 dead_tmp(tmp);
3752 dead_tmp(rd);
3753 }
3754
3755 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3756 {
3757 TCGv rd, tmp;
3758
3759 rd = new_tmp();
3760 tmp = new_tmp();
3761
3762 tcg_gen_shli_i32(rd, t0, 16);
3763 tcg_gen_andi_i32(tmp, t1, 0xffff);
3764 tcg_gen_or_i32(rd, rd, tmp);
3765 tcg_gen_shri_i32(t1, t1, 16);
3766 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3767 tcg_gen_or_i32(t1, t1, tmp);
3768 tcg_gen_mov_i32(t0, rd);
3769
3770 dead_tmp(tmp);
3771 dead_tmp(rd);
3772 }
3773
3774
3775 static struct {
3776 int nregs;
3777 int interleave;
3778 int spacing;
3779 } neon_ls_element_type[11] = {
3780 {4, 4, 1},
3781 {4, 4, 2},
3782 {4, 1, 1},
3783 {4, 2, 1},
3784 {3, 3, 1},
3785 {3, 3, 2},
3786 {3, 1, 1},
3787 {1, 1, 1},
3788 {2, 2, 1},
3789 {2, 2, 2},
3790 {2, 1, 1}
3791 };
3792
3793 /* Translate a NEON load/store element instruction. Return nonzero if the
3794 instruction is invalid. */
3795 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3796 {
3797 int rd, rn, rm;
3798 int op;
3799 int nregs;
3800 int interleave;
3801 int spacing;
3802 int stride;
3803 int size;
3804 int reg;
3805 int pass;
3806 int load;
3807 int shift;
3808 int n;
3809 TCGv addr;
3810 TCGv tmp;
3811 TCGv tmp2;
3812 TCGv_i64 tmp64;
3813
3814 if (!s->vfp_enabled)
3815 return 1;
3816 VFP_DREG_D(rd, insn);
3817 rn = (insn >> 16) & 0xf;
3818 rm = insn & 0xf;
3819 load = (insn & (1 << 21)) != 0;
3820 addr = new_tmp();
3821 if ((insn & (1 << 23)) == 0) {
3822 /* Load store all elements. */
3823 op = (insn >> 8) & 0xf;
3824 size = (insn >> 6) & 3;
3825 if (op > 10)
3826 return 1;
3827 nregs = neon_ls_element_type[op].nregs;
3828 interleave = neon_ls_element_type[op].interleave;
3829 spacing = neon_ls_element_type[op].spacing;
3830 if (size == 3 && (interleave | spacing) != 1)
3831 return 1;
3832 load_reg_var(s, addr, rn);
3833 stride = (1 << size) * interleave;
3834 for (reg = 0; reg < nregs; reg++) {
3835 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3836 load_reg_var(s, addr, rn);
3837 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3838 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3839 load_reg_var(s, addr, rn);
3840 tcg_gen_addi_i32(addr, addr, 1 << size);
3841 }
3842 if (size == 3) {
3843 if (load) {
3844 tmp64 = gen_ld64(addr, IS_USER(s));
3845 neon_store_reg64(tmp64, rd);
3846 tcg_temp_free_i64(tmp64);
3847 } else {
3848 tmp64 = tcg_temp_new_i64();
3849 neon_load_reg64(tmp64, rd);
3850 gen_st64(tmp64, addr, IS_USER(s));
3851 }
3852 tcg_gen_addi_i32(addr, addr, stride);
3853 } else {
3854 for (pass = 0; pass < 2; pass++) {
3855 if (size == 2) {
3856 if (load) {
3857 tmp = gen_ld32(addr, IS_USER(s));
3858 neon_store_reg(rd, pass, tmp);
3859 } else {
3860 tmp = neon_load_reg(rd, pass);
3861 gen_st32(tmp, addr, IS_USER(s));
3862 }
3863 tcg_gen_addi_i32(addr, addr, stride);
3864 } else if (size == 1) {
3865 if (load) {
3866 tmp = gen_ld16u(addr, IS_USER(s));
3867 tcg_gen_addi_i32(addr, addr, stride);
3868 tmp2 = gen_ld16u(addr, IS_USER(s));
3869 tcg_gen_addi_i32(addr, addr, stride);
3870 tcg_gen_shli_i32(tmp2, tmp2, 16);
3871 tcg_gen_or_i32(tmp, tmp, tmp2);
3872 dead_tmp(tmp2);
3873 neon_store_reg(rd, pass, tmp);
3874 } else {
3875 tmp = neon_load_reg(rd, pass);
3876 tmp2 = new_tmp();
3877 tcg_gen_shri_i32(tmp2, tmp, 16);
3878 gen_st16(tmp, addr, IS_USER(s));
3879 tcg_gen_addi_i32(addr, addr, stride);
3880 gen_st16(tmp2, addr, IS_USER(s));
3881 tcg_gen_addi_i32(addr, addr, stride);
3882 }
3883 } else /* size == 0 */ {
3884 if (load) {
3885 TCGV_UNUSED(tmp2);
3886 for (n = 0; n < 4; n++) {
3887 tmp = gen_ld8u(addr, IS_USER(s));
3888 tcg_gen_addi_i32(addr, addr, stride);
3889 if (n == 0) {
3890 tmp2 = tmp;
3891 } else {
3892 tcg_gen_shli_i32(tmp, tmp, n * 8);
3893 tcg_gen_or_i32(tmp2, tmp2, tmp);
3894 dead_tmp(tmp);
3895 }
3896 }
3897 neon_store_reg(rd, pass, tmp2);
3898 } else {
3899 tmp2 = neon_load_reg(rd, pass);
3900 for (n = 0; n < 4; n++) {
3901 tmp = new_tmp();
3902 if (n == 0) {
3903 tcg_gen_mov_i32(tmp, tmp2);
3904 } else {
3905 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3906 }
3907 gen_st8(tmp, addr, IS_USER(s));
3908 tcg_gen_addi_i32(addr, addr, stride);
3909 }
3910 dead_tmp(tmp2);
3911 }
3912 }
3913 }
3914 }
3915 rd += spacing;
3916 }
3917 stride = nregs * 8;
3918 } else {
3919 size = (insn >> 10) & 3;
3920 if (size == 3) {
3921 /* Load single element to all lanes. */
3922 if (!load)
3923 return 1;
3924 size = (insn >> 6) & 3;
3925 nregs = ((insn >> 8) & 3) + 1;
3926 stride = (insn & (1 << 5)) ? 2 : 1;
3927 load_reg_var(s, addr, rn);
3928 for (reg = 0; reg < nregs; reg++) {
3929 switch (size) {
3930 case 0:
3931 tmp = gen_ld8u(addr, IS_USER(s));
3932 gen_neon_dup_u8(tmp, 0);
3933 break;
3934 case 1:
3935 tmp = gen_ld16u(addr, IS_USER(s));
3936 gen_neon_dup_low16(tmp);
3937 break;
3938 case 2:
3939 tmp = gen_ld32(addr, IS_USER(s));
3940 break;
3941 case 3:
3942 return 1;
3943 default: /* Avoid compiler warnings. */
3944 abort();
3945 }
3946 tcg_gen_addi_i32(addr, addr, 1 << size);
3947 tmp2 = new_tmp();
3948 tcg_gen_mov_i32(tmp2, tmp);
3949 neon_store_reg(rd, 0, tmp2);
3950 neon_store_reg(rd, 1, tmp);
3951 rd += stride;
3952 }
3953 stride = (1 << size) * nregs;
3954 } else {
3955 /* Single element. */
3956 pass = (insn >> 7) & 1;
3957 switch (size) {
3958 case 0:
3959 shift = ((insn >> 5) & 3) * 8;
3960 stride = 1;
3961 break;
3962 case 1:
3963 shift = ((insn >> 6) & 1) * 16;
3964 stride = (insn & (1 << 5)) ? 2 : 1;
3965 break;
3966 case 2:
3967 shift = 0;
3968 stride = (insn & (1 << 6)) ? 2 : 1;
3969 break;
3970 default:
3971 abort();
3972 }
3973 nregs = ((insn >> 8) & 3) + 1;
3974 load_reg_var(s, addr, rn);
3975 for (reg = 0; reg < nregs; reg++) {
3976 if (load) {
3977 switch (size) {
3978 case 0:
3979 tmp = gen_ld8u(addr, IS_USER(s));
3980 break;
3981 case 1:
3982 tmp = gen_ld16u(addr, IS_USER(s));
3983 break;
3984 case 2:
3985 tmp = gen_ld32(addr, IS_USER(s));
3986 break;
3987 default: /* Avoid compiler warnings. */
3988 abort();
3989 }
3990 if (size != 2) {
3991 tmp2 = neon_load_reg(rd, pass);
3992 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3993 dead_tmp(tmp2);
3994 }
3995 neon_store_reg(rd, pass, tmp);
3996 } else { /* Store */
3997 tmp = neon_load_reg(rd, pass);
3998 if (shift)
3999 tcg_gen_shri_i32(tmp, tmp, shift);
4000 switch (size) {
4001 case 0:
4002 gen_st8(tmp, addr, IS_USER(s));
4003 break;
4004 case 1:
4005 gen_st16(tmp, addr, IS_USER(s));
4006 break;
4007 case 2:
4008 gen_st32(tmp, addr, IS_USER(s));
4009 break;
4010 }
4011 }
4012 rd += stride;
4013 tcg_gen_addi_i32(addr, addr, 1 << size);
4014 }
4015 stride = nregs * (1 << size);
4016 }
4017 }
4018 dead_tmp(addr);
4019 if (rm != 15) {
4020 TCGv base;
4021
4022 base = load_reg(s, rn);
4023 if (rm == 13) {
4024 tcg_gen_addi_i32(base, base, stride);
4025 } else {
4026 TCGv index;
4027 index = load_reg(s, rm);
4028 tcg_gen_add_i32(base, base, index);
4029 dead_tmp(index);
4030 }
4031 store_reg(s, rn, base);
4032 }
4033 return 0;
4034 }
4035
4036 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4037 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4038 {
4039 tcg_gen_and_i32(t, t, c);
4040 tcg_gen_andc_i32(f, f, c);
4041 tcg_gen_or_i32(dest, t, f);
4042 }
4043
4044 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4045 {
4046 switch (size) {
4047 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4048 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4049 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4050 default: abort();
4051 }
4052 }
4053
4054 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4055 {
4056 switch (size) {
4057 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4058 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4059 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4060 default: abort();
4061 }
4062 }
4063
4064 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4065 {
4066 switch (size) {
4067 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4068 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4069 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4070 default: abort();
4071 }
4072 }
4073
4074 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4075 int q, int u)
4076 {
4077 if (q) {
4078 if (u) {
4079 switch (size) {
4080 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4081 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4082 default: abort();
4083 }
4084 } else {
4085 switch (size) {
4086 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4087 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4088 default: abort();
4089 }
4090 }
4091 } else {
4092 if (u) {
4093 switch (size) {
4094 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4095 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4096 default: abort();
4097 }
4098 } else {
4099 switch (size) {
4100 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4101 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4102 default: abort();
4103 }
4104 }
4105 }
4106 }
4107
4108 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4109 {
4110 if (u) {
4111 switch (size) {
4112 case 0: gen_helper_neon_widen_u8(dest, src); break;
4113 case 1: gen_helper_neon_widen_u16(dest, src); break;
4114 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4115 default: abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 0: gen_helper_neon_widen_s8(dest, src); break;
4120 case 1: gen_helper_neon_widen_s16(dest, src); break;
4121 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4122 default: abort();
4123 }
4124 }
4125 dead_tmp(src);
4126 }
4127
4128 static inline void gen_neon_addl(int size)
4129 {
4130 switch (size) {
4131 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4132 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4133 case 2: tcg_gen_add_i64(CPU_V001); break;
4134 default: abort();
4135 }
4136 }
4137
4138 static inline void gen_neon_subl(int size)
4139 {
4140 switch (size) {
4141 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4142 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4143 case 2: tcg_gen_sub_i64(CPU_V001); break;
4144 default: abort();
4145 }
4146 }
4147
4148 static inline void gen_neon_negl(TCGv_i64 var, int size)
4149 {
4150 switch (size) {
4151 case 0: gen_helper_neon_negl_u16(var, var); break;
4152 case 1: gen_helper_neon_negl_u32(var, var); break;
4153 case 2: gen_helper_neon_negl_u64(var, var); break;
4154 default: abort();
4155 }
4156 }
4157
4158 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4159 {
4160 switch (size) {
4161 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4162 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4163 default: abort();
4164 }
4165 }
4166
4167 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4168 {
4169 TCGv_i64 tmp;
4170
4171 switch ((size << 1) | u) {
4172 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4173 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4174 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4175 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4176 case 4:
4177 tmp = gen_muls_i64_i32(a, b);
4178 tcg_gen_mov_i64(dest, tmp);
4179 break;
4180 case 5:
4181 tmp = gen_mulu_i64_i32(a, b);
4182 tcg_gen_mov_i64(dest, tmp);
4183 break;
4184 default: abort();
4185 }
4186
4187 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4188 Don't forget to clean them now. */
4189 if (size < 2) {
4190 dead_tmp(a);
4191 dead_tmp(b);
4192 }
4193 }
4194
4195 /* Translate a NEON data processing instruction. Return nonzero if the
4196 instruction is invalid.
4197 We process data in a mixture of 32-bit and 64-bit chunks.
4198 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4199
4200 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4201 {
4202 int op;
4203 int q;
4204 int rd, rn, rm;
4205 int size;
4206 int shift;
4207 int pass;
4208 int count;
4209 int pairwise;
4210 int u;
4211 int n;
4212 uint32_t imm, mask;
4213 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4214 TCGv_i64 tmp64;
4215
4216 if (!s->vfp_enabled)
4217 return 1;
4218 q = (insn & (1 << 6)) != 0;
4219 u = (insn >> 24) & 1;
4220 VFP_DREG_D(rd, insn);
4221 VFP_DREG_N(rn, insn);
4222 VFP_DREG_M(rm, insn);
4223 size = (insn >> 20) & 3;
4224 if ((insn & (1 << 23)) == 0) {
4225 /* Three register same length. */
4226 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4227 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4228 || op == 10 || op == 11 || op == 16)) {
4229 /* 64-bit element instructions. */
4230 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4231 neon_load_reg64(cpu_V0, rn + pass);
4232 neon_load_reg64(cpu_V1, rm + pass);
4233 switch (op) {
4234 case 1: /* VQADD */
4235 if (u) {
4236 gen_helper_neon_add_saturate_u64(CPU_V001);
4237 } else {
4238 gen_helper_neon_add_saturate_s64(CPU_V001);
4239 }
4240 break;
4241 case 5: /* VQSUB */
4242 if (u) {
4243 gen_helper_neon_sub_saturate_u64(CPU_V001);
4244 } else {
4245 gen_helper_neon_sub_saturate_s64(CPU_V001);
4246 }
4247 break;
4248 case 8: /* VSHL */
4249 if (u) {
4250 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4251 } else {
4252 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4253 }
4254 break;
4255 case 9: /* VQSHL */
4256 if (u) {
4257 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4258 cpu_V1, cpu_V0);
4259 } else {
4260 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4261 cpu_V1, cpu_V0);
4262 }
4263 break;
4264 case 10: /* VRSHL */
4265 if (u) {
4266 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4267 } else {
4268 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4269 }
4270 break;
4271 case 11: /* VQRSHL */
4272 if (u) {
4273 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4274 cpu_V1, cpu_V0);
4275 } else {
4276 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4277 cpu_V1, cpu_V0);
4278 }
4279 break;
4280 case 16:
4281 if (u) {
4282 tcg_gen_sub_i64(CPU_V001);
4283 } else {
4284 tcg_gen_add_i64(CPU_V001);
4285 }
4286 break;
4287 default:
4288 abort();
4289 }
4290 neon_store_reg64(cpu_V0, rd + pass);
4291 }
4292 return 0;
4293 }
4294 switch (op) {
4295 case 8: /* VSHL */
4296 case 9: /* VQSHL */
4297 case 10: /* VRSHL */
4298 case 11: /* VQRSHL */
4299 {
4300 int rtmp;
4301 /* Shift instruction operands are reversed. */
4302 rtmp = rn;
4303 rn = rm;
4304 rm = rtmp;
4305 pairwise = 0;
4306 }
4307 break;
4308 case 20: /* VPMAX */
4309 case 21: /* VPMIN */
4310 case 23: /* VPADD */
4311 pairwise = 1;
4312 break;
4313 case 26: /* VPADD (float) */
4314 pairwise = (u && size < 2);
4315 break;
4316 case 30: /* VPMIN/VPMAX (float) */
4317 pairwise = u;
4318 break;
4319 default:
4320 pairwise = 0;
4321 break;
4322 }
4323
4324 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4325
4326 if (pairwise) {
4327 /* Pairwise. */
4328 if (q)
4329 n = (pass & 1) * 2;
4330 else
4331 n = 0;
4332 if (pass < q + 1) {
4333 tmp = neon_load_reg(rn, n);
4334 tmp2 = neon_load_reg(rn, n + 1);
4335 } else {
4336 tmp = neon_load_reg(rm, n);
4337 tmp2 = neon_load_reg(rm, n + 1);
4338 }
4339 } else {
4340 /* Elementwise. */
4341 tmp = neon_load_reg(rn, pass);
4342 tmp2 = neon_load_reg(rm, pass);
4343 }
4344 switch (op) {
4345 case 0: /* VHADD */
4346 GEN_NEON_INTEGER_OP(hadd);
4347 break;
4348 case 1: /* VQADD */
4349 GEN_NEON_INTEGER_OP_ENV(qadd);
4350 break;
4351 case 2: /* VRHADD */
4352 GEN_NEON_INTEGER_OP(rhadd);
4353 break;
4354 case 3: /* Logic ops. */
4355 switch ((u << 2) | size) {
4356 case 0: /* VAND */
4357 tcg_gen_and_i32(tmp, tmp, tmp2);
4358 break;
4359 case 1: /* BIC */
4360 tcg_gen_andc_i32(tmp, tmp, tmp2);
4361 break;
4362 case 2: /* VORR */
4363 tcg_gen_or_i32(tmp, tmp, tmp2);
4364 break;
4365 case 3: /* VORN */
4366 tcg_gen_orc_i32(tmp, tmp, tmp2);
4367 break;
4368 case 4: /* VEOR */
4369 tcg_gen_xor_i32(tmp, tmp, tmp2);
4370 break;
4371 case 5: /* VBSL */
4372 tmp3 = neon_load_reg(rd, pass);
4373 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4374 dead_tmp(tmp3);
4375 break;
4376 case 6: /* VBIT */
4377 tmp3 = neon_load_reg(rd, pass);
4378 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4379 dead_tmp(tmp3);
4380 break;
4381 case 7: /* VBIF */
4382 tmp3 = neon_load_reg(rd, pass);
4383 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4384 dead_tmp(tmp3);
4385 break;
4386 }
4387 break;
4388 case 4: /* VHSUB */
4389 GEN_NEON_INTEGER_OP(hsub);
4390 break;
4391 case 5: /* VQSUB */
4392 GEN_NEON_INTEGER_OP_ENV(qsub);
4393 break;
4394 case 6: /* VCGT */
4395 GEN_NEON_INTEGER_OP(cgt);
4396 break;
4397 case 7: /* VCGE */
4398 GEN_NEON_INTEGER_OP(cge);
4399 break;
4400 case 8: /* VSHL */
4401 GEN_NEON_INTEGER_OP(shl);
4402 break;
4403 case 9: /* VQSHL */
4404 GEN_NEON_INTEGER_OP_ENV(qshl);
4405 break;
4406 case 10: /* VRSHL */
4407 GEN_NEON_INTEGER_OP(rshl);
4408 break;
4409 case 11: /* VQRSHL */
4410 GEN_NEON_INTEGER_OP_ENV(qrshl);
4411 break;
4412 case 12: /* VMAX */
4413 GEN_NEON_INTEGER_OP(max);
4414 break;
4415 case 13: /* VMIN */
4416 GEN_NEON_INTEGER_OP(min);
4417 break;
4418 case 14: /* VABD */
4419 GEN_NEON_INTEGER_OP(abd);
4420 break;
4421 case 15: /* VABA */
4422 GEN_NEON_INTEGER_OP(abd);
4423 dead_tmp(tmp2);
4424 tmp2 = neon_load_reg(rd, pass);
4425 gen_neon_add(size, tmp, tmp2);
4426 break;
4427 case 16:
4428 if (!u) { /* VADD */
4429 if (gen_neon_add(size, tmp, tmp2))
4430 return 1;
4431 } else { /* VSUB */
4432 switch (size) {
4433 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4434 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4435 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4436 default: return 1;
4437 }
4438 }
4439 break;
4440 case 17:
4441 if (!u) { /* VTST */
4442 switch (size) {
4443 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4444 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4445 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4446 default: return 1;
4447 }
4448 } else { /* VCEQ */
4449 switch (size) {
4450 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4451 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4452 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4453 default: return 1;
4454 }
4455 }
4456 break;
4457 case 18: /* Multiply. */
4458 switch (size) {
4459 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4460 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4461 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4462 default: return 1;
4463 }
4464 dead_tmp(tmp2);
4465 tmp2 = neon_load_reg(rd, pass);
4466 if (u) { /* VMLS */
4467 gen_neon_rsb(size, tmp, tmp2);
4468 } else { /* VMLA */
4469 gen_neon_add(size, tmp, tmp2);
4470 }
4471 break;
4472 case 19: /* VMUL */
4473 if (u) { /* polynomial */
4474 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4475 } else { /* Integer */
4476 switch (size) {
4477 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4478 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4479 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4480 default: return 1;
4481 }
4482 }
4483 break;
4484 case 20: /* VPMAX */
4485 GEN_NEON_INTEGER_OP(pmax);
4486 break;
4487 case 21: /* VPMIN */
4488 GEN_NEON_INTEGER_OP(pmin);
4489 break;
4490 case 22: /* Hultiply high. */
4491 if (!u) { /* VQDMULH */
4492 switch (size) {
4493 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4494 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4495 default: return 1;
4496 }
4497 } else { /* VQRDHMUL */
4498 switch (size) {
4499 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4500 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4501 default: return 1;
4502 }
4503 }
4504 break;
4505 case 23: /* VPADD */
4506 if (u)
4507 return 1;
4508 switch (size) {
4509 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4510 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4511 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4512 default: return 1;
4513 }
4514 break;
4515 case 26: /* Floating point arithnetic. */
4516 switch ((u << 2) | size) {
4517 case 0: /* VADD */
4518 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4519 break;
4520 case 2: /* VSUB */
4521 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4522 break;
4523 case 4: /* VPADD */
4524 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4525 break;
4526 case 6: /* VABD */
4527 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4528 break;
4529 default:
4530 return 1;
4531 }
4532 break;
4533 case 27: /* Float multiply. */
4534 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4535 if (!u) {
4536 dead_tmp(tmp2);
4537 tmp2 = neon_load_reg(rd, pass);
4538 if (size == 0) {
4539 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4540 } else {
4541 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4542 }
4543 }
4544 break;
4545 case 28: /* Float compare. */
4546 if (!u) {
4547 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4548 } else {
4549 if (size == 0)
4550 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4551 else
4552 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4553 }
4554 break;
4555 case 29: /* Float compare absolute. */
4556 if (!u)
4557 return 1;
4558 if (size == 0)
4559 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4560 else
4561 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4562 break;
4563 case 30: /* Float min/max. */
4564 if (size == 0)
4565 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4566 else
4567 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4568 break;
4569 case 31:
4570 if (size == 0)
4571 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4572 else
4573 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4574 break;
4575 default:
4576 abort();
4577 }
4578 dead_tmp(tmp2);
4579
4580 /* Save the result. For elementwise operations we can put it
4581 straight into the destination register. For pairwise operations
4582 we have to be careful to avoid clobbering the source operands. */
4583 if (pairwise && rd == rm) {
4584 neon_store_scratch(pass, tmp);
4585 } else {
4586 neon_store_reg(rd, pass, tmp);
4587 }
4588
4589 } /* for pass */
4590 if (pairwise && rd == rm) {
4591 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4592 tmp = neon_load_scratch(pass);
4593 neon_store_reg(rd, pass, tmp);
4594 }
4595 }
4596 /* End of 3 register same size operations. */
4597 } else if (insn & (1 << 4)) {
4598 if ((insn & 0x00380080) != 0) {
4599 /* Two registers and shift. */
4600 op = (insn >> 8) & 0xf;
4601 if (insn & (1 << 7)) {
4602 /* 64-bit shift. */
4603 size = 3;
4604 } else {
4605 size = 2;
4606 while ((insn & (1 << (size + 19))) == 0)
4607 size--;
4608 }
4609 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4610 /* To avoid excessive dumplication of ops we implement shift
4611 by immediate using the variable shift operations. */
4612 if (op < 8) {
4613 /* Shift by immediate:
4614 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4615 /* Right shifts are encoded as N - shift, where N is the
4616 element size in bits. */
4617 if (op <= 4)
4618 shift = shift - (1 << (size + 3));
4619 if (size == 3) {
4620 count = q + 1;
4621 } else {
4622 count = q ? 4: 2;
4623 }
4624 switch (size) {
4625 case 0:
4626 imm = (uint8_t) shift;
4627 imm |= imm << 8;
4628 imm |= imm << 16;
4629 break;
4630 case 1:
4631 imm = (uint16_t) shift;
4632 imm |= imm << 16;
4633 break;
4634 case 2:
4635 case 3:
4636 imm = shift;
4637 break;
4638 default:
4639 abort();
4640 }
4641
4642 for (pass = 0; pass < count; pass++) {
4643 if (size == 3) {
4644 neon_load_reg64(cpu_V0, rm + pass);
4645 tcg_gen_movi_i64(cpu_V1, imm);
4646 switch (op) {
4647 case 0: /* VSHR */
4648 case 1: /* VSRA */
4649 if (u)
4650 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4651 else
4652 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4653 break;
4654 case 2: /* VRSHR */
4655 case 3: /* VRSRA */
4656 if (u)
4657 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4658 else
4659 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4660 break;
4661 case 4: /* VSRI */
4662 if (!u)
4663 return 1;
4664 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4665 break;
4666 case 5: /* VSHL, VSLI */
4667 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4668 break;
4669 case 6: /* VQSHLU */
4670 if (u) {
4671 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4672 cpu_V0, cpu_V1);
4673 } else {
4674 return 1;
4675 }
4676 break;
4677 case 7: /* VQSHL */
4678 if (u) {
4679 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4680 cpu_V0, cpu_V1);
4681 } else {
4682 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4683 cpu_V0, cpu_V1);
4684 }
4685 break;
4686 }
4687 if (op == 1 || op == 3) {
4688 /* Accumulate. */
4689 neon_load_reg64(cpu_V0, rd + pass);
4690 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4691 } else if (op == 4 || (op == 5 && u)) {
4692 /* Insert */
4693 cpu_abort(env, "VS[LR]I.64 not implemented");
4694 }
4695 neon_store_reg64(cpu_V0, rd + pass);
4696 } else { /* size < 3 */
4697 /* Operands in T0 and T1. */
4698 tmp = neon_load_reg(rm, pass);
4699 tmp2 = new_tmp();
4700 tcg_gen_movi_i32(tmp2, imm);
4701 switch (op) {
4702 case 0: /* VSHR */
4703 case 1: /* VSRA */
4704 GEN_NEON_INTEGER_OP(shl);
4705 break;
4706 case 2: /* VRSHR */
4707 case 3: /* VRSRA */
4708 GEN_NEON_INTEGER_OP(rshl);
4709 break;
4710 case 4: /* VSRI */
4711 if (!u)
4712 return 1;
4713 GEN_NEON_INTEGER_OP(shl);
4714 break;
4715 case 5: /* VSHL, VSLI */
4716 switch (size) {
4717 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4718 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4719 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4720 default: return 1;
4721 }
4722 break;
4723 case 6: /* VQSHLU */
4724 if (!u) {
4725 return 1;
4726 }
4727 switch (size) {
4728 case 0:
4729 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4730 tmp, tmp2);
4731 break;
4732 case 1:
4733 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4734 tmp, tmp2);
4735 break;
4736 case 2:
4737 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4738 tmp, tmp2);
4739 break;
4740 default:
4741 return 1;
4742 }
4743 break;
4744 case 7: /* VQSHL */
4745 GEN_NEON_INTEGER_OP_ENV(qshl);
4746 break;
4747 }
4748 dead_tmp(tmp2);
4749
4750 if (op == 1 || op == 3) {
4751 /* Accumulate. */
4752 tmp2 = neon_load_reg(rd, pass);
4753 gen_neon_add(size, tmp2, tmp);
4754 dead_tmp(tmp2);
4755 } else if (op == 4 || (op == 5 && u)) {
4756 /* Insert */
4757 switch (size) {
4758 case 0:
4759 if (op == 4)
4760 mask = 0xff >> -shift;
4761 else
4762 mask = (uint8_t)(0xff << shift);
4763 mask |= mask << 8;
4764 mask |= mask << 16;
4765 break;
4766 case 1:
4767 if (op == 4)
4768 mask = 0xffff >> -shift;
4769 else
4770 mask = (uint16_t)(0xffff << shift);
4771 mask |= mask << 16;
4772 break;
4773 case 2:
4774 if (shift < -31 || shift > 31) {
4775 mask = 0;
4776 } else {
4777 if (op == 4)
4778 mask = 0xffffffffu >> -shift;
4779 else
4780 mask = 0xffffffffu << shift;
4781 }
4782 break;
4783 default:
4784 abort();
4785 }
4786 tmp2 = neon_load_reg(rd, pass);
4787 tcg_gen_andi_i32(tmp, tmp, mask);
4788 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
4789 tcg_gen_or_i32(tmp, tmp, tmp2);
4790 dead_tmp(tmp2);
4791 }
4792 neon_store_reg(rd, pass, tmp);
4793 }
4794 } /* for pass */
4795 } else if (op < 10) {
4796 /* Shift by immediate and narrow:
4797 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4798 shift = shift - (1 << (size + 3));
4799 size++;
4800 switch (size) {
4801 case 1:
4802 imm = (uint16_t)shift;
4803 imm |= imm << 16;
4804 tmp2 = tcg_const_i32(imm);
4805 TCGV_UNUSED_I64(tmp64);
4806 break;
4807 case 2:
4808 imm = (uint32_t)shift;
4809 tmp2 = tcg_const_i32(imm);
4810 TCGV_UNUSED_I64(tmp64);
4811 break;
4812 case 3:
4813 tmp64 = tcg_const_i64(shift);
4814 TCGV_UNUSED(tmp2);
4815 break;
4816 default:
4817 abort();
4818 }
4819
4820 for (pass = 0; pass < 2; pass++) {
4821 if (size == 3) {
4822 neon_load_reg64(cpu_V0, rm + pass);
4823 if (q) {
4824 if (u)
4825 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
4826 else
4827 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
4828 } else {
4829 if (u)
4830 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
4831 else
4832 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
4833 }
4834 } else {
4835 tmp = neon_load_reg(rm + pass, 0);
4836 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4837 tmp3 = neon_load_reg(rm + pass, 1);
4838 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4839 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4840 dead_tmp(tmp);
4841 dead_tmp(tmp3);
4842 }
4843 tmp = new_tmp();
4844 if (op == 8 && !u) {
4845 gen_neon_narrow(size - 1, tmp, cpu_V0);
4846 } else {
4847 if (op == 8)
4848 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4849 else
4850 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4851 }
4852 neon_store_reg(rd, pass, tmp);
4853 } /* for pass */
4854 if (size == 3) {
4855 tcg_temp_free_i64(tmp64);
4856 } else {
4857 tcg_temp_free_i32(tmp2);
4858 }
4859 } else if (op == 10) {
4860 /* VSHLL */
4861 if (q || size == 3)
4862 return 1;
4863 tmp = neon_load_reg(rm, 0);
4864 tmp2 = neon_load_reg(rm, 1);
4865 for (pass = 0; pass < 2; pass++) {
4866 if (pass == 1)
4867 tmp = tmp2;
4868
4869 gen_neon_widen(cpu_V0, tmp, size, u);
4870
4871 if (shift != 0) {
4872 /* The shift is less than the width of the source
4873 type, so we can just shift the whole register. */
4874 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4875 if (size < 2 || !u) {
4876 uint64_t imm64;
4877 if (size == 0) {
4878 imm = (0xffu >> (8 - shift));
4879 imm |= imm << 16;
4880 } else {
4881 imm = 0xffff >> (16 - shift);
4882 }
4883 imm64 = imm | (((uint64_t)imm) << 32);
4884 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
4885 }
4886 }
4887 neon_store_reg64(cpu_V0, rd + pass);
4888 }
4889 } else if (op >= 14) {
4890 /* VCVT fixed-point. */
4891 /* We have already masked out the must-be-1 top bit of imm6,
4892 * hence this 32-shift where the ARM ARM has 64-imm6.
4893 */
4894 shift = 32 - shift;
4895 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4896 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4897 if (!(op & 1)) {
4898 if (u)
4899 gen_vfp_ulto(0, shift);
4900 else
4901 gen_vfp_slto(0, shift);
4902 } else {
4903 if (u)
4904 gen_vfp_toul(0, shift);
4905 else
4906 gen_vfp_tosl(0, shift);
4907 }
4908 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
4909 }
4910 } else {
4911 return 1;
4912 }
4913 } else { /* (insn & 0x00380080) == 0 */
4914 int invert;
4915
4916 op = (insn >> 8) & 0xf;
4917 /* One register and immediate. */
4918 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4919 invert = (insn & (1 << 5)) != 0;
4920 switch (op) {
4921 case 0: case 1:
4922 /* no-op */
4923 break;
4924 case 2: case 3:
4925 imm <<= 8;
4926 break;
4927 case 4: case 5:
4928 imm <<= 16;
4929 break;
4930 case 6: case 7:
4931 imm <<= 24;
4932 break;
4933 case 8: case 9:
4934 imm |= imm << 16;
4935 break;
4936 case 10: case 11:
4937 imm = (imm << 8) | (imm << 24);
4938 break;
4939 case 12:
4940 imm = (imm << 8) | 0xff;
4941 break;
4942 case 13:
4943 imm = (imm << 16) | 0xffff;
4944 break;
4945 case 14:
4946 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4947 if (invert)
4948 imm = ~imm;
4949 break;
4950 case 15:
4951 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4952 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4953 break;
4954 }
4955 if (invert)
4956 imm = ~imm;
4957
4958 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4959 if (op & 1 && op < 12) {
4960 tmp = neon_load_reg(rd, pass);
4961 if (invert) {
4962 /* The immediate value has already been inverted, so
4963 BIC becomes AND. */
4964 tcg_gen_andi_i32(tmp, tmp, imm);
4965 } else {
4966 tcg_gen_ori_i32(tmp, tmp, imm);
4967 }
4968 } else {
4969 /* VMOV, VMVN. */
4970 tmp = new_tmp();
4971 if (op == 14 && invert) {
4972 uint32_t val;
4973 val = 0;
4974 for (n = 0; n < 4; n++) {
4975 if (imm & (1 << (n + (pass & 1) * 4)))
4976 val |= 0xff << (n * 8);
4977 }
4978 tcg_gen_movi_i32(tmp, val);
4979 } else {
4980 tcg_gen_movi_i32(tmp, imm);
4981 }
4982 }
4983 neon_store_reg(rd, pass, tmp);
4984 }
4985 }
4986 } else { /* (insn & 0x00800010 == 0x00800000) */
4987 if (size != 3) {
4988 op = (insn >> 8) & 0xf;
4989 if ((insn & (1 << 6)) == 0) {
4990 /* Three registers of different lengths. */
4991 int src1_wide;
4992 int src2_wide;
4993 int prewiden;
4994 /* prewiden, src1_wide, src2_wide */
4995 static const int neon_3reg_wide[16][3] = {
4996 {1, 0, 0}, /* VADDL */
4997 {1, 1, 0}, /* VADDW */
4998 {1, 0, 0}, /* VSUBL */
4999 {1, 1, 0}, /* VSUBW */
5000 {0, 1, 1}, /* VADDHN */
5001 {0, 0, 0}, /* VABAL */
5002 {0, 1, 1}, /* VSUBHN */
5003 {0, 0, 0}, /* VABDL */
5004 {0, 0, 0}, /* VMLAL */
5005 {0, 0, 0}, /* VQDMLAL */
5006 {0, 0, 0}, /* VMLSL */
5007 {0, 0, 0}, /* VQDMLSL */
5008 {0, 0, 0}, /* Integer VMULL */
5009 {0, 0, 0}, /* VQDMULL */
5010 {0, 0, 0} /* Polynomial VMULL */
5011 };
5012
5013 prewiden = neon_3reg_wide[op][0];
5014 src1_wide = neon_3reg_wide[op][1];
5015 src2_wide = neon_3reg_wide[op][2];
5016
5017 if (size == 0 && (op == 9 || op == 11 || op == 13))
5018 return 1;
5019
5020 /* Avoid overlapping operands. Wide source operands are
5021 always aligned so will never overlap with wide
5022 destinations in problematic ways. */
5023 if (rd == rm && !src2_wide) {
5024 tmp = neon_load_reg(rm, 1);
5025 neon_store_scratch(2, tmp);
5026 } else if (rd == rn && !src1_wide) {
5027 tmp = neon_load_reg(rn, 1);
5028 neon_store_scratch(2, tmp);
5029 }
5030 TCGV_UNUSED(tmp3);
5031 for (pass = 0; pass < 2; pass++) {
5032 if (src1_wide) {
5033 neon_load_reg64(cpu_V0, rn + pass);
5034 TCGV_UNUSED(tmp);
5035 } else {
5036 if (pass == 1 && rd == rn) {
5037 tmp = neon_load_scratch(2);
5038 } else {
5039 tmp = neon_load_reg(rn, pass);
5040 }
5041 if (prewiden) {
5042 gen_neon_widen(cpu_V0, tmp, size, u);
5043 }
5044 }
5045 if (src2_wide) {
5046 neon_load_reg64(cpu_V1, rm + pass);
5047 TCGV_UNUSED(tmp2);
5048 } else {
5049 if (pass == 1 && rd == rm) {
5050 tmp2 = neon_load_scratch(2);
5051 } else {
5052 tmp2 = neon_load_reg(rm, pass);
5053 }
5054 if (prewiden) {
5055 gen_neon_widen(cpu_V1, tmp2, size, u);
5056 }
5057 }
5058 switch (op) {
5059 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5060 gen_neon_addl(size);
5061 break;
5062 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5063 gen_neon_subl(size);
5064 break;
5065 case 5: case 7: /* VABAL, VABDL */
5066 switch ((size << 1) | u) {
5067 case 0:
5068 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5069 break;
5070 case 1:
5071 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5072 break;
5073 case 2:
5074 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5075 break;
5076 case 3:
5077 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5078 break;
5079 case 4:
5080 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5081 break;
5082 case 5:
5083 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5084 break;
5085 default: abort();
5086 }
5087 dead_tmp(tmp2);
5088 dead_tmp(tmp);
5089 break;
5090 case 8: case 9: case 10: case 11: case 12: case 13:
5091 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5092 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5093 break;
5094 case 14: /* Polynomial VMULL */
5095 cpu_abort(env, "Polynomial VMULL not implemented");
5096
5097 default: /* 15 is RESERVED. */
5098 return 1;
5099 }
5100 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5101 /* Accumulate. */
5102 if (op == 10 || op == 11) {
5103 gen_neon_negl(cpu_V0, size);
5104 }
5105
5106 if (op != 13) {
5107 neon_load_reg64(cpu_V1, rd + pass);
5108 }
5109
5110 switch (op) {
5111 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
5112 gen_neon_addl(size);
5113 break;
5114 case 9: case 11: /* VQDMLAL, VQDMLSL */
5115 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5116 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5117 break;
5118 /* Fall through. */
5119 case 13: /* VQDMULL */
5120 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5121 break;
5122 default:
5123 abort();
5124 }
5125 neon_store_reg64(cpu_V0, rd + pass);
5126 } else if (op == 4 || op == 6) {
5127 /* Narrowing operation. */
5128 tmp = new_tmp();
5129 if (!u) {
5130 switch (size) {
5131 case 0:
5132 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5133 break;
5134 case 1:
5135 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5136 break;
5137 case 2:
5138 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5139 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5140 break;
5141 default: abort();
5142 }
5143 } else {
5144 switch (size) {
5145 case 0:
5146 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5147 break;
5148 case 1:
5149 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5150 break;
5151 case 2:
5152 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5153 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5154 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5155 break;
5156 default: abort();
5157 }
5158 }
5159 if (pass == 0) {
5160 tmp3 = tmp;
5161 } else {
5162 neon_store_reg(rd, 0, tmp3);
5163 neon_store_reg(rd, 1, tmp);
5164 }
5165 } else {
5166 /* Write back the result. */
5167 neon_store_reg64(cpu_V0, rd + pass);
5168 }
5169 }
5170 } else {
5171 /* Two registers and a scalar. */
5172 switch (op) {
5173 case 0: /* Integer VMLA scalar */
5174 case 1: /* Float VMLA scalar */
5175 case 4: /* Integer VMLS scalar */
5176 case 5: /* Floating point VMLS scalar */
5177 case 8: /* Integer VMUL scalar */
5178 case 9: /* Floating point VMUL scalar */
5179 case 12: /* VQDMULH scalar */
5180 case 13: /* VQRDMULH scalar */
5181 tmp = neon_get_scalar(size, rm);
5182 neon_store_scratch(0, tmp);
5183 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5184 tmp = neon_load_scratch(0);
5185 tmp2 = neon_load_reg(rn, pass);
5186 if (op == 12) {
5187 if (size == 1) {
5188 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5189 } else {
5190 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5191 }
5192 } else if (op == 13) {
5193 if (size == 1) {
5194 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5195 } else {
5196 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5197 }
5198 } else if (op & 1) {
5199 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5200 } else {
5201 switch (size) {
5202 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5203 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5204 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5205 default: return 1;
5206 }
5207 }
5208 dead_tmp(tmp2);
5209 if (op < 8) {
5210 /* Accumulate. */
5211 tmp2 = neon_load_reg(rd, pass);
5212 switch (op) {
5213 case 0:
5214 gen_neon_add(size, tmp, tmp2);
5215 break;
5216 case 1:
5217 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5218 break;
5219 case 4:
5220 gen_neon_rsb(size, tmp, tmp2);
5221 break;
5222 case 5:
5223 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5224 break;
5225 default:
5226 abort();
5227 }
5228 dead_tmp(tmp2);
5229 }
5230 neon_store_reg(rd, pass, tmp);
5231 }
5232 break;
5233 case 2: /* VMLAL sclar */
5234 case 3: /* VQDMLAL scalar */
5235 case 6: /* VMLSL scalar */
5236 case 7: /* VQDMLSL scalar */
5237 case 10: /* VMULL scalar */
5238 case 11: /* VQDMULL scalar */
5239 if (size == 0 && (op == 3 || op == 7 || op == 11))
5240 return 1;
5241
5242 tmp2 = neon_get_scalar(size, rm);
5243 /* We need a copy of tmp2 because gen_neon_mull
5244 * deletes it during pass 0. */
5245 tmp4 = new_tmp();
5246 tcg_gen_mov_i32(tmp4, tmp2);
5247 tmp3 = neon_load_reg(rn, 1);
5248
5249 for (pass = 0; pass < 2; pass++) {
5250 if (pass == 0) {
5251 tmp = neon_load_reg(rn, 0);
5252 } else {
5253 tmp = tmp3;
5254 tmp2 = tmp4;
5255 }
5256 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5257 if (op == 6 || op == 7) {
5258 gen_neon_negl(cpu_V0, size);
5259 }
5260 if (op != 11) {
5261 neon_load_reg64(cpu_V1, rd + pass);
5262 }
5263 switch (op) {
5264 case 2: case 6:
5265 gen_neon_addl(size);
5266 break;
5267 case 3: case 7:
5268 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5269 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5270 break;
5271 case 10:
5272 /* no-op */
5273 break;
5274 case 11:
5275 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5276 break;
5277 default:
5278 abort();
5279 }
5280 neon_store_reg64(cpu_V0, rd + pass);
5281 }
5282
5283
5284 break;
5285 default: /* 14 and 15 are RESERVED */
5286 return 1;
5287 }
5288 }
5289 } else { /* size == 3 */
5290 if (!u) {
5291 /* Extract. */
5292 imm = (insn >> 8) & 0xf;
5293
5294 if (imm > 7 && !q)
5295 return 1;
5296
5297 if (imm == 0) {
5298 neon_load_reg64(cpu_V0, rn);
5299 if (q) {
5300 neon_load_reg64(cpu_V1, rn + 1);
5301 }
5302 } else if (imm == 8) {
5303 neon_load_reg64(cpu_V0, rn + 1);
5304 if (q) {
5305 neon_load_reg64(cpu_V1, rm);
5306 }
5307 } else if (q) {
5308 tmp64 = tcg_temp_new_i64();
5309 if (imm < 8) {
5310 neon_load_reg64(cpu_V0, rn);
5311 neon_load_reg64(tmp64, rn + 1);
5312 } else {
5313 neon_load_reg64(cpu_V0, rn + 1);
5314 neon_load_reg64(tmp64, rm);
5315 }
5316 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5317 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5318 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5319 if (imm < 8) {
5320 neon_load_reg64(cpu_V1, rm);
5321 } else {
5322 neon_load_reg64(cpu_V1, rm + 1);
5323 imm -= 8;
5324 }
5325 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5326 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5327 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5328 tcg_temp_free_i64(tmp64);
5329 } else {
5330 /* BUGFIX */
5331 neon_load_reg64(cpu_V0, rn);
5332 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5333 neon_load_reg64(cpu_V1, rm);
5334 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5335 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5336 }
5337 neon_store_reg64(cpu_V0, rd);
5338 if (q) {
5339 neon_store_reg64(cpu_V1, rd + 1);
5340 }
5341 } else if ((insn & (1 << 11)) == 0) {
5342 /* Two register misc. */
5343 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5344 size = (insn >> 18) & 3;
5345 switch (op) {
5346 case 0: /* VREV64 */
5347 if (size == 3)
5348 return 1;
5349 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5350 tmp = neon_load_reg(rm, pass * 2);
5351 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5352 switch (size) {
5353 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5354 case 1: gen_swap_half(tmp); break;
5355 case 2: /* no-op */ break;
5356 default: abort();
5357 }
5358 neon_store_reg(rd, pass * 2 + 1, tmp);
5359 if (size == 2) {
5360 neon_store_reg(rd, pass * 2, tmp2);
5361 } else {
5362 switch (size) {
5363 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5364 case 1: gen_swap_half(tmp2); break;
5365 default: abort();
5366 }
5367 neon_store_reg(rd, pass * 2, tmp2);
5368 }
5369 }
5370 break;
5371 case 4: case 5: /* VPADDL */
5372 case 12: case 13: /* VPADAL */
5373 if (size == 3)
5374 return 1;
5375 for (pass = 0; pass < q + 1; pass++) {
5376 tmp = neon_load_reg(rm, pass * 2);
5377 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5378 tmp = neon_load_reg(rm, pass * 2 + 1);
5379 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5380 switch (size) {
5381 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5382 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5383 case 2: tcg_gen_add_i64(CPU_V001); break;
5384 default: abort();
5385 }
5386 if (op >= 12) {
5387 /* Accumulate. */
5388 neon_load_reg64(cpu_V1, rd + pass);
5389 gen_neon_addl(size);
5390 }
5391 neon_store_reg64(cpu_V0, rd + pass);
5392 }
5393 break;
5394 case 33: /* VTRN */
5395 if (size == 2) {
5396 for (n = 0; n < (q ? 4 : 2); n += 2) {
5397 tmp = neon_load_reg(rm, n);
5398 tmp2 = neon_load_reg(rd, n + 1);
5399 neon_store_reg(rm, n, tmp2);
5400 neon_store_reg(rd, n + 1, tmp);
5401 }
5402 } else {
5403 goto elementwise;
5404 }
5405 break;
5406 case 34: /* VUZP */
5407 /* Reg Before After
5408 Rd A3 A2 A1 A0 B2 B0 A2 A0
5409 Rm B3 B2 B1 B0 B3 B1 A3 A1
5410 */
5411 if (size == 3)
5412 return 1;
5413 gen_neon_unzip(rd, q, 0, size);
5414 gen_neon_unzip(rm, q, 4, size);
5415 if (q) {
5416 static int unzip_order_q[8] =
5417 {0, 2, 4, 6, 1, 3, 5, 7};
5418 for (n = 0; n < 8; n++) {
5419 int reg = (n < 4) ? rd : rm;
5420 tmp = neon_load_scratch(unzip_order_q[n]);
5421 neon_store_reg(reg, n % 4, tmp);
5422 }
5423 } else {
5424 static int unzip_order[4] =
5425 {0, 4, 1, 5};
5426 for (n = 0; n < 4; n++) {
5427 int reg = (n < 2) ? rd : rm;
5428 tmp = neon_load_scratch(unzip_order[n]);
5429 neon_store_reg(reg, n % 2, tmp);
5430 }
5431 }
5432 break;
5433 case 35: /* VZIP */
5434 /* Reg Before After
5435 Rd A3 A2 A1 A0 B1 A1 B0 A0
5436 Rm B3 B2 B1 B0 B3 A3 B2 A2
5437 */
5438 if (size == 3)
5439 return 1;
5440 count = (q ? 4 : 2);
5441 for (n = 0; n < count; n++) {
5442 tmp = neon_load_reg(rd, n);
5443 tmp2 = neon_load_reg(rd, n);
5444 switch (size) {
5445 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5446 case 1: gen_neon_zip_u16(tmp, tmp2); break;
5447 case 2: /* no-op */; break;
5448 default: abort();
5449 }
5450 neon_store_scratch(n * 2, tmp);
5451 neon_store_scratch(n * 2 + 1, tmp2);
5452 }
5453 for (n = 0; n < count * 2; n++) {
5454 int reg = (n < count) ? rd : rm;
5455 tmp = neon_load_scratch(n);
5456 neon_store_reg(reg, n % count, tmp);
5457 }
5458 break;
5459 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5460 if (size == 3)
5461 return 1;
5462 TCGV_UNUSED(tmp2);
5463 for (pass = 0; pass < 2; pass++) {
5464 neon_load_reg64(cpu_V0, rm + pass);
5465 tmp = new_tmp();
5466 if (op == 36 && q == 0) {
5467 gen_neon_narrow(size, tmp, cpu_V0);
5468 } else if (q) {
5469 gen_neon_narrow_satu(size, tmp, cpu_V0);
5470 } else {
5471 gen_neon_narrow_sats(size, tmp, cpu_V0);
5472 }
5473 if (pass == 0) {
5474 tmp2 = tmp;
5475 } else {
5476 neon_store_reg(rd, 0, tmp2);
5477 neon_store_reg(rd, 1, tmp);
5478 }
5479 }
5480 break;
5481 case 38: /* VSHLL */
5482 if (q || size == 3)
5483 return 1;
5484 tmp = neon_load_reg(rm, 0);
5485 tmp2 = neon_load_reg(rm, 1);
5486 for (pass = 0; pass < 2; pass++) {
5487 if (pass == 1)
5488 tmp = tmp2;
5489 gen_neon_widen(cpu_V0, tmp, size, 1);
5490 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5491 neon_store_reg64(cpu_V0, rd + pass);
5492 }
5493 break;
5494 case 44: /* VCVT.F16.F32 */
5495 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5496 return 1;
5497 tmp = new_tmp();
5498 tmp2 = new_tmp();
5499 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5500 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5501 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5502 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5503 tcg_gen_shli_i32(tmp2, tmp2, 16);
5504 tcg_gen_or_i32(tmp2, tmp2, tmp);
5505 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5506 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5507 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5508 neon_store_reg(rd, 0, tmp2);
5509 tmp2 = new_tmp();
5510 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5511 tcg_gen_shli_i32(tmp2, tmp2, 16);
5512 tcg_gen_or_i32(tmp2, tmp2, tmp);
5513 neon_store_reg(rd, 1, tmp2);
5514 dead_tmp(tmp);
5515 break;
5516 case 46: /* VCVT.F32.F16 */
5517 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5518 return 1;
5519 tmp3 = new_tmp();
5520 tmp = neon_load_reg(rm, 0);
5521 tmp2 = neon_load_reg(rm, 1);
5522 tcg_gen_ext16u_i32(tmp3, tmp);
5523 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5524 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5525 tcg_gen_shri_i32(tmp3, tmp, 16);
5526 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5527 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5528 dead_tmp(tmp);
5529 tcg_gen_ext16u_i32(tmp3, tmp2);
5530 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5531 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5532 tcg_gen_shri_i32(tmp3, tmp2, 16);
5533 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5534 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5535 dead_tmp(tmp2);
5536 dead_tmp(tmp3);
5537 break;
5538 default:
5539 elementwise:
5540 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5541 if (op == 30 || op == 31 || op >= 58) {
5542 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5543 neon_reg_offset(rm, pass));
5544 TCGV_UNUSED(tmp);
5545 } else {
5546 tmp = neon_load_reg(rm, pass);
5547 }
5548 switch (op) {
5549 case 1: /* VREV32 */
5550 switch (size) {
5551 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5552 case 1: gen_swap_half(tmp); break;
5553 default: return 1;
5554 }
5555 break;
5556 case 2: /* VREV16 */
5557 if (size != 0)
5558 return 1;
5559 gen_rev16(tmp);
5560 break;
5561 case 8: /* CLS */
5562 switch (size) {
5563 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5564 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5565 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5566 default: return 1;
5567 }
5568 break;
5569 case 9: /* CLZ */
5570 switch (size) {
5571 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5572 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5573 case 2: gen_helper_clz(tmp, tmp); break;
5574 default: return 1;
5575 }
5576 break;
5577 case 10: /* CNT */
5578 if (size != 0)
5579 return 1;
5580 gen_helper_neon_cnt_u8(tmp, tmp);
5581 break;
5582 case 11: /* VNOT */
5583 if (size != 0)
5584 return 1;
5585 tcg_gen_not_i32(tmp, tmp);
5586 break;
5587 case 14: /* VQABS */
5588 switch (size) {
5589 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5590 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5591 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
5592 default: return 1;
5593 }
5594 break;
5595 case 15: /* VQNEG */
5596 switch (size) {
5597 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5598 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5599 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
5600 default: return 1;
5601 }
5602 break;
5603 case 16: case 19: /* VCGT #0, VCLE #0 */
5604 tmp2 = tcg_const_i32(0);
5605 switch(size) {
5606 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5607 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5608 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5609 default: return 1;
5610 }
5611 tcg_temp_free(tmp2);
5612 if (op == 19)
5613 tcg_gen_not_i32(tmp, tmp);
5614 break;
5615 case 17: case 20: /* VCGE #0, VCLT #0 */
5616 tmp2 = tcg_const_i32(0);
5617 switch(size) {
5618 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5619 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5620 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5621 default: return 1;
5622 }
5623 tcg_temp_free(tmp2);
5624 if (op == 20)
5625 tcg_gen_not_i32(tmp, tmp);
5626 break;
5627 case 18: /* VCEQ #0 */
5628 tmp2 = tcg_const_i32(0);
5629 switch(size) {
5630 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5631 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5632 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5633 default: return 1;
5634 }
5635 tcg_temp_free(tmp2);
5636 break;
5637 case 22: /* VABS */
5638 switch(size) {
5639 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5640 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5641 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5642 default: return 1;
5643 }
5644 break;
5645 case 23: /* VNEG */
5646 if (size == 3)
5647 return 1;
5648 tmp2 = tcg_const_i32(0);
5649 gen_neon_rsb(size, tmp, tmp2);
5650 tcg_temp_free(tmp2);
5651 break;
5652 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5653 tmp2 = tcg_const_i32(0);
5654 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5655 tcg_temp_free(tmp2);
5656 if (op == 27)
5657 tcg_gen_not_i32(tmp, tmp);
5658 break;
5659 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5660 tmp2 = tcg_const_i32(0);
5661 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5662 tcg_temp_free(tmp2);
5663 if (op == 28)
5664 tcg_gen_not_i32(tmp, tmp);
5665 break;
5666 case 26: /* Float VCEQ #0 */
5667 tmp2 = tcg_const_i32(0);
5668 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5669 tcg_temp_free(tmp2);
5670 break;
5671 case 30: /* Float VABS */
5672 gen_vfp_abs(0);
5673 break;
5674 case 31: /* Float VNEG */
5675 gen_vfp_neg(0);
5676 break;
5677 case 32: /* VSWP */
5678 tmp2 = neon_load_reg(rd, pass);
5679 neon_store_reg(rm, pass, tmp2);
5680 break;
5681 case 33: /* VTRN */
5682 tmp2 = neon_load_reg(rd, pass);
5683 switch (size) {
5684 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5685 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5686 case 2: abort();
5687 default: return 1;
5688 }
5689 neon_store_reg(rm, pass, tmp2);
5690 break;
5691 case 56: /* Integer VRECPE */
5692 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5693 break;
5694 case 57: /* Integer VRSQRTE */
5695 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5696 break;
5697 case 58: /* Float VRECPE */
5698 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5699 break;
5700 case 59: /* Float VRSQRTE */
5701 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5702 break;
5703 case 60: /* VCVT.F32.S32 */
5704 gen_vfp_sito(0);
5705 break;
5706 case 61: /* VCVT.F32.U32 */
5707 gen_vfp_uito(0);
5708 break;
5709 case 62: /* VCVT.S32.F32 */
5710 gen_vfp_tosiz(0);
5711 break;
5712 case 63: /* VCVT.U32.F32 */
5713 gen_vfp_touiz(0);
5714 break;
5715 default:
5716 /* Reserved: 21, 29, 39-56 */
5717 return 1;
5718 }
5719 if (op == 30 || op == 31 || op >= 58) {
5720 tcg_gen_st_f32(cpu_F0s, cpu_env,
5721 neon_reg_offset(rd, pass));
5722 } else {
5723 neon_store_reg(rd, pass, tmp);
5724 }
5725 }
5726 break;
5727 }
5728 } else if ((insn & (1 << 10)) == 0) {
5729 /* VTBL, VTBX. */
5730 n = ((insn >> 5) & 0x18) + 8;
5731 if (insn & (1 << 6)) {
5732 tmp = neon_load_reg(rd, 0);
5733 } else {
5734 tmp = new_tmp();
5735 tcg_gen_movi_i32(tmp, 0);
5736 }
5737 tmp2 = neon_load_reg(rm, 0);
5738 tmp4 = tcg_const_i32(rn);
5739 tmp5 = tcg_const_i32(n);
5740 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5741 dead_tmp(tmp);
5742 if (insn & (1 << 6)) {
5743 tmp = neon_load_reg(rd, 1);
5744 } else {
5745 tmp = new_tmp();
5746 tcg_gen_movi_i32(tmp, 0);
5747 }
5748 tmp3 = neon_load_reg(rm, 1);
5749 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5750 tcg_temp_free_i32(tmp5);
5751 tcg_temp_free_i32(tmp4);
5752 neon_store_reg(rd, 0, tmp2);
5753 neon_store_reg(rd, 1, tmp3);
5754 dead_tmp(tmp);
5755 } else if ((insn & 0x380) == 0) {
5756 /* VDUP */
5757 if (insn & (1 << 19)) {
5758 tmp = neon_load_reg(rm, 1);
5759 } else {
5760 tmp = neon_load_reg(rm, 0);
5761 }
5762 if (insn & (1 << 16)) {
5763 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
5764 } else if (insn & (1 << 17)) {
5765 if ((insn >> 18) & 1)
5766 gen_neon_dup_high16(tmp);
5767 else
5768 gen_neon_dup_low16(tmp);
5769 }
5770 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5771 tmp2 = new_tmp();
5772 tcg_gen_mov_i32(tmp2, tmp);
5773 neon_store_reg(rd, pass, tmp2);
5774 }
5775 dead_tmp(tmp);
5776 } else {
5777 return 1;
5778 }
5779 }
5780 }
5781 return 0;
5782 }
5783
5784 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5785 {
5786 int crn = (insn >> 16) & 0xf;
5787 int crm = insn & 0xf;
5788 int op1 = (insn >> 21) & 7;
5789 int op2 = (insn >> 5) & 7;
5790 int rt = (insn >> 12) & 0xf;
5791 TCGv tmp;
5792
5793 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5794 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5795 /* TEECR */
5796 if (IS_USER(s))
5797 return 1;
5798 tmp = load_cpu_field(teecr);
5799 store_reg(s, rt, tmp);
5800 return 0;
5801 }
5802 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5803 /* TEEHBR */
5804 if (IS_USER(s) && (env->teecr & 1))
5805 return 1;
5806 tmp = load_cpu_field(teehbr);
5807 store_reg(s, rt, tmp);
5808 return 0;
5809 }
5810 }
5811 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5812 op1, crn, crm, op2);
5813 return 1;
5814 }
5815
5816 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5817 {
5818 int crn = (insn >> 16) & 0xf;
5819 int crm = insn & 0xf;
5820 int op1 = (insn >> 21) & 7;
5821 int op2 = (insn >> 5) & 7;
5822 int rt = (insn >> 12) & 0xf;
5823 TCGv tmp;
5824
5825 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5826 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5827 /* TEECR */
5828 if (IS_USER(s))
5829 return 1;
5830 tmp = load_reg(s, rt);
5831 gen_helper_set_teecr(cpu_env, tmp);
5832 dead_tmp(tmp);
5833 return 0;
5834 }
5835 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5836 /* TEEHBR */
5837 if (IS_USER(s) && (env->teecr & 1))
5838 return 1;
5839 tmp = load_reg(s, rt);
5840 store_cpu_field(tmp, teehbr);
5841 return 0;
5842 }
5843 }
5844 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5845 op1, crn, crm, op2);
5846 return 1;
5847 }
5848
5849 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5850 {
5851 int cpnum;
5852
5853 cpnum = (insn >> 8) & 0xf;
5854 if (arm_feature(env, ARM_FEATURE_XSCALE)
5855 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5856 return 1;
5857
5858 switch (cpnum) {
5859 case 0:
5860 case 1:
5861 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5862 return disas_iwmmxt_insn(env, s, insn);
5863 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5864 return disas_dsp_insn(env, s, insn);
5865 }
5866 return 1;
5867 case 10:
5868 case 11:
5869 return disas_vfp_insn (env, s, insn);
5870 case 14:
5871 /* Coprocessors 7-15 are architecturally reserved by ARM.
5872 Unfortunately Intel decided to ignore this. */
5873 if (arm_feature(env, ARM_FEATURE_XSCALE))
5874 goto board;
5875 if (insn & (1 << 20))
5876 return disas_cp14_read(env, s, insn);
5877 else
5878 return disas_cp14_write(env, s, insn);
5879 case 15:
5880 return disas_cp15_insn (env, s, insn);
5881 default:
5882 board:
5883 /* Unknown coprocessor. See if the board has hooked it. */
5884 return disas_cp_insn (env, s, insn);
5885 }
5886 }
5887
5888
5889 /* Store a 64-bit value to a register pair. Clobbers val. */
5890 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5891 {
5892 TCGv tmp;
5893 tmp = new_tmp();
5894 tcg_gen_trunc_i64_i32(tmp, val);
5895 store_reg(s, rlow, tmp);
5896 tmp = new_tmp();
5897 tcg_gen_shri_i64(val, val, 32);
5898 tcg_gen_trunc_i64_i32(tmp, val);
5899 store_reg(s, rhigh, tmp);
5900 }
5901
5902 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5903 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5904 {
5905 TCGv_i64 tmp;
5906 TCGv tmp2;
5907
5908 /* Load value and extend to 64 bits. */
5909 tmp = tcg_temp_new_i64();
5910 tmp2 = load_reg(s, rlow);
5911 tcg_gen_extu_i32_i64(tmp, tmp2);
5912 dead_tmp(tmp2);
5913 tcg_gen_add_i64(val, val, tmp);
5914 tcg_temp_free_i64(tmp);
5915 }
5916
5917 /* load and add a 64-bit value from a register pair. */
5918 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5919 {
5920 TCGv_i64 tmp;
5921 TCGv tmpl;
5922 TCGv tmph;
5923
5924 /* Load 64-bit value rd:rn. */
5925 tmpl = load_reg(s, rlow);
5926 tmph = load_reg(s, rhigh);
5927 tmp = tcg_temp_new_i64();
5928 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5929 dead_tmp(tmpl);
5930 dead_tmp(tmph);
5931 tcg_gen_add_i64(val, val, tmp);
5932 tcg_temp_free_i64(tmp);
5933 }
5934
5935 /* Set N and Z flags from a 64-bit value. */
5936 static void gen_logicq_cc(TCGv_i64 val)
5937 {
5938 TCGv tmp = new_tmp();
5939 gen_helper_logicq_cc(tmp, val);
5940 gen_logic_CC(tmp);
5941 dead_tmp(tmp);
5942 }
5943
5944 /* Load/Store exclusive instructions are implemented by remembering
5945 the value/address loaded, and seeing if these are the same
5946 when the store is performed. This should be is sufficient to implement
5947 the architecturally mandated semantics, and avoids having to monitor
5948 regular stores.
5949
5950 In system emulation mode only one CPU will be running at once, so
5951 this sequence is effectively atomic. In user emulation mode we
5952 throw an exception and handle the atomic operation elsewhere. */
5953 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5954 TCGv addr, int size)
5955 {
5956 TCGv tmp;
5957
5958 switch (size) {
5959 case 0:
5960 tmp = gen_ld8u(addr, IS_USER(s));
5961 break;
5962 case 1:
5963 tmp = gen_ld16u(addr, IS_USER(s));
5964 break;
5965 case 2:
5966 case 3:
5967 tmp = gen_ld32(addr, IS_USER(s));
5968 break;
5969 default:
5970 abort();
5971 }
5972 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5973 store_reg(s, rt, tmp);
5974 if (size == 3) {
5975 TCGv tmp2 = new_tmp();
5976 tcg_gen_addi_i32(tmp2, addr, 4);
5977 tmp = gen_ld32(tmp2, IS_USER(s));
5978 dead_tmp(tmp2);
5979 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5980 store_reg(s, rt2, tmp);
5981 }
5982 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5983 }
5984
5985 static void gen_clrex(DisasContext *s)
5986 {
5987 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5988 }
5989
5990 #ifdef CONFIG_USER_ONLY
5991 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5992 TCGv addr, int size)
5993 {
5994 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5995 tcg_gen_movi_i32(cpu_exclusive_info,
5996 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5997 gen_exception_insn(s, 4, EXCP_STREX);
5998 }
5999 #else
6000 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6001 TCGv addr, int size)
6002 {
6003 TCGv tmp;
6004 int done_label;
6005 int fail_label;
6006
6007 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6008 [addr] = {Rt};
6009 {Rd} = 0;
6010 } else {
6011 {Rd} = 1;
6012 } */
6013 fail_label = gen_new_label();
6014 done_label = gen_new_label();
6015 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6016 switch (size) {
6017 case 0:
6018 tmp = gen_ld8u(addr, IS_USER(s));
6019 break;
6020 case 1:
6021 tmp = gen_ld16u(addr, IS_USER(s));
6022 break;
6023 case 2:
6024 case 3:
6025 tmp = gen_ld32(addr, IS_USER(s));
6026 break;
6027 default:
6028 abort();
6029 }
6030 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6031 dead_tmp(tmp);
6032 if (size == 3) {
6033 TCGv tmp2 = new_tmp();
6034 tcg_gen_addi_i32(tmp2, addr, 4);
6035 tmp = gen_ld32(tmp2, IS_USER(s));
6036 dead_tmp(tmp2);
6037 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6038 dead_tmp(tmp);
6039 }
6040 tmp = load_reg(s, rt);
6041 switch (size) {
6042 case 0:
6043 gen_st8(tmp, addr, IS_USER(s));
6044 break;
6045 case 1:
6046 gen_st16(tmp, addr, IS_USER(s));
6047 break;
6048 case 2:
6049 case 3:
6050 gen_st32(tmp, addr, IS_USER(s));
6051 break;
6052 default:
6053 abort();
6054 }
6055 if (size == 3) {
6056 tcg_gen_addi_i32(addr, addr, 4);
6057 tmp = load_reg(s, rt2);
6058 gen_st32(tmp, addr, IS_USER(s));
6059 }
6060 tcg_gen_movi_i32(cpu_R[rd], 0);
6061 tcg_gen_br(done_label);
6062 gen_set_label(fail_label);
6063 tcg_gen_movi_i32(cpu_R[rd], 1);
6064 gen_set_label(done_label);
6065 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6066 }
6067 #endif
6068
6069 static void disas_arm_insn(CPUState * env, DisasContext *s)
6070 {
6071 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6072 TCGv tmp;
6073 TCGv tmp2;
6074 TCGv tmp3;
6075 TCGv addr;
6076 TCGv_i64 tmp64;
6077
6078 insn = ldl_code(s->pc);
6079 s->pc += 4;
6080
6081 /* M variants do not implement ARM mode. */
6082 if (IS_M(env))
6083 goto illegal_op;
6084 cond = insn >> 28;
6085 if (cond == 0xf){
6086 /* Unconditional instructions. */
6087 if (((insn >> 25) & 7) == 1) {
6088 /* NEON Data processing. */
6089 if (!arm_feature(env, ARM_FEATURE_NEON))
6090 goto illegal_op;
6091
6092 if (disas_neon_data_insn(env, s, insn))
6093 goto illegal_op;
6094 return;
6095 }
6096 if ((insn & 0x0f100000) == 0x04000000) {
6097 /* NEON load/store. */
6098 if (!arm_feature(env, ARM_FEATURE_NEON))
6099 goto illegal_op;
6100
6101 if (disas_neon_ls_insn(env, s, insn))
6102 goto illegal_op;
6103 return;
6104 }
6105 if ((insn & 0x0d70f000) == 0x0550f000)
6106 return; /* PLD */
6107 else if ((insn & 0x0ffffdff) == 0x01010000) {
6108 ARCH(6);
6109 /* setend */
6110 if (insn & (1 << 9)) {
6111 /* BE8 mode not implemented. */
6112 goto illegal_op;
6113 }
6114 return;
6115 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6116 switch ((insn >> 4) & 0xf) {
6117 case 1: /* clrex */
6118 ARCH(6K);
6119 gen_clrex(s);
6120 return;
6121 case 4: /* dsb */
6122 case 5: /* dmb */
6123 case 6: /* isb */
6124 ARCH(7);
6125 /* We don't emulate caches so these are a no-op. */
6126 return;
6127 default:
6128 goto illegal_op;
6129 }
6130 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6131 /* srs */
6132 int32_t offset;
6133 if (IS_USER(s))
6134 goto illegal_op;
6135 ARCH(6);
6136 op1 = (insn & 0x1f);
6137 addr = new_tmp();
6138 tmp = tcg_const_i32(op1);
6139 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6140 tcg_temp_free_i32(tmp);
6141 i = (insn >> 23) & 3;
6142 switch (i) {
6143 case 0: offset = -4; break; /* DA */
6144 case 1: offset = 0; break; /* IA */
6145 case 2: offset = -8; break; /* DB */
6146 case 3: offset = 4; break; /* IB */
6147 default: abort();
6148 }
6149 if (offset)
6150 tcg_gen_addi_i32(addr, addr, offset);
6151 tmp = load_reg(s, 14);
6152 gen_st32(tmp, addr, 0);
6153 tmp = load_cpu_field(spsr);
6154 tcg_gen_addi_i32(addr, addr, 4);
6155 gen_st32(tmp, addr, 0);
6156 if (insn & (1 << 21)) {
6157 /* Base writeback. */
6158 switch (i) {
6159 case 0: offset = -8; break;
6160 case 1: offset = 4; break;
6161 case 2: offset = -4; break;
6162 case 3: offset = 0; break;
6163 default: abort();
6164 }
6165 if (offset)
6166 tcg_gen_addi_i32(addr, addr, offset);
6167 tmp = tcg_const_i32(op1);
6168 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6169 tcg_temp_free_i32(tmp);
6170 dead_tmp(addr);
6171 } else {
6172 dead_tmp(addr);
6173 }
6174 return;
6175 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6176 /* rfe */
6177 int32_t offset;
6178 if (IS_USER(s))
6179 goto illegal_op;
6180 ARCH(6);
6181 rn = (insn >> 16) & 0xf;
6182 addr = load_reg(s, rn);
6183 i = (insn >> 23) & 3;
6184 switch (i) {
6185 case 0: offset = -4; break; /* DA */
6186 case 1: offset = 0; break; /* IA */
6187 case 2: offset = -8; break; /* DB */
6188 case 3: offset = 4; break; /* IB */
6189 default: abort();
6190 }
6191 if (offset)
6192 tcg_gen_addi_i32(addr, addr, offset);
6193 /* Load PC into tmp and CPSR into tmp2. */
6194 tmp = gen_ld32(addr, 0);
6195 tcg_gen_addi_i32(addr, addr, 4);
6196 tmp2 = gen_ld32(addr, 0);
6197 if (insn & (1 << 21)) {
6198 /* Base writeback. */
6199 switch (i) {
6200 case 0: offset = -8; break;
6201 case 1: offset = 4; break;
6202 case 2: offset = -4; break;
6203 case 3: offset = 0; break;
6204 default: abort();
6205 }
6206 if (offset)
6207 tcg_gen_addi_i32(addr, addr, offset);
6208 store_reg(s, rn, addr);
6209 } else {
6210 dead_tmp(addr);
6211 }
6212 gen_rfe(s, tmp, tmp2);
6213 return;
6214 } else if ((insn & 0x0e000000) == 0x0a000000) {
6215 /* branch link and change to thumb (blx <offset>) */
6216 int32_t offset;
6217
6218 val = (uint32_t)s->pc;
6219 tmp = new_tmp();
6220 tcg_gen_movi_i32(tmp, val);
6221 store_reg(s, 14, tmp);
6222 /* Sign-extend the 24-bit offset */
6223 offset = (((int32_t)insn) << 8) >> 8;
6224 /* offset * 4 + bit24 * 2 + (thumb bit) */
6225 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6226 /* pipeline offset */
6227 val += 4;
6228 gen_bx_im(s, val);
6229 return;
6230 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6231 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6232 /* iWMMXt register transfer. */
6233 if (env->cp15.c15_cpar & (1 << 1))
6234 if (!disas_iwmmxt_insn(env, s, insn))
6235 return;
6236 }
6237 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6238 /* Coprocessor double register transfer. */
6239 } else if ((insn & 0x0f000010) == 0x0e000010) {
6240 /* Additional coprocessor register transfer. */
6241 } else if ((insn & 0x0ff10020) == 0x01000000) {
6242 uint32_t mask;
6243 uint32_t val;
6244 /* cps (privileged) */
6245 if (IS_USER(s))
6246 return;
6247 mask = val = 0;
6248 if (insn & (1 << 19)) {
6249 if (insn & (1 << 8))
6250 mask |= CPSR_A;
6251 if (insn & (1 << 7))
6252 mask |= CPSR_I;
6253 if (insn & (1 << 6))
6254 mask |= CPSR_F;
6255 if (insn & (1 << 18))
6256 val |= mask;
6257 }
6258 if (insn & (1 << 17)) {
6259 mask |= CPSR_M;
6260 val |= (insn & 0x1f);
6261 }
6262 if (mask) {
6263 gen_set_psr_im(s, mask, 0, val);
6264 }
6265 return;
6266 }
6267 goto illegal_op;
6268 }
6269 if (cond != 0xe) {
6270 /* if not always execute, we generate a conditional jump to
6271 next instruction */
6272 s->condlabel = gen_new_label();
6273 gen_test_cc(cond ^ 1, s->condlabel);
6274 s->condjmp = 1;
6275 }
6276 if ((insn & 0x0f900000) == 0x03000000) {
6277 if ((insn & (1 << 21)) == 0) {
6278 ARCH(6T2);
6279 rd = (insn >> 12) & 0xf;
6280 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6281 if ((insn & (1 << 22)) == 0) {
6282 /* MOVW */
6283 tmp = new_tmp();
6284 tcg_gen_movi_i32(tmp, val);
6285 } else {
6286 /* MOVT */
6287 tmp = load_reg(s, rd);
6288 tcg_gen_ext16u_i32(tmp, tmp);
6289 tcg_gen_ori_i32(tmp, tmp, val << 16);
6290 }
6291 store_reg(s, rd, tmp);
6292 } else {
6293 if (((insn >> 12) & 0xf) != 0xf)
6294 goto illegal_op;
6295 if (((insn >> 16) & 0xf) == 0) {
6296 gen_nop_hint(s, insn & 0xff);
6297 } else {
6298 /* CPSR = immediate */
6299 val = insn & 0xff;
6300 shift = ((insn >> 8) & 0xf) * 2;
6301 if (shift)
6302 val = (val >> shift) | (val << (32 - shift));
6303 i = ((insn & (1 << 22)) != 0);
6304 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6305 goto illegal_op;
6306 }
6307 }
6308 } else if ((insn & 0x0f900000) == 0x01000000
6309 && (insn & 0x00000090) != 0x00000090) {
6310 /* miscellaneous instructions */
6311 op1 = (insn >> 21) & 3;
6312 sh = (insn >> 4) & 0xf;
6313 rm = insn & 0xf;
6314 switch (sh) {
6315 case 0x0: /* move program status register */
6316 if (op1 & 1) {
6317 /* PSR = reg */
6318 tmp = load_reg(s, rm);
6319 i = ((op1 & 2) != 0);
6320 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6321 goto illegal_op;
6322 } else {
6323 /* reg = PSR */
6324 rd = (insn >> 12) & 0xf;
6325 if (op1 & 2) {
6326 if (IS_USER(s))
6327 goto illegal_op;
6328 tmp = load_cpu_field(spsr);
6329 } else {
6330 tmp = new_tmp();
6331 gen_helper_cpsr_read(tmp);
6332 }
6333 store_reg(s, rd, tmp);
6334 }
6335 break;
6336 case 0x1:
6337 if (op1 == 1) {
6338 /* branch/exchange thumb (bx). */
6339 tmp = load_reg(s, rm);
6340 gen_bx(s, tmp);
6341 } else if (op1 == 3) {
6342 /* clz */
6343 rd = (insn >> 12) & 0xf;
6344 tmp = load_reg(s, rm);
6345 gen_helper_clz(tmp, tmp);
6346 store_reg(s, rd, tmp);
6347 } else {
6348 goto illegal_op;
6349 }
6350 break;
6351 case 0x2:
6352 if (op1 == 1) {
6353 ARCH(5J); /* bxj */
6354 /* Trivial implementation equivalent to bx. */
6355 tmp = load_reg(s, rm);
6356 gen_bx(s, tmp);
6357 } else {
6358 goto illegal_op;
6359 }
6360 break;
6361 case 0x3:
6362 if (op1 != 1)
6363 goto illegal_op;
6364
6365 /* branch link/exchange thumb (blx) */
6366 tmp = load_reg(s, rm);
6367 tmp2 = new_tmp();
6368 tcg_gen_movi_i32(tmp2, s->pc);
6369 store_reg(s, 14, tmp2);
6370 gen_bx(s, tmp);
6371 break;
6372 case 0x5: /* saturating add/subtract */
6373 rd = (insn >> 12) & 0xf;
6374 rn = (insn >> 16) & 0xf;
6375 tmp = load_reg(s, rm);
6376 tmp2 = load_reg(s, rn);
6377 if (op1 & 2)
6378 gen_helper_double_saturate(tmp2, tmp2);
6379 if (op1 & 1)
6380 gen_helper_sub_saturate(tmp, tmp, tmp2);
6381 else
6382 gen_helper_add_saturate(tmp, tmp, tmp2);
6383 dead_tmp(tmp2);
6384 store_reg(s, rd, tmp);
6385 break;
6386 case 7:
6387 /* SMC instruction (op1 == 3)
6388 and undefined instructions (op1 == 0 || op1 == 2)
6389 will trap */
6390 if (op1 != 1) {
6391 goto illegal_op;
6392 }
6393 /* bkpt */
6394 gen_exception_insn(s, 4, EXCP_BKPT);
6395 break;
6396 case 0x8: /* signed multiply */
6397 case 0xa:
6398 case 0xc:
6399 case 0xe:
6400 rs = (insn >> 8) & 0xf;
6401 rn = (insn >> 12) & 0xf;
6402 rd = (insn >> 16) & 0xf;
6403 if (op1 == 1) {
6404 /* (32 * 16) >> 16 */
6405 tmp = load_reg(s, rm);
6406 tmp2 = load_reg(s, rs);
6407 if (sh & 4)
6408 tcg_gen_sari_i32(tmp2, tmp2, 16);
6409 else
6410 gen_sxth(tmp2);
6411 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6412 tcg_gen_shri_i64(tmp64, tmp64, 16);
6413 tmp = new_tmp();
6414 tcg_gen_trunc_i64_i32(tmp, tmp64);
6415 tcg_temp_free_i64(tmp64);
6416 if ((sh & 2) == 0) {
6417 tmp2 = load_reg(s, rn);
6418 gen_helper_add_setq(tmp, tmp, tmp2);
6419 dead_tmp(tmp2);
6420 }
6421 store_reg(s, rd, tmp);
6422 } else {
6423 /* 16 * 16 */
6424 tmp = load_reg(s, rm);
6425 tmp2 = load_reg(s, rs);
6426 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6427 dead_tmp(tmp2);
6428 if (op1 == 2) {
6429 tmp64 = tcg_temp_new_i64();
6430 tcg_gen_ext_i32_i64(tmp64, tmp);
6431 dead_tmp(tmp);
6432 gen_addq(s, tmp64, rn, rd);
6433 gen_storeq_reg(s, rn, rd, tmp64);
6434 tcg_temp_free_i64(tmp64);
6435 } else {
6436 if (op1 == 0) {
6437 tmp2 = load_reg(s, rn);
6438 gen_helper_add_setq(tmp, tmp, tmp2);
6439 dead_tmp(tmp2);
6440 }
6441 store_reg(s, rd, tmp);
6442 }
6443 }
6444 break;
6445 default:
6446 goto illegal_op;
6447 }
6448 } else if (((insn & 0x0e000000) == 0 &&
6449 (insn & 0x00000090) != 0x90) ||
6450 ((insn & 0x0e000000) == (1 << 25))) {
6451 int set_cc, logic_cc, shiftop;
6452
6453 op1 = (insn >> 21) & 0xf;
6454 set_cc = (insn >> 20) & 1;
6455 logic_cc = table_logic_cc[op1] & set_cc;
6456
6457 /* data processing instruction */
6458 if (insn & (1 << 25)) {
6459 /* immediate operand */
6460 val = insn & 0xff;
6461 shift = ((insn >> 8) & 0xf) * 2;
6462 if (shift) {
6463 val = (val >> shift) | (val << (32 - shift));
6464 }
6465 tmp2 = new_tmp();
6466 tcg_gen_movi_i32(tmp2, val);
6467 if (logic_cc && shift) {
6468 gen_set_CF_bit31(tmp2);
6469 }
6470 } else {
6471 /* register */
6472 rm = (insn) & 0xf;
6473 tmp2 = load_reg(s, rm);
6474 shiftop = (insn >> 5) & 3;
6475 if (!(insn & (1 << 4))) {
6476 shift = (insn >> 7) & 0x1f;
6477 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6478 } else {
6479 rs = (insn >> 8) & 0xf;
6480 tmp = load_reg(s, rs);
6481 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6482 }
6483 }
6484 if (op1 != 0x0f && op1 != 0x0d) {
6485 rn = (insn >> 16) & 0xf;
6486 tmp = load_reg(s, rn);
6487 } else {
6488 TCGV_UNUSED(tmp);
6489 }
6490 rd = (insn >> 12) & 0xf;
6491 switch(op1) {
6492 case 0x00:
6493 tcg_gen_and_i32(tmp, tmp, tmp2);
6494 if (logic_cc) {
6495 gen_logic_CC(tmp);
6496 }
6497 store_reg_bx(env, s, rd, tmp);
6498 break;
6499 case 0x01:
6500 tcg_gen_xor_i32(tmp, tmp, tmp2);
6501 if (logic_cc) {
6502 gen_logic_CC(tmp);
6503 }
6504 store_reg_bx(env, s, rd, tmp);
6505 break;
6506 case 0x02:
6507 if (set_cc && rd == 15) {
6508 /* SUBS r15, ... is used for exception return. */
6509 if (IS_USER(s)) {
6510 goto illegal_op;
6511 }
6512 gen_helper_sub_cc(tmp, tmp, tmp2);
6513 gen_exception_return(s, tmp);
6514 } else {
6515 if (set_cc) {
6516 gen_helper_sub_cc(tmp, tmp, tmp2);
6517 } else {
6518 tcg_gen_sub_i32(tmp, tmp, tmp2);
6519 }
6520 store_reg_bx(env, s, rd, tmp);
6521 }
6522 break;
6523 case 0x03:
6524 if (set_cc) {
6525 gen_helper_sub_cc(tmp, tmp2, tmp);
6526 } else {
6527 tcg_gen_sub_i32(tmp, tmp2, tmp);
6528 }
6529 store_reg_bx(env, s, rd, tmp);
6530 break;
6531 case 0x04:
6532 if (set_cc) {
6533 gen_helper_add_cc(tmp, tmp, tmp2);
6534 } else {
6535 tcg_gen_add_i32(tmp, tmp, tmp2);
6536 }
6537 store_reg_bx(env, s, rd, tmp);
6538 break;
6539 case 0x05:
6540 if (set_cc) {
6541 gen_helper_adc_cc(tmp, tmp, tmp2);
6542 } else {
6543 gen_add_carry(tmp, tmp, tmp2);
6544 }
6545 store_reg_bx(env, s, rd, tmp);
6546 break;
6547 case 0x06:
6548 if (set_cc) {
6549 gen_helper_sbc_cc(tmp, tmp, tmp2);
6550 } else {
6551 gen_sub_carry(tmp, tmp, tmp2);
6552 }
6553 store_reg_bx(env, s, rd, tmp);
6554 break;
6555 case 0x07:
6556 if (set_cc) {
6557 gen_helper_sbc_cc(tmp, tmp2, tmp);
6558 } else {
6559 gen_sub_carry(tmp, tmp2, tmp);
6560 }
6561 store_reg_bx(env, s, rd, tmp);
6562 break;
6563 case 0x08:
6564 if (set_cc) {
6565 tcg_gen_and_i32(tmp, tmp, tmp2);
6566 gen_logic_CC(tmp);
6567 }
6568 dead_tmp(tmp);
6569 break;
6570 case 0x09:
6571 if (set_cc) {
6572 tcg_gen_xor_i32(tmp, tmp, tmp2);
6573 gen_logic_CC(tmp);
6574 }
6575 dead_tmp(tmp);
6576 break;
6577 case 0x0a:
6578 if (set_cc) {
6579 gen_helper_sub_cc(tmp, tmp, tmp2);
6580 }
6581 dead_tmp(tmp);
6582 break;
6583 case 0x0b:
6584 if (set_cc) {
6585 gen_helper_add_cc(tmp, tmp, tmp2);
6586 }
6587 dead_tmp(tmp);
6588 break;
6589 case 0x0c:
6590 tcg_gen_or_i32(tmp, tmp, tmp2);
6591 if (logic_cc) {
6592 gen_logic_CC(tmp);
6593 }
6594 store_reg_bx(env, s, rd, tmp);
6595 break;
6596 case 0x0d:
6597 if (logic_cc && rd == 15) {
6598 /* MOVS r15, ... is used for exception return. */
6599 if (IS_USER(s)) {
6600 goto illegal_op;
6601 }
6602 gen_exception_return(s, tmp2);
6603 } else {
6604 if (logic_cc) {
6605 gen_logic_CC(tmp2);
6606 }
6607 store_reg_bx(env, s, rd, tmp2);
6608 }
6609 break;
6610 case 0x0e:
6611 tcg_gen_andc_i32(tmp, tmp, tmp2);
6612 if (logic_cc) {
6613 gen_logic_CC(tmp);
6614 }
6615 store_reg_bx(env, s, rd, tmp);
6616 break;
6617 default:
6618 case 0x0f:
6619 tcg_gen_not_i32(tmp2, tmp2);
6620 if (logic_cc) {
6621 gen_logic_CC(tmp2);
6622 }
6623 store_reg_bx(env, s, rd, tmp2);
6624 break;
6625 }
6626 if (op1 != 0x0f && op1 != 0x0d) {
6627 dead_tmp(tmp2);
6628 }
6629 } else {
6630 /* other instructions */
6631 op1 = (insn >> 24) & 0xf;
6632 switch(op1) {
6633 case 0x0:
6634 case 0x1:
6635 /* multiplies, extra load/stores */
6636 sh = (insn >> 5) & 3;
6637 if (sh == 0) {
6638 if (op1 == 0x0) {
6639 rd = (insn >> 16) & 0xf;
6640 rn = (insn >> 12) & 0xf;
6641 rs = (insn >> 8) & 0xf;
6642 rm = (insn) & 0xf;
6643 op1 = (insn >> 20) & 0xf;
6644 switch (op1) {
6645 case 0: case 1: case 2: case 3: case 6:
6646 /* 32 bit mul */
6647 tmp = load_reg(s, rs);
6648 tmp2 = load_reg(s, rm);
6649 tcg_gen_mul_i32(tmp, tmp, tmp2);
6650 dead_tmp(tmp2);
6651 if (insn & (1 << 22)) {
6652 /* Subtract (mls) */
6653 ARCH(6T2);
6654 tmp2 = load_reg(s, rn);
6655 tcg_gen_sub_i32(tmp, tmp2, tmp);
6656 dead_tmp(tmp2);
6657 } else if (insn & (1 << 21)) {
6658 /* Add */
6659 tmp2 = load_reg(s, rn);
6660 tcg_gen_add_i32(tmp, tmp, tmp2);
6661 dead_tmp(tmp2);
6662 }
6663 if (insn & (1 << 20))
6664 gen_logic_CC(tmp);
6665 store_reg(s, rd, tmp);
6666 break;
6667 case 4:
6668 /* 64 bit mul double accumulate (UMAAL) */
6669 ARCH(6);
6670 tmp = load_reg(s, rs);
6671 tmp2 = load_reg(s, rm);
6672 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6673 gen_addq_lo(s, tmp64, rn);
6674 gen_addq_lo(s, tmp64, rd);
6675 gen_storeq_reg(s, rn, rd, tmp64);
6676 tcg_temp_free_i64(tmp64);
6677 break;
6678 case 8: case 9: case 10: case 11:
6679 case 12: case 13: case 14: case 15:
6680 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6681 tmp = load_reg(s, rs);
6682 tmp2 = load_reg(s, rm);
6683 if (insn & (1 << 22)) {
6684 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6685 } else {
6686 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6687 }
6688 if (insn & (1 << 21)) { /* mult accumulate */
6689 gen_addq(s, tmp64, rn, rd);
6690 }
6691 if (insn & (1 << 20)) {
6692 gen_logicq_cc(tmp64);
6693 }
6694 gen_storeq_reg(s, rn, rd, tmp64);
6695 tcg_temp_free_i64(tmp64);
6696 break;
6697 default:
6698 goto illegal_op;
6699 }
6700 } else {
6701 rn = (insn >> 16) & 0xf;
6702 rd = (insn >> 12) & 0xf;
6703 if (insn & (1 << 23)) {
6704 /* load/store exclusive */
6705 op1 = (insn >> 21) & 0x3;
6706 if (op1)
6707 ARCH(6K);
6708 else
6709 ARCH(6);
6710 addr = tcg_temp_local_new_i32();
6711 load_reg_var(s, addr, rn);
6712 if (insn & (1 << 20)) {
6713 switch (op1) {
6714 case 0: /* ldrex */
6715 gen_load_exclusive(s, rd, 15, addr, 2);
6716 break;
6717 case 1: /* ldrexd */
6718 gen_load_exclusive(s, rd, rd + 1, addr, 3);
6719 break;
6720 case 2: /* ldrexb */
6721 gen_load_exclusive(s, rd, 15, addr, 0);
6722 break;
6723 case 3: /* ldrexh */
6724 gen_load_exclusive(s, rd, 15, addr, 1);
6725 break;
6726 default:
6727 abort();
6728 }
6729 } else {
6730 rm = insn & 0xf;
6731 switch (op1) {
6732 case 0: /* strex */
6733 gen_store_exclusive(s, rd, rm, 15, addr, 2);
6734 break;
6735 case 1: /* strexd */
6736 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
6737 break;
6738 case 2: /* strexb */
6739 gen_store_exclusive(s, rd, rm, 15, addr, 0);
6740 break;
6741 case 3: /* strexh */
6742 gen_store_exclusive(s, rd, rm, 15, addr, 1);
6743 break;
6744 default:
6745 abort();
6746 }
6747 }
6748 tcg_temp_free(addr);
6749 } else {
6750 /* SWP instruction */
6751 rm = (insn) & 0xf;
6752
6753 /* ??? This is not really atomic. However we know
6754 we never have multiple CPUs running in parallel,
6755 so it is good enough. */
6756 addr = load_reg(s, rn);
6757 tmp = load_reg(s, rm);
6758 if (insn & (1 << 22)) {
6759 tmp2 = gen_ld8u(addr, IS_USER(s));
6760 gen_st8(tmp, addr, IS_USER(s));
6761 } else {
6762 tmp2 = gen_ld32(addr, IS_USER(s));
6763 gen_st32(tmp, addr, IS_USER(s));
6764 }
6765 dead_tmp(addr);
6766 store_reg(s, rd, tmp2);
6767 }
6768 }
6769 } else {
6770 int address_offset;
6771 int load;
6772 /* Misc load/store */
6773 rn = (insn >> 16) & 0xf;
6774 rd = (insn >> 12) & 0xf;
6775 addr = load_reg(s, rn);
6776 if (insn & (1 << 24))
6777 gen_add_datah_offset(s, insn, 0, addr);
6778 address_offset = 0;
6779 if (insn & (1 << 20)) {
6780 /* load */
6781 switch(sh) {
6782 case 1:
6783 tmp = gen_ld16u(addr, IS_USER(s));
6784 break;
6785 case 2:
6786 tmp = gen_ld8s(addr, IS_USER(s));
6787 break;
6788 default:
6789 case 3:
6790 tmp = gen_ld16s(addr, IS_USER(s));
6791 break;
6792 }
6793 load = 1;
6794 } else if (sh & 2) {
6795 /* doubleword */
6796 if (sh & 1) {
6797 /* store */
6798 tmp = load_reg(s, rd);
6799 gen_st32(tmp, addr, IS_USER(s));
6800 tcg_gen_addi_i32(addr, addr, 4);
6801 tmp = load_reg(s, rd + 1);
6802 gen_st32(tmp, addr, IS_USER(s));
6803 load = 0;
6804 } else {
6805 /* load */
6806 tmp = gen_ld32(addr, IS_USER(s));
6807 store_reg(s, rd, tmp);
6808 tcg_gen_addi_i32(addr, addr, 4);
6809 tmp = gen_ld32(addr, IS_USER(s));
6810 rd++;
6811 load = 1;
6812 }
6813 address_offset = -4;
6814 } else {
6815 /* store */
6816 tmp = load_reg(s, rd);
6817 gen_st16(tmp, addr, IS_USER(s));
6818 load = 0;
6819 }
6820 /* Perform base writeback before the loaded value to
6821 ensure correct behavior with overlapping index registers.
6822 ldrd with base writeback is is undefined if the
6823 destination and index registers overlap. */
6824 if (!(insn & (1 << 24))) {
6825 gen_add_datah_offset(s, insn, address_offset, addr);
6826 store_reg(s, rn, addr);
6827 } else if (insn & (1 << 21)) {
6828 if (address_offset)
6829 tcg_gen_addi_i32(addr, addr, address_offset);
6830 store_reg(s, rn, addr);
6831 } else {
6832 dead_tmp(addr);
6833 }
6834 if (load) {
6835 /* Complete the load. */
6836 store_reg(s, rd, tmp);
6837 }
6838 }
6839 break;
6840 case 0x4:
6841 case 0x5:
6842 goto do_ldst;
6843 case 0x6:
6844 case 0x7:
6845 if (insn & (1 << 4)) {
6846 ARCH(6);
6847 /* Armv6 Media instructions. */
6848 rm = insn & 0xf;
6849 rn = (insn >> 16) & 0xf;
6850 rd = (insn >> 12) & 0xf;
6851 rs = (insn >> 8) & 0xf;
6852 switch ((insn >> 23) & 3) {
6853 case 0: /* Parallel add/subtract. */
6854 op1 = (insn >> 20) & 7;
6855 tmp = load_reg(s, rn);
6856 tmp2 = load_reg(s, rm);
6857 sh = (insn >> 5) & 7;
6858 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6859 goto illegal_op;
6860 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6861 dead_tmp(tmp2);
6862 store_reg(s, rd, tmp);
6863 break;
6864 case 1:
6865 if ((insn & 0x00700020) == 0) {
6866 /* Halfword pack. */
6867 tmp = load_reg(s, rn);
6868 tmp2 = load_reg(s, rm);
6869 shift = (insn >> 7) & 0x1f;
6870 if (insn & (1 << 6)) {
6871 /* pkhtb */
6872 if (shift == 0)
6873 shift = 31;
6874 tcg_gen_sari_i32(tmp2, tmp2, shift);
6875 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6876 tcg_gen_ext16u_i32(tmp2, tmp2);
6877 } else {
6878 /* pkhbt */
6879 if (shift)
6880 tcg_gen_shli_i32(tmp2, tmp2, shift);
6881 tcg_gen_ext16u_i32(tmp, tmp);
6882 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6883 }
6884 tcg_gen_or_i32(tmp, tmp, tmp2);
6885 dead_tmp(tmp2);
6886 store_reg(s, rd, tmp);
6887 } else if ((insn & 0x00200020) == 0x00200000) {
6888 /* [us]sat */
6889 tmp = load_reg(s, rm);
6890 shift = (insn >> 7) & 0x1f;
6891 if (insn & (1 << 6)) {
6892 if (shift == 0)
6893 shift = 31;
6894 tcg_gen_sari_i32(tmp, tmp, shift);
6895 } else {
6896 tcg_gen_shli_i32(tmp, tmp, shift);
6897 }
6898 sh = (insn >> 16) & 0x1f;
6899 tmp2 = tcg_const_i32(sh);
6900 if (insn & (1 << 22))
6901 gen_helper_usat(tmp, tmp, tmp2);
6902 else
6903 gen_helper_ssat(tmp, tmp, tmp2);
6904 tcg_temp_free_i32(tmp2);
6905 store_reg(s, rd, tmp);
6906 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6907 /* [us]sat16 */
6908 tmp = load_reg(s, rm);
6909 sh = (insn >> 16) & 0x1f;
6910 tmp2 = tcg_const_i32(sh);
6911 if (insn & (1 << 22))
6912 gen_helper_usat16(tmp, tmp, tmp2);
6913 else
6914 gen_helper_ssat16(tmp, tmp, tmp2);
6915 tcg_temp_free_i32(tmp2);
6916 store_reg(s, rd, tmp);
6917 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6918 /* Select bytes. */
6919 tmp = load_reg(s, rn);
6920 tmp2 = load_reg(s, rm);
6921 tmp3 = new_tmp();
6922 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6923 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6924 dead_tmp(tmp3);
6925 dead_tmp(tmp2);
6926 store_reg(s, rd, tmp);
6927 } else if ((insn & 0x000003e0) == 0x00000060) {
6928 tmp = load_reg(s, rm);
6929 shift = (insn >> 10) & 3;
6930 /* ??? In many cases it's not neccessary to do a
6931 rotate, a shift is sufficient. */
6932 if (shift != 0)
6933 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
6934 op1 = (insn >> 20) & 7;
6935 switch (op1) {
6936 case 0: gen_sxtb16(tmp); break;
6937 case 2: gen_sxtb(tmp); break;
6938 case 3: gen_sxth(tmp); break;
6939 case 4: gen_uxtb16(tmp); break;
6940 case 6: gen_uxtb(tmp); break;
6941 case 7: gen_uxth(tmp); break;
6942 default: goto illegal_op;
6943 }
6944 if (rn != 15) {
6945 tmp2 = load_reg(s, rn);
6946 if ((op1 & 3) == 0) {
6947 gen_add16(tmp, tmp2);
6948 } else {
6949 tcg_gen_add_i32(tmp, tmp, tmp2);
6950 dead_tmp(tmp2);
6951 }
6952 }
6953 store_reg(s, rd, tmp);
6954 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6955 /* rev */
6956 tmp = load_reg(s, rm);
6957 if (insn & (1 << 22)) {
6958 if (insn & (1 << 7)) {
6959 gen_revsh(tmp);
6960 } else {
6961 ARCH(6T2);
6962 gen_helper_rbit(tmp, tmp);
6963 }
6964 } else {
6965 if (insn & (1 << 7))
6966 gen_rev16(tmp);
6967 else
6968 tcg_gen_bswap32_i32(tmp, tmp);
6969 }
6970 store_reg(s, rd, tmp);
6971 } else {
6972 goto illegal_op;
6973 }
6974 break;
6975 case 2: /* Multiplies (Type 3). */
6976 tmp = load_reg(s, rm);
6977 tmp2 = load_reg(s, rs);
6978 if (insn & (1 << 20)) {
6979 /* Signed multiply most significant [accumulate].
6980 (SMMUL, SMMLA, SMMLS) */
6981 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6982
6983 if (rd != 15) {
6984 tmp = load_reg(s, rd);
6985 if (insn & (1 << 6)) {
6986 tmp64 = gen_subq_msw(tmp64, tmp);
6987 } else {
6988 tmp64 = gen_addq_msw(tmp64, tmp);
6989 }
6990 }
6991 if (insn & (1 << 5)) {
6992 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6993 }
6994 tcg_gen_shri_i64(tmp64, tmp64, 32);
6995 tmp = new_tmp();
6996 tcg_gen_trunc_i64_i32(tmp, tmp64);
6997 tcg_temp_free_i64(tmp64);
6998 store_reg(s, rn, tmp);
6999 } else {
7000 if (insn & (1 << 5))
7001 gen_swap_half(tmp2);
7002 gen_smul_dual(tmp, tmp2);
7003 /* This addition cannot overflow. */
7004 if (insn & (1 << 6)) {
7005 tcg_gen_sub_i32(tmp, tmp, tmp2);
7006 } else {
7007 tcg_gen_add_i32(tmp, tmp, tmp2);
7008 }
7009 dead_tmp(tmp2);
7010 if (insn & (1 << 22)) {
7011 /* smlald, smlsld */
7012 tmp64 = tcg_temp_new_i64();
7013 tcg_gen_ext_i32_i64(tmp64, tmp);
7014 dead_tmp(tmp);
7015 gen_addq(s, tmp64, rd, rn);
7016 gen_storeq_reg(s, rd, rn, tmp64);
7017 tcg_temp_free_i64(tmp64);
7018 } else {
7019 /* smuad, smusd, smlad, smlsd */
7020 if (rd != 15)
7021 {
7022 tmp2 = load_reg(s, rd);
7023 gen_helper_add_setq(tmp, tmp, tmp2);
7024 dead_tmp(tmp2);
7025 }
7026 store_reg(s, rn, tmp);
7027 }
7028 }
7029 break;
7030 case 3:
7031 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7032 switch (op1) {
7033 case 0: /* Unsigned sum of absolute differences. */
7034 ARCH(6);
7035 tmp = load_reg(s, rm);
7036 tmp2 = load_reg(s, rs);
7037 gen_helper_usad8(tmp, tmp, tmp2);
7038 dead_tmp(tmp2);
7039 if (rd != 15) {
7040 tmp2 = load_reg(s, rd);
7041 tcg_gen_add_i32(tmp, tmp, tmp2);
7042 dead_tmp(tmp2);
7043 }
7044 store_reg(s, rn, tmp);
7045 break;
7046 case 0x20: case 0x24: case 0x28: case 0x2c:
7047 /* Bitfield insert/clear. */
7048 ARCH(6T2);
7049 shift = (insn >> 7) & 0x1f;
7050 i = (insn >> 16) & 0x1f;
7051 i = i + 1 - shift;
7052 if (rm == 15) {
7053 tmp = new_tmp();
7054 tcg_gen_movi_i32(tmp, 0);
7055 } else {
7056 tmp = load_reg(s, rm);
7057 }
7058 if (i != 32) {
7059 tmp2 = load_reg(s, rd);
7060 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7061 dead_tmp(tmp2);
7062 }
7063 store_reg(s, rd, tmp);
7064 break;
7065 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7066 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7067 ARCH(6T2);
7068 tmp = load_reg(s, rm);
7069 shift = (insn >> 7) & 0x1f;
7070 i = ((insn >> 16) & 0x1f) + 1;
7071 if (shift + i > 32)
7072 goto illegal_op;
7073 if (i < 32) {
7074 if (op1 & 0x20) {
7075 gen_ubfx(tmp, shift, (1u << i) - 1);
7076 } else {
7077 gen_sbfx(tmp, shift, i);
7078 }
7079 }
7080 store_reg(s, rd, tmp);
7081 break;
7082 default:
7083 goto illegal_op;
7084 }
7085 break;
7086 }
7087 break;
7088 }
7089 do_ldst:
7090 /* Check for undefined extension instructions
7091 * per the ARM Bible IE:
7092 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7093 */
7094 sh = (0xf << 20) | (0xf << 4);
7095 if (op1 == 0x7 && ((insn & sh) == sh))
7096 {
7097 goto illegal_op;
7098 }
7099 /* load/store byte/word */
7100 rn = (insn >> 16) & 0xf;
7101 rd = (insn >> 12) & 0xf;
7102 tmp2 = load_reg(s, rn);
7103 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7104 if (insn & (1 << 24))
7105 gen_add_data_offset(s, insn, tmp2);
7106 if (insn & (1 << 20)) {
7107 /* load */
7108 if (insn & (1 << 22)) {
7109 tmp = gen_ld8u(tmp2, i);
7110 } else {
7111 tmp = gen_ld32(tmp2, i);
7112 }
7113 } else {
7114 /* store */
7115 tmp = load_reg(s, rd);
7116 if (insn & (1 << 22))
7117 gen_st8(tmp, tmp2, i);
7118 else
7119 gen_st32(tmp, tmp2, i);
7120 }
7121 if (!(insn & (1 << 24))) {
7122 gen_add_data_offset(s, insn, tmp2);
7123 store_reg(s, rn, tmp2);
7124 } else if (insn & (1 << 21)) {
7125 store_reg(s, rn, tmp2);
7126 } else {
7127 dead_tmp(tmp2);
7128 }
7129 if (insn & (1 << 20)) {
7130 /* Complete the load. */
7131 if (rd == 15)
7132 gen_bx(s, tmp);
7133 else
7134 store_reg(s, rd, tmp);
7135 }
7136 break;
7137 case 0x08:
7138 case 0x09:
7139 {
7140 int j, n, user, loaded_base;
7141 TCGv loaded_var;
7142 /* load/store multiple words */
7143 /* XXX: store correct base if write back */
7144 user = 0;
7145 if (insn & (1 << 22)) {
7146 if (IS_USER(s))
7147 goto illegal_op; /* only usable in supervisor mode */
7148
7149 if ((insn & (1 << 15)) == 0)
7150 user = 1;
7151 }
7152 rn = (insn >> 16) & 0xf;
7153 addr = load_reg(s, rn);
7154
7155 /* compute total size */
7156 loaded_base = 0;
7157 TCGV_UNUSED(loaded_var);
7158 n = 0;
7159 for(i=0;i<16;i++) {
7160 if (insn & (1 << i))
7161 n++;
7162 }
7163 /* XXX: test invalid n == 0 case ? */
7164 if (insn & (1 << 23)) {
7165 if (insn & (1 << 24)) {
7166 /* pre increment */
7167 tcg_gen_addi_i32(addr, addr, 4);
7168 } else {
7169 /* post increment */
7170 }
7171 } else {
7172 if (insn & (1 << 24)) {
7173 /* pre decrement */
7174 tcg_gen_addi_i32(addr, addr, -(n * 4));
7175 } else {
7176 /* post decrement */
7177 if (n != 1)
7178 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7179 }
7180 }
7181 j = 0;
7182 for(i=0;i<16;i++) {
7183 if (insn & (1 << i)) {
7184 if (insn & (1 << 20)) {
7185 /* load */
7186 tmp = gen_ld32(addr, IS_USER(s));
7187 if (i == 15) {
7188 gen_bx(s, tmp);
7189 } else if (user) {
7190 tmp2 = tcg_const_i32(i);
7191 gen_helper_set_user_reg(tmp2, tmp);
7192 tcg_temp_free_i32(tmp2);
7193 dead_tmp(tmp);
7194 } else if (i == rn) {
7195 loaded_var = tmp;
7196 loaded_base = 1;
7197 } else {
7198 store_reg(s, i, tmp);
7199 }
7200 } else {
7201 /* store */
7202 if (i == 15) {
7203 /* special case: r15 = PC + 8 */
7204 val = (long)s->pc + 4;
7205 tmp = new_tmp();
7206 tcg_gen_movi_i32(tmp, val);
7207 } else if (user) {
7208 tmp = new_tmp();
7209 tmp2 = tcg_const_i32(i);
7210 gen_helper_get_user_reg(tmp, tmp2);
7211 tcg_temp_free_i32(tmp2);
7212 } else {
7213 tmp = load_reg(s, i);
7214 }
7215 gen_st32(tmp, addr, IS_USER(s));
7216 }
7217 j++;
7218 /* no need to add after the last transfer */
7219 if (j != n)
7220 tcg_gen_addi_i32(addr, addr, 4);
7221 }
7222 }
7223 if (insn & (1 << 21)) {
7224 /* write back */
7225 if (insn & (1 << 23)) {
7226 if (insn & (1 << 24)) {
7227 /* pre increment */
7228 } else {
7229 /* post increment */
7230 tcg_gen_addi_i32(addr, addr, 4);
7231 }
7232 } else {
7233 if (insn & (1 << 24)) {
7234 /* pre decrement */
7235 if (n != 1)
7236 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7237 } else {
7238 /* post decrement */
7239 tcg_gen_addi_i32(addr, addr, -(n * 4));
7240 }
7241 }
7242 store_reg(s, rn, addr);
7243 } else {
7244 dead_tmp(addr);
7245 }
7246 if (loaded_base) {
7247 store_reg(s, rn, loaded_var);
7248 }
7249 if ((insn & (1 << 22)) && !user) {
7250 /* Restore CPSR from SPSR. */
7251 tmp = load_cpu_field(spsr);
7252 gen_set_cpsr(tmp, 0xffffffff);
7253 dead_tmp(tmp);
7254 s->is_jmp = DISAS_UPDATE;
7255 }
7256 }
7257 break;
7258 case 0xa:
7259 case 0xb:
7260 {
7261 int32_t offset;
7262
7263 /* branch (and link) */
7264 val = (int32_t)s->pc;
7265 if (insn & (1 << 24)) {
7266 tmp = new_tmp();
7267 tcg_gen_movi_i32(tmp, val);
7268 store_reg(s, 14, tmp);
7269 }
7270 offset = (((int32_t)insn << 8) >> 8);
7271 val += (offset << 2) + 4;
7272 gen_jmp(s, val);
7273 }
7274 break;
7275 case 0xc:
7276 case 0xd:
7277 case 0xe:
7278 /* Coprocessor. */
7279 if (disas_coproc_insn(env, s, insn))
7280 goto illegal_op;
7281 break;
7282 case 0xf:
7283 /* swi */
7284 gen_set_pc_im(s->pc);
7285 s->is_jmp = DISAS_SWI;
7286 break;
7287 default:
7288 illegal_op:
7289 gen_exception_insn(s, 4, EXCP_UDEF);
7290 break;
7291 }
7292 }
7293 }
7294
7295 /* Return true if this is a Thumb-2 logical op. */
7296 static int
7297 thumb2_logic_op(int op)
7298 {
7299 return (op < 8);
7300 }
7301
7302 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7303 then set condition code flags based on the result of the operation.
7304 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7305 to the high bit of T1.
7306 Returns zero if the opcode is valid. */
7307
7308 static int
7309 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7310 {
7311 int logic_cc;
7312
7313 logic_cc = 0;
7314 switch (op) {
7315 case 0: /* and */
7316 tcg_gen_and_i32(t0, t0, t1);
7317 logic_cc = conds;
7318 break;
7319 case 1: /* bic */
7320 tcg_gen_andc_i32(t0, t0, t1);
7321 logic_cc = conds;
7322 break;
7323 case 2: /* orr */
7324 tcg_gen_or_i32(t0, t0, t1);
7325 logic_cc = conds;
7326 break;
7327 case 3: /* orn */
7328 tcg_gen_not_i32(t1, t1);
7329 tcg_gen_or_i32(t0, t0, t1);
7330 logic_cc = conds;
7331 break;
7332 case 4: /* eor */
7333 tcg_gen_xor_i32(t0, t0, t1);
7334 logic_cc = conds;
7335 break;
7336 case 8: /* add */
7337 if (conds)
7338 gen_helper_add_cc(t0, t0, t1);
7339 else
7340 tcg_gen_add_i32(t0, t0, t1);
7341 break;
7342 case 10: /* adc */
7343 if (conds)
7344 gen_helper_adc_cc(t0, t0, t1);
7345 else
7346 gen_adc(t0, t1);
7347 break;
7348 case 11: /* sbc */
7349 if (conds)
7350 gen_helper_sbc_cc(t0, t0, t1);
7351 else
7352 gen_sub_carry(t0, t0, t1);
7353 break;
7354 case 13: /* sub */
7355 if (conds)
7356 gen_helper_sub_cc(t0, t0, t1);
7357 else
7358 tcg_gen_sub_i32(t0, t0, t1);
7359 break;
7360 case 14: /* rsb */
7361 if (conds)
7362 gen_helper_sub_cc(t0, t1, t0);
7363 else
7364 tcg_gen_sub_i32(t0, t1, t0);
7365 break;
7366 default: /* 5, 6, 7, 9, 12, 15. */
7367 return 1;
7368 }
7369 if (logic_cc) {
7370 gen_logic_CC(t0);
7371 if (shifter_out)
7372 gen_set_CF_bit31(t1);
7373 }
7374 return 0;
7375 }
7376
7377 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7378 is not legal. */
7379 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7380 {
7381 uint32_t insn, imm, shift, offset;
7382 uint32_t rd, rn, rm, rs;
7383 TCGv tmp;
7384 TCGv tmp2;
7385 TCGv tmp3;
7386 TCGv addr;
7387 TCGv_i64 tmp64;
7388 int op;
7389 int shiftop;
7390 int conds;
7391 int logic_cc;
7392
7393 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7394 || arm_feature (env, ARM_FEATURE_M))) {
7395 /* Thumb-1 cores may need to treat bl and blx as a pair of
7396 16-bit instructions to get correct prefetch abort behavior. */
7397 insn = insn_hw1;
7398 if ((insn & (1 << 12)) == 0) {
7399 /* Second half of blx. */
7400 offset = ((insn & 0x7ff) << 1);
7401 tmp = load_reg(s, 14);
7402 tcg_gen_addi_i32(tmp, tmp, offset);
7403 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7404
7405 tmp2 = new_tmp();
7406 tcg_gen_movi_i32(tmp2, s->pc | 1);
7407 store_reg(s, 14, tmp2);
7408 gen_bx(s, tmp);
7409 return 0;
7410 }
7411 if (insn & (1 << 11)) {
7412 /* Second half of bl. */
7413 offset = ((insn & 0x7ff) << 1) | 1;
7414 tmp = load_reg(s, 14);
7415 tcg_gen_addi_i32(tmp, tmp, offset);
7416
7417 tmp2 = new_tmp();
7418 tcg_gen_movi_i32(tmp2, s->pc | 1);
7419 store_reg(s, 14, tmp2);
7420 gen_bx(s, tmp);
7421 return 0;
7422 }
7423 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7424 /* Instruction spans a page boundary. Implement it as two
7425 16-bit instructions in case the second half causes an
7426 prefetch abort. */
7427 offset = ((int32_t)insn << 21) >> 9;
7428 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7429 return 0;
7430 }
7431 /* Fall through to 32-bit decode. */
7432 }
7433
7434 insn = lduw_code(s->pc);
7435 s->pc += 2;
7436 insn |= (uint32_t)insn_hw1 << 16;
7437
7438 if ((insn & 0xf800e800) != 0xf000e800) {
7439 ARCH(6T2);
7440 }
7441
7442 rn = (insn >> 16) & 0xf;
7443 rs = (insn >> 12) & 0xf;
7444 rd = (insn >> 8) & 0xf;
7445 rm = insn & 0xf;
7446 switch ((insn >> 25) & 0xf) {
7447 case 0: case 1: case 2: case 3:
7448 /* 16-bit instructions. Should never happen. */
7449 abort();
7450 case 4:
7451 if (insn & (1 << 22)) {
7452 /* Other load/store, table branch. */
7453 if (insn & 0x01200000) {
7454 /* Load/store doubleword. */
7455 if (rn == 15) {
7456 addr = new_tmp();
7457 tcg_gen_movi_i32(addr, s->pc & ~3);
7458 } else {
7459 addr = load_reg(s, rn);
7460 }
7461 offset = (insn & 0xff) * 4;
7462 if ((insn & (1 << 23)) == 0)
7463 offset = -offset;
7464 if (insn & (1 << 24)) {
7465 tcg_gen_addi_i32(addr, addr, offset);
7466 offset = 0;
7467 }
7468 if (insn & (1 << 20)) {
7469 /* ldrd */
7470 tmp = gen_ld32(addr, IS_USER(s));
7471 store_reg(s, rs, tmp);
7472 tcg_gen_addi_i32(addr, addr, 4);
7473 tmp = gen_ld32(addr, IS_USER(s));
7474 store_reg(s, rd, tmp);
7475 } else {
7476 /* strd */
7477 tmp = load_reg(s, rs);
7478 gen_st32(tmp, addr, IS_USER(s));
7479 tcg_gen_addi_i32(addr, addr, 4);
7480 tmp = load_reg(s, rd);
7481 gen_st32(tmp, addr, IS_USER(s));
7482 }
7483 if (insn & (1 << 21)) {
7484 /* Base writeback. */
7485 if (rn == 15)
7486 goto illegal_op;
7487 tcg_gen_addi_i32(addr, addr, offset - 4);
7488 store_reg(s, rn, addr);
7489 } else {
7490 dead_tmp(addr);
7491 }
7492 } else if ((insn & (1 << 23)) == 0) {
7493 /* Load/store exclusive word. */
7494 addr = tcg_temp_local_new();
7495 load_reg_var(s, addr, rn);
7496 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7497 if (insn & (1 << 20)) {
7498 gen_load_exclusive(s, rs, 15, addr, 2);
7499 } else {
7500 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7501 }
7502 tcg_temp_free(addr);
7503 } else if ((insn & (1 << 6)) == 0) {
7504 /* Table Branch. */
7505 if (rn == 15) {
7506 addr = new_tmp();
7507 tcg_gen_movi_i32(addr, s->pc);
7508 } else {
7509 addr = load_reg(s, rn);
7510 }
7511 tmp = load_reg(s, rm);
7512 tcg_gen_add_i32(addr, addr, tmp);
7513 if (insn & (1 << 4)) {
7514 /* tbh */
7515 tcg_gen_add_i32(addr, addr, tmp);
7516 dead_tmp(tmp);
7517 tmp = gen_ld16u(addr, IS_USER(s));
7518 } else { /* tbb */
7519 dead_tmp(tmp);
7520 tmp = gen_ld8u(addr, IS_USER(s));
7521 }
7522 dead_tmp(addr);
7523 tcg_gen_shli_i32(tmp, tmp, 1);
7524 tcg_gen_addi_i32(tmp, tmp, s->pc);
7525 store_reg(s, 15, tmp);
7526 } else {
7527 /* Load/store exclusive byte/halfword/doubleword. */
7528 ARCH(7);
7529 op = (insn >> 4) & 0x3;
7530 if (op == 2) {
7531 goto illegal_op;
7532 }
7533 addr = tcg_temp_local_new();
7534 load_reg_var(s, addr, rn);
7535 if (insn & (1 << 20)) {
7536 gen_load_exclusive(s, rs, rd, addr, op);
7537 } else {
7538 gen_store_exclusive(s, rm, rs, rd, addr, op);
7539 }
7540 tcg_temp_free(addr);
7541 }
7542 } else {
7543 /* Load/store multiple, RFE, SRS. */
7544 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7545 /* Not available in user mode. */
7546 if (IS_USER(s))
7547 goto illegal_op;
7548 if (insn & (1 << 20)) {
7549 /* rfe */
7550 addr = load_reg(s, rn);
7551 if ((insn & (1 << 24)) == 0)
7552 tcg_gen_addi_i32(addr, addr, -8);
7553 /* Load PC into tmp and CPSR into tmp2. */
7554 tmp = gen_ld32(addr, 0);
7555 tcg_gen_addi_i32(addr, addr, 4);
7556 tmp2 = gen_ld32(addr, 0);
7557 if (insn & (1 << 21)) {
7558 /* Base writeback. */
7559 if (insn & (1 << 24)) {
7560 tcg_gen_addi_i32(addr, addr, 4);
7561 } else {
7562 tcg_gen_addi_i32(addr, addr, -4);
7563 }
7564 store_reg(s, rn, addr);
7565 } else {
7566 dead_tmp(addr);
7567 }
7568 gen_rfe(s, tmp, tmp2);
7569 } else {
7570 /* srs */
7571 op = (insn & 0x1f);
7572 addr = new_tmp();
7573 tmp = tcg_const_i32(op);
7574 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7575 tcg_temp_free_i32(tmp);
7576 if ((insn & (1 << 24)) == 0) {
7577 tcg_gen_addi_i32(addr, addr, -8);
7578 }
7579 tmp = load_reg(s, 14);
7580 gen_st32(tmp, addr, 0);
7581 tcg_gen_addi_i32(addr, addr, 4);
7582 tmp = new_tmp();
7583 gen_helper_cpsr_read(tmp);
7584 gen_st32(tmp, addr, 0);
7585 if (insn & (1 << 21)) {
7586 if ((insn & (1 << 24)) == 0) {
7587 tcg_gen_addi_i32(addr, addr, -4);
7588 } else {
7589 tcg_gen_addi_i32(addr, addr, 4);
7590 }
7591 tmp = tcg_const_i32(op);
7592 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7593 tcg_temp_free_i32(tmp);
7594 } else {
7595 dead_tmp(addr);
7596 }
7597 }
7598 } else {
7599 int i;
7600 /* Load/store multiple. */
7601 addr = load_reg(s, rn);
7602 offset = 0;
7603 for (i = 0; i < 16; i++) {
7604 if (insn & (1 << i))
7605 offset += 4;
7606 }
7607 if (insn & (1 << 24)) {
7608 tcg_gen_addi_i32(addr, addr, -offset);
7609 }
7610
7611 for (i = 0; i < 16; i++) {
7612 if ((insn & (1 << i)) == 0)
7613 continue;
7614 if (insn & (1 << 20)) {
7615 /* Load. */
7616 tmp = gen_ld32(addr, IS_USER(s));
7617 if (i == 15) {
7618 gen_bx(s, tmp);
7619 } else {
7620 store_reg(s, i, tmp);
7621 }
7622 } else {
7623 /* Store. */
7624 tmp = load_reg(s, i);
7625 gen_st32(tmp, addr, IS_USER(s));
7626 }
7627 tcg_gen_addi_i32(addr, addr, 4);
7628 }
7629 if (insn & (1 << 21)) {
7630 /* Base register writeback. */
7631 if (insn & (1 << 24)) {
7632 tcg_gen_addi_i32(addr, addr, -offset);
7633 }
7634 /* Fault if writeback register is in register list. */
7635 if (insn & (1 << rn))
7636 goto illegal_op;
7637 store_reg(s, rn, addr);
7638 } else {
7639 dead_tmp(addr);
7640 }
7641 }
7642 }
7643 break;
7644 case 5:
7645
7646 op = (insn >> 21) & 0xf;
7647 if (op == 6) {
7648 /* Halfword pack. */
7649 tmp = load_reg(s, rn);
7650 tmp2 = load_reg(s, rm);
7651 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7652 if (insn & (1 << 5)) {
7653 /* pkhtb */
7654 if (shift == 0)
7655 shift = 31;
7656 tcg_gen_sari_i32(tmp2, tmp2, shift);
7657 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7658 tcg_gen_ext16u_i32(tmp2, tmp2);
7659 } else {
7660 /* pkhbt */
7661 if (shift)
7662 tcg_gen_shli_i32(tmp2, tmp2, shift);
7663 tcg_gen_ext16u_i32(tmp, tmp);
7664 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7665 }
7666 tcg_gen_or_i32(tmp, tmp, tmp2);
7667 dead_tmp(tmp2);
7668 store_reg(s, rd, tmp);
7669 } else {
7670 /* Data processing register constant shift. */
7671 if (rn == 15) {
7672 tmp = new_tmp();
7673 tcg_gen_movi_i32(tmp, 0);
7674 } else {
7675 tmp = load_reg(s, rn);
7676 }
7677 tmp2 = load_reg(s, rm);
7678
7679 shiftop = (insn >> 4) & 3;
7680 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7681 conds = (insn & (1 << 20)) != 0;
7682 logic_cc = (conds && thumb2_logic_op(op));
7683 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7684 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7685 goto illegal_op;
7686 dead_tmp(tmp2);
7687 if (rd != 15) {
7688 store_reg(s, rd, tmp);
7689 } else {
7690 dead_tmp(tmp);
7691 }
7692 }
7693 break;
7694 case 13: /* Misc data processing. */
7695 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7696 if (op < 4 && (insn & 0xf000) != 0xf000)
7697 goto illegal_op;
7698 switch (op) {
7699 case 0: /* Register controlled shift. */
7700 tmp = load_reg(s, rn);
7701 tmp2 = load_reg(s, rm);
7702 if ((insn & 0x70) != 0)
7703 goto illegal_op;
7704 op = (insn >> 21) & 3;
7705 logic_cc = (insn & (1 << 20)) != 0;
7706 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7707 if (logic_cc)
7708 gen_logic_CC(tmp);
7709 store_reg_bx(env, s, rd, tmp);
7710 break;
7711 case 1: /* Sign/zero extend. */
7712 tmp = load_reg(s, rm);
7713 shift = (insn >> 4) & 3;
7714 /* ??? In many cases it's not neccessary to do a
7715 rotate, a shift is sufficient. */
7716 if (shift != 0)
7717 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7718 op = (insn >> 20) & 7;
7719 switch (op) {
7720 case 0: gen_sxth(tmp); break;
7721 case 1: gen_uxth(tmp); break;
7722 case 2: gen_sxtb16(tmp); break;
7723 case 3: gen_uxtb16(tmp); break;
7724 case 4: gen_sxtb(tmp); break;
7725 case 5: gen_uxtb(tmp); break;
7726 default: goto illegal_op;
7727 }
7728 if (rn != 15) {
7729 tmp2 = load_reg(s, rn);
7730 if ((op >> 1) == 1) {
7731 gen_add16(tmp, tmp2);
7732 } else {
7733 tcg_gen_add_i32(tmp, tmp, tmp2);
7734 dead_tmp(tmp2);
7735 }
7736 }
7737 store_reg(s, rd, tmp);
7738 break;
7739 case 2: /* SIMD add/subtract. */
7740 op = (insn >> 20) & 7;
7741 shift = (insn >> 4) & 7;
7742 if ((op & 3) == 3 || (shift & 3) == 3)
7743 goto illegal_op;
7744 tmp = load_reg(s, rn);
7745 tmp2 = load_reg(s, rm);
7746 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7747 dead_tmp(tmp2);
7748 store_reg(s, rd, tmp);
7749 break;
7750 case 3: /* Other data processing. */
7751 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7752 if (op < 4) {
7753 /* Saturating add/subtract. */
7754 tmp = load_reg(s, rn);
7755 tmp2 = load_reg(s, rm);
7756 if (op & 1)
7757 gen_helper_double_saturate(tmp, tmp);
7758 if (op & 2)
7759 gen_helper_sub_saturate(tmp, tmp2, tmp);
7760 else
7761 gen_helper_add_saturate(tmp, tmp, tmp2);
7762 dead_tmp(tmp2);
7763 } else {
7764 tmp = load_reg(s, rn);
7765 switch (op) {
7766 case 0x0a: /* rbit */
7767 gen_helper_rbit(tmp, tmp);
7768 break;
7769 case 0x08: /* rev */
7770 tcg_gen_bswap32_i32(tmp, tmp);
7771 break;
7772 case 0x09: /* rev16 */
7773 gen_rev16(tmp);
7774 break;
7775 case 0x0b: /* revsh */
7776 gen_revsh(tmp);
7777 break;
7778 case 0x10: /* sel */
7779 tmp2 = load_reg(s, rm);
7780 tmp3 = new_tmp();
7781 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7782 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7783 dead_tmp(tmp3);
7784 dead_tmp(tmp2);
7785 break;
7786 case 0x18: /* clz */
7787 gen_helper_clz(tmp, tmp);
7788 break;
7789 default:
7790 goto illegal_op;
7791 }
7792 }
7793 store_reg(s, rd, tmp);
7794 break;
7795 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7796 op = (insn >> 4) & 0xf;
7797 tmp = load_reg(s, rn);
7798 tmp2 = load_reg(s, rm);
7799 switch ((insn >> 20) & 7) {
7800 case 0: /* 32 x 32 -> 32 */
7801 tcg_gen_mul_i32(tmp, tmp, tmp2);
7802 dead_tmp(tmp2);
7803 if (rs != 15) {
7804 tmp2 = load_reg(s, rs);
7805 if (op)
7806 tcg_gen_sub_i32(tmp, tmp2, tmp);
7807 else
7808 tcg_gen_add_i32(tmp, tmp, tmp2);
7809 dead_tmp(tmp2);
7810 }
7811 break;
7812 case 1: /* 16 x 16 -> 32 */
7813 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7814 dead_tmp(tmp2);
7815 if (rs != 15) {
7816 tmp2 = load_reg(s, rs);
7817 gen_helper_add_setq(tmp, tmp, tmp2);
7818 dead_tmp(tmp2);
7819 }
7820 break;
7821 case 2: /* Dual multiply add. */
7822 case 4: /* Dual multiply subtract. */
7823 if (op)
7824 gen_swap_half(tmp2);
7825 gen_smul_dual(tmp, tmp2);
7826 /* This addition cannot overflow. */
7827 if (insn & (1 << 22)) {
7828 tcg_gen_sub_i32(tmp, tmp, tmp2);
7829 } else {
7830 tcg_gen_add_i32(tmp, tmp, tmp2);
7831 }
7832 dead_tmp(tmp2);
7833 if (rs != 15)
7834 {
7835 tmp2 = load_reg(s, rs);
7836 gen_helper_add_setq(tmp, tmp, tmp2);
7837 dead_tmp(tmp2);
7838 }
7839 break;
7840 case 3: /* 32 * 16 -> 32msb */
7841 if (op)
7842 tcg_gen_sari_i32(tmp2, tmp2, 16);
7843 else
7844 gen_sxth(tmp2);
7845 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7846 tcg_gen_shri_i64(tmp64, tmp64, 16);
7847 tmp = new_tmp();
7848 tcg_gen_trunc_i64_i32(tmp, tmp64);
7849 tcg_temp_free_i64(tmp64);
7850 if (rs != 15)
7851 {
7852 tmp2 = load_reg(s, rs);
7853 gen_helper_add_setq(tmp, tmp, tmp2);
7854 dead_tmp(tmp2);
7855 }
7856 break;
7857 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7858 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7859 if (rs != 15) {
7860 tmp = load_reg(s, rs);
7861 if (insn & (1 << 20)) {
7862 tmp64 = gen_addq_msw(tmp64, tmp);
7863 } else {
7864 tmp64 = gen_subq_msw(tmp64, tmp);
7865 }
7866 }
7867 if (insn & (1 << 4)) {
7868 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7869 }
7870 tcg_gen_shri_i64(tmp64, tmp64, 32);
7871 tmp = new_tmp();
7872 tcg_gen_trunc_i64_i32(tmp, tmp64);
7873 tcg_temp_free_i64(tmp64);
7874 break;
7875 case 7: /* Unsigned sum of absolute differences. */
7876 gen_helper_usad8(tmp, tmp, tmp2);
7877 dead_tmp(tmp2);
7878 if (rs != 15) {
7879 tmp2 = load_reg(s, rs);
7880 tcg_gen_add_i32(tmp, tmp, tmp2);
7881 dead_tmp(tmp2);
7882 }
7883 break;
7884 }
7885 store_reg(s, rd, tmp);
7886 break;
7887 case 6: case 7: /* 64-bit multiply, Divide. */
7888 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7889 tmp = load_reg(s, rn);
7890 tmp2 = load_reg(s, rm);
7891 if ((op & 0x50) == 0x10) {
7892 /* sdiv, udiv */
7893 if (!arm_feature(env, ARM_FEATURE_DIV))
7894 goto illegal_op;
7895 if (op & 0x20)
7896 gen_helper_udiv(tmp, tmp, tmp2);
7897 else
7898 gen_helper_sdiv(tmp, tmp, tmp2);
7899 dead_tmp(tmp2);
7900 store_reg(s, rd, tmp);
7901 } else if ((op & 0xe) == 0xc) {
7902 /* Dual multiply accumulate long. */
7903 if (op & 1)
7904 gen_swap_half(tmp2);
7905 gen_smul_dual(tmp, tmp2);
7906 if (op & 0x10) {
7907 tcg_gen_sub_i32(tmp, tmp, tmp2);
7908 } else {
7909 tcg_gen_add_i32(tmp, tmp, tmp2);
7910 }
7911 dead_tmp(tmp2);
7912 /* BUGFIX */
7913 tmp64 = tcg_temp_new_i64();
7914 tcg_gen_ext_i32_i64(tmp64, tmp);
7915 dead_tmp(tmp);
7916 gen_addq(s, tmp64, rs, rd);
7917 gen_storeq_reg(s, rs, rd, tmp64);
7918 tcg_temp_free_i64(tmp64);
7919 } else {
7920 if (op & 0x20) {
7921 /* Unsigned 64-bit multiply */
7922 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7923 } else {
7924 if (op & 8) {
7925 /* smlalxy */
7926 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7927 dead_tmp(tmp2);
7928 tmp64 = tcg_temp_new_i64();
7929 tcg_gen_ext_i32_i64(tmp64, tmp);
7930 dead_tmp(tmp);
7931 } else {
7932 /* Signed 64-bit multiply */
7933 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7934 }
7935 }
7936 if (op & 4) {
7937 /* umaal */
7938 gen_addq_lo(s, tmp64, rs);
7939 gen_addq_lo(s, tmp64, rd);
7940 } else if (op & 0x40) {
7941 /* 64-bit accumulate. */
7942 gen_addq(s, tmp64, rs, rd);
7943 }
7944 gen_storeq_reg(s, rs, rd, tmp64);
7945 tcg_temp_free_i64(tmp64);
7946 }
7947 break;
7948 }
7949 break;
7950 case 6: case 7: case 14: case 15:
7951 /* Coprocessor. */
7952 if (((insn >> 24) & 3) == 3) {
7953 /* Translate into the equivalent ARM encoding. */
7954 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7955 if (disas_neon_data_insn(env, s, insn))
7956 goto illegal_op;
7957 } else {
7958 if (insn & (1 << 28))
7959 goto illegal_op;
7960 if (disas_coproc_insn (env, s, insn))
7961 goto illegal_op;
7962 }
7963 break;
7964 case 8: case 9: case 10: case 11:
7965 if (insn & (1 << 15)) {
7966 /* Branches, misc control. */
7967 if (insn & 0x5000) {
7968 /* Unconditional branch. */
7969 /* signextend(hw1[10:0]) -> offset[:12]. */
7970 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7971 /* hw1[10:0] -> offset[11:1]. */
7972 offset |= (insn & 0x7ff) << 1;
7973 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7974 offset[24:22] already have the same value because of the
7975 sign extension above. */
7976 offset ^= ((~insn) & (1 << 13)) << 10;
7977 offset ^= ((~insn) & (1 << 11)) << 11;
7978
7979 if (insn & (1 << 14)) {
7980 /* Branch and link. */
7981 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
7982 }
7983
7984 offset += s->pc;
7985 if (insn & (1 << 12)) {
7986 /* b/bl */
7987 gen_jmp(s, offset);
7988 } else {
7989 /* blx */
7990 offset &= ~(uint32_t)2;
7991 gen_bx_im(s, offset);
7992 }
7993 } else if (((insn >> 23) & 7) == 7) {
7994 /* Misc control */
7995 if (insn & (1 << 13))
7996 goto illegal_op;
7997
7998 if (insn & (1 << 26)) {
7999 /* Secure monitor call (v6Z) */
8000 goto illegal_op; /* not implemented. */
8001 } else {
8002 op = (insn >> 20) & 7;
8003 switch (op) {
8004 case 0: /* msr cpsr. */
8005 if (IS_M(env)) {
8006 tmp = load_reg(s, rn);
8007 addr = tcg_const_i32(insn & 0xff);
8008 gen_helper_v7m_msr(cpu_env, addr, tmp);
8009 tcg_temp_free_i32(addr);
8010 dead_tmp(tmp);
8011 gen_lookup_tb(s);
8012 break;
8013 }
8014 /* fall through */
8015 case 1: /* msr spsr. */
8016 if (IS_M(env))
8017 goto illegal_op;
8018 tmp = load_reg(s, rn);
8019 if (gen_set_psr(s,
8020 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8021 op == 1, tmp))
8022 goto illegal_op;
8023 break;
8024 case 2: /* cps, nop-hint. */
8025 if (((insn >> 8) & 7) == 0) {
8026 gen_nop_hint(s, insn & 0xff);
8027 }
8028 /* Implemented as NOP in user mode. */
8029 if (IS_USER(s))
8030 break;
8031 offset = 0;
8032 imm = 0;
8033 if (insn & (1 << 10)) {
8034 if (insn & (1 << 7))
8035 offset |= CPSR_A;
8036 if (insn & (1 << 6))
8037 offset |= CPSR_I;
8038 if (insn & (1 << 5))
8039 offset |= CPSR_F;
8040 if (insn & (1 << 9))
8041 imm = CPSR_A | CPSR_I | CPSR_F;
8042 }
8043 if (insn & (1 << 8)) {
8044 offset |= 0x1f;
8045 imm |= (insn & 0x1f);
8046 }
8047 if (offset) {
8048 gen_set_psr_im(s, offset, 0, imm);
8049 }
8050 break;
8051 case 3: /* Special control operations. */
8052 ARCH(7);
8053 op = (insn >> 4) & 0xf;
8054 switch (op) {
8055 case 2: /* clrex */
8056 gen_clrex(s);
8057 break;
8058 case 4: /* dsb */
8059 case 5: /* dmb */
8060 case 6: /* isb */
8061 /* These execute as NOPs. */
8062 break;
8063 default:
8064 goto illegal_op;
8065 }
8066 break;
8067 case 4: /* bxj */
8068 /* Trivial implementation equivalent to bx. */
8069 tmp = load_reg(s, rn);
8070 gen_bx(s, tmp);
8071 break;
8072 case 5: /* Exception return. */
8073 if (IS_USER(s)) {
8074 goto illegal_op;
8075 }
8076 if (rn != 14 || rd != 15) {
8077 goto illegal_op;
8078 }
8079 tmp = load_reg(s, rn);
8080 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8081 gen_exception_return(s, tmp);
8082 break;
8083 case 6: /* mrs cpsr. */
8084 tmp = new_tmp();
8085 if (IS_M(env)) {
8086 addr = tcg_const_i32(insn & 0xff);
8087 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8088 tcg_temp_free_i32(addr);
8089 } else {
8090 gen_helper_cpsr_read(tmp);
8091 }
8092 store_reg(s, rd, tmp);
8093 break;
8094 case 7: /* mrs spsr. */
8095 /* Not accessible in user mode. */
8096 if (IS_USER(s) || IS_M(env))
8097 goto illegal_op;
8098 tmp = load_cpu_field(spsr);
8099 store_reg(s, rd, tmp);
8100 break;
8101 }
8102 }
8103 } else {
8104 /* Conditional branch. */
8105 op = (insn >> 22) & 0xf;
8106 /* Generate a conditional jump to next instruction. */
8107 s->condlabel = gen_new_label();
8108 gen_test_cc(op ^ 1, s->condlabel);
8109 s->condjmp = 1;
8110
8111 /* offset[11:1] = insn[10:0] */
8112 offset = (insn & 0x7ff) << 1;
8113 /* offset[17:12] = insn[21:16]. */
8114 offset |= (insn & 0x003f0000) >> 4;
8115 /* offset[31:20] = insn[26]. */
8116 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8117 /* offset[18] = insn[13]. */
8118 offset |= (insn & (1 << 13)) << 5;
8119 /* offset[19] = insn[11]. */
8120 offset |= (insn & (1 << 11)) << 8;
8121
8122 /* jump to the offset */
8123 gen_jmp(s, s->pc + offset);
8124 }
8125 } else {
8126 /* Data processing immediate. */
8127 if (insn & (1 << 25)) {
8128 if (insn & (1 << 24)) {
8129 if (insn & (1 << 20))
8130 goto illegal_op;
8131 /* Bitfield/Saturate. */
8132 op = (insn >> 21) & 7;
8133 imm = insn & 0x1f;
8134 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8135 if (rn == 15) {
8136 tmp = new_tmp();
8137 tcg_gen_movi_i32(tmp, 0);
8138 } else {
8139 tmp = load_reg(s, rn);
8140 }
8141 switch (op) {
8142 case 2: /* Signed bitfield extract. */
8143 imm++;
8144 if (shift + imm > 32)
8145 goto illegal_op;
8146 if (imm < 32)
8147 gen_sbfx(tmp, shift, imm);
8148 break;
8149 case 6: /* Unsigned bitfield extract. */
8150 imm++;
8151 if (shift + imm > 32)
8152 goto illegal_op;
8153 if (imm < 32)
8154 gen_ubfx(tmp, shift, (1u << imm) - 1);
8155 break;
8156 case 3: /* Bitfield insert/clear. */
8157 if (imm < shift)
8158 goto illegal_op;
8159 imm = imm + 1 - shift;
8160 if (imm != 32) {
8161 tmp2 = load_reg(s, rd);
8162 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8163 dead_tmp(tmp2);
8164 }
8165 break;
8166 case 7:
8167 goto illegal_op;
8168 default: /* Saturate. */
8169 if (shift) {
8170 if (op & 1)
8171 tcg_gen_sari_i32(tmp, tmp, shift);
8172 else
8173 tcg_gen_shli_i32(tmp, tmp, shift);
8174 }
8175 tmp2 = tcg_const_i32(imm);
8176 if (op & 4) {
8177 /* Unsigned. */
8178 if ((op & 1) && shift == 0)
8179 gen_helper_usat16(tmp, tmp, tmp2);
8180 else
8181 gen_helper_usat(tmp, tmp, tmp2);
8182 } else {
8183 /* Signed. */
8184 if ((op & 1) && shift == 0)
8185 gen_helper_ssat16(tmp, tmp, tmp2);
8186 else
8187 gen_helper_ssat(tmp, tmp, tmp2);
8188 }
8189 tcg_temp_free_i32(tmp2);
8190 break;
8191 }
8192 store_reg(s, rd, tmp);
8193 } else {
8194 imm = ((insn & 0x04000000) >> 15)
8195 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8196 if (insn & (1 << 22)) {
8197 /* 16-bit immediate. */
8198 imm |= (insn >> 4) & 0xf000;
8199 if (insn & (1 << 23)) {
8200 /* movt */
8201 tmp = load_reg(s, rd);
8202 tcg_gen_ext16u_i32(tmp, tmp);
8203 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8204 } else {
8205 /* movw */
8206 tmp = new_tmp();
8207 tcg_gen_movi_i32(tmp, imm);
8208 }
8209 } else {
8210 /* Add/sub 12-bit immediate. */
8211 if (rn == 15) {
8212 offset = s->pc & ~(uint32_t)3;
8213 if (insn & (1 << 23))
8214 offset -= imm;
8215 else
8216 offset += imm;
8217 tmp = new_tmp();
8218 tcg_gen_movi_i32(tmp, offset);
8219 } else {
8220 tmp = load_reg(s, rn);
8221 if (insn & (1 << 23))
8222 tcg_gen_subi_i32(tmp, tmp, imm);
8223 else
8224 tcg_gen_addi_i32(tmp, tmp, imm);
8225 }
8226 }
8227 store_reg(s, rd, tmp);
8228 }
8229 } else {
8230 int shifter_out = 0;
8231 /* modified 12-bit immediate. */
8232 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8233 imm = (insn & 0xff);
8234 switch (shift) {
8235 case 0: /* XY */
8236 /* Nothing to do. */
8237 break;
8238 case 1: /* 00XY00XY */
8239 imm |= imm << 16;
8240 break;
8241 case 2: /* XY00XY00 */
8242 imm |= imm << 16;
8243 imm <<= 8;
8244 break;
8245 case 3: /* XYXYXYXY */
8246 imm |= imm << 16;
8247 imm |= imm << 8;
8248 break;
8249 default: /* Rotated constant. */
8250 shift = (shift << 1) | (imm >> 7);
8251 imm |= 0x80;
8252 imm = imm << (32 - shift);
8253 shifter_out = 1;
8254 break;
8255 }
8256 tmp2 = new_tmp();
8257 tcg_gen_movi_i32(tmp2, imm);
8258 rn = (insn >> 16) & 0xf;
8259 if (rn == 15) {
8260 tmp = new_tmp();
8261 tcg_gen_movi_i32(tmp, 0);
8262 } else {
8263 tmp = load_reg(s, rn);
8264 }
8265 op = (insn >> 21) & 0xf;
8266 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8267 shifter_out, tmp, tmp2))
8268 goto illegal_op;
8269 dead_tmp(tmp2);
8270 rd = (insn >> 8) & 0xf;
8271 if (rd != 15) {
8272 store_reg(s, rd, tmp);
8273 } else {
8274 dead_tmp(tmp);
8275 }
8276 }
8277 }
8278 break;
8279 case 12: /* Load/store single data item. */
8280 {
8281 int postinc = 0;
8282 int writeback = 0;
8283 int user;
8284 if ((insn & 0x01100000) == 0x01000000) {
8285 if (disas_neon_ls_insn(env, s, insn))
8286 goto illegal_op;
8287 break;
8288 }
8289 user = IS_USER(s);
8290 if (rn == 15) {
8291 addr = new_tmp();
8292 /* PC relative. */
8293 /* s->pc has already been incremented by 4. */
8294 imm = s->pc & 0xfffffffc;
8295 if (insn & (1 << 23))
8296 imm += insn & 0xfff;
8297 else
8298 imm -= insn & 0xfff;
8299 tcg_gen_movi_i32(addr, imm);
8300 } else {
8301 addr = load_reg(s, rn);
8302 if (insn & (1 << 23)) {
8303 /* Positive offset. */
8304 imm = insn & 0xfff;
8305 tcg_gen_addi_i32(addr, addr, imm);
8306 } else {
8307 op = (insn >> 8) & 7;
8308 imm = insn & 0xff;
8309 switch (op) {
8310 case 0: case 8: /* Shifted Register. */
8311 shift = (insn >> 4) & 0xf;
8312 if (shift > 3)
8313 goto illegal_op;
8314 tmp = load_reg(s, rm);
8315 if (shift)
8316 tcg_gen_shli_i32(tmp, tmp, shift);
8317 tcg_gen_add_i32(addr, addr, tmp);
8318 dead_tmp(tmp);
8319 break;
8320 case 4: /* Negative offset. */
8321 tcg_gen_addi_i32(addr, addr, -imm);
8322 break;
8323 case 6: /* User privilege. */
8324 tcg_gen_addi_i32(addr, addr, imm);
8325 user = 1;
8326 break;
8327 case 1: /* Post-decrement. */
8328 imm = -imm;
8329 /* Fall through. */
8330 case 3: /* Post-increment. */
8331 postinc = 1;
8332 writeback = 1;
8333 break;
8334 case 5: /* Pre-decrement. */
8335 imm = -imm;
8336 /* Fall through. */
8337 case 7: /* Pre-increment. */
8338 tcg_gen_addi_i32(addr, addr, imm);
8339 writeback = 1;
8340 break;
8341 default:
8342 goto illegal_op;
8343 }
8344 }
8345 }
8346 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8347 if (insn & (1 << 20)) {
8348 /* Load. */
8349 if (rs == 15 && op != 2) {
8350 if (op & 2)
8351 goto illegal_op;
8352 /* Memory hint. Implemented as NOP. */
8353 } else {
8354 switch (op) {
8355 case 0: tmp = gen_ld8u(addr, user); break;
8356 case 4: tmp = gen_ld8s(addr, user); break;
8357 case 1: tmp = gen_ld16u(addr, user); break;
8358 case 5: tmp = gen_ld16s(addr, user); break;
8359 case 2: tmp = gen_ld32(addr, user); break;
8360 default: goto illegal_op;
8361 }
8362 if (rs == 15) {
8363 gen_bx(s, tmp);
8364 } else {
8365 store_reg(s, rs, tmp);
8366 }
8367 }
8368 } else {
8369 /* Store. */
8370 if (rs == 15)
8371 goto illegal_op;
8372 tmp = load_reg(s, rs);
8373 switch (op) {
8374 case 0: gen_st8(tmp, addr, user); break;
8375 case 1: gen_st16(tmp, addr, user); break;
8376 case 2: gen_st32(tmp, addr, user); break;
8377 default: goto illegal_op;
8378 }
8379 }
8380 if (postinc)
8381 tcg_gen_addi_i32(addr, addr, imm);
8382 if (writeback) {
8383 store_reg(s, rn, addr);
8384 } else {
8385 dead_tmp(addr);
8386 }
8387 }
8388 break;
8389 default:
8390 goto illegal_op;
8391 }
8392 return 0;
8393 illegal_op:
8394 return 1;
8395 }
8396
8397 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8398 {
8399 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8400 int32_t offset;
8401 int i;
8402 TCGv tmp;
8403 TCGv tmp2;
8404 TCGv addr;
8405
8406 if (s->condexec_mask) {
8407 cond = s->condexec_cond;
8408 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8409 s->condlabel = gen_new_label();
8410 gen_test_cc(cond ^ 1, s->condlabel);
8411 s->condjmp = 1;
8412 }
8413 }
8414
8415 insn = lduw_code(s->pc);
8416 s->pc += 2;
8417
8418 switch (insn >> 12) {
8419 case 0: case 1:
8420
8421 rd = insn & 7;
8422 op = (insn >> 11) & 3;
8423 if (op == 3) {
8424 /* add/subtract */
8425 rn = (insn >> 3) & 7;
8426 tmp = load_reg(s, rn);
8427 if (insn & (1 << 10)) {
8428 /* immediate */
8429 tmp2 = new_tmp();
8430 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8431 } else {
8432 /* reg */
8433 rm = (insn >> 6) & 7;
8434 tmp2 = load_reg(s, rm);
8435 }
8436 if (insn & (1 << 9)) {
8437 if (s->condexec_mask)
8438 tcg_gen_sub_i32(tmp, tmp, tmp2);
8439 else
8440 gen_helper_sub_cc(tmp, tmp, tmp2);
8441 } else {
8442 if (s->condexec_mask)
8443 tcg_gen_add_i32(tmp, tmp, tmp2);
8444 else
8445 gen_helper_add_cc(tmp, tmp, tmp2);
8446 }
8447 dead_tmp(tmp2);
8448 store_reg(s, rd, tmp);
8449 } else {
8450 /* shift immediate */
8451 rm = (insn >> 3) & 7;
8452 shift = (insn >> 6) & 0x1f;
8453 tmp = load_reg(s, rm);
8454 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8455 if (!s->condexec_mask)
8456 gen_logic_CC(tmp);
8457 store_reg(s, rd, tmp);
8458 }
8459 break;
8460 case 2: case 3:
8461 /* arithmetic large immediate */
8462 op = (insn >> 11) & 3;
8463 rd = (insn >> 8) & 0x7;
8464 if (op == 0) { /* mov */
8465 tmp = new_tmp();
8466 tcg_gen_movi_i32(tmp, insn & 0xff);
8467 if (!s->condexec_mask)
8468 gen_logic_CC(tmp);
8469 store_reg(s, rd, tmp);
8470 } else {
8471 tmp = load_reg(s, rd);
8472 tmp2 = new_tmp();
8473 tcg_gen_movi_i32(tmp2, insn & 0xff);
8474 switch (op) {
8475 case 1: /* cmp */
8476 gen_helper_sub_cc(tmp, tmp, tmp2);
8477 dead_tmp(tmp);
8478 dead_tmp(tmp2);
8479 break;
8480 case 2: /* add */
8481 if (s->condexec_mask)
8482 tcg_gen_add_i32(tmp, tmp, tmp2);
8483 else
8484 gen_helper_add_cc(tmp, tmp, tmp2);
8485 dead_tmp(tmp2);
8486 store_reg(s, rd, tmp);
8487 break;
8488 case 3: /* sub */
8489 if (s->condexec_mask)
8490 tcg_gen_sub_i32(tmp, tmp, tmp2);
8491 else
8492 gen_helper_sub_cc(tmp, tmp, tmp2);
8493 dead_tmp(tmp2);
8494 store_reg(s, rd, tmp);
8495 break;
8496 }
8497 }
8498 break;
8499 case 4:
8500 if (insn & (1 << 11)) {
8501 rd = (insn >> 8) & 7;
8502 /* load pc-relative. Bit 1 of PC is ignored. */
8503 val = s->pc + 2 + ((insn & 0xff) * 4);
8504 val &= ~(uint32_t)2;
8505 addr = new_tmp();
8506 tcg_gen_movi_i32(addr, val);
8507 tmp = gen_ld32(addr, IS_USER(s));
8508 dead_tmp(addr);
8509 store_reg(s, rd, tmp);
8510 break;
8511 }
8512 if (insn & (1 << 10)) {
8513 /* data processing extended or blx */
8514 rd = (insn & 7) | ((insn >> 4) & 8);
8515 rm = (insn >> 3) & 0xf;
8516 op = (insn >> 8) & 3;
8517 switch (op) {
8518 case 0: /* add */
8519 tmp = load_reg(s, rd);
8520 tmp2 = load_reg(s, rm);
8521 tcg_gen_add_i32(tmp, tmp, tmp2);
8522 dead_tmp(tmp2);
8523 store_reg(s, rd, tmp);
8524 break;
8525 case 1: /* cmp */
8526 tmp = load_reg(s, rd);
8527 tmp2 = load_reg(s, rm);
8528 gen_helper_sub_cc(tmp, tmp, tmp2);
8529 dead_tmp(tmp2);
8530 dead_tmp(tmp);
8531 break;
8532 case 2: /* mov/cpy */
8533 tmp = load_reg(s, rm);
8534 store_reg(s, rd, tmp);
8535 break;
8536 case 3:/* branch [and link] exchange thumb register */
8537 tmp = load_reg(s, rm);
8538 if (insn & (1 << 7)) {
8539 val = (uint32_t)s->pc | 1;
8540 tmp2 = new_tmp();
8541 tcg_gen_movi_i32(tmp2, val);
8542 store_reg(s, 14, tmp2);
8543 }
8544 gen_bx(s, tmp);
8545 break;
8546 }
8547 break;
8548 }
8549
8550 /* data processing register */
8551 rd = insn & 7;
8552 rm = (insn >> 3) & 7;
8553 op = (insn >> 6) & 0xf;
8554 if (op == 2 || op == 3 || op == 4 || op == 7) {
8555 /* the shift/rotate ops want the operands backwards */
8556 val = rm;
8557 rm = rd;
8558 rd = val;
8559 val = 1;
8560 } else {
8561 val = 0;
8562 }
8563
8564 if (op == 9) { /* neg */
8565 tmp = new_tmp();
8566 tcg_gen_movi_i32(tmp, 0);
8567 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8568 tmp = load_reg(s, rd);
8569 } else {
8570 TCGV_UNUSED(tmp);
8571 }
8572
8573 tmp2 = load_reg(s, rm);
8574 switch (op) {
8575 case 0x0: /* and */
8576 tcg_gen_and_i32(tmp, tmp, tmp2);
8577 if (!s->condexec_mask)
8578 gen_logic_CC(tmp);
8579 break;
8580 case 0x1: /* eor */
8581 tcg_gen_xor_i32(tmp, tmp, tmp2);
8582 if (!s->condexec_mask)
8583 gen_logic_CC(tmp);
8584 break;
8585 case 0x2: /* lsl */
8586 if (s->condexec_mask) {
8587 gen_helper_shl(tmp2, tmp2, tmp);
8588 } else {
8589 gen_helper_shl_cc(tmp2, tmp2, tmp);
8590 gen_logic_CC(tmp2);
8591 }
8592 break;
8593 case 0x3: /* lsr */
8594 if (s->condexec_mask) {
8595 gen_helper_shr(tmp2, tmp2, tmp);
8596 } else {
8597 gen_helper_shr_cc(tmp2, tmp2, tmp);
8598 gen_logic_CC(tmp2);
8599 }
8600 break;
8601 case 0x4: /* asr */
8602 if (s->condexec_mask) {
8603 gen_helper_sar(tmp2, tmp2, tmp);
8604 } else {
8605 gen_helper_sar_cc(tmp2, tmp2, tmp);
8606 gen_logic_CC(tmp2);
8607 }
8608 break;
8609 case 0x5: /* adc */
8610 if (s->condexec_mask)
8611 gen_adc(tmp, tmp2);
8612 else
8613 gen_helper_adc_cc(tmp, tmp, tmp2);
8614 break;
8615 case 0x6: /* sbc */
8616 if (s->condexec_mask)
8617 gen_sub_carry(tmp, tmp, tmp2);
8618 else
8619 gen_helper_sbc_cc(tmp, tmp, tmp2);
8620 break;
8621 case 0x7: /* ror */
8622 if (s->condexec_mask) {
8623 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8624 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
8625 } else {
8626 gen_helper_ror_cc(tmp2, tmp2, tmp);
8627 gen_logic_CC(tmp2);
8628 }
8629 break;
8630 case 0x8: /* tst */
8631 tcg_gen_and_i32(tmp, tmp, tmp2);
8632 gen_logic_CC(tmp);
8633 rd = 16;
8634 break;
8635 case 0x9: /* neg */
8636 if (s->condexec_mask)
8637 tcg_gen_neg_i32(tmp, tmp2);
8638 else
8639 gen_helper_sub_cc(tmp, tmp, tmp2);
8640 break;
8641 case 0xa: /* cmp */
8642 gen_helper_sub_cc(tmp, tmp, tmp2);
8643 rd = 16;
8644 break;
8645 case 0xb: /* cmn */
8646 gen_helper_add_cc(tmp, tmp, tmp2);
8647 rd = 16;
8648 break;
8649 case 0xc: /* orr */
8650 tcg_gen_or_i32(tmp, tmp, tmp2);
8651 if (!s->condexec_mask)
8652 gen_logic_CC(tmp);
8653 break;
8654 case 0xd: /* mul */
8655 tcg_gen_mul_i32(tmp, tmp, tmp2);
8656 if (!s->condexec_mask)
8657 gen_logic_CC(tmp);
8658 break;
8659 case 0xe: /* bic */
8660 tcg_gen_andc_i32(tmp, tmp, tmp2);
8661 if (!s->condexec_mask)
8662 gen_logic_CC(tmp);
8663 break;
8664 case 0xf: /* mvn */
8665 tcg_gen_not_i32(tmp2, tmp2);
8666 if (!s->condexec_mask)
8667 gen_logic_CC(tmp2);
8668 val = 1;
8669 rm = rd;
8670 break;
8671 }
8672 if (rd != 16) {
8673 if (val) {
8674 store_reg(s, rm, tmp2);
8675 if (op != 0xf)
8676 dead_tmp(tmp);
8677 } else {
8678 store_reg(s, rd, tmp);
8679 dead_tmp(tmp2);
8680 }
8681 } else {
8682 dead_tmp(tmp);
8683 dead_tmp(tmp2);
8684 }
8685 break;
8686
8687 case 5:
8688 /* load/store register offset. */
8689 rd = insn & 7;
8690 rn = (insn >> 3) & 7;
8691 rm = (insn >> 6) & 7;
8692 op = (insn >> 9) & 7;
8693 addr = load_reg(s, rn);
8694 tmp = load_reg(s, rm);
8695 tcg_gen_add_i32(addr, addr, tmp);
8696 dead_tmp(tmp);
8697
8698 if (op < 3) /* store */
8699 tmp = load_reg(s, rd);
8700
8701 switch (op) {
8702 case 0: /* str */
8703 gen_st32(tmp, addr, IS_USER(s));
8704 break;
8705 case 1: /* strh */
8706 gen_st16(tmp, addr, IS_USER(s));
8707 break;
8708 case 2: /* strb */
8709 gen_st8(tmp, addr, IS_USER(s));
8710 break;
8711 case 3: /* ldrsb */
8712 tmp = gen_ld8s(addr, IS_USER(s));
8713 break;
8714 case 4: /* ldr */
8715 tmp = gen_ld32(addr, IS_USER(s));
8716 break;
8717 case 5: /* ldrh */
8718 tmp = gen_ld16u(addr, IS_USER(s));
8719 break;
8720 case 6: /* ldrb */
8721 tmp = gen_ld8u(addr, IS_USER(s));
8722 break;
8723 case 7: /* ldrsh */
8724 tmp = gen_ld16s(addr, IS_USER(s));
8725 break;
8726 }
8727 if (op >= 3) /* load */
8728 store_reg(s, rd, tmp);
8729 dead_tmp(addr);
8730 break;
8731
8732 case 6:
8733 /* load/store word immediate offset */
8734 rd = insn & 7;
8735 rn = (insn >> 3) & 7;
8736 addr = load_reg(s, rn);
8737 val = (insn >> 4) & 0x7c;
8738 tcg_gen_addi_i32(addr, addr, val);
8739
8740 if (insn & (1 << 11)) {
8741 /* load */
8742 tmp = gen_ld32(addr, IS_USER(s));
8743 store_reg(s, rd, tmp);
8744 } else {
8745 /* store */
8746 tmp = load_reg(s, rd);
8747 gen_st32(tmp, addr, IS_USER(s));
8748 }
8749 dead_tmp(addr);
8750 break;
8751
8752 case 7:
8753 /* load/store byte immediate offset */
8754 rd = insn & 7;
8755 rn = (insn >> 3) & 7;
8756 addr = load_reg(s, rn);
8757 val = (insn >> 6) & 0x1f;
8758 tcg_gen_addi_i32(addr, addr, val);
8759
8760 if (insn & (1 << 11)) {
8761 /* load */
8762 tmp = gen_ld8u(addr, IS_USER(s));
8763 store_reg(s, rd, tmp);
8764 } else {
8765 /* store */
8766 tmp = load_reg(s, rd);
8767 gen_st8(tmp, addr, IS_USER(s));
8768 }
8769 dead_tmp(addr);
8770 break;
8771
8772 case 8:
8773 /* load/store halfword immediate offset */
8774 rd = insn & 7;
8775 rn = (insn >> 3) & 7;
8776 addr = load_reg(s, rn);
8777 val = (insn >> 5) & 0x3e;
8778 tcg_gen_addi_i32(addr, addr, val);
8779
8780 if (insn & (1 << 11)) {
8781 /* load */
8782 tmp = gen_ld16u(addr, IS_USER(s));
8783 store_reg(s, rd, tmp);
8784 } else {
8785 /* store */
8786 tmp = load_reg(s, rd);
8787 gen_st16(tmp, addr, IS_USER(s));
8788 }
8789 dead_tmp(addr);
8790 break;
8791
8792 case 9:
8793 /* load/store from stack */
8794 rd = (insn >> 8) & 7;
8795 addr = load_reg(s, 13);
8796 val = (insn & 0xff) * 4;
8797 tcg_gen_addi_i32(addr, addr, val);
8798
8799 if (insn & (1 << 11)) {
8800 /* load */
8801 tmp = gen_ld32(addr, IS_USER(s));
8802 store_reg(s, rd, tmp);
8803 } else {
8804 /* store */
8805 tmp = load_reg(s, rd);
8806 gen_st32(tmp, addr, IS_USER(s));
8807 }
8808 dead_tmp(addr);
8809 break;
8810
8811 case 10:
8812 /* add to high reg */
8813 rd = (insn >> 8) & 7;
8814 if (insn & (1 << 11)) {
8815 /* SP */
8816 tmp = load_reg(s, 13);
8817 } else {
8818 /* PC. bit 1 is ignored. */
8819 tmp = new_tmp();
8820 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
8821 }
8822 val = (insn & 0xff) * 4;
8823 tcg_gen_addi_i32(tmp, tmp, val);
8824 store_reg(s, rd, tmp);
8825 break;
8826
8827 case 11:
8828 /* misc */
8829 op = (insn >> 8) & 0xf;
8830 switch (op) {
8831 case 0:
8832 /* adjust stack pointer */
8833 tmp = load_reg(s, 13);
8834 val = (insn & 0x7f) * 4;
8835 if (insn & (1 << 7))
8836 val = -(int32_t)val;
8837 tcg_gen_addi_i32(tmp, tmp, val);
8838 store_reg(s, 13, tmp);
8839 break;
8840
8841 case 2: /* sign/zero extend. */
8842 ARCH(6);
8843 rd = insn & 7;
8844 rm = (insn >> 3) & 7;
8845 tmp = load_reg(s, rm);
8846 switch ((insn >> 6) & 3) {
8847 case 0: gen_sxth(tmp); break;
8848 case 1: gen_sxtb(tmp); break;
8849 case 2: gen_uxth(tmp); break;
8850 case 3: gen_uxtb(tmp); break;
8851 }
8852 store_reg(s, rd, tmp);
8853 break;
8854 case 4: case 5: case 0xc: case 0xd:
8855 /* push/pop */
8856 addr = load_reg(s, 13);
8857 if (insn & (1 << 8))
8858 offset = 4;
8859 else
8860 offset = 0;
8861 for (i = 0; i < 8; i++) {
8862 if (insn & (1 << i))
8863 offset += 4;
8864 }
8865 if ((insn & (1 << 11)) == 0) {
8866 tcg_gen_addi_i32(addr, addr, -offset);
8867 }
8868 for (i = 0; i < 8; i++) {
8869 if (insn & (1 << i)) {
8870 if (insn & (1 << 11)) {
8871 /* pop */
8872 tmp = gen_ld32(addr, IS_USER(s));
8873 store_reg(s, i, tmp);
8874 } else {
8875 /* push */
8876 tmp = load_reg(s, i);
8877 gen_st32(tmp, addr, IS_USER(s));
8878 }
8879 /* advance to the next address. */
8880 tcg_gen_addi_i32(addr, addr, 4);
8881 }
8882 }
8883 TCGV_UNUSED(tmp);
8884 if (insn & (1 << 8)) {
8885 if (insn & (1 << 11)) {
8886 /* pop pc */
8887 tmp = gen_ld32(addr, IS_USER(s));
8888 /* don't set the pc until the rest of the instruction
8889 has completed */
8890 } else {
8891 /* push lr */
8892 tmp = load_reg(s, 14);
8893 gen_st32(tmp, addr, IS_USER(s));
8894 }
8895 tcg_gen_addi_i32(addr, addr, 4);
8896 }
8897 if ((insn & (1 << 11)) == 0) {
8898 tcg_gen_addi_i32(addr, addr, -offset);
8899 }
8900 /* write back the new stack pointer */
8901 store_reg(s, 13, addr);
8902 /* set the new PC value */
8903 if ((insn & 0x0900) == 0x0900)
8904 gen_bx(s, tmp);
8905 break;
8906
8907 case 1: case 3: case 9: case 11: /* czb */
8908 rm = insn & 7;
8909 tmp = load_reg(s, rm);
8910 s->condlabel = gen_new_label();
8911 s->condjmp = 1;
8912 if (insn & (1 << 11))
8913 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
8914 else
8915 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
8916 dead_tmp(tmp);
8917 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8918 val = (uint32_t)s->pc + 2;
8919 val += offset;
8920 gen_jmp(s, val);
8921 break;
8922
8923 case 15: /* IT, nop-hint. */
8924 if ((insn & 0xf) == 0) {
8925 gen_nop_hint(s, (insn >> 4) & 0xf);
8926 break;
8927 }
8928 /* If Then. */
8929 s->condexec_cond = (insn >> 4) & 0xe;
8930 s->condexec_mask = insn & 0x1f;
8931 /* No actual code generated for this insn, just setup state. */
8932 break;
8933
8934 case 0xe: /* bkpt */
8935 gen_exception_insn(s, 2, EXCP_BKPT);
8936 break;
8937
8938 case 0xa: /* rev */
8939 ARCH(6);
8940 rn = (insn >> 3) & 0x7;
8941 rd = insn & 0x7;
8942 tmp = load_reg(s, rn);
8943 switch ((insn >> 6) & 3) {
8944 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
8945 case 1: gen_rev16(tmp); break;
8946 case 3: gen_revsh(tmp); break;
8947 default: goto illegal_op;
8948 }
8949 store_reg(s, rd, tmp);
8950 break;
8951
8952 case 6: /* cps */
8953 ARCH(6);
8954 if (IS_USER(s))
8955 break;
8956 if (IS_M(env)) {
8957 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
8958 /* PRIMASK */
8959 if (insn & 1) {
8960 addr = tcg_const_i32(16);
8961 gen_helper_v7m_msr(cpu_env, addr, tmp);
8962 tcg_temp_free_i32(addr);
8963 }
8964 /* FAULTMASK */
8965 if (insn & 2) {
8966 addr = tcg_const_i32(17);
8967 gen_helper_v7m_msr(cpu_env, addr, tmp);
8968 tcg_temp_free_i32(addr);
8969 }
8970 tcg_temp_free_i32(tmp);
8971 gen_lookup_tb(s);
8972 } else {
8973 if (insn & (1 << 4))
8974 shift = CPSR_A | CPSR_I | CPSR_F;
8975 else
8976 shift = 0;
8977 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
8978 }
8979 break;
8980
8981 default:
8982 goto undef;
8983 }
8984 break;
8985
8986 case 12:
8987 /* load/store multiple */
8988 rn = (insn >> 8) & 0x7;
8989 addr = load_reg(s, rn);
8990 for (i = 0; i < 8; i++) {
8991 if (insn & (1 << i)) {
8992 if (insn & (1 << 11)) {
8993 /* load */
8994 tmp = gen_ld32(addr, IS_USER(s));
8995 store_reg(s, i, tmp);
8996 } else {
8997 /* store */
8998 tmp = load_reg(s, i);
8999 gen_st32(tmp, addr, IS_USER(s));
9000 }
9001 /* advance to the next address */
9002 tcg_gen_addi_i32(addr, addr, 4);
9003 }
9004 }
9005 /* Base register writeback. */
9006 if ((insn & (1 << rn)) == 0) {
9007 store_reg(s, rn, addr);
9008 } else {
9009 dead_tmp(addr);
9010 }
9011 break;
9012
9013 case 13:
9014 /* conditional branch or swi */
9015 cond = (insn >> 8) & 0xf;
9016 if (cond == 0xe)
9017 goto undef;
9018
9019 if (cond == 0xf) {
9020 /* swi */
9021 gen_set_pc_im(s->pc);
9022 s->is_jmp = DISAS_SWI;
9023 break;
9024 }
9025 /* generate a conditional jump to next instruction */
9026 s->condlabel = gen_new_label();
9027 gen_test_cc(cond ^ 1, s->condlabel);
9028 s->condjmp = 1;
9029
9030 /* jump to the offset */
9031 val = (uint32_t)s->pc + 2;
9032 offset = ((int32_t)insn << 24) >> 24;
9033 val += offset << 1;
9034 gen_jmp(s, val);
9035 break;
9036
9037 case 14:
9038 if (insn & (1 << 11)) {
9039 if (disas_thumb2_insn(env, s, insn))
9040 goto undef32;
9041 break;
9042 }
9043 /* unconditional branch */
9044 val = (uint32_t)s->pc;
9045 offset = ((int32_t)insn << 21) >> 21;
9046 val += (offset << 1) + 2;
9047 gen_jmp(s, val);
9048 break;
9049
9050 case 15:
9051 if (disas_thumb2_insn(env, s, insn))
9052 goto undef32;
9053 break;
9054 }
9055 return;
9056 undef32:
9057 gen_exception_insn(s, 4, EXCP_UDEF);
9058 return;
9059 illegal_op:
9060 undef:
9061 gen_exception_insn(s, 2, EXCP_UDEF);
9062 }
9063
9064 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9065 basic block 'tb'. If search_pc is TRUE, also generate PC
9066 information for each intermediate instruction. */
9067 static inline void gen_intermediate_code_internal(CPUState *env,
9068 TranslationBlock *tb,
9069 int search_pc)
9070 {
9071 DisasContext dc1, *dc = &dc1;
9072 CPUBreakpoint *bp;
9073 uint16_t *gen_opc_end;
9074 int j, lj;
9075 target_ulong pc_start;
9076 uint32_t next_page_start;
9077 int num_insns;
9078 int max_insns;
9079
9080 /* generate intermediate code */
9081 num_temps = 0;
9082
9083 pc_start = tb->pc;
9084
9085 dc->tb = tb;
9086
9087 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9088
9089 dc->is_jmp = DISAS_NEXT;
9090 dc->pc = pc_start;
9091 dc->singlestep_enabled = env->singlestep_enabled;
9092 dc->condjmp = 0;
9093 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9094 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9095 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9096 #if !defined(CONFIG_USER_ONLY)
9097 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9098 #endif
9099 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9100 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9101 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9102 cpu_F0s = tcg_temp_new_i32();
9103 cpu_F1s = tcg_temp_new_i32();
9104 cpu_F0d = tcg_temp_new_i64();
9105 cpu_F1d = tcg_temp_new_i64();
9106 cpu_V0 = cpu_F0d;
9107 cpu_V1 = cpu_F1d;
9108 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9109 cpu_M0 = tcg_temp_new_i64();
9110 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9111 lj = -1;
9112 num_insns = 0;
9113 max_insns = tb->cflags & CF_COUNT_MASK;
9114 if (max_insns == 0)
9115 max_insns = CF_COUNT_MASK;
9116
9117 gen_icount_start();
9118
9119 /* A note on handling of the condexec (IT) bits:
9120 *
9121 * We want to avoid the overhead of having to write the updated condexec
9122 * bits back to the CPUState for every instruction in an IT block. So:
9123 * (1) if the condexec bits are not already zero then we write
9124 * zero back into the CPUState now. This avoids complications trying
9125 * to do it at the end of the block. (For example if we don't do this
9126 * it's hard to identify whether we can safely skip writing condexec
9127 * at the end of the TB, which we definitely want to do for the case
9128 * where a TB doesn't do anything with the IT state at all.)
9129 * (2) if we are going to leave the TB then we call gen_set_condexec()
9130 * which will write the correct value into CPUState if zero is wrong.
9131 * This is done both for leaving the TB at the end, and for leaving
9132 * it because of an exception we know will happen, which is done in
9133 * gen_exception_insn(). The latter is necessary because we need to
9134 * leave the TB with the PC/IT state just prior to execution of the
9135 * instruction which caused the exception.
9136 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9137 * then the CPUState will be wrong and we need to reset it.
9138 * This is handled in the same way as restoration of the
9139 * PC in these situations: we will be called again with search_pc=1
9140 * and generate a mapping of the condexec bits for each PC in
9141 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9142 * the condexec bits.
9143 *
9144 * Note that there are no instructions which can read the condexec
9145 * bits, and none which can write non-static values to them, so
9146 * we don't need to care about whether CPUState is correct in the
9147 * middle of a TB.
9148 */
9149
9150 /* Reset the conditional execution bits immediately. This avoids
9151 complications trying to do it at the end of the block. */
9152 if (dc->condexec_mask || dc->condexec_cond)
9153 {
9154 TCGv tmp = new_tmp();
9155 tcg_gen_movi_i32(tmp, 0);
9156 store_cpu_field(tmp, condexec_bits);
9157 }
9158 do {
9159 #ifdef CONFIG_USER_ONLY
9160 /* Intercept jump to the magic kernel page. */
9161 if (dc->pc >= 0xffff0000) {
9162 /* We always get here via a jump, so know we are not in a
9163 conditional execution block. */
9164 gen_exception(EXCP_KERNEL_TRAP);
9165 dc->is_jmp = DISAS_UPDATE;
9166 break;
9167 }
9168 #else
9169 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9170 /* We always get here via a jump, so know we are not in a
9171 conditional execution block. */
9172 gen_exception(EXCP_EXCEPTION_EXIT);
9173 dc->is_jmp = DISAS_UPDATE;
9174 break;
9175 }
9176 #endif
9177
9178 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9179 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9180 if (bp->pc == dc->pc) {
9181 gen_exception_insn(dc, 0, EXCP_DEBUG);
9182 /* Advance PC so that clearing the breakpoint will
9183 invalidate this TB. */
9184 dc->pc += 2;
9185 goto done_generating;
9186 break;
9187 }
9188 }
9189 }
9190 if (search_pc) {
9191 j = gen_opc_ptr - gen_opc_buf;
9192 if (lj < j) {
9193 lj++;
9194 while (lj < j)
9195 gen_opc_instr_start[lj++] = 0;
9196 }
9197 gen_opc_pc[lj] = dc->pc;
9198 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9199 gen_opc_instr_start[lj] = 1;
9200 gen_opc_icount[lj] = num_insns;
9201 }
9202
9203 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9204 gen_io_start();
9205
9206 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9207 tcg_gen_debug_insn_start(dc->pc);
9208 }
9209
9210 if (dc->thumb) {
9211 disas_thumb_insn(env, dc);
9212 if (dc->condexec_mask) {
9213 dc->condexec_cond = (dc->condexec_cond & 0xe)
9214 | ((dc->condexec_mask >> 4) & 1);
9215 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9216 if (dc->condexec_mask == 0) {
9217 dc->condexec_cond = 0;
9218 }
9219 }
9220 } else {
9221 disas_arm_insn(env, dc);
9222 }
9223 if (num_temps) {
9224 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9225 num_temps = 0;
9226 }
9227
9228 if (dc->condjmp && !dc->is_jmp) {
9229 gen_set_label(dc->condlabel);
9230 dc->condjmp = 0;
9231 }
9232 /* Translation stops when a conditional branch is encountered.
9233 * Otherwise the subsequent code could get translated several times.
9234 * Also stop translation when a page boundary is reached. This
9235 * ensures prefetch aborts occur at the right place. */
9236 num_insns ++;
9237 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9238 !env->singlestep_enabled &&
9239 !singlestep &&
9240 dc->pc < next_page_start &&
9241 num_insns < max_insns);
9242
9243 if (tb->cflags & CF_LAST_IO) {
9244 if (dc->condjmp) {
9245 /* FIXME: This can theoretically happen with self-modifying
9246 code. */
9247 cpu_abort(env, "IO on conditional branch instruction");
9248 }
9249 gen_io_end();
9250 }
9251
9252 /* At this stage dc->condjmp will only be set when the skipped
9253 instruction was a conditional branch or trap, and the PC has
9254 already been written. */
9255 if (unlikely(env->singlestep_enabled)) {
9256 /* Make sure the pc is updated, and raise a debug exception. */
9257 if (dc->condjmp) {
9258 gen_set_condexec(dc);
9259 if (dc->is_jmp == DISAS_SWI) {
9260 gen_exception(EXCP_SWI);
9261 } else {
9262 gen_exception(EXCP_DEBUG);
9263 }
9264 gen_set_label(dc->condlabel);
9265 }
9266 if (dc->condjmp || !dc->is_jmp) {
9267 gen_set_pc_im(dc->pc);
9268 dc->condjmp = 0;
9269 }
9270 gen_set_condexec(dc);
9271 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9272 gen_exception(EXCP_SWI);
9273 } else {
9274 /* FIXME: Single stepping a WFI insn will not halt
9275 the CPU. */
9276 gen_exception(EXCP_DEBUG);
9277 }
9278 } else {
9279 /* While branches must always occur at the end of an IT block,
9280 there are a few other things that can cause us to terminate
9281 the TB in the middel of an IT block:
9282 - Exception generating instructions (bkpt, swi, undefined).
9283 - Page boundaries.
9284 - Hardware watchpoints.
9285 Hardware breakpoints have already been handled and skip this code.
9286 */
9287 gen_set_condexec(dc);
9288 switch(dc->is_jmp) {
9289 case DISAS_NEXT:
9290 gen_goto_tb(dc, 1, dc->pc);
9291 break;
9292 default:
9293 case DISAS_JUMP:
9294 case DISAS_UPDATE:
9295 /* indicate that the hash table must be used to find the next TB */
9296 tcg_gen_exit_tb(0);
9297 break;
9298 case DISAS_TB_JUMP:
9299 /* nothing more to generate */
9300 break;
9301 case DISAS_WFI:
9302 gen_helper_wfi();
9303 break;
9304 case DISAS_SWI:
9305 gen_exception(EXCP_SWI);
9306 break;
9307 }
9308 if (dc->condjmp) {
9309 gen_set_label(dc->condlabel);
9310 gen_set_condexec(dc);
9311 gen_goto_tb(dc, 1, dc->pc);
9312 dc->condjmp = 0;
9313 }
9314 }
9315
9316 done_generating:
9317 gen_icount_end(tb, num_insns);
9318 *gen_opc_ptr = INDEX_op_end;
9319
9320 #ifdef DEBUG_DISAS
9321 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9322 qemu_log("----------------\n");
9323 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9324 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9325 qemu_log("\n");
9326 }
9327 #endif
9328 if (search_pc) {
9329 j = gen_opc_ptr - gen_opc_buf;
9330 lj++;
9331 while (lj <= j)
9332 gen_opc_instr_start[lj++] = 0;
9333 } else {
9334 tb->size = dc->pc - pc_start;
9335 tb->icount = num_insns;
9336 }
9337 }
9338
9339 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9340 {
9341 gen_intermediate_code_internal(env, tb, 0);
9342 }
9343
9344 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9345 {
9346 gen_intermediate_code_internal(env, tb, 1);
9347 }
9348
9349 static const char *cpu_mode_names[16] = {
9350 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9351 "???", "???", "???", "und", "???", "???", "???", "sys"
9352 };
9353
9354 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9355 int flags)
9356 {
9357 int i;
9358 #if 0
9359 union {
9360 uint32_t i;
9361 float s;
9362 } s0, s1;
9363 CPU_DoubleU d;
9364 /* ??? This assumes float64 and double have the same layout.
9365 Oh well, it's only debug dumps. */
9366 union {
9367 float64 f64;
9368 double d;
9369 } d0;
9370 #endif
9371 uint32_t psr;
9372
9373 for(i=0;i<16;i++) {
9374 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9375 if ((i % 4) == 3)
9376 cpu_fprintf(f, "\n");
9377 else
9378 cpu_fprintf(f, " ");
9379 }
9380 psr = cpsr_read(env);
9381 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9382 psr,
9383 psr & (1 << 31) ? 'N' : '-',
9384 psr & (1 << 30) ? 'Z' : '-',
9385 psr & (1 << 29) ? 'C' : '-',
9386 psr & (1 << 28) ? 'V' : '-',
9387 psr & CPSR_T ? 'T' : 'A',
9388 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9389
9390 #if 0
9391 for (i = 0; i < 16; i++) {
9392 d.d = env->vfp.regs[i];
9393 s0.i = d.l.lower;
9394 s1.i = d.l.upper;
9395 d0.f64 = d.d;
9396 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9397 i * 2, (int)s0.i, s0.s,
9398 i * 2 + 1, (int)s1.i, s1.s,
9399 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9400 d0.d);
9401 }
9402 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9403 #endif
9404 }
9405
9406 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9407 unsigned long searched_pc, int pc_pos, void *puc)
9408 {
9409 env->regs[15] = gen_opc_pc[pc_pos];
9410 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9411 }
Qemu copy for testing