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target-arm: Fix decoding of Thumb preload and hint space
[qemu.git] / target-arm / translate.c
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
42
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
44
45 /* internal defines */
46 typedef struct DisasContext {
47 target_ulong pc;
48 int is_jmp;
49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
56 struct TranslationBlock *tb;
57 int singlestep_enabled;
58 int thumb;
59 #if !defined(CONFIG_USER_ONLY)
60 int user;
61 #endif
62 int vfp_enabled;
63 int vec_len;
64 int vec_stride;
65 } DisasContext;
66
67 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
69 #if defined(CONFIG_USER_ONLY)
70 #define IS_USER(s) 1
71 #else
72 #define IS_USER(s) (s->user)
73 #endif
74
75 /* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77 #define DISAS_WFI 4
78 #define DISAS_SWI 5
79
80 static TCGv_ptr cpu_env;
81 /* We reuse the same 64-bit temporaries for efficiency. */
82 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
83 static TCGv_i32 cpu_R[16];
84 static TCGv_i32 cpu_exclusive_addr;
85 static TCGv_i32 cpu_exclusive_val;
86 static TCGv_i32 cpu_exclusive_high;
87 #ifdef CONFIG_USER_ONLY
88 static TCGv_i32 cpu_exclusive_test;
89 static TCGv_i32 cpu_exclusive_info;
90 #endif
91
92 /* FIXME: These should be removed. */
93 static TCGv cpu_F0s, cpu_F1s;
94 static TCGv_i64 cpu_F0d, cpu_F1d;
95
96 #include "gen-icount.h"
97
98 static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
102 /* initialize TCG globals. */
103 void arm_translate_init(void)
104 {
105 int i;
106
107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120 #ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125 #endif
126
127 #define GEN_HELPER 2
128 #include "helpers.h"
129 }
130
131 static int num_temps;
132
133 /* Allocate a temporary variable. */
134 static TCGv_i32 new_tmp(void)
135 {
136 num_temps++;
137 return tcg_temp_new_i32();
138 }
139
140 /* Release a temporary variable. */
141 static void dead_tmp(TCGv tmp)
142 {
143 tcg_temp_free(tmp);
144 num_temps--;
145 }
146
147 static inline TCGv load_cpu_offset(int offset)
148 {
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152 }
153
154 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156 static inline void store_cpu_offset(TCGv var, int offset)
157 {
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160 }
161
162 #define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
165 /* Set a variable to the value of a CPU register. */
166 static void load_reg_var(DisasContext *s, TCGv var, int reg)
167 {
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
177 tcg_gen_mov_i32(var, cpu_R[reg]);
178 }
179 }
180
181 /* Create a new temporary and set it to the value of a CPU register. */
182 static inline TCGv load_reg(DisasContext *s, int reg)
183 {
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187 }
188
189 /* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191 static void store_reg(DisasContext *s, int reg, TCGv var)
192 {
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
197 tcg_gen_mov_i32(cpu_R[reg], var);
198 dead_tmp(var);
199 }
200
201 /* Value extensions. */
202 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
204 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
207 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
209
210
211 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212 {
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216 }
217 /* Set NZCV flags from the high 4 bits of var. */
218 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220 static void gen_exception(int excp)
221 {
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226 }
227
228 static void gen_smul_dual(TCGv a, TCGv b)
229 {
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241 }
242
243 /* Byteswap each halfword. */
244 static void gen_rev16(TCGv var)
245 {
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253 }
254
255 /* Byteswap low halfword and sign extend. */
256 static void gen_revsh(TCGv var)
257 {
258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
261 }
262
263 /* Unsigned bitfield extract. */
264 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265 {
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269 }
270
271 /* Signed bitfield extract. */
272 static void gen_sbfx(TCGv var, int shift, int width)
273 {
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284 }
285
286 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
287 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288 {
289 tcg_gen_andi_i32(val, val, mask);
290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
292 tcg_gen_or_i32(dest, base, val);
293 }
294
295 /* Return (b << 32) + a. Mark inputs as dead */
296 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
297 {
298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307 }
308
309 /* Return (b << 32) - a. Mark inputs as dead. */
310 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311 {
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
321 }
322
323 /* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
325 /* 32x32->64 multiply. Marks inputs as dead. */
326 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
327 {
328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
336 tcg_temp_free_i64(tmp2);
337 return tmp1;
338 }
339
340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
341 {
342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 tcg_temp_free_i64(tmp2);
351 return tmp1;
352 }
353
354 /* Swap low and high halfwords. */
355 static void gen_swap_half(TCGv var)
356 {
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
361 dead_tmp(tmp);
362 }
363
364 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371 static void gen_add16(TCGv t0, TCGv t1)
372 {
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382 }
383
384 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
386 /* Set CF to the top bit of var. */
387 static void gen_set_CF_bit31(TCGv var)
388 {
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
391 gen_set_CF(tmp);
392 dead_tmp(tmp);
393 }
394
395 /* Set N and Z flags from var. */
396 static inline void gen_logic_CC(TCGv var)
397 {
398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
400 }
401
402 /* T0 += T1 + CF. */
403 static void gen_adc(TCGv t0, TCGv t1)
404 {
405 TCGv tmp;
406 tcg_gen_add_i32(t0, t0, t1);
407 tmp = load_cpu_field(CF);
408 tcg_gen_add_i32(t0, t0, tmp);
409 dead_tmp(tmp);
410 }
411
412 /* dest = T0 + T1 + CF. */
413 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414 {
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420 }
421
422 /* dest = T0 - T1 + CF - 1. */
423 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424 {
425 TCGv tmp;
426 tcg_gen_sub_i32(dest, t0, t1);
427 tmp = load_cpu_field(CF);
428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431 }
432
433 /* FIXME: Implement this natively. */
434 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
436 static void shifter_out_im(TCGv var, int shift)
437 {
438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
441 } else {
442 tcg_gen_shri_i32(tmp, var, shift);
443 if (shift != 31)
444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448 }
449
450 /* Shift by immediate. Includes special handling for shift == 0. */
451 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452 {
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
487 tcg_gen_rotri_i32(var, var, shift); break;
488 } else {
489 TCGv tmp = load_cpu_field(CF);
490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
496 }
497 }
498 };
499
500 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502 {
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
517 }
518 }
519 dead_tmp(shift);
520 }
521
522 #define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
531 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
532 {
533 TCGv_ptr tmp;
534
535 switch (op1) {
536 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
538 tmp = tcg_temp_new_ptr();
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
541 tcg_temp_free_ptr(tmp);
542 break;
543 case 5:
544 tmp = tcg_temp_new_ptr();
545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
547 tcg_temp_free_ptr(tmp);
548 break;
549 #undef gen_pas_helper
550 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563 #undef gen_pas_helper
564 }
565 }
566 #undef PAS_OP
567
568 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569 #define PAS_OP(pfx) \
570 switch (op1) { \
571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
578 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
579 {
580 TCGv_ptr tmp;
581
582 switch (op2) {
583 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
585 tmp = tcg_temp_new_ptr();
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
588 tcg_temp_free_ptr(tmp);
589 break;
590 case 4:
591 tmp = tcg_temp_new_ptr();
592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
594 tcg_temp_free_ptr(tmp);
595 break;
596 #undef gen_pas_helper
597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610 #undef gen_pas_helper
611 }
612 }
613 #undef PAS_OP
614
615 static void gen_test_cc(int cc, int label)
616 {
617 TCGv tmp;
618 TCGv tmp2;
619 int inv;
620
621 switch (cc) {
622 case 0: /* eq: Z */
623 tmp = load_cpu_field(ZF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 1: /* ne: !Z */
627 tmp = load_cpu_field(ZF);
628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
637 break;
638 case 4: /* mi: N */
639 tmp = load_cpu_field(NF);
640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
641 break;
642 case 5: /* pl: !N */
643 tmp = load_cpu_field(NF);
644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
658 dead_tmp(tmp);
659 tmp = load_cpu_field(ZF);
660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
666 dead_tmp(tmp);
667 tmp = load_cpu_field(ZF);
668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
672 tmp2 = load_cpu_field(NF);
673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
679 tmp2 = load_cpu_field(NF);
680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
686 tmp = load_cpu_field(ZF);
687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
690 tmp2 = load_cpu_field(NF);
691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
697 tmp = load_cpu_field(ZF);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
701 tmp2 = load_cpu_field(NF);
702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711 }
712
713 static const uint8_t table_logic_cc[16] = {
714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730 };
731
732 /* Set PC and Thumb state from an immediate address. */
733 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
734 {
735 TCGv tmp;
736
737 s->is_jmp = DISAS_UPDATE;
738 if (s->thumb != (addr & 1)) {
739 tmp = new_tmp();
740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
742 dead_tmp(tmp);
743 }
744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
745 }
746
747 /* Set PC and Thumb state from var. var is marked as dead. */
748 static inline void gen_bx(DisasContext *s, TCGv var)
749 {
750 s->is_jmp = DISAS_UPDATE;
751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
754 }
755
756 /* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759 static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761 {
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767 }
768
769 static inline TCGv gen_ld8s(TCGv addr, int index)
770 {
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774 }
775 static inline TCGv gen_ld8u(TCGv addr, int index)
776 {
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780 }
781 static inline TCGv gen_ld16s(TCGv addr, int index)
782 {
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786 }
787 static inline TCGv gen_ld16u(TCGv addr, int index)
788 {
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792 }
793 static inline TCGv gen_ld32(TCGv addr, int index)
794 {
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798 }
799 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800 {
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804 }
805 static inline void gen_st8(TCGv val, TCGv addr, int index)
806 {
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809 }
810 static inline void gen_st16(TCGv val, TCGv addr, int index)
811 {
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814 }
815 static inline void gen_st32(TCGv val, TCGv addr, int index)
816 {
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819 }
820 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821 {
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824 }
825
826 static inline void gen_set_pc_im(uint32_t val)
827 {
828 tcg_gen_movi_i32(cpu_R[15], val);
829 }
830
831 /* Force a TB lookup after an instruction that changes the CPU state. */
832 static inline void gen_lookup_tb(DisasContext *s)
833 {
834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
835 s->is_jmp = DISAS_UPDATE;
836 }
837
838 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
840 {
841 int val, rm, shift, shiftop;
842 TCGv offset;
843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
849 if (val != 0)
850 tcg_gen_addi_i32(var, var, val);
851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
855 shiftop = (insn >> 5) & 3;
856 offset = load_reg(s, rm);
857 gen_arm_shift_im(offset, shiftop, shift, 0);
858 if (!(insn & (1 << 23)))
859 tcg_gen_sub_i32(var, var, offset);
860 else
861 tcg_gen_add_i32(var, var, offset);
862 dead_tmp(offset);
863 }
864 }
865
866 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
867 int extra, TCGv var)
868 {
869 int val, rm;
870 TCGv offset;
871
872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
877 val += extra;
878 if (val != 0)
879 tcg_gen_addi_i32(var, var, val);
880 } else {
881 /* register */
882 if (extra)
883 tcg_gen_addi_i32(var, var, extra);
884 rm = (insn) & 0xf;
885 offset = load_reg(s, rm);
886 if (!(insn & (1 << 23)))
887 tcg_gen_sub_i32(var, var, offset);
888 else
889 tcg_gen_add_i32(var, var, offset);
890 dead_tmp(offset);
891 }
892 }
893
894 #define VFP_OP2(name) \
895 static inline void gen_vfp_##name(int dp) \
896 { \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
901 }
902
903 VFP_OP2(add)
904 VFP_OP2(sub)
905 VFP_OP2(mul)
906 VFP_OP2(div)
907
908 #undef VFP_OP2
909
910 static inline void gen_vfp_abs(int dp)
911 {
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916 }
917
918 static inline void gen_vfp_neg(int dp)
919 {
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924 }
925
926 static inline void gen_vfp_sqrt(int dp)
927 {
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932 }
933
934 static inline void gen_vfp_cmp(int dp)
935 {
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940 }
941
942 static inline void gen_vfp_cmpe(int dp)
943 {
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948 }
949
950 static inline void gen_vfp_F1_ld0(int dp)
951 {
952 if (dp)
953 tcg_gen_movi_i64(cpu_F1d, 0);
954 else
955 tcg_gen_movi_i32(cpu_F1s, 0);
956 }
957
958 static inline void gen_vfp_uito(int dp)
959 {
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964 }
965
966 static inline void gen_vfp_sito(int dp)
967 {
968 if (dp)
969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
970 else
971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
972 }
973
974 static inline void gen_vfp_toui(int dp)
975 {
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980 }
981
982 static inline void gen_vfp_touiz(int dp)
983 {
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988 }
989
990 static inline void gen_vfp_tosi(int dp)
991 {
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996 }
997
998 static inline void gen_vfp_tosiz(int dp)
999 {
1000 if (dp)
1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1002 else
1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004 }
1005
1006 #define VFP_GEN_FIX(name) \
1007 static inline void gen_vfp_##name(int dp, int shift) \
1008 { \
1009 TCGv tmp_shift = tcg_const_i32(shift); \
1010 if (dp) \
1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1012 else \
1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
1015 }
1016 VFP_GEN_FIX(tosh)
1017 VFP_GEN_FIX(tosl)
1018 VFP_GEN_FIX(touh)
1019 VFP_GEN_FIX(toul)
1020 VFP_GEN_FIX(shto)
1021 VFP_GEN_FIX(slto)
1022 VFP_GEN_FIX(uhto)
1023 VFP_GEN_FIX(ulto)
1024 #undef VFP_GEN_FIX
1025
1026 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1027 {
1028 if (dp)
1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1030 else
1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1032 }
1033
1034 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1035 {
1036 if (dp)
1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1038 else
1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1040 }
1041
1042 static inline long
1043 vfp_reg_offset (int dp, int reg)
1044 {
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054 }
1055
1056 /* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058 static inline long
1059 neon_reg_offset (int reg, int n)
1060 {
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064 }
1065
1066 static TCGv neon_load_reg(int reg, int pass)
1067 {
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071 }
1072
1073 static void neon_store_reg(int reg, int pass, TCGv var)
1074 {
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077 }
1078
1079 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1080 {
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082 }
1083
1084 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1085 {
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087 }
1088
1089 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1090 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1091 #define tcg_gen_st_f32 tcg_gen_st_i32
1092 #define tcg_gen_st_f64 tcg_gen_st_i64
1093
1094 static inline void gen_mov_F0_vreg(int dp, int reg)
1095 {
1096 if (dp)
1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1098 else
1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1100 }
1101
1102 static inline void gen_mov_F1_vreg(int dp, int reg)
1103 {
1104 if (dp)
1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1106 else
1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1108 }
1109
1110 static inline void gen_mov_vreg_F0(int dp, int reg)
1111 {
1112 if (dp)
1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1114 else
1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1116 }
1117
1118 #define ARM_CP_RW_BIT (1 << 20)
1119
1120 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1121 {
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123 }
1124
1125 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1126 {
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128 }
1129
1130 static inline TCGv iwmmxt_load_creg(int reg)
1131 {
1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
1135 }
1136
1137 static inline void iwmmxt_store_creg(int reg, TCGv var)
1138 {
1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1140 dead_tmp(var);
1141 }
1142
1143 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144 {
1145 iwmmxt_store_reg(cpu_M0, rn);
1146 }
1147
1148 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149 {
1150 iwmmxt_load_reg(cpu_M0, rn);
1151 }
1152
1153 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154 {
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157 }
1158
1159 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160 {
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163 }
1164
1165 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166 {
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169 }
1170
1171 #define IWMMXT_OP(name) \
1172 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173 { \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176 }
1177
1178 #define IWMMXT_OP_ENV(name) \
1179 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180 { \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183 }
1184
1185 #define IWMMXT_OP_ENV_SIZE(name) \
1186 IWMMXT_OP_ENV(name##b) \
1187 IWMMXT_OP_ENV(name##w) \
1188 IWMMXT_OP_ENV(name##l)
1189
1190 #define IWMMXT_OP_ENV1(name) \
1191 static inline void gen_op_iwmmxt_##name##_M0(void) \
1192 { \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194 }
1195
1196 IWMMXT_OP(maddsq)
1197 IWMMXT_OP(madduq)
1198 IWMMXT_OP(sadb)
1199 IWMMXT_OP(sadw)
1200 IWMMXT_OP(mulslw)
1201 IWMMXT_OP(mulshw)
1202 IWMMXT_OP(mululw)
1203 IWMMXT_OP(muluhw)
1204 IWMMXT_OP(macsw)
1205 IWMMXT_OP(macuw)
1206
1207 IWMMXT_OP_ENV_SIZE(unpackl)
1208 IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210 IWMMXT_OP_ENV1(unpacklub)
1211 IWMMXT_OP_ENV1(unpackluw)
1212 IWMMXT_OP_ENV1(unpacklul)
1213 IWMMXT_OP_ENV1(unpackhub)
1214 IWMMXT_OP_ENV1(unpackhuw)
1215 IWMMXT_OP_ENV1(unpackhul)
1216 IWMMXT_OP_ENV1(unpacklsb)
1217 IWMMXT_OP_ENV1(unpacklsw)
1218 IWMMXT_OP_ENV1(unpacklsl)
1219 IWMMXT_OP_ENV1(unpackhsb)
1220 IWMMXT_OP_ENV1(unpackhsw)
1221 IWMMXT_OP_ENV1(unpackhsl)
1222
1223 IWMMXT_OP_ENV_SIZE(cmpeq)
1224 IWMMXT_OP_ENV_SIZE(cmpgtu)
1225 IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227 IWMMXT_OP_ENV_SIZE(mins)
1228 IWMMXT_OP_ENV_SIZE(minu)
1229 IWMMXT_OP_ENV_SIZE(maxs)
1230 IWMMXT_OP_ENV_SIZE(maxu)
1231
1232 IWMMXT_OP_ENV_SIZE(subn)
1233 IWMMXT_OP_ENV_SIZE(addn)
1234 IWMMXT_OP_ENV_SIZE(subu)
1235 IWMMXT_OP_ENV_SIZE(addu)
1236 IWMMXT_OP_ENV_SIZE(subs)
1237 IWMMXT_OP_ENV_SIZE(adds)
1238
1239 IWMMXT_OP_ENV(avgb0)
1240 IWMMXT_OP_ENV(avgb1)
1241 IWMMXT_OP_ENV(avgw0)
1242 IWMMXT_OP_ENV(avgw1)
1243
1244 IWMMXT_OP(msadb)
1245
1246 IWMMXT_OP_ENV(packuw)
1247 IWMMXT_OP_ENV(packul)
1248 IWMMXT_OP_ENV(packuq)
1249 IWMMXT_OP_ENV(packsw)
1250 IWMMXT_OP_ENV(packsl)
1251 IWMMXT_OP_ENV(packsq)
1252
1253 static void gen_op_iwmmxt_set_mup(void)
1254 {
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 }
1260
1261 static void gen_op_iwmmxt_set_cup(void)
1262 {
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267 }
1268
1269 static void gen_op_iwmmxt_setpsr_nz(void)
1270 {
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274 }
1275
1276 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277 {
1278 iwmmxt_load_reg(cpu_V1, rn);
1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281 }
1282
1283 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1284 {
1285 int rd;
1286 uint32_t offset;
1287 TCGv tmp;
1288
1289 rd = (insn >> 16) & 0xf;
1290 tmp = load_reg(s, rd);
1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
1296 tcg_gen_addi_i32(tmp, tmp, offset);
1297 else
1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
1300 if (insn & (1 << 21))
1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
1306 tcg_gen_mov_i32(dest, tmp);
1307 if (insn & (1 << 23))
1308 tcg_gen_addi_i32(tmp, tmp, offset);
1309 else
1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315 }
1316
1317 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1318 {
1319 int rd = (insn >> 0) & 0xf;
1320 TCGv tmp;
1321
1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1324 return 1;
1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
1336 return 0;
1337 }
1338
1339 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342 {
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1358 } else { /* TMCRR */
1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
1370 return 1;
1371 }
1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
1377 } else {
1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1382 i = 0;
1383 } else { /* WLDRW wRd */
1384 tmp = gen_ld32(addr, IS_USER(s));
1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
1388 tmp = gen_ld16u(addr, IS_USER(s));
1389 } else { /* WLDRB */
1390 tmp = gen_ld8u(addr, IS_USER(s));
1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st32(tmp, addr, IS_USER(s));
1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1417 gen_st16(tmp, addr, IS_USER(s));
1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1420 gen_st8(tmp, addr, IS_USER(s));
1421 }
1422 }
1423 }
1424 }
1425 dead_tmp(addr);
1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
1682 tmp = load_reg(s, rd);
1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
1688 break;
1689 case 1:
1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
1692 break;
1693 case 2:
1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
1696 break;
1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
1700 }
1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
1714 tmp = new_tmp();
1715 switch ((insn >> 22) & 3) {
1716 case 0:
1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
1723 }
1724 break;
1725 case 1:
1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1732 }
1733 break;
1734 case 2:
1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1737 break;
1738 }
1739 store_reg(s, rd, tmp);
1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1743 return 1;
1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1745 switch ((insn >> 22) & 3) {
1746 case 0:
1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1748 break;
1749 case 1:
1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1751 break;
1752 case 2:
1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1754 break;
1755 }
1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
1765 tmp = load_reg(s, rd);
1766 switch ((insn >> 6) & 3) {
1767 case 0:
1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1769 break;
1770 case 1:
1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1772 break;
1773 case 2:
1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1775 break;
1776 }
1777 dead_tmp(tmp);
1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1783 return 1;
1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 }
1799 break;
1800 case 2:
1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
1803 break;
1804 }
1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1816 break;
1817 case 1:
1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1819 break;
1820 case 2:
1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1831 return 1;
1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 }
1847 break;
1848 case 2:
1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
1851 break;
1852 }
1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
1863 tmp = new_tmp();
1864 switch ((insn >> 22) & 3) {
1865 case 0:
1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1867 break;
1868 case 1:
1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1870 break;
1871 case 2:
1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1873 break;
1874 }
1875 store_reg(s, rd, tmp);
1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
1981 return 1;
1982 }
1983 switch ((insn >> 22) & 3) {
1984 case 1:
1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
1986 break;
1987 case 2:
1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
1989 break;
1990 case 3:
1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
1992 break;
1993 }
1994 dead_tmp(tmp);
1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
2009 return 1;
2010 }
2011 switch ((insn >> 22) & 3) {
2012 case 1:
2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2014 break;
2015 case 2:
2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2017 break;
2018 case 3:
2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2020 break;
2021 }
2022 dead_tmp(tmp);
2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
2037 return 1;
2038 }
2039 switch ((insn >> 22) & 3) {
2040 case 1:
2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2042 break;
2043 case 2:
2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2045 break;
2046 case 3:
2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2048 break;
2049 }
2050 dead_tmp(tmp);
2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
2062 tmp = new_tmp();
2063 switch ((insn >> 22) & 3) {
2064 case 1:
2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
2067 return 1;
2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2070 break;
2071 case 2:
2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
2074 return 1;
2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2077 break;
2078 case 3:
2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
2081 return 1;
2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2084 break;
2085 }
2086 dead_tmp(tmp);
2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
2276 switch ((insn >> 22) & 3) {
2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2315 break;
2316 case 0x8: /* TMIAPH */
2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2320 if (insn & (1 << 16))
2321 tcg_gen_shri_i32(tmp, tmp, 16);
2322 if (insn & (1 << 17))
2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2325 break;
2326 default:
2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
2329 return 1;
2330 }
2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341 }
2342
2343 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346 {
2347 int acc, rd0, rd1, rdhi, rdlo;
2348 TCGv tmp, tmp2;
2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2364 break;
2365 case 0x8: /* MIAPH */
2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
2372 if (insn & (1 << 16))
2373 tcg_gen_shri_i32(tmp, tmp, 16);
2374 if (insn & (1 << 17))
2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2377 break;
2378 default:
2379 return 1;
2380 }
2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2403 } else { /* MAR */
2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411 }
2412
2413 /* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416 {
2417 TCGv tmp, tmp2;
2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
2424 if (insn & ARM_CP_RW_BIT) {
2425 if (!env->cp[cp].cp_read)
2426 return 1;
2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
2432 store_reg(s, rd, tmp);
2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
2441 dead_tmp(tmp);
2442 }
2443 return 0;
2444 }
2445
2446 static int cp15_user_ok(uint32_t insn)
2447 {
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464 }
2465
2466 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467 {
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
2480 switch (op) {
2481 case 2:
2482 tmp = load_cpu_field(cp15.c13_tls1);
2483 break;
2484 case 3:
2485 tmp = load_cpu_field(cp15.c13_tls2);
2486 break;
2487 case 4:
2488 tmp = load_cpu_field(cp15.c13_tls3);
2489 break;
2490 default:
2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
2499 store_cpu_field(tmp, cp15.c13_tls1);
2500 break;
2501 case 3:
2502 store_cpu_field(tmp, cp15.c13_tls2);
2503 break;
2504 case 4:
2505 store_cpu_field(tmp, cp15.c13_tls3);
2506 break;
2507 default:
2508 dead_tmp(tmp);
2509 return 0;
2510 }
2511 }
2512 return 1;
2513 }
2514
2515 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
2517 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2518 {
2519 uint32_t rd;
2520 TCGv tmp, tmp2;
2521
2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
2539 return 1;
2540 }
2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
2544 gen_set_pc_im(s->pc);
2545 s->is_jmp = DISAS_WFI;
2546 return 0;
2547 }
2548 rd = (insn >> 12) & 0xf;
2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
2553 tmp2 = tcg_const_i32(insn);
2554 if (insn & ARM_CP_RW_BIT) {
2555 tmp = new_tmp();
2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
2562 } else {
2563 tmp = load_reg(s, rd);
2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2565 dead_tmp(tmp);
2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
2572 }
2573 tcg_temp_free_i32(tmp2);
2574 return 0;
2575 }
2576
2577 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578 #define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
2597 /* Move between integer and VFP cores. */
2598 static TCGv gen_vfp_mrs(void)
2599 {
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603 }
2604
2605 static void gen_vfp_msr(TCGv tmp)
2606 {
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609 }
2610
2611 static void gen_neon_dup_u8(TCGv var, int shift)
2612 {
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
2616 tcg_gen_ext8u_i32(var, var);
2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622 }
2623
2624 static void gen_neon_dup_low16(TCGv var)
2625 {
2626 TCGv tmp = new_tmp();
2627 tcg_gen_ext16u_i32(var, var);
2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631 }
2632
2633 static void gen_neon_dup_high16(TCGv var)
2634 {
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640 }
2641
2642 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645 {
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
2648 TCGv addr;
2649 TCGv tmp;
2650 TCGv tmp2;
2651
2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
2655 if (!s->vfp_enabled) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2662 return 1;
2663 }
2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
2676 return 1;
2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
2692 if (insn & ARM_CP_RW_BIT) {
2693 /* vfp->arm */
2694 tmp = neon_load_reg(rn, pass);
2695 switch (size) {
2696 case 0:
2697 if (offset)
2698 tcg_gen_shri_i32(tmp, tmp, offset);
2699 if (insn & (1 << 23))
2700 gen_uxtb(tmp);
2701 else
2702 gen_sxtb(tmp);
2703 break;
2704 case 1:
2705 if (insn & (1 << 23)) {
2706 if (offset) {
2707 tcg_gen_shri_i32(tmp, tmp, 16);
2708 } else {
2709 gen_uxth(tmp);
2710 }
2711 } else {
2712 if (offset) {
2713 tcg_gen_sari_i32(tmp, tmp, 16);
2714 } else {
2715 gen_sxth(tmp);
2716 }
2717 }
2718 break;
2719 case 2:
2720 break;
2721 }
2722 store_reg(s, rd, tmp);
2723 } else {
2724 /* arm->vfp */
2725 tmp = load_reg(s, rd);
2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
2729 gen_neon_dup_u8(tmp, 0);
2730 } else if (size == 1) {
2731 gen_neon_dup_low16(tmp);
2732 }
2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
2746 break;
2747 case 1:
2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
2751 break;
2752 case 2:
2753 break;
2754 }
2755 neon_store_reg(rn, pass, tmp);
2756 }
2757 }
2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
2762 if (insn & ARM_CP_RW_BIT) {
2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
2766 rn >>= 1;
2767
2768 switch (rn) {
2769 case ARM_VFP_FPSID:
2770 /* VFP2 allows access to FSID from userspace.
2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
2776 tmp = load_cpu_field(vfp.xregs[rn]);
2777 break;
2778 case ARM_VFP_FPEXC:
2779 if (IS_USER(s))
2780 return 1;
2781 tmp = load_cpu_field(vfp.xregs[rn]);
2782 break;
2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
2789 tmp = load_cpu_field(vfp.xregs[rn]);
2790 break;
2791 case ARM_VFP_FPSCR:
2792 if (rd == 15) {
2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
2799 break;
2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
2805 tmp = load_cpu_field(vfp.xregs[rn]);
2806 break;
2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
2812 tmp = gen_vfp_mrs();
2813 }
2814 if (rd == 15) {
2815 /* Set the 4 flag bits in the CPSR. */
2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
2821 } else {
2822 /* arm->vfp */
2823 tmp = load_reg(s, rd);
2824 if (insn & (1 << 21)) {
2825 rn >>= 1;
2826 /* system register */
2827 switch (rn) {
2828 case ARM_VFP_FPSID:
2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
2831 /* Writes are ignored. */
2832 break;
2833 case ARM_VFP_FPSCR:
2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
2836 gen_lookup_tb(s);
2837 break;
2838 case ARM_VFP_FPEXC:
2839 if (IS_USER(s))
2840 return 1;
2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2844 store_cpu_field(tmp, vfp.xregs[rn]);
2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
2849 store_cpu_field(tmp, vfp.xregs[rn]);
2850 break;
2851 default:
2852 return 1;
2853 }
2854 } else {
2855 gen_vfp_msr(tmp);
2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
2870 VFP_DREG_N(rn, insn);
2871 }
2872
2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2874 /* Integer or single precision destination. */
2875 rd = VFP_SREG_D(insn);
2876 } else {
2877 VFP_DREG_D(rd, insn);
2878 }
2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
2885 } else {
2886 VFP_DREG_M(rm, insn);
2887 }
2888 } else {
2889 rn = VFP_SREG_N(insn);
2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
2899 rm = VFP_SREG_M(insn);
2900 }
2901
2902 veclen = s->vec_len;
2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
2910
2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
2923 delta_d = (s->vec_stride >> 1) + 1;
2924 else
2925 delta_d = s->vec_stride + 1;
2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
2971 break;
2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
3000 gen_vfp_neg(dp);
3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
3039 tcg_gen_movi_i32(cpu_F0s, n);
3040 }
3041 break;
3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3113 else
3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
3125 gen_vfp_shto(dp, 16 - rm);
3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
3130 gen_vfp_slto(dp, 32 - rm);
3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
3135 gen_vfp_uhto(dp, 16 - rm);
3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
3140 gen_vfp_ulto(dp, 32 - rm);
3141 break;
3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
3157 gen_vfp_tosh(dp, 16 - rm);
3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
3162 gen_vfp_tosl(dp, 32 - rm);
3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_touh(dp, 16 - rm);
3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_toul(dp, 32 - rm);
3173 break;
3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
3244
3245 if (insn & ARM_CP_RW_BIT) {
3246 /* vfp->arm */
3247 if (dp) {
3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
3254 } else {
3255 gen_mov_F0_vreg(0, rm);
3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
3258 gen_mov_F0_vreg(0, rm + 1);
3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
3271 } else {
3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
3274 gen_mov_vreg_F0(0, rm);
3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
3284 VFP_DREG_D(rd, insn);
3285 else
3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
3290 } else {
3291 addr = load_reg(s, rn);
3292 }
3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
3298 tcg_gen_addi_i32(addr, addr, offset);
3299 if (insn & (1 << 20)) {
3300 gen_vfp_ld(s, dp, addr);
3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
3304 gen_vfp_st(s, dp, addr);
3305 }
3306 dead_tmp(addr);
3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
3322 if (insn & ARM_CP_RW_BIT) {
3323 /* load */
3324 gen_vfp_ld(s, dp, addr);
3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
3329 gen_vfp_st(s, dp, addr);
3330 }
3331 tcg_gen_addi_i32(addr, addr, offset);
3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356 }
3357
3358 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3359 {
3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3364 tcg_gen_goto_tb(n);
3365 gen_set_pc_im(dest);
3366 tcg_gen_exit_tb((long)tb + n);
3367 } else {
3368 gen_set_pc_im(dest);
3369 tcg_gen_exit_tb(0);
3370 }
3371 }
3372
3373 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374 {
3375 if (unlikely(s->singlestep_enabled)) {
3376 /* An indirect jump so that we still trigger the debug exception. */
3377 if (s->thumb)
3378 dest |= 1;
3379 gen_bx_im(s, dest);
3380 } else {
3381 gen_goto_tb(s, 0, dest);
3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384 }
3385
3386 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3387 {
3388 if (x)
3389 tcg_gen_sari_i32(t0, t0, 16);
3390 else
3391 gen_sxth(t0);
3392 if (y)
3393 tcg_gen_sari_i32(t1, t1, 16);
3394 else
3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
3397 }
3398
3399 /* Return the mask of PSR bits set by a MSR instruction. */
3400 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
3412
3413 /* Mask out undefined bits. */
3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
3416 mask &= ~(CPSR_E | CPSR_GE);
3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3418 mask &= ~CPSR_IT;
3419 /* Mask out execution state bits. */
3420 if (!spsr)
3421 mask &= ~CPSR_EXEC;
3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
3424 mask &= CPSR_USER;
3425 return mask;
3426 }
3427
3428 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3430 {
3431 TCGv tmp;
3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
3441 store_cpu_field(tmp, spsr);
3442 } else {
3443 gen_set_cpsr(t0, mask);
3444 }
3445 dead_tmp(t0);
3446 gen_lookup_tb(s);
3447 return 0;
3448 }
3449
3450 /* Returns nonzero if access to the PSR is not permitted. */
3451 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452 {
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457 }
3458
3459 /* Generate an old-style exception return. Marks pc as dead. */
3460 static void gen_exception_return(DisasContext *s, TCGv pc)
3461 {
3462 TCGv tmp;
3463 store_reg(s, 15, pc);
3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
3467 s->is_jmp = DISAS_UPDATE;
3468 }
3469
3470 /* Generate a v6 exception return. Marks both values as dead. */
3471 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3472 {
3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
3476 s->is_jmp = DISAS_UPDATE;
3477 }
3478
3479 static inline void
3480 gen_set_condexec (DisasContext *s)
3481 {
3482 if (s->condexec_mask) {
3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
3486 store_cpu_field(tmp, condexec_bits);
3487 }
3488 }
3489
3490 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491 {
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496 }
3497
3498 static void gen_nop_hint(DisasContext *s, int val)
3499 {
3500 switch (val) {
3501 case 3: /* wfi */
3502 gen_set_pc_im(s->pc);
3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511 }
3512
3513 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3514
3515 static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
3516 {
3517 switch (size) {
3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3521 default: return 1;
3522 }
3523 return 0;
3524 }
3525
3526 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3527 {
3528 switch (size) {
3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3532 default: return;
3533 }
3534 }
3535
3536 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3537 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
3542 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3543 switch ((size << 1) | u) { \
3544 case 0: \
3545 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3546 break; \
3547 case 1: \
3548 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3549 break; \
3550 case 2: \
3551 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3552 break; \
3553 case 3: \
3554 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3555 break; \
3556 case 4: \
3557 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3558 break; \
3559 case 5: \
3560 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3561 break; \
3562 default: return 1; \
3563 }} while (0)
3564
3565 #define GEN_NEON_INTEGER_OP(name) do { \
3566 switch ((size << 1) | u) { \
3567 case 0: \
3568 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3569 break; \
3570 case 1: \
3571 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3572 break; \
3573 case 2: \
3574 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3575 break; \
3576 case 3: \
3577 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3578 break; \
3579 case 4: \
3580 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3581 break; \
3582 case 5: \
3583 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3584 break; \
3585 default: return 1; \
3586 }} while (0)
3587
3588 static TCGv neon_load_scratch(int scratch)
3589 {
3590 TCGv tmp = new_tmp();
3591 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3592 return tmp;
3593 }
3594
3595 static void neon_store_scratch(int scratch, TCGv var)
3596 {
3597 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 dead_tmp(var);
3599 }
3600
3601 static inline TCGv neon_get_scalar(int size, int reg)
3602 {
3603 TCGv tmp;
3604 if (size == 1) {
3605 tmp = neon_load_reg(reg & 7, reg >> 4);
3606 if (reg & 8) {
3607 gen_neon_dup_high16(tmp);
3608 } else {
3609 gen_neon_dup_low16(tmp);
3610 }
3611 } else {
3612 tmp = neon_load_reg(reg & 15, reg >> 4);
3613 }
3614 return tmp;
3615 }
3616
3617 static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3618 {
3619 TCGv rd, rm, tmp;
3620
3621 rd = new_tmp();
3622 rm = new_tmp();
3623 tmp = new_tmp();
3624
3625 tcg_gen_andi_i32(rd, t0, 0xff);
3626 tcg_gen_shri_i32(tmp, t0, 8);
3627 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3628 tcg_gen_or_i32(rd, rd, tmp);
3629 tcg_gen_shli_i32(tmp, t1, 16);
3630 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3631 tcg_gen_or_i32(rd, rd, tmp);
3632 tcg_gen_shli_i32(tmp, t1, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3634 tcg_gen_or_i32(rd, rd, tmp);
3635
3636 tcg_gen_shri_i32(rm, t0, 8);
3637 tcg_gen_andi_i32(rm, rm, 0xff);
3638 tcg_gen_shri_i32(tmp, t0, 16);
3639 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3640 tcg_gen_or_i32(rm, rm, tmp);
3641 tcg_gen_shli_i32(tmp, t1, 8);
3642 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3643 tcg_gen_or_i32(rm, rm, tmp);
3644 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3645 tcg_gen_or_i32(t1, rm, tmp);
3646 tcg_gen_mov_i32(t0, rd);
3647
3648 dead_tmp(tmp);
3649 dead_tmp(rm);
3650 dead_tmp(rd);
3651 }
3652
3653 static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3654 {
3655 TCGv rd, rm, tmp;
3656
3657 rd = new_tmp();
3658 rm = new_tmp();
3659 tmp = new_tmp();
3660
3661 tcg_gen_andi_i32(rd, t0, 0xff);
3662 tcg_gen_shli_i32(tmp, t1, 8);
3663 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3664 tcg_gen_or_i32(rd, rd, tmp);
3665 tcg_gen_shli_i32(tmp, t0, 16);
3666 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3667 tcg_gen_or_i32(rd, rd, tmp);
3668 tcg_gen_shli_i32(tmp, t1, 24);
3669 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3670 tcg_gen_or_i32(rd, rd, tmp);
3671
3672 tcg_gen_andi_i32(rm, t1, 0xff000000);
3673 tcg_gen_shri_i32(tmp, t0, 8);
3674 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3675 tcg_gen_or_i32(rm, rm, tmp);
3676 tcg_gen_shri_i32(tmp, t1, 8);
3677 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3678 tcg_gen_or_i32(rm, rm, tmp);
3679 tcg_gen_shri_i32(tmp, t0, 16);
3680 tcg_gen_andi_i32(tmp, tmp, 0xff);
3681 tcg_gen_or_i32(t1, rm, tmp);
3682 tcg_gen_mov_i32(t0, rd);
3683
3684 dead_tmp(tmp);
3685 dead_tmp(rm);
3686 dead_tmp(rd);
3687 }
3688
3689 static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3690 {
3691 TCGv tmp, tmp2;
3692
3693 tmp = new_tmp();
3694 tmp2 = new_tmp();
3695
3696 tcg_gen_andi_i32(tmp, t0, 0xffff);
3697 tcg_gen_shli_i32(tmp2, t1, 16);
3698 tcg_gen_or_i32(tmp, tmp, tmp2);
3699 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3700 tcg_gen_shri_i32(tmp2, t0, 16);
3701 tcg_gen_or_i32(t1, t1, tmp2);
3702 tcg_gen_mov_i32(t0, tmp);
3703
3704 dead_tmp(tmp2);
3705 dead_tmp(tmp);
3706 }
3707
3708 static void gen_neon_unzip(int reg, int q, int tmp, int size)
3709 {
3710 int n;
3711 TCGv t0, t1;
3712
3713 for (n = 0; n < q + 1; n += 2) {
3714 t0 = neon_load_reg(reg, n);
3715 t1 = neon_load_reg(reg, n + 1);
3716 switch (size) {
3717 case 0: gen_neon_unzip_u8(t0, t1); break;
3718 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
3719 case 2: /* no-op */; break;
3720 default: abort();
3721 }
3722 neon_store_scratch(tmp + n, t0);
3723 neon_store_scratch(tmp + n + 1, t1);
3724 }
3725 }
3726
3727 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3728 {
3729 TCGv rd, tmp;
3730
3731 rd = new_tmp();
3732 tmp = new_tmp();
3733
3734 tcg_gen_shli_i32(rd, t0, 8);
3735 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3736 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3737 tcg_gen_or_i32(rd, rd, tmp);
3738
3739 tcg_gen_shri_i32(t1, t1, 8);
3740 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3741 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3742 tcg_gen_or_i32(t1, t1, tmp);
3743 tcg_gen_mov_i32(t0, rd);
3744
3745 dead_tmp(tmp);
3746 dead_tmp(rd);
3747 }
3748
3749 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3750 {
3751 TCGv rd, tmp;
3752
3753 rd = new_tmp();
3754 tmp = new_tmp();
3755
3756 tcg_gen_shli_i32(rd, t0, 16);
3757 tcg_gen_andi_i32(tmp, t1, 0xffff);
3758 tcg_gen_or_i32(rd, rd, tmp);
3759 tcg_gen_shri_i32(t1, t1, 16);
3760 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3761 tcg_gen_or_i32(t1, t1, tmp);
3762 tcg_gen_mov_i32(t0, rd);
3763
3764 dead_tmp(tmp);
3765 dead_tmp(rd);
3766 }
3767
3768
3769 static struct {
3770 int nregs;
3771 int interleave;
3772 int spacing;
3773 } neon_ls_element_type[11] = {
3774 {4, 4, 1},
3775 {4, 4, 2},
3776 {4, 1, 1},
3777 {4, 2, 1},
3778 {3, 3, 1},
3779 {3, 3, 2},
3780 {3, 1, 1},
3781 {1, 1, 1},
3782 {2, 2, 1},
3783 {2, 2, 2},
3784 {2, 1, 1}
3785 };
3786
3787 /* Translate a NEON load/store element instruction. Return nonzero if the
3788 instruction is invalid. */
3789 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3790 {
3791 int rd, rn, rm;
3792 int op;
3793 int nregs;
3794 int interleave;
3795 int spacing;
3796 int stride;
3797 int size;
3798 int reg;
3799 int pass;
3800 int load;
3801 int shift;
3802 int n;
3803 TCGv addr;
3804 TCGv tmp;
3805 TCGv tmp2;
3806 TCGv_i64 tmp64;
3807
3808 if (!s->vfp_enabled)
3809 return 1;
3810 VFP_DREG_D(rd, insn);
3811 rn = (insn >> 16) & 0xf;
3812 rm = insn & 0xf;
3813 load = (insn & (1 << 21)) != 0;
3814 addr = new_tmp();
3815 if ((insn & (1 << 23)) == 0) {
3816 /* Load store all elements. */
3817 op = (insn >> 8) & 0xf;
3818 size = (insn >> 6) & 3;
3819 if (op > 10)
3820 return 1;
3821 nregs = neon_ls_element_type[op].nregs;
3822 interleave = neon_ls_element_type[op].interleave;
3823 spacing = neon_ls_element_type[op].spacing;
3824 if (size == 3 && (interleave | spacing) != 1)
3825 return 1;
3826 load_reg_var(s, addr, rn);
3827 stride = (1 << size) * interleave;
3828 for (reg = 0; reg < nregs; reg++) {
3829 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3830 load_reg_var(s, addr, rn);
3831 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3832 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3833 load_reg_var(s, addr, rn);
3834 tcg_gen_addi_i32(addr, addr, 1 << size);
3835 }
3836 if (size == 3) {
3837 if (load) {
3838 tmp64 = gen_ld64(addr, IS_USER(s));
3839 neon_store_reg64(tmp64, rd);
3840 tcg_temp_free_i64(tmp64);
3841 } else {
3842 tmp64 = tcg_temp_new_i64();
3843 neon_load_reg64(tmp64, rd);
3844 gen_st64(tmp64, addr, IS_USER(s));
3845 }
3846 tcg_gen_addi_i32(addr, addr, stride);
3847 } else {
3848 for (pass = 0; pass < 2; pass++) {
3849 if (size == 2) {
3850 if (load) {
3851 tmp = gen_ld32(addr, IS_USER(s));
3852 neon_store_reg(rd, pass, tmp);
3853 } else {
3854 tmp = neon_load_reg(rd, pass);
3855 gen_st32(tmp, addr, IS_USER(s));
3856 }
3857 tcg_gen_addi_i32(addr, addr, stride);
3858 } else if (size == 1) {
3859 if (load) {
3860 tmp = gen_ld16u(addr, IS_USER(s));
3861 tcg_gen_addi_i32(addr, addr, stride);
3862 tmp2 = gen_ld16u(addr, IS_USER(s));
3863 tcg_gen_addi_i32(addr, addr, stride);
3864 tcg_gen_shli_i32(tmp2, tmp2, 16);
3865 tcg_gen_or_i32(tmp, tmp, tmp2);
3866 dead_tmp(tmp2);
3867 neon_store_reg(rd, pass, tmp);
3868 } else {
3869 tmp = neon_load_reg(rd, pass);
3870 tmp2 = new_tmp();
3871 tcg_gen_shri_i32(tmp2, tmp, 16);
3872 gen_st16(tmp, addr, IS_USER(s));
3873 tcg_gen_addi_i32(addr, addr, stride);
3874 gen_st16(tmp2, addr, IS_USER(s));
3875 tcg_gen_addi_i32(addr, addr, stride);
3876 }
3877 } else /* size == 0 */ {
3878 if (load) {
3879 TCGV_UNUSED(tmp2);
3880 for (n = 0; n < 4; n++) {
3881 tmp = gen_ld8u(addr, IS_USER(s));
3882 tcg_gen_addi_i32(addr, addr, stride);
3883 if (n == 0) {
3884 tmp2 = tmp;
3885 } else {
3886 tcg_gen_shli_i32(tmp, tmp, n * 8);
3887 tcg_gen_or_i32(tmp2, tmp2, tmp);
3888 dead_tmp(tmp);
3889 }
3890 }
3891 neon_store_reg(rd, pass, tmp2);
3892 } else {
3893 tmp2 = neon_load_reg(rd, pass);
3894 for (n = 0; n < 4; n++) {
3895 tmp = new_tmp();
3896 if (n == 0) {
3897 tcg_gen_mov_i32(tmp, tmp2);
3898 } else {
3899 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3900 }
3901 gen_st8(tmp, addr, IS_USER(s));
3902 tcg_gen_addi_i32(addr, addr, stride);
3903 }
3904 dead_tmp(tmp2);
3905 }
3906 }
3907 }
3908 }
3909 rd += spacing;
3910 }
3911 stride = nregs * 8;
3912 } else {
3913 size = (insn >> 10) & 3;
3914 if (size == 3) {
3915 /* Load single element to all lanes. */
3916 if (!load)
3917 return 1;
3918 size = (insn >> 6) & 3;
3919 nregs = ((insn >> 8) & 3) + 1;
3920 stride = (insn & (1 << 5)) ? 2 : 1;
3921 load_reg_var(s, addr, rn);
3922 for (reg = 0; reg < nregs; reg++) {
3923 switch (size) {
3924 case 0:
3925 tmp = gen_ld8u(addr, IS_USER(s));
3926 gen_neon_dup_u8(tmp, 0);
3927 break;
3928 case 1:
3929 tmp = gen_ld16u(addr, IS_USER(s));
3930 gen_neon_dup_low16(tmp);
3931 break;
3932 case 2:
3933 tmp = gen_ld32(addr, IS_USER(s));
3934 break;
3935 case 3:
3936 return 1;
3937 default: /* Avoid compiler warnings. */
3938 abort();
3939 }
3940 tcg_gen_addi_i32(addr, addr, 1 << size);
3941 tmp2 = new_tmp();
3942 tcg_gen_mov_i32(tmp2, tmp);
3943 neon_store_reg(rd, 0, tmp2);
3944 neon_store_reg(rd, 1, tmp);
3945 rd += stride;
3946 }
3947 stride = (1 << size) * nregs;
3948 } else {
3949 /* Single element. */
3950 pass = (insn >> 7) & 1;
3951 switch (size) {
3952 case 0:
3953 shift = ((insn >> 5) & 3) * 8;
3954 stride = 1;
3955 break;
3956 case 1:
3957 shift = ((insn >> 6) & 1) * 16;
3958 stride = (insn & (1 << 5)) ? 2 : 1;
3959 break;
3960 case 2:
3961 shift = 0;
3962 stride = (insn & (1 << 6)) ? 2 : 1;
3963 break;
3964 default:
3965 abort();
3966 }
3967 nregs = ((insn >> 8) & 3) + 1;
3968 load_reg_var(s, addr, rn);
3969 for (reg = 0; reg < nregs; reg++) {
3970 if (load) {
3971 switch (size) {
3972 case 0:
3973 tmp = gen_ld8u(addr, IS_USER(s));
3974 break;
3975 case 1:
3976 tmp = gen_ld16u(addr, IS_USER(s));
3977 break;
3978 case 2:
3979 tmp = gen_ld32(addr, IS_USER(s));
3980 break;
3981 default: /* Avoid compiler warnings. */
3982 abort();
3983 }
3984 if (size != 2) {
3985 tmp2 = neon_load_reg(rd, pass);
3986 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3987 dead_tmp(tmp2);
3988 }
3989 neon_store_reg(rd, pass, tmp);
3990 } else { /* Store */
3991 tmp = neon_load_reg(rd, pass);
3992 if (shift)
3993 tcg_gen_shri_i32(tmp, tmp, shift);
3994 switch (size) {
3995 case 0:
3996 gen_st8(tmp, addr, IS_USER(s));
3997 break;
3998 case 1:
3999 gen_st16(tmp, addr, IS_USER(s));
4000 break;
4001 case 2:
4002 gen_st32(tmp, addr, IS_USER(s));
4003 break;
4004 }
4005 }
4006 rd += stride;
4007 tcg_gen_addi_i32(addr, addr, 1 << size);
4008 }
4009 stride = nregs * (1 << size);
4010 }
4011 }
4012 dead_tmp(addr);
4013 if (rm != 15) {
4014 TCGv base;
4015
4016 base = load_reg(s, rn);
4017 if (rm == 13) {
4018 tcg_gen_addi_i32(base, base, stride);
4019 } else {
4020 TCGv index;
4021 index = load_reg(s, rm);
4022 tcg_gen_add_i32(base, base, index);
4023 dead_tmp(index);
4024 }
4025 store_reg(s, rn, base);
4026 }
4027 return 0;
4028 }
4029
4030 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4031 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4032 {
4033 tcg_gen_and_i32(t, t, c);
4034 tcg_gen_andc_i32(f, f, c);
4035 tcg_gen_or_i32(dest, t, f);
4036 }
4037
4038 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4039 {
4040 switch (size) {
4041 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4042 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4043 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4044 default: abort();
4045 }
4046 }
4047
4048 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4049 {
4050 switch (size) {
4051 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4052 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4053 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4054 default: abort();
4055 }
4056 }
4057
4058 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4059 {
4060 switch (size) {
4061 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4062 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4063 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4064 default: abort();
4065 }
4066 }
4067
4068 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4069 int q, int u)
4070 {
4071 if (q) {
4072 if (u) {
4073 switch (size) {
4074 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4075 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4076 default: abort();
4077 }
4078 } else {
4079 switch (size) {
4080 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4081 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4082 default: abort();
4083 }
4084 }
4085 } else {
4086 if (u) {
4087 switch (size) {
4088 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4089 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4090 default: abort();
4091 }
4092 } else {
4093 switch (size) {
4094 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4095 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4096 default: abort();
4097 }
4098 }
4099 }
4100 }
4101
4102 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4103 {
4104 if (u) {
4105 switch (size) {
4106 case 0: gen_helper_neon_widen_u8(dest, src); break;
4107 case 1: gen_helper_neon_widen_u16(dest, src); break;
4108 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4109 default: abort();
4110 }
4111 } else {
4112 switch (size) {
4113 case 0: gen_helper_neon_widen_s8(dest, src); break;
4114 case 1: gen_helper_neon_widen_s16(dest, src); break;
4115 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4116 default: abort();
4117 }
4118 }
4119 dead_tmp(src);
4120 }
4121
4122 static inline void gen_neon_addl(int size)
4123 {
4124 switch (size) {
4125 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4126 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4127 case 2: tcg_gen_add_i64(CPU_V001); break;
4128 default: abort();
4129 }
4130 }
4131
4132 static inline void gen_neon_subl(int size)
4133 {
4134 switch (size) {
4135 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4136 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4137 case 2: tcg_gen_sub_i64(CPU_V001); break;
4138 default: abort();
4139 }
4140 }
4141
4142 static inline void gen_neon_negl(TCGv_i64 var, int size)
4143 {
4144 switch (size) {
4145 case 0: gen_helper_neon_negl_u16(var, var); break;
4146 case 1: gen_helper_neon_negl_u32(var, var); break;
4147 case 2: gen_helper_neon_negl_u64(var, var); break;
4148 default: abort();
4149 }
4150 }
4151
4152 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4153 {
4154 switch (size) {
4155 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4156 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4157 default: abort();
4158 }
4159 }
4160
4161 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4162 {
4163 TCGv_i64 tmp;
4164
4165 switch ((size << 1) | u) {
4166 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4167 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4168 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4169 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4170 case 4:
4171 tmp = gen_muls_i64_i32(a, b);
4172 tcg_gen_mov_i64(dest, tmp);
4173 break;
4174 case 5:
4175 tmp = gen_mulu_i64_i32(a, b);
4176 tcg_gen_mov_i64(dest, tmp);
4177 break;
4178 default: abort();
4179 }
4180
4181 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4182 Don't forget to clean them now. */
4183 if (size < 2) {
4184 dead_tmp(a);
4185 dead_tmp(b);
4186 }
4187 }
4188
4189 /* Translate a NEON data processing instruction. Return nonzero if the
4190 instruction is invalid.
4191 We process data in a mixture of 32-bit and 64-bit chunks.
4192 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4193
4194 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4195 {
4196 int op;
4197 int q;
4198 int rd, rn, rm;
4199 int size;
4200 int shift;
4201 int pass;
4202 int count;
4203 int pairwise;
4204 int u;
4205 int n;
4206 uint32_t imm, mask;
4207 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4208 TCGv_i64 tmp64;
4209
4210 if (!s->vfp_enabled)
4211 return 1;
4212 q = (insn & (1 << 6)) != 0;
4213 u = (insn >> 24) & 1;
4214 VFP_DREG_D(rd, insn);
4215 VFP_DREG_N(rn, insn);
4216 VFP_DREG_M(rm, insn);
4217 size = (insn >> 20) & 3;
4218 if ((insn & (1 << 23)) == 0) {
4219 /* Three register same length. */
4220 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4221 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4222 || op == 10 || op == 11 || op == 16)) {
4223 /* 64-bit element instructions. */
4224 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4225 neon_load_reg64(cpu_V0, rn + pass);
4226 neon_load_reg64(cpu_V1, rm + pass);
4227 switch (op) {
4228 case 1: /* VQADD */
4229 if (u) {
4230 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4231 cpu_V0, cpu_V1);
4232 } else {
4233 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4234 cpu_V0, cpu_V1);
4235 }
4236 break;
4237 case 5: /* VQSUB */
4238 if (u) {
4239 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4240 cpu_V0, cpu_V1);
4241 } else {
4242 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4243 cpu_V0, cpu_V1);
4244 }
4245 break;
4246 case 8: /* VSHL */
4247 if (u) {
4248 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4249 } else {
4250 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4251 }
4252 break;
4253 case 9: /* VQSHL */
4254 if (u) {
4255 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4256 cpu_V1, cpu_V0);
4257 } else {
4258 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4259 cpu_V1, cpu_V0);
4260 }
4261 break;
4262 case 10: /* VRSHL */
4263 if (u) {
4264 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4265 } else {
4266 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4267 }
4268 break;
4269 case 11: /* VQRSHL */
4270 if (u) {
4271 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4272 cpu_V1, cpu_V0);
4273 } else {
4274 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4275 cpu_V1, cpu_V0);
4276 }
4277 break;
4278 case 16:
4279 if (u) {
4280 tcg_gen_sub_i64(CPU_V001);
4281 } else {
4282 tcg_gen_add_i64(CPU_V001);
4283 }
4284 break;
4285 default:
4286 abort();
4287 }
4288 neon_store_reg64(cpu_V0, rd + pass);
4289 }
4290 return 0;
4291 }
4292 switch (op) {
4293 case 8: /* VSHL */
4294 case 9: /* VQSHL */
4295 case 10: /* VRSHL */
4296 case 11: /* VQRSHL */
4297 {
4298 int rtmp;
4299 /* Shift instruction operands are reversed. */
4300 rtmp = rn;
4301 rn = rm;
4302 rm = rtmp;
4303 pairwise = 0;
4304 }
4305 break;
4306 case 20: /* VPMAX */
4307 case 21: /* VPMIN */
4308 case 23: /* VPADD */
4309 pairwise = 1;
4310 break;
4311 case 26: /* VPADD (float) */
4312 pairwise = (u && size < 2);
4313 break;
4314 case 30: /* VPMIN/VPMAX (float) */
4315 pairwise = u;
4316 break;
4317 default:
4318 pairwise = 0;
4319 break;
4320 }
4321
4322 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4323
4324 if (pairwise) {
4325 /* Pairwise. */
4326 if (q)
4327 n = (pass & 1) * 2;
4328 else
4329 n = 0;
4330 if (pass < q + 1) {
4331 tmp = neon_load_reg(rn, n);
4332 tmp2 = neon_load_reg(rn, n + 1);
4333 } else {
4334 tmp = neon_load_reg(rm, n);
4335 tmp2 = neon_load_reg(rm, n + 1);
4336 }
4337 } else {
4338 /* Elementwise. */
4339 tmp = neon_load_reg(rn, pass);
4340 tmp2 = neon_load_reg(rm, pass);
4341 }
4342 switch (op) {
4343 case 0: /* VHADD */
4344 GEN_NEON_INTEGER_OP(hadd);
4345 break;
4346 case 1: /* VQADD */
4347 GEN_NEON_INTEGER_OP_ENV(qadd);
4348 break;
4349 case 2: /* VRHADD */
4350 GEN_NEON_INTEGER_OP(rhadd);
4351 break;
4352 case 3: /* Logic ops. */
4353 switch ((u << 2) | size) {
4354 case 0: /* VAND */
4355 tcg_gen_and_i32(tmp, tmp, tmp2);
4356 break;
4357 case 1: /* BIC */
4358 tcg_gen_andc_i32(tmp, tmp, tmp2);
4359 break;
4360 case 2: /* VORR */
4361 tcg_gen_or_i32(tmp, tmp, tmp2);
4362 break;
4363 case 3: /* VORN */
4364 tcg_gen_orc_i32(tmp, tmp, tmp2);
4365 break;
4366 case 4: /* VEOR */
4367 tcg_gen_xor_i32(tmp, tmp, tmp2);
4368 break;
4369 case 5: /* VBSL */
4370 tmp3 = neon_load_reg(rd, pass);
4371 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4372 dead_tmp(tmp3);
4373 break;
4374 case 6: /* VBIT */
4375 tmp3 = neon_load_reg(rd, pass);
4376 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4377 dead_tmp(tmp3);
4378 break;
4379 case 7: /* VBIF */
4380 tmp3 = neon_load_reg(rd, pass);
4381 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4382 dead_tmp(tmp3);
4383 break;
4384 }
4385 break;
4386 case 4: /* VHSUB */
4387 GEN_NEON_INTEGER_OP(hsub);
4388 break;
4389 case 5: /* VQSUB */
4390 GEN_NEON_INTEGER_OP_ENV(qsub);
4391 break;
4392 case 6: /* VCGT */
4393 GEN_NEON_INTEGER_OP(cgt);
4394 break;
4395 case 7: /* VCGE */
4396 GEN_NEON_INTEGER_OP(cge);
4397 break;
4398 case 8: /* VSHL */
4399 GEN_NEON_INTEGER_OP(shl);
4400 break;
4401 case 9: /* VQSHL */
4402 GEN_NEON_INTEGER_OP_ENV(qshl);
4403 break;
4404 case 10: /* VRSHL */
4405 GEN_NEON_INTEGER_OP(rshl);
4406 break;
4407 case 11: /* VQRSHL */
4408 GEN_NEON_INTEGER_OP_ENV(qrshl);
4409 break;
4410 case 12: /* VMAX */
4411 GEN_NEON_INTEGER_OP(max);
4412 break;
4413 case 13: /* VMIN */
4414 GEN_NEON_INTEGER_OP(min);
4415 break;
4416 case 14: /* VABD */
4417 GEN_NEON_INTEGER_OP(abd);
4418 break;
4419 case 15: /* VABA */
4420 GEN_NEON_INTEGER_OP(abd);
4421 dead_tmp(tmp2);
4422 tmp2 = neon_load_reg(rd, pass);
4423 gen_neon_add(size, tmp, tmp2);
4424 break;
4425 case 16:
4426 if (!u) { /* VADD */
4427 if (gen_neon_add(size, tmp, tmp2))
4428 return 1;
4429 } else { /* VSUB */
4430 switch (size) {
4431 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4432 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4433 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4434 default: return 1;
4435 }
4436 }
4437 break;
4438 case 17:
4439 if (!u) { /* VTST */
4440 switch (size) {
4441 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4442 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4443 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4444 default: return 1;
4445 }
4446 } else { /* VCEQ */
4447 switch (size) {
4448 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4449 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4450 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4451 default: return 1;
4452 }
4453 }
4454 break;
4455 case 18: /* Multiply. */
4456 switch (size) {
4457 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4458 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4459 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4460 default: return 1;
4461 }
4462 dead_tmp(tmp2);
4463 tmp2 = neon_load_reg(rd, pass);
4464 if (u) { /* VMLS */
4465 gen_neon_rsb(size, tmp, tmp2);
4466 } else { /* VMLA */
4467 gen_neon_add(size, tmp, tmp2);
4468 }
4469 break;
4470 case 19: /* VMUL */
4471 if (u) { /* polynomial */
4472 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4473 } else { /* Integer */
4474 switch (size) {
4475 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4476 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4477 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4478 default: return 1;
4479 }
4480 }
4481 break;
4482 case 20: /* VPMAX */
4483 GEN_NEON_INTEGER_OP(pmax);
4484 break;
4485 case 21: /* VPMIN */
4486 GEN_NEON_INTEGER_OP(pmin);
4487 break;
4488 case 22: /* Hultiply high. */
4489 if (!u) { /* VQDMULH */
4490 switch (size) {
4491 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4492 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4493 default: return 1;
4494 }
4495 } else { /* VQRDHMUL */
4496 switch (size) {
4497 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4498 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4499 default: return 1;
4500 }
4501 }
4502 break;
4503 case 23: /* VPADD */
4504 if (u)
4505 return 1;
4506 switch (size) {
4507 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4508 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4509 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4510 default: return 1;
4511 }
4512 break;
4513 case 26: /* Floating point arithnetic. */
4514 switch ((u << 2) | size) {
4515 case 0: /* VADD */
4516 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4517 break;
4518 case 2: /* VSUB */
4519 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4520 break;
4521 case 4: /* VPADD */
4522 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4523 break;
4524 case 6: /* VABD */
4525 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4526 break;
4527 default:
4528 return 1;
4529 }
4530 break;
4531 case 27: /* Float multiply. */
4532 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4533 if (!u) {
4534 dead_tmp(tmp2);
4535 tmp2 = neon_load_reg(rd, pass);
4536 if (size == 0) {
4537 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4538 } else {
4539 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4540 }
4541 }
4542 break;
4543 case 28: /* Float compare. */
4544 if (!u) {
4545 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4546 } else {
4547 if (size == 0)
4548 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4549 else
4550 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4551 }
4552 break;
4553 case 29: /* Float compare absolute. */
4554 if (!u)
4555 return 1;
4556 if (size == 0)
4557 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4558 else
4559 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4560 break;
4561 case 30: /* Float min/max. */
4562 if (size == 0)
4563 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4564 else
4565 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4566 break;
4567 case 31:
4568 if (size == 0)
4569 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4570 else
4571 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4572 break;
4573 default:
4574 abort();
4575 }
4576 dead_tmp(tmp2);
4577
4578 /* Save the result. For elementwise operations we can put it
4579 straight into the destination register. For pairwise operations
4580 we have to be careful to avoid clobbering the source operands. */
4581 if (pairwise && rd == rm) {
4582 neon_store_scratch(pass, tmp);
4583 } else {
4584 neon_store_reg(rd, pass, tmp);
4585 }
4586
4587 } /* for pass */
4588 if (pairwise && rd == rm) {
4589 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4590 tmp = neon_load_scratch(pass);
4591 neon_store_reg(rd, pass, tmp);
4592 }
4593 }
4594 /* End of 3 register same size operations. */
4595 } else if (insn & (1 << 4)) {
4596 if ((insn & 0x00380080) != 0) {
4597 /* Two registers and shift. */
4598 op = (insn >> 8) & 0xf;
4599 if (insn & (1 << 7)) {
4600 /* 64-bit shift. */
4601 size = 3;
4602 } else {
4603 size = 2;
4604 while ((insn & (1 << (size + 19))) == 0)
4605 size--;
4606 }
4607 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4608 /* To avoid excessive dumplication of ops we implement shift
4609 by immediate using the variable shift operations. */
4610 if (op < 8) {
4611 /* Shift by immediate:
4612 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4613 /* Right shifts are encoded as N - shift, where N is the
4614 element size in bits. */
4615 if (op <= 4)
4616 shift = shift - (1 << (size + 3));
4617 if (size == 3) {
4618 count = q + 1;
4619 } else {
4620 count = q ? 4: 2;
4621 }
4622 switch (size) {
4623 case 0:
4624 imm = (uint8_t) shift;
4625 imm |= imm << 8;
4626 imm |= imm << 16;
4627 break;
4628 case 1:
4629 imm = (uint16_t) shift;
4630 imm |= imm << 16;
4631 break;
4632 case 2:
4633 case 3:
4634 imm = shift;
4635 break;
4636 default:
4637 abort();
4638 }
4639
4640 for (pass = 0; pass < count; pass++) {
4641 if (size == 3) {
4642 neon_load_reg64(cpu_V0, rm + pass);
4643 tcg_gen_movi_i64(cpu_V1, imm);
4644 switch (op) {
4645 case 0: /* VSHR */
4646 case 1: /* VSRA */
4647 if (u)
4648 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4649 else
4650 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4651 break;
4652 case 2: /* VRSHR */
4653 case 3: /* VRSRA */
4654 if (u)
4655 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4656 else
4657 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4658 break;
4659 case 4: /* VSRI */
4660 if (!u)
4661 return 1;
4662 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4663 break;
4664 case 5: /* VSHL, VSLI */
4665 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4666 break;
4667 case 6: /* VQSHLU */
4668 if (u) {
4669 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4670 cpu_V0, cpu_V1);
4671 } else {
4672 return 1;
4673 }
4674 break;
4675 case 7: /* VQSHL */
4676 if (u) {
4677 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4678 cpu_V0, cpu_V1);
4679 } else {
4680 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4681 cpu_V0, cpu_V1);
4682 }
4683 break;
4684 }
4685 if (op == 1 || op == 3) {
4686 /* Accumulate. */
4687 neon_load_reg64(cpu_V1, rd + pass);
4688 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4689 } else if (op == 4 || (op == 5 && u)) {
4690 /* Insert */
4691 cpu_abort(env, "VS[LR]I.64 not implemented");
4692 }
4693 neon_store_reg64(cpu_V0, rd + pass);
4694 } else { /* size < 3 */
4695 /* Operands in T0 and T1. */
4696 tmp = neon_load_reg(rm, pass);
4697 tmp2 = new_tmp();
4698 tcg_gen_movi_i32(tmp2, imm);
4699 switch (op) {
4700 case 0: /* VSHR */
4701 case 1: /* VSRA */
4702 GEN_NEON_INTEGER_OP(shl);
4703 break;
4704 case 2: /* VRSHR */
4705 case 3: /* VRSRA */
4706 GEN_NEON_INTEGER_OP(rshl);
4707 break;
4708 case 4: /* VSRI */
4709 if (!u)
4710 return 1;
4711 GEN_NEON_INTEGER_OP(shl);
4712 break;
4713 case 5: /* VSHL, VSLI */
4714 switch (size) {
4715 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4716 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4717 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4718 default: return 1;
4719 }
4720 break;
4721 case 6: /* VQSHLU */
4722 if (!u) {
4723 return 1;
4724 }
4725 switch (size) {
4726 case 0:
4727 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4728 tmp, tmp2);
4729 break;
4730 case 1:
4731 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4732 tmp, tmp2);
4733 break;
4734 case 2:
4735 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4736 tmp, tmp2);
4737 break;
4738 default:
4739 return 1;
4740 }
4741 break;
4742 case 7: /* VQSHL */
4743 GEN_NEON_INTEGER_OP_ENV(qshl);
4744 break;
4745 }
4746 dead_tmp(tmp2);
4747
4748 if (op == 1 || op == 3) {
4749 /* Accumulate. */
4750 tmp2 = neon_load_reg(rd, pass);
4751 gen_neon_add(size, tmp, tmp2);
4752 dead_tmp(tmp2);
4753 } else if (op == 4 || (op == 5 && u)) {
4754 /* Insert */
4755 switch (size) {
4756 case 0:
4757 if (op == 4)
4758 mask = 0xff >> -shift;
4759 else
4760 mask = (uint8_t)(0xff << shift);
4761 mask |= mask << 8;
4762 mask |= mask << 16;
4763 break;
4764 case 1:
4765 if (op == 4)
4766 mask = 0xffff >> -shift;
4767 else
4768 mask = (uint16_t)(0xffff << shift);
4769 mask |= mask << 16;
4770 break;
4771 case 2:
4772 if (shift < -31 || shift > 31) {
4773 mask = 0;
4774 } else {
4775 if (op == 4)
4776 mask = 0xffffffffu >> -shift;
4777 else
4778 mask = 0xffffffffu << shift;
4779 }
4780 break;
4781 default:
4782 abort();
4783 }
4784 tmp2 = neon_load_reg(rd, pass);
4785 tcg_gen_andi_i32(tmp, tmp, mask);
4786 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
4787 tcg_gen_or_i32(tmp, tmp, tmp2);
4788 dead_tmp(tmp2);
4789 }
4790 neon_store_reg(rd, pass, tmp);
4791 }
4792 } /* for pass */
4793 } else if (op < 10) {
4794 /* Shift by immediate and narrow:
4795 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4796 shift = shift - (1 << (size + 3));
4797 size++;
4798 switch (size) {
4799 case 1:
4800 imm = (uint16_t)shift;
4801 imm |= imm << 16;
4802 tmp2 = tcg_const_i32(imm);
4803 TCGV_UNUSED_I64(tmp64);
4804 break;
4805 case 2:
4806 imm = (uint32_t)shift;
4807 tmp2 = tcg_const_i32(imm);
4808 TCGV_UNUSED_I64(tmp64);
4809 break;
4810 case 3:
4811 tmp64 = tcg_const_i64(shift);
4812 TCGV_UNUSED(tmp2);
4813 break;
4814 default:
4815 abort();
4816 }
4817
4818 for (pass = 0; pass < 2; pass++) {
4819 if (size == 3) {
4820 neon_load_reg64(cpu_V0, rm + pass);
4821 if (q) {
4822 if (u)
4823 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
4824 else
4825 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
4826 } else {
4827 if (u)
4828 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
4829 else
4830 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
4831 }
4832 } else {
4833 tmp = neon_load_reg(rm + pass, 0);
4834 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4835 tmp3 = neon_load_reg(rm + pass, 1);
4836 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4837 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4838 dead_tmp(tmp);
4839 dead_tmp(tmp3);
4840 }
4841 tmp = new_tmp();
4842 if (op == 8 && !u) {
4843 gen_neon_narrow(size - 1, tmp, cpu_V0);
4844 } else {
4845 if (op == 8)
4846 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4847 else
4848 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4849 }
4850 neon_store_reg(rd, pass, tmp);
4851 } /* for pass */
4852 if (size == 3) {
4853 tcg_temp_free_i64(tmp64);
4854 } else {
4855 tcg_temp_free_i32(tmp2);
4856 }
4857 } else if (op == 10) {
4858 /* VSHLL */
4859 if (q || size == 3)
4860 return 1;
4861 tmp = neon_load_reg(rm, 0);
4862 tmp2 = neon_load_reg(rm, 1);
4863 for (pass = 0; pass < 2; pass++) {
4864 if (pass == 1)
4865 tmp = tmp2;
4866
4867 gen_neon_widen(cpu_V0, tmp, size, u);
4868
4869 if (shift != 0) {
4870 /* The shift is less than the width of the source
4871 type, so we can just shift the whole register. */
4872 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4873 if (size < 2 || !u) {
4874 uint64_t imm64;
4875 if (size == 0) {
4876 imm = (0xffu >> (8 - shift));
4877 imm |= imm << 16;
4878 } else {
4879 imm = 0xffff >> (16 - shift);
4880 }
4881 imm64 = imm | (((uint64_t)imm) << 32);
4882 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
4883 }
4884 }
4885 neon_store_reg64(cpu_V0, rd + pass);
4886 }
4887 } else if (op >= 14) {
4888 /* VCVT fixed-point. */
4889 /* We have already masked out the must-be-1 top bit of imm6,
4890 * hence this 32-shift where the ARM ARM has 64-imm6.
4891 */
4892 shift = 32 - shift;
4893 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4894 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4895 if (!(op & 1)) {
4896 if (u)
4897 gen_vfp_ulto(0, shift);
4898 else
4899 gen_vfp_slto(0, shift);
4900 } else {
4901 if (u)
4902 gen_vfp_toul(0, shift);
4903 else
4904 gen_vfp_tosl(0, shift);
4905 }
4906 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
4907 }
4908 } else {
4909 return 1;
4910 }
4911 } else { /* (insn & 0x00380080) == 0 */
4912 int invert;
4913
4914 op = (insn >> 8) & 0xf;
4915 /* One register and immediate. */
4916 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4917 invert = (insn & (1 << 5)) != 0;
4918 switch (op) {
4919 case 0: case 1:
4920 /* no-op */
4921 break;
4922 case 2: case 3:
4923 imm <<= 8;
4924 break;
4925 case 4: case 5:
4926 imm <<= 16;
4927 break;
4928 case 6: case 7:
4929 imm <<= 24;
4930 break;
4931 case 8: case 9:
4932 imm |= imm << 16;
4933 break;
4934 case 10: case 11:
4935 imm = (imm << 8) | (imm << 24);
4936 break;
4937 case 12:
4938 imm = (imm << 8) | 0xff;
4939 break;
4940 case 13:
4941 imm = (imm << 16) | 0xffff;
4942 break;
4943 case 14:
4944 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4945 if (invert)
4946 imm = ~imm;
4947 break;
4948 case 15:
4949 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4950 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4951 break;
4952 }
4953 if (invert)
4954 imm = ~imm;
4955
4956 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4957 if (op & 1 && op < 12) {
4958 tmp = neon_load_reg(rd, pass);
4959 if (invert) {
4960 /* The immediate value has already been inverted, so
4961 BIC becomes AND. */
4962 tcg_gen_andi_i32(tmp, tmp, imm);
4963 } else {
4964 tcg_gen_ori_i32(tmp, tmp, imm);
4965 }
4966 } else {
4967 /* VMOV, VMVN. */
4968 tmp = new_tmp();
4969 if (op == 14 && invert) {
4970 uint32_t val;
4971 val = 0;
4972 for (n = 0; n < 4; n++) {
4973 if (imm & (1 << (n + (pass & 1) * 4)))
4974 val |= 0xff << (n * 8);
4975 }
4976 tcg_gen_movi_i32(tmp, val);
4977 } else {
4978 tcg_gen_movi_i32(tmp, imm);
4979 }
4980 }
4981 neon_store_reg(rd, pass, tmp);
4982 }
4983 }
4984 } else { /* (insn & 0x00800010 == 0x00800000) */
4985 if (size != 3) {
4986 op = (insn >> 8) & 0xf;
4987 if ((insn & (1 << 6)) == 0) {
4988 /* Three registers of different lengths. */
4989 int src1_wide;
4990 int src2_wide;
4991 int prewiden;
4992 /* prewiden, src1_wide, src2_wide */
4993 static const int neon_3reg_wide[16][3] = {
4994 {1, 0, 0}, /* VADDL */
4995 {1, 1, 0}, /* VADDW */
4996 {1, 0, 0}, /* VSUBL */
4997 {1, 1, 0}, /* VSUBW */
4998 {0, 1, 1}, /* VADDHN */
4999 {0, 0, 0}, /* VABAL */
5000 {0, 1, 1}, /* VSUBHN */
5001 {0, 0, 0}, /* VABDL */
5002 {0, 0, 0}, /* VMLAL */
5003 {0, 0, 0}, /* VQDMLAL */
5004 {0, 0, 0}, /* VMLSL */
5005 {0, 0, 0}, /* VQDMLSL */
5006 {0, 0, 0}, /* Integer VMULL */
5007 {0, 0, 0}, /* VQDMULL */
5008 {0, 0, 0} /* Polynomial VMULL */
5009 };
5010
5011 prewiden = neon_3reg_wide[op][0];
5012 src1_wide = neon_3reg_wide[op][1];
5013 src2_wide = neon_3reg_wide[op][2];
5014
5015 if (size == 0 && (op == 9 || op == 11 || op == 13))
5016 return 1;
5017
5018 /* Avoid overlapping operands. Wide source operands are
5019 always aligned so will never overlap with wide
5020 destinations in problematic ways. */
5021 if (rd == rm && !src2_wide) {
5022 tmp = neon_load_reg(rm, 1);
5023 neon_store_scratch(2, tmp);
5024 } else if (rd == rn && !src1_wide) {
5025 tmp = neon_load_reg(rn, 1);
5026 neon_store_scratch(2, tmp);
5027 }
5028 TCGV_UNUSED(tmp3);
5029 for (pass = 0; pass < 2; pass++) {
5030 if (src1_wide) {
5031 neon_load_reg64(cpu_V0, rn + pass);
5032 TCGV_UNUSED(tmp);
5033 } else {
5034 if (pass == 1 && rd == rn) {
5035 tmp = neon_load_scratch(2);
5036 } else {
5037 tmp = neon_load_reg(rn, pass);
5038 }
5039 if (prewiden) {
5040 gen_neon_widen(cpu_V0, tmp, size, u);
5041 }
5042 }
5043 if (src2_wide) {
5044 neon_load_reg64(cpu_V1, rm + pass);
5045 TCGV_UNUSED(tmp2);
5046 } else {
5047 if (pass == 1 && rd == rm) {
5048 tmp2 = neon_load_scratch(2);
5049 } else {
5050 tmp2 = neon_load_reg(rm, pass);
5051 }
5052 if (prewiden) {
5053 gen_neon_widen(cpu_V1, tmp2, size, u);
5054 }
5055 }
5056 switch (op) {
5057 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5058 gen_neon_addl(size);
5059 break;
5060 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5061 gen_neon_subl(size);
5062 break;
5063 case 5: case 7: /* VABAL, VABDL */
5064 switch ((size << 1) | u) {
5065 case 0:
5066 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5067 break;
5068 case 1:
5069 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5070 break;
5071 case 2:
5072 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5073 break;
5074 case 3:
5075 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5076 break;
5077 case 4:
5078 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5079 break;
5080 case 5:
5081 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5082 break;
5083 default: abort();
5084 }
5085 dead_tmp(tmp2);
5086 dead_tmp(tmp);
5087 break;
5088 case 8: case 9: case 10: case 11: case 12: case 13:
5089 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5090 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5091 break;
5092 case 14: /* Polynomial VMULL */
5093 cpu_abort(env, "Polynomial VMULL not implemented");
5094
5095 default: /* 15 is RESERVED. */
5096 return 1;
5097 }
5098 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5099 /* Accumulate. */
5100 if (op == 10 || op == 11) {
5101 gen_neon_negl(cpu_V0, size);
5102 }
5103
5104 if (op != 13) {
5105 neon_load_reg64(cpu_V1, rd + pass);
5106 }
5107
5108 switch (op) {
5109 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
5110 gen_neon_addl(size);
5111 break;
5112 case 9: case 11: /* VQDMLAL, VQDMLSL */
5113 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5114 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5115 break;
5116 /* Fall through. */
5117 case 13: /* VQDMULL */
5118 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5119 break;
5120 default:
5121 abort();
5122 }
5123 neon_store_reg64(cpu_V0, rd + pass);
5124 } else if (op == 4 || op == 6) {
5125 /* Narrowing operation. */
5126 tmp = new_tmp();
5127 if (!u) {
5128 switch (size) {
5129 case 0:
5130 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5131 break;
5132 case 1:
5133 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5134 break;
5135 case 2:
5136 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5137 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5138 break;
5139 default: abort();
5140 }
5141 } else {
5142 switch (size) {
5143 case 0:
5144 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5145 break;
5146 case 1:
5147 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5148 break;
5149 case 2:
5150 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5151 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5152 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5153 break;
5154 default: abort();
5155 }
5156 }
5157 if (pass == 0) {
5158 tmp3 = tmp;
5159 } else {
5160 neon_store_reg(rd, 0, tmp3);
5161 neon_store_reg(rd, 1, tmp);
5162 }
5163 } else {
5164 /* Write back the result. */
5165 neon_store_reg64(cpu_V0, rd + pass);
5166 }
5167 }
5168 } else {
5169 /* Two registers and a scalar. */
5170 switch (op) {
5171 case 0: /* Integer VMLA scalar */
5172 case 1: /* Float VMLA scalar */
5173 case 4: /* Integer VMLS scalar */
5174 case 5: /* Floating point VMLS scalar */
5175 case 8: /* Integer VMUL scalar */
5176 case 9: /* Floating point VMUL scalar */
5177 case 12: /* VQDMULH scalar */
5178 case 13: /* VQRDMULH scalar */
5179 tmp = neon_get_scalar(size, rm);
5180 neon_store_scratch(0, tmp);
5181 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5182 tmp = neon_load_scratch(0);
5183 tmp2 = neon_load_reg(rn, pass);
5184 if (op == 12) {
5185 if (size == 1) {
5186 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5187 } else {
5188 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5189 }
5190 } else if (op == 13) {
5191 if (size == 1) {
5192 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5193 } else {
5194 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5195 }
5196 } else if (op & 1) {
5197 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5198 } else {
5199 switch (size) {
5200 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5201 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5202 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5203 default: return 1;
5204 }
5205 }
5206 dead_tmp(tmp2);
5207 if (op < 8) {
5208 /* Accumulate. */
5209 tmp2 = neon_load_reg(rd, pass);
5210 switch (op) {
5211 case 0:
5212 gen_neon_add(size, tmp, tmp2);
5213 break;
5214 case 1:
5215 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5216 break;
5217 case 4:
5218 gen_neon_rsb(size, tmp, tmp2);
5219 break;
5220 case 5:
5221 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5222 break;
5223 default:
5224 abort();
5225 }
5226 dead_tmp(tmp2);
5227 }
5228 neon_store_reg(rd, pass, tmp);
5229 }
5230 break;
5231 case 2: /* VMLAL sclar */
5232 case 3: /* VQDMLAL scalar */
5233 case 6: /* VMLSL scalar */
5234 case 7: /* VQDMLSL scalar */
5235 case 10: /* VMULL scalar */
5236 case 11: /* VQDMULL scalar */
5237 if (size == 0 && (op == 3 || op == 7 || op == 11))
5238 return 1;
5239
5240 tmp2 = neon_get_scalar(size, rm);
5241 /* We need a copy of tmp2 because gen_neon_mull
5242 * deletes it during pass 0. */
5243 tmp4 = new_tmp();
5244 tcg_gen_mov_i32(tmp4, tmp2);
5245 tmp3 = neon_load_reg(rn, 1);
5246
5247 for (pass = 0; pass < 2; pass++) {
5248 if (pass == 0) {
5249 tmp = neon_load_reg(rn, 0);
5250 } else {
5251 tmp = tmp3;
5252 tmp2 = tmp4;
5253 }
5254 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5255 if (op == 6 || op == 7) {
5256 gen_neon_negl(cpu_V0, size);
5257 }
5258 if (op != 11) {
5259 neon_load_reg64(cpu_V1, rd + pass);
5260 }
5261 switch (op) {
5262 case 2: case 6:
5263 gen_neon_addl(size);
5264 break;
5265 case 3: case 7:
5266 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5267 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5268 break;
5269 case 10:
5270 /* no-op */
5271 break;
5272 case 11:
5273 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5274 break;
5275 default:
5276 abort();
5277 }
5278 neon_store_reg64(cpu_V0, rd + pass);
5279 }
5280
5281
5282 break;
5283 default: /* 14 and 15 are RESERVED */
5284 return 1;
5285 }
5286 }
5287 } else { /* size == 3 */
5288 if (!u) {
5289 /* Extract. */
5290 imm = (insn >> 8) & 0xf;
5291
5292 if (imm > 7 && !q)
5293 return 1;
5294
5295 if (imm == 0) {
5296 neon_load_reg64(cpu_V0, rn);
5297 if (q) {
5298 neon_load_reg64(cpu_V1, rn + 1);
5299 }
5300 } else if (imm == 8) {
5301 neon_load_reg64(cpu_V0, rn + 1);
5302 if (q) {
5303 neon_load_reg64(cpu_V1, rm);
5304 }
5305 } else if (q) {
5306 tmp64 = tcg_temp_new_i64();
5307 if (imm < 8) {
5308 neon_load_reg64(cpu_V0, rn);
5309 neon_load_reg64(tmp64, rn + 1);
5310 } else {
5311 neon_load_reg64(cpu_V0, rn + 1);
5312 neon_load_reg64(tmp64, rm);
5313 }
5314 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5315 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5316 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5317 if (imm < 8) {
5318 neon_load_reg64(cpu_V1, rm);
5319 } else {
5320 neon_load_reg64(cpu_V1, rm + 1);
5321 imm -= 8;
5322 }
5323 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5324 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5325 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5326 tcg_temp_free_i64(tmp64);
5327 } else {
5328 /* BUGFIX */
5329 neon_load_reg64(cpu_V0, rn);
5330 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5331 neon_load_reg64(cpu_V1, rm);
5332 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5333 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5334 }
5335 neon_store_reg64(cpu_V0, rd);
5336 if (q) {
5337 neon_store_reg64(cpu_V1, rd + 1);
5338 }
5339 } else if ((insn & (1 << 11)) == 0) {
5340 /* Two register misc. */
5341 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5342 size = (insn >> 18) & 3;
5343 switch (op) {
5344 case 0: /* VREV64 */
5345 if (size == 3)
5346 return 1;
5347 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5348 tmp = neon_load_reg(rm, pass * 2);
5349 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5350 switch (size) {
5351 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5352 case 1: gen_swap_half(tmp); break;
5353 case 2: /* no-op */ break;
5354 default: abort();
5355 }
5356 neon_store_reg(rd, pass * 2 + 1, tmp);
5357 if (size == 2) {
5358 neon_store_reg(rd, pass * 2, tmp2);
5359 } else {
5360 switch (size) {
5361 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5362 case 1: gen_swap_half(tmp2); break;
5363 default: abort();
5364 }
5365 neon_store_reg(rd, pass * 2, tmp2);
5366 }
5367 }
5368 break;
5369 case 4: case 5: /* VPADDL */
5370 case 12: case 13: /* VPADAL */
5371 if (size == 3)
5372 return 1;
5373 for (pass = 0; pass < q + 1; pass++) {
5374 tmp = neon_load_reg(rm, pass * 2);
5375 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5376 tmp = neon_load_reg(rm, pass * 2 + 1);
5377 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5378 switch (size) {
5379 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5380 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5381 case 2: tcg_gen_add_i64(CPU_V001); break;
5382 default: abort();
5383 }
5384 if (op >= 12) {
5385 /* Accumulate. */
5386 neon_load_reg64(cpu_V1, rd + pass);
5387 gen_neon_addl(size);
5388 }
5389 neon_store_reg64(cpu_V0, rd + pass);
5390 }
5391 break;
5392 case 33: /* VTRN */
5393 if (size == 2) {
5394 for (n = 0; n < (q ? 4 : 2); n += 2) {
5395 tmp = neon_load_reg(rm, n);
5396 tmp2 = neon_load_reg(rd, n + 1);
5397 neon_store_reg(rm, n, tmp2);
5398 neon_store_reg(rd, n + 1, tmp);
5399 }
5400 } else {
5401 goto elementwise;
5402 }
5403 break;
5404 case 34: /* VUZP */
5405 /* Reg Before After
5406 Rd A3 A2 A1 A0 B2 B0 A2 A0
5407 Rm B3 B2 B1 B0 B3 B1 A3 A1
5408 */
5409 if (size == 3)
5410 return 1;
5411 gen_neon_unzip(rd, q, 0, size);
5412 gen_neon_unzip(rm, q, 4, size);
5413 if (q) {
5414 static int unzip_order_q[8] =
5415 {0, 2, 4, 6, 1, 3, 5, 7};
5416 for (n = 0; n < 8; n++) {
5417 int reg = (n < 4) ? rd : rm;
5418 tmp = neon_load_scratch(unzip_order_q[n]);
5419 neon_store_reg(reg, n % 4, tmp);
5420 }
5421 } else {
5422 static int unzip_order[4] =
5423 {0, 4, 1, 5};
5424 for (n = 0; n < 4; n++) {
5425 int reg = (n < 2) ? rd : rm;
5426 tmp = neon_load_scratch(unzip_order[n]);
5427 neon_store_reg(reg, n % 2, tmp);
5428 }
5429 }
5430 break;
5431 case 35: /* VZIP */
5432 /* Reg Before After
5433 Rd A3 A2 A1 A0 B1 A1 B0 A0
5434 Rm B3 B2 B1 B0 B3 A3 B2 A2
5435 */
5436 if (size == 3)
5437 return 1;
5438 count = (q ? 4 : 2);
5439 for (n = 0; n < count; n++) {
5440 tmp = neon_load_reg(rd, n);
5441 tmp2 = neon_load_reg(rd, n);
5442 switch (size) {
5443 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5444 case 1: gen_neon_zip_u16(tmp, tmp2); break;
5445 case 2: /* no-op */; break;
5446 default: abort();
5447 }
5448 neon_store_scratch(n * 2, tmp);
5449 neon_store_scratch(n * 2 + 1, tmp2);
5450 }
5451 for (n = 0; n < count * 2; n++) {
5452 int reg = (n < count) ? rd : rm;
5453 tmp = neon_load_scratch(n);
5454 neon_store_reg(reg, n % count, tmp);
5455 }
5456 break;
5457 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5458 if (size == 3)
5459 return 1;
5460 TCGV_UNUSED(tmp2);
5461 for (pass = 0; pass < 2; pass++) {
5462 neon_load_reg64(cpu_V0, rm + pass);
5463 tmp = new_tmp();
5464 if (op == 36 && q == 0) {
5465 gen_neon_narrow(size, tmp, cpu_V0);
5466 } else if (q) {
5467 gen_neon_narrow_satu(size, tmp, cpu_V0);
5468 } else {
5469 gen_neon_narrow_sats(size, tmp, cpu_V0);
5470 }
5471 if (pass == 0) {
5472 tmp2 = tmp;
5473 } else {
5474 neon_store_reg(rd, 0, tmp2);
5475 neon_store_reg(rd, 1, tmp);
5476 }
5477 }
5478 break;
5479 case 38: /* VSHLL */
5480 if (q || size == 3)
5481 return 1;
5482 tmp = neon_load_reg(rm, 0);
5483 tmp2 = neon_load_reg(rm, 1);
5484 for (pass = 0; pass < 2; pass++) {
5485 if (pass == 1)
5486 tmp = tmp2;
5487 gen_neon_widen(cpu_V0, tmp, size, 1);
5488 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5489 neon_store_reg64(cpu_V0, rd + pass);
5490 }
5491 break;
5492 case 44: /* VCVT.F16.F32 */
5493 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5494 return 1;
5495 tmp = new_tmp();
5496 tmp2 = new_tmp();
5497 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5498 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5499 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5500 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5501 tcg_gen_shli_i32(tmp2, tmp2, 16);
5502 tcg_gen_or_i32(tmp2, tmp2, tmp);
5503 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5504 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5505 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5506 neon_store_reg(rd, 0, tmp2);
5507 tmp2 = new_tmp();
5508 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5509 tcg_gen_shli_i32(tmp2, tmp2, 16);
5510 tcg_gen_or_i32(tmp2, tmp2, tmp);
5511 neon_store_reg(rd, 1, tmp2);
5512 dead_tmp(tmp);
5513 break;
5514 case 46: /* VCVT.F32.F16 */
5515 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5516 return 1;
5517 tmp3 = new_tmp();
5518 tmp = neon_load_reg(rm, 0);
5519 tmp2 = neon_load_reg(rm, 1);
5520 tcg_gen_ext16u_i32(tmp3, tmp);
5521 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5522 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5523 tcg_gen_shri_i32(tmp3, tmp, 16);
5524 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5525 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5526 dead_tmp(tmp);
5527 tcg_gen_ext16u_i32(tmp3, tmp2);
5528 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5529 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5530 tcg_gen_shri_i32(tmp3, tmp2, 16);
5531 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5532 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5533 dead_tmp(tmp2);
5534 dead_tmp(tmp3);
5535 break;
5536 default:
5537 elementwise:
5538 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5539 if (op == 30 || op == 31 || op >= 58) {
5540 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5541 neon_reg_offset(rm, pass));
5542 TCGV_UNUSED(tmp);
5543 } else {
5544 tmp = neon_load_reg(rm, pass);
5545 }
5546 switch (op) {
5547 case 1: /* VREV32 */
5548 switch (size) {
5549 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5550 case 1: gen_swap_half(tmp); break;
5551 default: return 1;
5552 }
5553 break;
5554 case 2: /* VREV16 */
5555 if (size != 0)
5556 return 1;
5557 gen_rev16(tmp);
5558 break;
5559 case 8: /* CLS */
5560 switch (size) {
5561 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5562 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5563 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5564 default: return 1;
5565 }
5566 break;
5567 case 9: /* CLZ */
5568 switch (size) {
5569 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5570 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5571 case 2: gen_helper_clz(tmp, tmp); break;
5572 default: return 1;
5573 }
5574 break;
5575 case 10: /* CNT */
5576 if (size != 0)
5577 return 1;
5578 gen_helper_neon_cnt_u8(tmp, tmp);
5579 break;
5580 case 11: /* VNOT */
5581 if (size != 0)
5582 return 1;
5583 tcg_gen_not_i32(tmp, tmp);
5584 break;
5585 case 14: /* VQABS */
5586 switch (size) {
5587 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5588 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5589 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
5590 default: return 1;
5591 }
5592 break;
5593 case 15: /* VQNEG */
5594 switch (size) {
5595 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5596 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5597 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
5598 default: return 1;
5599 }
5600 break;
5601 case 16: case 19: /* VCGT #0, VCLE #0 */
5602 tmp2 = tcg_const_i32(0);
5603 switch(size) {
5604 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5605 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5606 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5607 default: return 1;
5608 }
5609 tcg_temp_free(tmp2);
5610 if (op == 19)
5611 tcg_gen_not_i32(tmp, tmp);
5612 break;
5613 case 17: case 20: /* VCGE #0, VCLT #0 */
5614 tmp2 = tcg_const_i32(0);
5615 switch(size) {
5616 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5617 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5618 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5619 default: return 1;
5620 }
5621 tcg_temp_free(tmp2);
5622 if (op == 20)
5623 tcg_gen_not_i32(tmp, tmp);
5624 break;
5625 case 18: /* VCEQ #0 */
5626 tmp2 = tcg_const_i32(0);
5627 switch(size) {
5628 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5629 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5630 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5631 default: return 1;
5632 }
5633 tcg_temp_free(tmp2);
5634 break;
5635 case 22: /* VABS */
5636 switch(size) {
5637 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5638 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5639 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5640 default: return 1;
5641 }
5642 break;
5643 case 23: /* VNEG */
5644 if (size == 3)
5645 return 1;
5646 tmp2 = tcg_const_i32(0);
5647 gen_neon_rsb(size, tmp, tmp2);
5648 tcg_temp_free(tmp2);
5649 break;
5650 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5651 tmp2 = tcg_const_i32(0);
5652 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5653 tcg_temp_free(tmp2);
5654 if (op == 27)
5655 tcg_gen_not_i32(tmp, tmp);
5656 break;
5657 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5658 tmp2 = tcg_const_i32(0);
5659 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5660 tcg_temp_free(tmp2);
5661 if (op == 28)
5662 tcg_gen_not_i32(tmp, tmp);
5663 break;
5664 case 26: /* Float VCEQ #0 */
5665 tmp2 = tcg_const_i32(0);
5666 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5667 tcg_temp_free(tmp2);
5668 break;
5669 case 30: /* Float VABS */
5670 gen_vfp_abs(0);
5671 break;
5672 case 31: /* Float VNEG */
5673 gen_vfp_neg(0);
5674 break;
5675 case 32: /* VSWP */
5676 tmp2 = neon_load_reg(rd, pass);
5677 neon_store_reg(rm, pass, tmp2);
5678 break;
5679 case 33: /* VTRN */
5680 tmp2 = neon_load_reg(rd, pass);
5681 switch (size) {
5682 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5683 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5684 case 2: abort();
5685 default: return 1;
5686 }
5687 neon_store_reg(rm, pass, tmp2);
5688 break;
5689 case 56: /* Integer VRECPE */
5690 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5691 break;
5692 case 57: /* Integer VRSQRTE */
5693 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5694 break;
5695 case 58: /* Float VRECPE */
5696 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5697 break;
5698 case 59: /* Float VRSQRTE */
5699 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5700 break;
5701 case 60: /* VCVT.F32.S32 */
5702 gen_vfp_sito(0);
5703 break;
5704 case 61: /* VCVT.F32.U32 */
5705 gen_vfp_uito(0);
5706 break;
5707 case 62: /* VCVT.S32.F32 */
5708 gen_vfp_tosiz(0);
5709 break;
5710 case 63: /* VCVT.U32.F32 */
5711 gen_vfp_touiz(0);
5712 break;
5713 default:
5714 /* Reserved: 21, 29, 39-56 */
5715 return 1;
5716 }
5717 if (op == 30 || op == 31 || op >= 58) {
5718 tcg_gen_st_f32(cpu_F0s, cpu_env,
5719 neon_reg_offset(rd, pass));
5720 } else {
5721 neon_store_reg(rd, pass, tmp);
5722 }
5723 }
5724 break;
5725 }
5726 } else if ((insn & (1 << 10)) == 0) {
5727 /* VTBL, VTBX. */
5728 n = ((insn >> 5) & 0x18) + 8;
5729 if (insn & (1 << 6)) {
5730 tmp = neon_load_reg(rd, 0);
5731 } else {
5732 tmp = new_tmp();
5733 tcg_gen_movi_i32(tmp, 0);
5734 }
5735 tmp2 = neon_load_reg(rm, 0);
5736 tmp4 = tcg_const_i32(rn);
5737 tmp5 = tcg_const_i32(n);
5738 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5739 dead_tmp(tmp);
5740 if (insn & (1 << 6)) {
5741 tmp = neon_load_reg(rd, 1);
5742 } else {
5743 tmp = new_tmp();
5744 tcg_gen_movi_i32(tmp, 0);
5745 }
5746 tmp3 = neon_load_reg(rm, 1);
5747 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5748 tcg_temp_free_i32(tmp5);
5749 tcg_temp_free_i32(tmp4);
5750 neon_store_reg(rd, 0, tmp2);
5751 neon_store_reg(rd, 1, tmp3);
5752 dead_tmp(tmp);
5753 } else if ((insn & 0x380) == 0) {
5754 /* VDUP */
5755 if (insn & (1 << 19)) {
5756 tmp = neon_load_reg(rm, 1);
5757 } else {
5758 tmp = neon_load_reg(rm, 0);
5759 }
5760 if (insn & (1 << 16)) {
5761 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
5762 } else if (insn & (1 << 17)) {
5763 if ((insn >> 18) & 1)
5764 gen_neon_dup_high16(tmp);
5765 else
5766 gen_neon_dup_low16(tmp);
5767 }
5768 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5769 tmp2 = new_tmp();
5770 tcg_gen_mov_i32(tmp2, tmp);
5771 neon_store_reg(rd, pass, tmp2);
5772 }
5773 dead_tmp(tmp);
5774 } else {
5775 return 1;
5776 }
5777 }
5778 }
5779 return 0;
5780 }
5781
5782 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5783 {
5784 int crn = (insn >> 16) & 0xf;
5785 int crm = insn & 0xf;
5786 int op1 = (insn >> 21) & 7;
5787 int op2 = (insn >> 5) & 7;
5788 int rt = (insn >> 12) & 0xf;
5789 TCGv tmp;
5790
5791 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5792 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5793 /* TEECR */
5794 if (IS_USER(s))
5795 return 1;
5796 tmp = load_cpu_field(teecr);
5797 store_reg(s, rt, tmp);
5798 return 0;
5799 }
5800 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5801 /* TEEHBR */
5802 if (IS_USER(s) && (env->teecr & 1))
5803 return 1;
5804 tmp = load_cpu_field(teehbr);
5805 store_reg(s, rt, tmp);
5806 return 0;
5807 }
5808 }
5809 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5810 op1, crn, crm, op2);
5811 return 1;
5812 }
5813
5814 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5815 {
5816 int crn = (insn >> 16) & 0xf;
5817 int crm = insn & 0xf;
5818 int op1 = (insn >> 21) & 7;
5819 int op2 = (insn >> 5) & 7;
5820 int rt = (insn >> 12) & 0xf;
5821 TCGv tmp;
5822
5823 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5824 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5825 /* TEECR */
5826 if (IS_USER(s))
5827 return 1;
5828 tmp = load_reg(s, rt);
5829 gen_helper_set_teecr(cpu_env, tmp);
5830 dead_tmp(tmp);
5831 return 0;
5832 }
5833 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5834 /* TEEHBR */
5835 if (IS_USER(s) && (env->teecr & 1))
5836 return 1;
5837 tmp = load_reg(s, rt);
5838 store_cpu_field(tmp, teehbr);
5839 return 0;
5840 }
5841 }
5842 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5843 op1, crn, crm, op2);
5844 return 1;
5845 }
5846
5847 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5848 {
5849 int cpnum;
5850
5851 cpnum = (insn >> 8) & 0xf;
5852 if (arm_feature(env, ARM_FEATURE_XSCALE)
5853 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5854 return 1;
5855
5856 switch (cpnum) {
5857 case 0:
5858 case 1:
5859 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5860 return disas_iwmmxt_insn(env, s, insn);
5861 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5862 return disas_dsp_insn(env, s, insn);
5863 }
5864 return 1;
5865 case 10:
5866 case 11:
5867 return disas_vfp_insn (env, s, insn);
5868 case 14:
5869 /* Coprocessors 7-15 are architecturally reserved by ARM.
5870 Unfortunately Intel decided to ignore this. */
5871 if (arm_feature(env, ARM_FEATURE_XSCALE))
5872 goto board;
5873 if (insn & (1 << 20))
5874 return disas_cp14_read(env, s, insn);
5875 else
5876 return disas_cp14_write(env, s, insn);
5877 case 15:
5878 return disas_cp15_insn (env, s, insn);
5879 default:
5880 board:
5881 /* Unknown coprocessor. See if the board has hooked it. */
5882 return disas_cp_insn (env, s, insn);
5883 }
5884 }
5885
5886
5887 /* Store a 64-bit value to a register pair. Clobbers val. */
5888 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5889 {
5890 TCGv tmp;
5891 tmp = new_tmp();
5892 tcg_gen_trunc_i64_i32(tmp, val);
5893 store_reg(s, rlow, tmp);
5894 tmp = new_tmp();
5895 tcg_gen_shri_i64(val, val, 32);
5896 tcg_gen_trunc_i64_i32(tmp, val);
5897 store_reg(s, rhigh, tmp);
5898 }
5899
5900 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5901 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5902 {
5903 TCGv_i64 tmp;
5904 TCGv tmp2;
5905
5906 /* Load value and extend to 64 bits. */
5907 tmp = tcg_temp_new_i64();
5908 tmp2 = load_reg(s, rlow);
5909 tcg_gen_extu_i32_i64(tmp, tmp2);
5910 dead_tmp(tmp2);
5911 tcg_gen_add_i64(val, val, tmp);
5912 tcg_temp_free_i64(tmp);
5913 }
5914
5915 /* load and add a 64-bit value from a register pair. */
5916 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5917 {
5918 TCGv_i64 tmp;
5919 TCGv tmpl;
5920 TCGv tmph;
5921
5922 /* Load 64-bit value rd:rn. */
5923 tmpl = load_reg(s, rlow);
5924 tmph = load_reg(s, rhigh);
5925 tmp = tcg_temp_new_i64();
5926 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5927 dead_tmp(tmpl);
5928 dead_tmp(tmph);
5929 tcg_gen_add_i64(val, val, tmp);
5930 tcg_temp_free_i64(tmp);
5931 }
5932
5933 /* Set N and Z flags from a 64-bit value. */
5934 static void gen_logicq_cc(TCGv_i64 val)
5935 {
5936 TCGv tmp = new_tmp();
5937 gen_helper_logicq_cc(tmp, val);
5938 gen_logic_CC(tmp);
5939 dead_tmp(tmp);
5940 }
5941
5942 /* Load/Store exclusive instructions are implemented by remembering
5943 the value/address loaded, and seeing if these are the same
5944 when the store is performed. This should be is sufficient to implement
5945 the architecturally mandated semantics, and avoids having to monitor
5946 regular stores.
5947
5948 In system emulation mode only one CPU will be running at once, so
5949 this sequence is effectively atomic. In user emulation mode we
5950 throw an exception and handle the atomic operation elsewhere. */
5951 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5952 TCGv addr, int size)
5953 {
5954 TCGv tmp;
5955
5956 switch (size) {
5957 case 0:
5958 tmp = gen_ld8u(addr, IS_USER(s));
5959 break;
5960 case 1:
5961 tmp = gen_ld16u(addr, IS_USER(s));
5962 break;
5963 case 2:
5964 case 3:
5965 tmp = gen_ld32(addr, IS_USER(s));
5966 break;
5967 default:
5968 abort();
5969 }
5970 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5971 store_reg(s, rt, tmp);
5972 if (size == 3) {
5973 TCGv tmp2 = new_tmp();
5974 tcg_gen_addi_i32(tmp2, addr, 4);
5975 tmp = gen_ld32(tmp2, IS_USER(s));
5976 dead_tmp(tmp2);
5977 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5978 store_reg(s, rt2, tmp);
5979 }
5980 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5981 }
5982
5983 static void gen_clrex(DisasContext *s)
5984 {
5985 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5986 }
5987
5988 #ifdef CONFIG_USER_ONLY
5989 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5990 TCGv addr, int size)
5991 {
5992 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5993 tcg_gen_movi_i32(cpu_exclusive_info,
5994 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5995 gen_exception_insn(s, 4, EXCP_STREX);
5996 }
5997 #else
5998 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5999 TCGv addr, int size)
6000 {
6001 TCGv tmp;
6002 int done_label;
6003 int fail_label;
6004
6005 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6006 [addr] = {Rt};
6007 {Rd} = 0;
6008 } else {
6009 {Rd} = 1;
6010 } */
6011 fail_label = gen_new_label();
6012 done_label = gen_new_label();
6013 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6014 switch (size) {
6015 case 0:
6016 tmp = gen_ld8u(addr, IS_USER(s));
6017 break;
6018 case 1:
6019 tmp = gen_ld16u(addr, IS_USER(s));
6020 break;
6021 case 2:
6022 case 3:
6023 tmp = gen_ld32(addr, IS_USER(s));
6024 break;
6025 default:
6026 abort();
6027 }
6028 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6029 dead_tmp(tmp);
6030 if (size == 3) {
6031 TCGv tmp2 = new_tmp();
6032 tcg_gen_addi_i32(tmp2, addr, 4);
6033 tmp = gen_ld32(tmp2, IS_USER(s));
6034 dead_tmp(tmp2);
6035 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6036 dead_tmp(tmp);
6037 }
6038 tmp = load_reg(s, rt);
6039 switch (size) {
6040 case 0:
6041 gen_st8(tmp, addr, IS_USER(s));
6042 break;
6043 case 1:
6044 gen_st16(tmp, addr, IS_USER(s));
6045 break;
6046 case 2:
6047 case 3:
6048 gen_st32(tmp, addr, IS_USER(s));
6049 break;
6050 default:
6051 abort();
6052 }
6053 if (size == 3) {
6054 tcg_gen_addi_i32(addr, addr, 4);
6055 tmp = load_reg(s, rt2);
6056 gen_st32(tmp, addr, IS_USER(s));
6057 }
6058 tcg_gen_movi_i32(cpu_R[rd], 0);
6059 tcg_gen_br(done_label);
6060 gen_set_label(fail_label);
6061 tcg_gen_movi_i32(cpu_R[rd], 1);
6062 gen_set_label(done_label);
6063 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6064 }
6065 #endif
6066
6067 static void disas_arm_insn(CPUState * env, DisasContext *s)
6068 {
6069 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6070 TCGv tmp;
6071 TCGv tmp2;
6072 TCGv tmp3;
6073 TCGv addr;
6074 TCGv_i64 tmp64;
6075
6076 insn = ldl_code(s->pc);
6077 s->pc += 4;
6078
6079 /* M variants do not implement ARM mode. */
6080 if (IS_M(env))
6081 goto illegal_op;
6082 cond = insn >> 28;
6083 if (cond == 0xf){
6084 /* Unconditional instructions. */
6085 if (((insn >> 25) & 7) == 1) {
6086 /* NEON Data processing. */
6087 if (!arm_feature(env, ARM_FEATURE_NEON))
6088 goto illegal_op;
6089
6090 if (disas_neon_data_insn(env, s, insn))
6091 goto illegal_op;
6092 return;
6093 }
6094 if ((insn & 0x0f100000) == 0x04000000) {
6095 /* NEON load/store. */
6096 if (!arm_feature(env, ARM_FEATURE_NEON))
6097 goto illegal_op;
6098
6099 if (disas_neon_ls_insn(env, s, insn))
6100 goto illegal_op;
6101 return;
6102 }
6103 if (((insn & 0x0f30f000) == 0x0510f000) ||
6104 ((insn & 0x0f30f010) == 0x0710f000)) {
6105 if ((insn & (1 << 22)) == 0) {
6106 /* PLDW; v7MP */
6107 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6108 goto illegal_op;
6109 }
6110 }
6111 /* Otherwise PLD; v5TE+ */
6112 return;
6113 }
6114 if (((insn & 0x0f70f000) == 0x0450f000) ||
6115 ((insn & 0x0f70f010) == 0x0650f000)) {
6116 ARCH(7);
6117 return; /* PLI; V7 */
6118 }
6119 if (((insn & 0x0f700000) == 0x04100000) ||
6120 ((insn & 0x0f700010) == 0x06100000)) {
6121 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6122 goto illegal_op;
6123 }
6124 return; /* v7MP: Unallocated memory hint: must NOP */
6125 }
6126
6127 if ((insn & 0x0ffffdff) == 0x01010000) {
6128 ARCH(6);
6129 /* setend */
6130 if (insn & (1 << 9)) {
6131 /* BE8 mode not implemented. */
6132 goto illegal_op;
6133 }
6134 return;
6135 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6136 switch ((insn >> 4) & 0xf) {
6137 case 1: /* clrex */
6138 ARCH(6K);
6139 gen_clrex(s);
6140 return;
6141 case 4: /* dsb */
6142 case 5: /* dmb */
6143 case 6: /* isb */
6144 ARCH(7);
6145 /* We don't emulate caches so these are a no-op. */
6146 return;
6147 default:
6148 goto illegal_op;
6149 }
6150 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6151 /* srs */
6152 int32_t offset;
6153 if (IS_USER(s))
6154 goto illegal_op;
6155 ARCH(6);
6156 op1 = (insn & 0x1f);
6157 addr = new_tmp();
6158 tmp = tcg_const_i32(op1);
6159 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6160 tcg_temp_free_i32(tmp);
6161 i = (insn >> 23) & 3;
6162 switch (i) {
6163 case 0: offset = -4; break; /* DA */
6164 case 1: offset = 0; break; /* IA */
6165 case 2: offset = -8; break; /* DB */
6166 case 3: offset = 4; break; /* IB */
6167 default: abort();
6168 }
6169 if (offset)
6170 tcg_gen_addi_i32(addr, addr, offset);
6171 tmp = load_reg(s, 14);
6172 gen_st32(tmp, addr, 0);
6173 tmp = load_cpu_field(spsr);
6174 tcg_gen_addi_i32(addr, addr, 4);
6175 gen_st32(tmp, addr, 0);
6176 if (insn & (1 << 21)) {
6177 /* Base writeback. */
6178 switch (i) {
6179 case 0: offset = -8; break;
6180 case 1: offset = 4; break;
6181 case 2: offset = -4; break;
6182 case 3: offset = 0; break;
6183 default: abort();
6184 }
6185 if (offset)
6186 tcg_gen_addi_i32(addr, addr, offset);
6187 tmp = tcg_const_i32(op1);
6188 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6189 tcg_temp_free_i32(tmp);
6190 dead_tmp(addr);
6191 } else {
6192 dead_tmp(addr);
6193 }
6194 return;
6195 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6196 /* rfe */
6197 int32_t offset;
6198 if (IS_USER(s))
6199 goto illegal_op;
6200 ARCH(6);
6201 rn = (insn >> 16) & 0xf;
6202 addr = load_reg(s, rn);
6203 i = (insn >> 23) & 3;
6204 switch (i) {
6205 case 0: offset = -4; break; /* DA */
6206 case 1: offset = 0; break; /* IA */
6207 case 2: offset = -8; break; /* DB */
6208 case 3: offset = 4; break; /* IB */
6209 default: abort();
6210 }
6211 if (offset)
6212 tcg_gen_addi_i32(addr, addr, offset);
6213 /* Load PC into tmp and CPSR into tmp2. */
6214 tmp = gen_ld32(addr, 0);
6215 tcg_gen_addi_i32(addr, addr, 4);
6216 tmp2 = gen_ld32(addr, 0);
6217 if (insn & (1 << 21)) {
6218 /* Base writeback. */
6219 switch (i) {
6220 case 0: offset = -8; break;
6221 case 1: offset = 4; break;
6222 case 2: offset = -4; break;
6223 case 3: offset = 0; break;
6224 default: abort();
6225 }
6226 if (offset)
6227 tcg_gen_addi_i32(addr, addr, offset);
6228 store_reg(s, rn, addr);
6229 } else {
6230 dead_tmp(addr);
6231 }
6232 gen_rfe(s, tmp, tmp2);
6233 return;
6234 } else if ((insn & 0x0e000000) == 0x0a000000) {
6235 /* branch link and change to thumb (blx <offset>) */
6236 int32_t offset;
6237
6238 val = (uint32_t)s->pc;
6239 tmp = new_tmp();
6240 tcg_gen_movi_i32(tmp, val);
6241 store_reg(s, 14, tmp);
6242 /* Sign-extend the 24-bit offset */
6243 offset = (((int32_t)insn) << 8) >> 8;
6244 /* offset * 4 + bit24 * 2 + (thumb bit) */
6245 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6246 /* pipeline offset */
6247 val += 4;
6248 gen_bx_im(s, val);
6249 return;
6250 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6251 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6252 /* iWMMXt register transfer. */
6253 if (env->cp15.c15_cpar & (1 << 1))
6254 if (!disas_iwmmxt_insn(env, s, insn))
6255 return;
6256 }
6257 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6258 /* Coprocessor double register transfer. */
6259 } else if ((insn & 0x0f000010) == 0x0e000010) {
6260 /* Additional coprocessor register transfer. */
6261 } else if ((insn & 0x0ff10020) == 0x01000000) {
6262 uint32_t mask;
6263 uint32_t val;
6264 /* cps (privileged) */
6265 if (IS_USER(s))
6266 return;
6267 mask = val = 0;
6268 if (insn & (1 << 19)) {
6269 if (insn & (1 << 8))
6270 mask |= CPSR_A;
6271 if (insn & (1 << 7))
6272 mask |= CPSR_I;
6273 if (insn & (1 << 6))
6274 mask |= CPSR_F;
6275 if (insn & (1 << 18))
6276 val |= mask;
6277 }
6278 if (insn & (1 << 17)) {
6279 mask |= CPSR_M;
6280 val |= (insn & 0x1f);
6281 }
6282 if (mask) {
6283 gen_set_psr_im(s, mask, 0, val);
6284 }
6285 return;
6286 }
6287 goto illegal_op;
6288 }
6289 if (cond != 0xe) {
6290 /* if not always execute, we generate a conditional jump to
6291 next instruction */
6292 s->condlabel = gen_new_label();
6293 gen_test_cc(cond ^ 1, s->condlabel);
6294 s->condjmp = 1;
6295 }
6296 if ((insn & 0x0f900000) == 0x03000000) {
6297 if ((insn & (1 << 21)) == 0) {
6298 ARCH(6T2);
6299 rd = (insn >> 12) & 0xf;
6300 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6301 if ((insn & (1 << 22)) == 0) {
6302 /* MOVW */
6303 tmp = new_tmp();
6304 tcg_gen_movi_i32(tmp, val);
6305 } else {
6306 /* MOVT */
6307 tmp = load_reg(s, rd);
6308 tcg_gen_ext16u_i32(tmp, tmp);
6309 tcg_gen_ori_i32(tmp, tmp, val << 16);
6310 }
6311 store_reg(s, rd, tmp);
6312 } else {
6313 if (((insn >> 12) & 0xf) != 0xf)
6314 goto illegal_op;
6315 if (((insn >> 16) & 0xf) == 0) {
6316 gen_nop_hint(s, insn & 0xff);
6317 } else {
6318 /* CPSR = immediate */
6319 val = insn & 0xff;
6320 shift = ((insn >> 8) & 0xf) * 2;
6321 if (shift)
6322 val = (val >> shift) | (val << (32 - shift));
6323 i = ((insn & (1 << 22)) != 0);
6324 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6325 goto illegal_op;
6326 }
6327 }
6328 } else if ((insn & 0x0f900000) == 0x01000000
6329 && (insn & 0x00000090) != 0x00000090) {
6330 /* miscellaneous instructions */
6331 op1 = (insn >> 21) & 3;
6332 sh = (insn >> 4) & 0xf;
6333 rm = insn & 0xf;
6334 switch (sh) {
6335 case 0x0: /* move program status register */
6336 if (op1 & 1) {
6337 /* PSR = reg */
6338 tmp = load_reg(s, rm);
6339 i = ((op1 & 2) != 0);
6340 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6341 goto illegal_op;
6342 } else {
6343 /* reg = PSR */
6344 rd = (insn >> 12) & 0xf;
6345 if (op1 & 2) {
6346 if (IS_USER(s))
6347 goto illegal_op;
6348 tmp = load_cpu_field(spsr);
6349 } else {
6350 tmp = new_tmp();
6351 gen_helper_cpsr_read(tmp);
6352 }
6353 store_reg(s, rd, tmp);
6354 }
6355 break;
6356 case 0x1:
6357 if (op1 == 1) {
6358 /* branch/exchange thumb (bx). */
6359 tmp = load_reg(s, rm);
6360 gen_bx(s, tmp);
6361 } else if (op1 == 3) {
6362 /* clz */
6363 rd = (insn >> 12) & 0xf;
6364 tmp = load_reg(s, rm);
6365 gen_helper_clz(tmp, tmp);
6366 store_reg(s, rd, tmp);
6367 } else {
6368 goto illegal_op;
6369 }
6370 break;
6371 case 0x2:
6372 if (op1 == 1) {
6373 ARCH(5J); /* bxj */
6374 /* Trivial implementation equivalent to bx. */
6375 tmp = load_reg(s, rm);
6376 gen_bx(s, tmp);
6377 } else {
6378 goto illegal_op;
6379 }
6380 break;
6381 case 0x3:
6382 if (op1 != 1)
6383 goto illegal_op;
6384
6385 /* branch link/exchange thumb (blx) */
6386 tmp = load_reg(s, rm);
6387 tmp2 = new_tmp();
6388 tcg_gen_movi_i32(tmp2, s->pc);
6389 store_reg(s, 14, tmp2);
6390 gen_bx(s, tmp);
6391 break;
6392 case 0x5: /* saturating add/subtract */
6393 rd = (insn >> 12) & 0xf;
6394 rn = (insn >> 16) & 0xf;
6395 tmp = load_reg(s, rm);
6396 tmp2 = load_reg(s, rn);
6397 if (op1 & 2)
6398 gen_helper_double_saturate(tmp2, tmp2);
6399 if (op1 & 1)
6400 gen_helper_sub_saturate(tmp, tmp, tmp2);
6401 else
6402 gen_helper_add_saturate(tmp, tmp, tmp2);
6403 dead_tmp(tmp2);
6404 store_reg(s, rd, tmp);
6405 break;
6406 case 7:
6407 /* SMC instruction (op1 == 3)
6408 and undefined instructions (op1 == 0 || op1 == 2)
6409 will trap */
6410 if (op1 != 1) {
6411 goto illegal_op;
6412 }
6413 /* bkpt */
6414 gen_exception_insn(s, 4, EXCP_BKPT);
6415 break;
6416 case 0x8: /* signed multiply */
6417 case 0xa:
6418 case 0xc:
6419 case 0xe:
6420 rs = (insn >> 8) & 0xf;
6421 rn = (insn >> 12) & 0xf;
6422 rd = (insn >> 16) & 0xf;
6423 if (op1 == 1) {
6424 /* (32 * 16) >> 16 */
6425 tmp = load_reg(s, rm);
6426 tmp2 = load_reg(s, rs);
6427 if (sh & 4)
6428 tcg_gen_sari_i32(tmp2, tmp2, 16);
6429 else
6430 gen_sxth(tmp2);
6431 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6432 tcg_gen_shri_i64(tmp64, tmp64, 16);
6433 tmp = new_tmp();
6434 tcg_gen_trunc_i64_i32(tmp, tmp64);
6435 tcg_temp_free_i64(tmp64);
6436 if ((sh & 2) == 0) {
6437 tmp2 = load_reg(s, rn);
6438 gen_helper_add_setq(tmp, tmp, tmp2);
6439 dead_tmp(tmp2);
6440 }
6441 store_reg(s, rd, tmp);
6442 } else {
6443 /* 16 * 16 */
6444 tmp = load_reg(s, rm);
6445 tmp2 = load_reg(s, rs);
6446 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6447 dead_tmp(tmp2);
6448 if (op1 == 2) {
6449 tmp64 = tcg_temp_new_i64();
6450 tcg_gen_ext_i32_i64(tmp64, tmp);
6451 dead_tmp(tmp);
6452 gen_addq(s, tmp64, rn, rd);
6453 gen_storeq_reg(s, rn, rd, tmp64);
6454 tcg_temp_free_i64(tmp64);
6455 } else {
6456 if (op1 == 0) {
6457 tmp2 = load_reg(s, rn);
6458 gen_helper_add_setq(tmp, tmp, tmp2);
6459 dead_tmp(tmp2);
6460 }
6461 store_reg(s, rd, tmp);
6462 }
6463 }
6464 break;
6465 default:
6466 goto illegal_op;
6467 }
6468 } else if (((insn & 0x0e000000) == 0 &&
6469 (insn & 0x00000090) != 0x90) ||
6470 ((insn & 0x0e000000) == (1 << 25))) {
6471 int set_cc, logic_cc, shiftop;
6472
6473 op1 = (insn >> 21) & 0xf;
6474 set_cc = (insn >> 20) & 1;
6475 logic_cc = table_logic_cc[op1] & set_cc;
6476
6477 /* data processing instruction */
6478 if (insn & (1 << 25)) {
6479 /* immediate operand */
6480 val = insn & 0xff;
6481 shift = ((insn >> 8) & 0xf) * 2;
6482 if (shift) {
6483 val = (val >> shift) | (val << (32 - shift));
6484 }
6485 tmp2 = new_tmp();
6486 tcg_gen_movi_i32(tmp2, val);
6487 if (logic_cc && shift) {
6488 gen_set_CF_bit31(tmp2);
6489 }
6490 } else {
6491 /* register */
6492 rm = (insn) & 0xf;
6493 tmp2 = load_reg(s, rm);
6494 shiftop = (insn >> 5) & 3;
6495 if (!(insn & (1 << 4))) {
6496 shift = (insn >> 7) & 0x1f;
6497 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6498 } else {
6499 rs = (insn >> 8) & 0xf;
6500 tmp = load_reg(s, rs);
6501 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6502 }
6503 }
6504 if (op1 != 0x0f && op1 != 0x0d) {
6505 rn = (insn >> 16) & 0xf;
6506 tmp = load_reg(s, rn);
6507 } else {
6508 TCGV_UNUSED(tmp);
6509 }
6510 rd = (insn >> 12) & 0xf;
6511 switch(op1) {
6512 case 0x00:
6513 tcg_gen_and_i32(tmp, tmp, tmp2);
6514 if (logic_cc) {
6515 gen_logic_CC(tmp);
6516 }
6517 store_reg_bx(env, s, rd, tmp);
6518 break;
6519 case 0x01:
6520 tcg_gen_xor_i32(tmp, tmp, tmp2);
6521 if (logic_cc) {
6522 gen_logic_CC(tmp);
6523 }
6524 store_reg_bx(env, s, rd, tmp);
6525 break;
6526 case 0x02:
6527 if (set_cc && rd == 15) {
6528 /* SUBS r15, ... is used for exception return. */
6529 if (IS_USER(s)) {
6530 goto illegal_op;
6531 }
6532 gen_helper_sub_cc(tmp, tmp, tmp2);
6533 gen_exception_return(s, tmp);
6534 } else {
6535 if (set_cc) {
6536 gen_helper_sub_cc(tmp, tmp, tmp2);
6537 } else {
6538 tcg_gen_sub_i32(tmp, tmp, tmp2);
6539 }
6540 store_reg_bx(env, s, rd, tmp);
6541 }
6542 break;
6543 case 0x03:
6544 if (set_cc) {
6545 gen_helper_sub_cc(tmp, tmp2, tmp);
6546 } else {
6547 tcg_gen_sub_i32(tmp, tmp2, tmp);
6548 }
6549 store_reg_bx(env, s, rd, tmp);
6550 break;
6551 case 0x04:
6552 if (set_cc) {
6553 gen_helper_add_cc(tmp, tmp, tmp2);
6554 } else {
6555 tcg_gen_add_i32(tmp, tmp, tmp2);
6556 }
6557 store_reg_bx(env, s, rd, tmp);
6558 break;
6559 case 0x05:
6560 if (set_cc) {
6561 gen_helper_adc_cc(tmp, tmp, tmp2);
6562 } else {
6563 gen_add_carry(tmp, tmp, tmp2);
6564 }
6565 store_reg_bx(env, s, rd, tmp);
6566 break;
6567 case 0x06:
6568 if (set_cc) {
6569 gen_helper_sbc_cc(tmp, tmp, tmp2);
6570 } else {
6571 gen_sub_carry(tmp, tmp, tmp2);
6572 }
6573 store_reg_bx(env, s, rd, tmp);
6574 break;
6575 case 0x07:
6576 if (set_cc) {
6577 gen_helper_sbc_cc(tmp, tmp2, tmp);
6578 } else {
6579 gen_sub_carry(tmp, tmp2, tmp);
6580 }
6581 store_reg_bx(env, s, rd, tmp);
6582 break;
6583 case 0x08:
6584 if (set_cc) {
6585 tcg_gen_and_i32(tmp, tmp, tmp2);
6586 gen_logic_CC(tmp);
6587 }
6588 dead_tmp(tmp);
6589 break;
6590 case 0x09:
6591 if (set_cc) {
6592 tcg_gen_xor_i32(tmp, tmp, tmp2);
6593 gen_logic_CC(tmp);
6594 }
6595 dead_tmp(tmp);
6596 break;
6597 case 0x0a:
6598 if (set_cc) {
6599 gen_helper_sub_cc(tmp, tmp, tmp2);
6600 }
6601 dead_tmp(tmp);
6602 break;
6603 case 0x0b:
6604 if (set_cc) {
6605 gen_helper_add_cc(tmp, tmp, tmp2);
6606 }
6607 dead_tmp(tmp);
6608 break;
6609 case 0x0c:
6610 tcg_gen_or_i32(tmp, tmp, tmp2);
6611 if (logic_cc) {
6612 gen_logic_CC(tmp);
6613 }
6614 store_reg_bx(env, s, rd, tmp);
6615 break;
6616 case 0x0d:
6617 if (logic_cc && rd == 15) {
6618 /* MOVS r15, ... is used for exception return. */
6619 if (IS_USER(s)) {
6620 goto illegal_op;
6621 }
6622 gen_exception_return(s, tmp2);
6623 } else {
6624 if (logic_cc) {
6625 gen_logic_CC(tmp2);
6626 }
6627 store_reg_bx(env, s, rd, tmp2);
6628 }
6629 break;
6630 case 0x0e:
6631 tcg_gen_andc_i32(tmp, tmp, tmp2);
6632 if (logic_cc) {
6633 gen_logic_CC(tmp);
6634 }
6635 store_reg_bx(env, s, rd, tmp);
6636 break;
6637 default:
6638 case 0x0f:
6639 tcg_gen_not_i32(tmp2, tmp2);
6640 if (logic_cc) {
6641 gen_logic_CC(tmp2);
6642 }
6643 store_reg_bx(env, s, rd, tmp2);
6644 break;
6645 }
6646 if (op1 != 0x0f && op1 != 0x0d) {
6647 dead_tmp(tmp2);
6648 }
6649 } else {
6650 /* other instructions */
6651 op1 = (insn >> 24) & 0xf;
6652 switch(op1) {
6653 case 0x0:
6654 case 0x1:
6655 /* multiplies, extra load/stores */
6656 sh = (insn >> 5) & 3;
6657 if (sh == 0) {
6658 if (op1 == 0x0) {
6659 rd = (insn >> 16) & 0xf;
6660 rn = (insn >> 12) & 0xf;
6661 rs = (insn >> 8) & 0xf;
6662 rm = (insn) & 0xf;
6663 op1 = (insn >> 20) & 0xf;
6664 switch (op1) {
6665 case 0: case 1: case 2: case 3: case 6:
6666 /* 32 bit mul */
6667 tmp = load_reg(s, rs);
6668 tmp2 = load_reg(s, rm);
6669 tcg_gen_mul_i32(tmp, tmp, tmp2);
6670 dead_tmp(tmp2);
6671 if (insn & (1 << 22)) {
6672 /* Subtract (mls) */
6673 ARCH(6T2);
6674 tmp2 = load_reg(s, rn);
6675 tcg_gen_sub_i32(tmp, tmp2, tmp);
6676 dead_tmp(tmp2);
6677 } else if (insn & (1 << 21)) {
6678 /* Add */
6679 tmp2 = load_reg(s, rn);
6680 tcg_gen_add_i32(tmp, tmp, tmp2);
6681 dead_tmp(tmp2);
6682 }
6683 if (insn & (1 << 20))
6684 gen_logic_CC(tmp);
6685 store_reg(s, rd, tmp);
6686 break;
6687 case 4:
6688 /* 64 bit mul double accumulate (UMAAL) */
6689 ARCH(6);
6690 tmp = load_reg(s, rs);
6691 tmp2 = load_reg(s, rm);
6692 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6693 gen_addq_lo(s, tmp64, rn);
6694 gen_addq_lo(s, tmp64, rd);
6695 gen_storeq_reg(s, rn, rd, tmp64);
6696 tcg_temp_free_i64(tmp64);
6697 break;
6698 case 8: case 9: case 10: case 11:
6699 case 12: case 13: case 14: case 15:
6700 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6701 tmp = load_reg(s, rs);
6702 tmp2 = load_reg(s, rm);
6703 if (insn & (1 << 22)) {
6704 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6705 } else {
6706 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6707 }
6708 if (insn & (1 << 21)) { /* mult accumulate */
6709 gen_addq(s, tmp64, rn, rd);
6710 }
6711 if (insn & (1 << 20)) {
6712 gen_logicq_cc(tmp64);
6713 }
6714 gen_storeq_reg(s, rn, rd, tmp64);
6715 tcg_temp_free_i64(tmp64);
6716 break;
6717 default:
6718 goto illegal_op;
6719 }
6720 } else {
6721 rn = (insn >> 16) & 0xf;
6722 rd = (insn >> 12) & 0xf;
6723 if (insn & (1 << 23)) {
6724 /* load/store exclusive */
6725 op1 = (insn >> 21) & 0x3;
6726 if (op1)
6727 ARCH(6K);
6728 else
6729 ARCH(6);
6730 addr = tcg_temp_local_new_i32();
6731 load_reg_var(s, addr, rn);
6732 if (insn & (1 << 20)) {
6733 switch (op1) {
6734 case 0: /* ldrex */
6735 gen_load_exclusive(s, rd, 15, addr, 2);
6736 break;
6737 case 1: /* ldrexd */
6738 gen_load_exclusive(s, rd, rd + 1, addr, 3);
6739 break;
6740 case 2: /* ldrexb */
6741 gen_load_exclusive(s, rd, 15, addr, 0);
6742 break;
6743 case 3: /* ldrexh */
6744 gen_load_exclusive(s, rd, 15, addr, 1);
6745 break;
6746 default:
6747 abort();
6748 }
6749 } else {
6750 rm = insn & 0xf;
6751 switch (op1) {
6752 case 0: /* strex */
6753 gen_store_exclusive(s, rd, rm, 15, addr, 2);
6754 break;
6755 case 1: /* strexd */
6756 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
6757 break;
6758 case 2: /* strexb */
6759 gen_store_exclusive(s, rd, rm, 15, addr, 0);
6760 break;
6761 case 3: /* strexh */
6762 gen_store_exclusive(s, rd, rm, 15, addr, 1);
6763 break;
6764 default:
6765 abort();
6766 }
6767 }
6768 tcg_temp_free(addr);
6769 } else {
6770 /* SWP instruction */
6771 rm = (insn) & 0xf;
6772
6773 /* ??? This is not really atomic. However we know
6774 we never have multiple CPUs running in parallel,
6775 so it is good enough. */
6776 addr = load_reg(s, rn);
6777 tmp = load_reg(s, rm);
6778 if (insn & (1 << 22)) {
6779 tmp2 = gen_ld8u(addr, IS_USER(s));
6780 gen_st8(tmp, addr, IS_USER(s));
6781 } else {
6782 tmp2 = gen_ld32(addr, IS_USER(s));
6783 gen_st32(tmp, addr, IS_USER(s));
6784 }
6785 dead_tmp(addr);
6786 store_reg(s, rd, tmp2);
6787 }
6788 }
6789 } else {
6790 int address_offset;
6791 int load;
6792 /* Misc load/store */
6793 rn = (insn >> 16) & 0xf;
6794 rd = (insn >> 12) & 0xf;
6795 addr = load_reg(s, rn);
6796 if (insn & (1 << 24))
6797 gen_add_datah_offset(s, insn, 0, addr);
6798 address_offset = 0;
6799 if (insn & (1 << 20)) {
6800 /* load */
6801 switch(sh) {
6802 case 1:
6803 tmp = gen_ld16u(addr, IS_USER(s));
6804 break;
6805 case 2:
6806 tmp = gen_ld8s(addr, IS_USER(s));
6807 break;
6808 default:
6809 case 3:
6810 tmp = gen_ld16s(addr, IS_USER(s));
6811 break;
6812 }
6813 load = 1;
6814 } else if (sh & 2) {
6815 /* doubleword */
6816 if (sh & 1) {
6817 /* store */
6818 tmp = load_reg(s, rd);
6819 gen_st32(tmp, addr, IS_USER(s));
6820 tcg_gen_addi_i32(addr, addr, 4);
6821 tmp = load_reg(s, rd + 1);
6822 gen_st32(tmp, addr, IS_USER(s));
6823 load = 0;
6824 } else {
6825 /* load */
6826 tmp = gen_ld32(addr, IS_USER(s));
6827 store_reg(s, rd, tmp);
6828 tcg_gen_addi_i32(addr, addr, 4);
6829 tmp = gen_ld32(addr, IS_USER(s));
6830 rd++;
6831 load = 1;
6832 }
6833 address_offset = -4;
6834 } else {
6835 /* store */
6836 tmp = load_reg(s, rd);
6837 gen_st16(tmp, addr, IS_USER(s));
6838 load = 0;
6839 }
6840 /* Perform base writeback before the loaded value to
6841 ensure correct behavior with overlapping index registers.
6842 ldrd with base writeback is is undefined if the
6843 destination and index registers overlap. */
6844 if (!(insn & (1 << 24))) {
6845 gen_add_datah_offset(s, insn, address_offset, addr);
6846 store_reg(s, rn, addr);
6847 } else if (insn & (1 << 21)) {
6848 if (address_offset)
6849 tcg_gen_addi_i32(addr, addr, address_offset);
6850 store_reg(s, rn, addr);
6851 } else {
6852 dead_tmp(addr);
6853 }
6854 if (load) {
6855 /* Complete the load. */
6856 store_reg(s, rd, tmp);
6857 }
6858 }
6859 break;
6860 case 0x4:
6861 case 0x5:
6862 goto do_ldst;
6863 case 0x6:
6864 case 0x7:
6865 if (insn & (1 << 4)) {
6866 ARCH(6);
6867 /* Armv6 Media instructions. */
6868 rm = insn & 0xf;
6869 rn = (insn >> 16) & 0xf;
6870 rd = (insn >> 12) & 0xf;
6871 rs = (insn >> 8) & 0xf;
6872 switch ((insn >> 23) & 3) {
6873 case 0: /* Parallel add/subtract. */
6874 op1 = (insn >> 20) & 7;
6875 tmp = load_reg(s, rn);
6876 tmp2 = load_reg(s, rm);
6877 sh = (insn >> 5) & 7;
6878 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6879 goto illegal_op;
6880 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6881 dead_tmp(tmp2);
6882 store_reg(s, rd, tmp);
6883 break;
6884 case 1:
6885 if ((insn & 0x00700020) == 0) {
6886 /* Halfword pack. */
6887 tmp = load_reg(s, rn);
6888 tmp2 = load_reg(s, rm);
6889 shift = (insn >> 7) & 0x1f;
6890 if (insn & (1 << 6)) {
6891 /* pkhtb */
6892 if (shift == 0)
6893 shift = 31;
6894 tcg_gen_sari_i32(tmp2, tmp2, shift);
6895 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6896 tcg_gen_ext16u_i32(tmp2, tmp2);
6897 } else {
6898 /* pkhbt */
6899 if (shift)
6900 tcg_gen_shli_i32(tmp2, tmp2, shift);
6901 tcg_gen_ext16u_i32(tmp, tmp);
6902 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6903 }
6904 tcg_gen_or_i32(tmp, tmp, tmp2);
6905 dead_tmp(tmp2);
6906 store_reg(s, rd, tmp);
6907 } else if ((insn & 0x00200020) == 0x00200000) {
6908 /* [us]sat */
6909 tmp = load_reg(s, rm);
6910 shift = (insn >> 7) & 0x1f;
6911 if (insn & (1 << 6)) {
6912 if (shift == 0)
6913 shift = 31;
6914 tcg_gen_sari_i32(tmp, tmp, shift);
6915 } else {
6916 tcg_gen_shli_i32(tmp, tmp, shift);
6917 }
6918 sh = (insn >> 16) & 0x1f;
6919 tmp2 = tcg_const_i32(sh);
6920 if (insn & (1 << 22))
6921 gen_helper_usat(tmp, tmp, tmp2);
6922 else
6923 gen_helper_ssat(tmp, tmp, tmp2);
6924 tcg_temp_free_i32(tmp2);
6925 store_reg(s, rd, tmp);
6926 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6927 /* [us]sat16 */
6928 tmp = load_reg(s, rm);
6929 sh = (insn >> 16) & 0x1f;
6930 tmp2 = tcg_const_i32(sh);
6931 if (insn & (1 << 22))
6932 gen_helper_usat16(tmp, tmp, tmp2);
6933 else
6934 gen_helper_ssat16(tmp, tmp, tmp2);
6935 tcg_temp_free_i32(tmp2);
6936 store_reg(s, rd, tmp);
6937 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6938 /* Select bytes. */
6939 tmp = load_reg(s, rn);
6940 tmp2 = load_reg(s, rm);
6941 tmp3 = new_tmp();
6942 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6943 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6944 dead_tmp(tmp3);
6945 dead_tmp(tmp2);
6946 store_reg(s, rd, tmp);
6947 } else if ((insn & 0x000003e0) == 0x00000060) {
6948 tmp = load_reg(s, rm);
6949 shift = (insn >> 10) & 3;
6950 /* ??? In many cases it's not neccessary to do a
6951 rotate, a shift is sufficient. */
6952 if (shift != 0)
6953 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
6954 op1 = (insn >> 20) & 7;
6955 switch (op1) {
6956 case 0: gen_sxtb16(tmp); break;
6957 case 2: gen_sxtb(tmp); break;
6958 case 3: gen_sxth(tmp); break;
6959 case 4: gen_uxtb16(tmp); break;
6960 case 6: gen_uxtb(tmp); break;
6961 case 7: gen_uxth(tmp); break;
6962 default: goto illegal_op;
6963 }
6964 if (rn != 15) {
6965 tmp2 = load_reg(s, rn);
6966 if ((op1 & 3) == 0) {
6967 gen_add16(tmp, tmp2);
6968 } else {
6969 tcg_gen_add_i32(tmp, tmp, tmp2);
6970 dead_tmp(tmp2);
6971 }
6972 }
6973 store_reg(s, rd, tmp);
6974 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6975 /* rev */
6976 tmp = load_reg(s, rm);
6977 if (insn & (1 << 22)) {
6978 if (insn & (1 << 7)) {
6979 gen_revsh(tmp);
6980 } else {
6981 ARCH(6T2);
6982 gen_helper_rbit(tmp, tmp);
6983 }
6984 } else {
6985 if (insn & (1 << 7))
6986 gen_rev16(tmp);
6987 else
6988 tcg_gen_bswap32_i32(tmp, tmp);
6989 }
6990 store_reg(s, rd, tmp);
6991 } else {
6992 goto illegal_op;
6993 }
6994 break;
6995 case 2: /* Multiplies (Type 3). */
6996 tmp = load_reg(s, rm);
6997 tmp2 = load_reg(s, rs);
6998 if (insn & (1 << 20)) {
6999 /* Signed multiply most significant [accumulate].
7000 (SMMUL, SMMLA, SMMLS) */
7001 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7002
7003 if (rd != 15) {
7004 tmp = load_reg(s, rd);
7005 if (insn & (1 << 6)) {
7006 tmp64 = gen_subq_msw(tmp64, tmp);
7007 } else {
7008 tmp64 = gen_addq_msw(tmp64, tmp);
7009 }
7010 }
7011 if (insn & (1 << 5)) {
7012 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7013 }
7014 tcg_gen_shri_i64(tmp64, tmp64, 32);
7015 tmp = new_tmp();
7016 tcg_gen_trunc_i64_i32(tmp, tmp64);
7017 tcg_temp_free_i64(tmp64);
7018 store_reg(s, rn, tmp);
7019 } else {
7020 if (insn & (1 << 5))
7021 gen_swap_half(tmp2);
7022 gen_smul_dual(tmp, tmp2);
7023 /* This addition cannot overflow. */
7024 if (insn & (1 << 6)) {
7025 tcg_gen_sub_i32(tmp, tmp, tmp2);
7026 } else {
7027 tcg_gen_add_i32(tmp, tmp, tmp2);
7028 }
7029 dead_tmp(tmp2);
7030 if (insn & (1 << 22)) {
7031 /* smlald, smlsld */
7032 tmp64 = tcg_temp_new_i64();
7033 tcg_gen_ext_i32_i64(tmp64, tmp);
7034 dead_tmp(tmp);
7035 gen_addq(s, tmp64, rd, rn);
7036 gen_storeq_reg(s, rd, rn, tmp64);
7037 tcg_temp_free_i64(tmp64);
7038 } else {
7039 /* smuad, smusd, smlad, smlsd */
7040 if (rd != 15)
7041 {
7042 tmp2 = load_reg(s, rd);
7043 gen_helper_add_setq(tmp, tmp, tmp2);
7044 dead_tmp(tmp2);
7045 }
7046 store_reg(s, rn, tmp);
7047 }
7048 }
7049 break;
7050 case 3:
7051 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7052 switch (op1) {
7053 case 0: /* Unsigned sum of absolute differences. */
7054 ARCH(6);
7055 tmp = load_reg(s, rm);
7056 tmp2 = load_reg(s, rs);
7057 gen_helper_usad8(tmp, tmp, tmp2);
7058 dead_tmp(tmp2);
7059 if (rd != 15) {
7060 tmp2 = load_reg(s, rd);
7061 tcg_gen_add_i32(tmp, tmp, tmp2);
7062 dead_tmp(tmp2);
7063 }
7064 store_reg(s, rn, tmp);
7065 break;
7066 case 0x20: case 0x24: case 0x28: case 0x2c:
7067 /* Bitfield insert/clear. */
7068 ARCH(6T2);
7069 shift = (insn >> 7) & 0x1f;
7070 i = (insn >> 16) & 0x1f;
7071 i = i + 1 - shift;
7072 if (rm == 15) {
7073 tmp = new_tmp();
7074 tcg_gen_movi_i32(tmp, 0);
7075 } else {
7076 tmp = load_reg(s, rm);
7077 }
7078 if (i != 32) {
7079 tmp2 = load_reg(s, rd);
7080 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7081 dead_tmp(tmp2);
7082 }
7083 store_reg(s, rd, tmp);
7084 break;
7085 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7086 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7087 ARCH(6T2);
7088 tmp = load_reg(s, rm);
7089 shift = (insn >> 7) & 0x1f;
7090 i = ((insn >> 16) & 0x1f) + 1;
7091 if (shift + i > 32)
7092 goto illegal_op;
7093 if (i < 32) {
7094 if (op1 & 0x20) {
7095 gen_ubfx(tmp, shift, (1u << i) - 1);
7096 } else {
7097 gen_sbfx(tmp, shift, i);
7098 }
7099 }
7100 store_reg(s, rd, tmp);
7101 break;
7102 default:
7103 goto illegal_op;
7104 }
7105 break;
7106 }
7107 break;
7108 }
7109 do_ldst:
7110 /* Check for undefined extension instructions
7111 * per the ARM Bible IE:
7112 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7113 */
7114 sh = (0xf << 20) | (0xf << 4);
7115 if (op1 == 0x7 && ((insn & sh) == sh))
7116 {
7117 goto illegal_op;
7118 }
7119 /* load/store byte/word */
7120 rn = (insn >> 16) & 0xf;
7121 rd = (insn >> 12) & 0xf;
7122 tmp2 = load_reg(s, rn);
7123 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7124 if (insn & (1 << 24))
7125 gen_add_data_offset(s, insn, tmp2);
7126 if (insn & (1 << 20)) {
7127 /* load */
7128 if (insn & (1 << 22)) {
7129 tmp = gen_ld8u(tmp2, i);
7130 } else {
7131 tmp = gen_ld32(tmp2, i);
7132 }
7133 } else {
7134 /* store */
7135 tmp = load_reg(s, rd);
7136 if (insn & (1 << 22))
7137 gen_st8(tmp, tmp2, i);
7138 else
7139 gen_st32(tmp, tmp2, i);
7140 }
7141 if (!(insn & (1 << 24))) {
7142 gen_add_data_offset(s, insn, tmp2);
7143 store_reg(s, rn, tmp2);
7144 } else if (insn & (1 << 21)) {
7145 store_reg(s, rn, tmp2);
7146 } else {
7147 dead_tmp(tmp2);
7148 }
7149 if (insn & (1 << 20)) {
7150 /* Complete the load. */
7151 if (rd == 15)
7152 gen_bx(s, tmp);
7153 else
7154 store_reg(s, rd, tmp);
7155 }
7156 break;
7157 case 0x08:
7158 case 0x09:
7159 {
7160 int j, n, user, loaded_base;
7161 TCGv loaded_var;
7162 /* load/store multiple words */
7163 /* XXX: store correct base if write back */
7164 user = 0;
7165 if (insn & (1 << 22)) {
7166 if (IS_USER(s))
7167 goto illegal_op; /* only usable in supervisor mode */
7168
7169 if ((insn & (1 << 15)) == 0)
7170 user = 1;
7171 }
7172 rn = (insn >> 16) & 0xf;
7173 addr = load_reg(s, rn);
7174
7175 /* compute total size */
7176 loaded_base = 0;
7177 TCGV_UNUSED(loaded_var);
7178 n = 0;
7179 for(i=0;i<16;i++) {
7180 if (insn & (1 << i))
7181 n++;
7182 }
7183 /* XXX: test invalid n == 0 case ? */
7184 if (insn & (1 << 23)) {
7185 if (insn & (1 << 24)) {
7186 /* pre increment */
7187 tcg_gen_addi_i32(addr, addr, 4);
7188 } else {
7189 /* post increment */
7190 }
7191 } else {
7192 if (insn & (1 << 24)) {
7193 /* pre decrement */
7194 tcg_gen_addi_i32(addr, addr, -(n * 4));
7195 } else {
7196 /* post decrement */
7197 if (n != 1)
7198 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7199 }
7200 }
7201 j = 0;
7202 for(i=0;i<16;i++) {
7203 if (insn & (1 << i)) {
7204 if (insn & (1 << 20)) {
7205 /* load */
7206 tmp = gen_ld32(addr, IS_USER(s));
7207 if (i == 15) {
7208 gen_bx(s, tmp);
7209 } else if (user) {
7210 tmp2 = tcg_const_i32(i);
7211 gen_helper_set_user_reg(tmp2, tmp);
7212 tcg_temp_free_i32(tmp2);
7213 dead_tmp(tmp);
7214 } else if (i == rn) {
7215 loaded_var = tmp;
7216 loaded_base = 1;
7217 } else {
7218 store_reg(s, i, tmp);
7219 }
7220 } else {
7221 /* store */
7222 if (i == 15) {
7223 /* special case: r15 = PC + 8 */
7224 val = (long)s->pc + 4;
7225 tmp = new_tmp();
7226 tcg_gen_movi_i32(tmp, val);
7227 } else if (user) {
7228 tmp = new_tmp();
7229 tmp2 = tcg_const_i32(i);
7230 gen_helper_get_user_reg(tmp, tmp2);
7231 tcg_temp_free_i32(tmp2);
7232 } else {
7233 tmp = load_reg(s, i);
7234 }
7235 gen_st32(tmp, addr, IS_USER(s));
7236 }
7237 j++;
7238 /* no need to add after the last transfer */
7239 if (j != n)
7240 tcg_gen_addi_i32(addr, addr, 4);
7241 }
7242 }
7243 if (insn & (1 << 21)) {
7244 /* write back */
7245 if (insn & (1 << 23)) {
7246 if (insn & (1 << 24)) {
7247 /* pre increment */
7248 } else {
7249 /* post increment */
7250 tcg_gen_addi_i32(addr, addr, 4);
7251 }
7252 } else {
7253 if (insn & (1 << 24)) {
7254 /* pre decrement */
7255 if (n != 1)
7256 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7257 } else {
7258 /* post decrement */
7259 tcg_gen_addi_i32(addr, addr, -(n * 4));
7260 }
7261 }
7262 store_reg(s, rn, addr);
7263 } else {
7264 dead_tmp(addr);
7265 }
7266 if (loaded_base) {
7267 store_reg(s, rn, loaded_var);
7268 }
7269 if ((insn & (1 << 22)) && !user) {
7270 /* Restore CPSR from SPSR. */
7271 tmp = load_cpu_field(spsr);
7272 gen_set_cpsr(tmp, 0xffffffff);
7273 dead_tmp(tmp);
7274 s->is_jmp = DISAS_UPDATE;
7275 }
7276 }
7277 break;
7278 case 0xa:
7279 case 0xb:
7280 {
7281 int32_t offset;
7282
7283 /* branch (and link) */
7284 val = (int32_t)s->pc;
7285 if (insn & (1 << 24)) {
7286 tmp = new_tmp();
7287 tcg_gen_movi_i32(tmp, val);
7288 store_reg(s, 14, tmp);
7289 }
7290 offset = (((int32_t)insn << 8) >> 8);
7291 val += (offset << 2) + 4;
7292 gen_jmp(s, val);
7293 }
7294 break;
7295 case 0xc:
7296 case 0xd:
7297 case 0xe:
7298 /* Coprocessor. */
7299 if (disas_coproc_insn(env, s, insn))
7300 goto illegal_op;
7301 break;
7302 case 0xf:
7303 /* swi */
7304 gen_set_pc_im(s->pc);
7305 s->is_jmp = DISAS_SWI;
7306 break;
7307 default:
7308 illegal_op:
7309 gen_exception_insn(s, 4, EXCP_UDEF);
7310 break;
7311 }
7312 }
7313 }
7314
7315 /* Return true if this is a Thumb-2 logical op. */
7316 static int
7317 thumb2_logic_op(int op)
7318 {
7319 return (op < 8);
7320 }
7321
7322 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7323 then set condition code flags based on the result of the operation.
7324 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7325 to the high bit of T1.
7326 Returns zero if the opcode is valid. */
7327
7328 static int
7329 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7330 {
7331 int logic_cc;
7332
7333 logic_cc = 0;
7334 switch (op) {
7335 case 0: /* and */
7336 tcg_gen_and_i32(t0, t0, t1);
7337 logic_cc = conds;
7338 break;
7339 case 1: /* bic */
7340 tcg_gen_andc_i32(t0, t0, t1);
7341 logic_cc = conds;
7342 break;
7343 case 2: /* orr */
7344 tcg_gen_or_i32(t0, t0, t1);
7345 logic_cc = conds;
7346 break;
7347 case 3: /* orn */
7348 tcg_gen_not_i32(t1, t1);
7349 tcg_gen_or_i32(t0, t0, t1);
7350 logic_cc = conds;
7351 break;
7352 case 4: /* eor */
7353 tcg_gen_xor_i32(t0, t0, t1);
7354 logic_cc = conds;
7355 break;
7356 case 8: /* add */
7357 if (conds)
7358 gen_helper_add_cc(t0, t0, t1);
7359 else
7360 tcg_gen_add_i32(t0, t0, t1);
7361 break;
7362 case 10: /* adc */
7363 if (conds)
7364 gen_helper_adc_cc(t0, t0, t1);
7365 else
7366 gen_adc(t0, t1);
7367 break;
7368 case 11: /* sbc */
7369 if (conds)
7370 gen_helper_sbc_cc(t0, t0, t1);
7371 else
7372 gen_sub_carry(t0, t0, t1);
7373 break;
7374 case 13: /* sub */
7375 if (conds)
7376 gen_helper_sub_cc(t0, t0, t1);
7377 else
7378 tcg_gen_sub_i32(t0, t0, t1);
7379 break;
7380 case 14: /* rsb */
7381 if (conds)
7382 gen_helper_sub_cc(t0, t1, t0);
7383 else
7384 tcg_gen_sub_i32(t0, t1, t0);
7385 break;
7386 default: /* 5, 6, 7, 9, 12, 15. */
7387 return 1;
7388 }
7389 if (logic_cc) {
7390 gen_logic_CC(t0);
7391 if (shifter_out)
7392 gen_set_CF_bit31(t1);
7393 }
7394 return 0;
7395 }
7396
7397 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7398 is not legal. */
7399 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7400 {
7401 uint32_t insn, imm, shift, offset;
7402 uint32_t rd, rn, rm, rs;
7403 TCGv tmp;
7404 TCGv tmp2;
7405 TCGv tmp3;
7406 TCGv addr;
7407 TCGv_i64 tmp64;
7408 int op;
7409 int shiftop;
7410 int conds;
7411 int logic_cc;
7412
7413 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7414 || arm_feature (env, ARM_FEATURE_M))) {
7415 /* Thumb-1 cores may need to treat bl and blx as a pair of
7416 16-bit instructions to get correct prefetch abort behavior. */
7417 insn = insn_hw1;
7418 if ((insn & (1 << 12)) == 0) {
7419 /* Second half of blx. */
7420 offset = ((insn & 0x7ff) << 1);
7421 tmp = load_reg(s, 14);
7422 tcg_gen_addi_i32(tmp, tmp, offset);
7423 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7424
7425 tmp2 = new_tmp();
7426 tcg_gen_movi_i32(tmp2, s->pc | 1);
7427 store_reg(s, 14, tmp2);
7428 gen_bx(s, tmp);
7429 return 0;
7430 }
7431 if (insn & (1 << 11)) {
7432 /* Second half of bl. */
7433 offset = ((insn & 0x7ff) << 1) | 1;
7434 tmp = load_reg(s, 14);
7435 tcg_gen_addi_i32(tmp, tmp, offset);
7436
7437 tmp2 = new_tmp();
7438 tcg_gen_movi_i32(tmp2, s->pc | 1);
7439 store_reg(s, 14, tmp2);
7440 gen_bx(s, tmp);
7441 return 0;
7442 }
7443 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7444 /* Instruction spans a page boundary. Implement it as two
7445 16-bit instructions in case the second half causes an
7446 prefetch abort. */
7447 offset = ((int32_t)insn << 21) >> 9;
7448 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7449 return 0;
7450 }
7451 /* Fall through to 32-bit decode. */
7452 }
7453
7454 insn = lduw_code(s->pc);
7455 s->pc += 2;
7456 insn |= (uint32_t)insn_hw1 << 16;
7457
7458 if ((insn & 0xf800e800) != 0xf000e800) {
7459 ARCH(6T2);
7460 }
7461
7462 rn = (insn >> 16) & 0xf;
7463 rs = (insn >> 12) & 0xf;
7464 rd = (insn >> 8) & 0xf;
7465 rm = insn & 0xf;
7466 switch ((insn >> 25) & 0xf) {
7467 case 0: case 1: case 2: case 3:
7468 /* 16-bit instructions. Should never happen. */
7469 abort();
7470 case 4:
7471 if (insn & (1 << 22)) {
7472 /* Other load/store, table branch. */
7473 if (insn & 0x01200000) {
7474 /* Load/store doubleword. */
7475 if (rn == 15) {
7476 addr = new_tmp();
7477 tcg_gen_movi_i32(addr, s->pc & ~3);
7478 } else {
7479 addr = load_reg(s, rn);
7480 }
7481 offset = (insn & 0xff) * 4;
7482 if ((insn & (1 << 23)) == 0)
7483 offset = -offset;
7484 if (insn & (1 << 24)) {
7485 tcg_gen_addi_i32(addr, addr, offset);
7486 offset = 0;
7487 }
7488 if (insn & (1 << 20)) {
7489 /* ldrd */
7490 tmp = gen_ld32(addr, IS_USER(s));
7491 store_reg(s, rs, tmp);
7492 tcg_gen_addi_i32(addr, addr, 4);
7493 tmp = gen_ld32(addr, IS_USER(s));
7494 store_reg(s, rd, tmp);
7495 } else {
7496 /* strd */
7497 tmp = load_reg(s, rs);
7498 gen_st32(tmp, addr, IS_USER(s));
7499 tcg_gen_addi_i32(addr, addr, 4);
7500 tmp = load_reg(s, rd);
7501 gen_st32(tmp, addr, IS_USER(s));
7502 }
7503 if (insn & (1 << 21)) {
7504 /* Base writeback. */
7505 if (rn == 15)
7506 goto illegal_op;
7507 tcg_gen_addi_i32(addr, addr, offset - 4);
7508 store_reg(s, rn, addr);
7509 } else {
7510 dead_tmp(addr);
7511 }
7512 } else if ((insn & (1 << 23)) == 0) {
7513 /* Load/store exclusive word. */
7514 addr = tcg_temp_local_new();
7515 load_reg_var(s, addr, rn);
7516 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7517 if (insn & (1 << 20)) {
7518 gen_load_exclusive(s, rs, 15, addr, 2);
7519 } else {
7520 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7521 }
7522 tcg_temp_free(addr);
7523 } else if ((insn & (1 << 6)) == 0) {
7524 /* Table Branch. */
7525 if (rn == 15) {
7526 addr = new_tmp();
7527 tcg_gen_movi_i32(addr, s->pc);
7528 } else {
7529 addr = load_reg(s, rn);
7530 }
7531 tmp = load_reg(s, rm);
7532 tcg_gen_add_i32(addr, addr, tmp);
7533 if (insn & (1 << 4)) {
7534 /* tbh */
7535 tcg_gen_add_i32(addr, addr, tmp);
7536 dead_tmp(tmp);
7537 tmp = gen_ld16u(addr, IS_USER(s));
7538 } else { /* tbb */
7539 dead_tmp(tmp);
7540 tmp = gen_ld8u(addr, IS_USER(s));
7541 }
7542 dead_tmp(addr);
7543 tcg_gen_shli_i32(tmp, tmp, 1);
7544 tcg_gen_addi_i32(tmp, tmp, s->pc);
7545 store_reg(s, 15, tmp);
7546 } else {
7547 /* Load/store exclusive byte/halfword/doubleword. */
7548 ARCH(7);
7549 op = (insn >> 4) & 0x3;
7550 if (op == 2) {
7551 goto illegal_op;
7552 }
7553 addr = tcg_temp_local_new();
7554 load_reg_var(s, addr, rn);
7555 if (insn & (1 << 20)) {
7556 gen_load_exclusive(s, rs, rd, addr, op);
7557 } else {
7558 gen_store_exclusive(s, rm, rs, rd, addr, op);
7559 }
7560 tcg_temp_free(addr);
7561 }
7562 } else {
7563 /* Load/store multiple, RFE, SRS. */
7564 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7565 /* Not available in user mode. */
7566 if (IS_USER(s))
7567 goto illegal_op;
7568 if (insn & (1 << 20)) {
7569 /* rfe */
7570 addr = load_reg(s, rn);
7571 if ((insn & (1 << 24)) == 0)
7572 tcg_gen_addi_i32(addr, addr, -8);
7573 /* Load PC into tmp and CPSR into tmp2. */
7574 tmp = gen_ld32(addr, 0);
7575 tcg_gen_addi_i32(addr, addr, 4);
7576 tmp2 = gen_ld32(addr, 0);
7577 if (insn & (1 << 21)) {
7578 /* Base writeback. */
7579 if (insn & (1 << 24)) {
7580 tcg_gen_addi_i32(addr, addr, 4);
7581 } else {
7582 tcg_gen_addi_i32(addr, addr, -4);
7583 }
7584 store_reg(s, rn, addr);
7585 } else {
7586 dead_tmp(addr);
7587 }
7588 gen_rfe(s, tmp, tmp2);
7589 } else {
7590 /* srs */
7591 op = (insn & 0x1f);
7592 addr = new_tmp();
7593 tmp = tcg_const_i32(op);
7594 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7595 tcg_temp_free_i32(tmp);
7596 if ((insn & (1 << 24)) == 0) {
7597 tcg_gen_addi_i32(addr, addr, -8);
7598 }
7599 tmp = load_reg(s, 14);
7600 gen_st32(tmp, addr, 0);
7601 tcg_gen_addi_i32(addr, addr, 4);
7602 tmp = new_tmp();
7603 gen_helper_cpsr_read(tmp);
7604 gen_st32(tmp, addr, 0);
7605 if (insn & (1 << 21)) {
7606 if ((insn & (1 << 24)) == 0) {
7607 tcg_gen_addi_i32(addr, addr, -4);
7608 } else {
7609 tcg_gen_addi_i32(addr, addr, 4);
7610 }
7611 tmp = tcg_const_i32(op);
7612 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7613 tcg_temp_free_i32(tmp);
7614 } else {
7615 dead_tmp(addr);
7616 }
7617 }
7618 } else {
7619 int i;
7620 /* Load/store multiple. */
7621 addr = load_reg(s, rn);
7622 offset = 0;
7623 for (i = 0; i < 16; i++) {
7624 if (insn & (1 << i))
7625 offset += 4;
7626 }
7627 if (insn & (1 << 24)) {
7628 tcg_gen_addi_i32(addr, addr, -offset);
7629 }
7630
7631 for (i = 0; i < 16; i++) {
7632 if ((insn & (1 << i)) == 0)
7633 continue;
7634 if (insn & (1 << 20)) {
7635 /* Load. */
7636 tmp = gen_ld32(addr, IS_USER(s));
7637 if (i == 15) {
7638 gen_bx(s, tmp);
7639 } else {
7640 store_reg(s, i, tmp);
7641 }
7642 } else {
7643 /* Store. */
7644 tmp = load_reg(s, i);
7645 gen_st32(tmp, addr, IS_USER(s));
7646 }
7647 tcg_gen_addi_i32(addr, addr, 4);
7648 }
7649 if (insn & (1 << 21)) {
7650 /* Base register writeback. */
7651 if (insn & (1 << 24)) {
7652 tcg_gen_addi_i32(addr, addr, -offset);
7653 }
7654 /* Fault if writeback register is in register list. */
7655 if (insn & (1 << rn))
7656 goto illegal_op;
7657 store_reg(s, rn, addr);
7658 } else {
7659 dead_tmp(addr);
7660 }
7661 }
7662 }
7663 break;
7664 case 5:
7665
7666 op = (insn >> 21) & 0xf;
7667 if (op == 6) {
7668 /* Halfword pack. */
7669 tmp = load_reg(s, rn);
7670 tmp2 = load_reg(s, rm);
7671 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7672 if (insn & (1 << 5)) {
7673 /* pkhtb */
7674 if (shift == 0)
7675 shift = 31;
7676 tcg_gen_sari_i32(tmp2, tmp2, shift);
7677 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7678 tcg_gen_ext16u_i32(tmp2, tmp2);
7679 } else {
7680 /* pkhbt */
7681 if (shift)
7682 tcg_gen_shli_i32(tmp2, tmp2, shift);
7683 tcg_gen_ext16u_i32(tmp, tmp);
7684 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7685 }
7686 tcg_gen_or_i32(tmp, tmp, tmp2);
7687 dead_tmp(tmp2);
7688 store_reg(s, rd, tmp);
7689 } else {
7690 /* Data processing register constant shift. */
7691 if (rn == 15) {
7692 tmp = new_tmp();
7693 tcg_gen_movi_i32(tmp, 0);
7694 } else {
7695 tmp = load_reg(s, rn);
7696 }
7697 tmp2 = load_reg(s, rm);
7698
7699 shiftop = (insn >> 4) & 3;
7700 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7701 conds = (insn & (1 << 20)) != 0;
7702 logic_cc = (conds && thumb2_logic_op(op));
7703 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7704 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7705 goto illegal_op;
7706 dead_tmp(tmp2);
7707 if (rd != 15) {
7708 store_reg(s, rd, tmp);
7709 } else {
7710 dead_tmp(tmp);
7711 }
7712 }
7713 break;
7714 case 13: /* Misc data processing. */
7715 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7716 if (op < 4 && (insn & 0xf000) != 0xf000)
7717 goto illegal_op;
7718 switch (op) {
7719 case 0: /* Register controlled shift. */
7720 tmp = load_reg(s, rn);
7721 tmp2 = load_reg(s, rm);
7722 if ((insn & 0x70) != 0)
7723 goto illegal_op;
7724 op = (insn >> 21) & 3;
7725 logic_cc = (insn & (1 << 20)) != 0;
7726 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7727 if (logic_cc)
7728 gen_logic_CC(tmp);
7729 store_reg_bx(env, s, rd, tmp);
7730 break;
7731 case 1: /* Sign/zero extend. */
7732 tmp = load_reg(s, rm);
7733 shift = (insn >> 4) & 3;
7734 /* ??? In many cases it's not neccessary to do a
7735 rotate, a shift is sufficient. */
7736 if (shift != 0)
7737 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7738 op = (insn >> 20) & 7;
7739 switch (op) {
7740 case 0: gen_sxth(tmp); break;
7741 case 1: gen_uxth(tmp); break;
7742 case 2: gen_sxtb16(tmp); break;
7743 case 3: gen_uxtb16(tmp); break;
7744 case 4: gen_sxtb(tmp); break;
7745 case 5: gen_uxtb(tmp); break;
7746 default: goto illegal_op;
7747 }
7748 if (rn != 15) {
7749 tmp2 = load_reg(s, rn);
7750 if ((op >> 1) == 1) {
7751 gen_add16(tmp, tmp2);
7752 } else {
7753 tcg_gen_add_i32(tmp, tmp, tmp2);
7754 dead_tmp(tmp2);
7755 }
7756 }
7757 store_reg(s, rd, tmp);
7758 break;
7759 case 2: /* SIMD add/subtract. */
7760 op = (insn >> 20) & 7;
7761 shift = (insn >> 4) & 7;
7762 if ((op & 3) == 3 || (shift & 3) == 3)
7763 goto illegal_op;
7764 tmp = load_reg(s, rn);
7765 tmp2 = load_reg(s, rm);
7766 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7767 dead_tmp(tmp2);
7768 store_reg(s, rd, tmp);
7769 break;
7770 case 3: /* Other data processing. */
7771 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7772 if (op < 4) {
7773 /* Saturating add/subtract. */
7774 tmp = load_reg(s, rn);
7775 tmp2 = load_reg(s, rm);
7776 if (op & 1)
7777 gen_helper_double_saturate(tmp, tmp);
7778 if (op & 2)
7779 gen_helper_sub_saturate(tmp, tmp2, tmp);
7780 else
7781 gen_helper_add_saturate(tmp, tmp, tmp2);
7782 dead_tmp(tmp2);
7783 } else {
7784 tmp = load_reg(s, rn);
7785 switch (op) {
7786 case 0x0a: /* rbit */
7787 gen_helper_rbit(tmp, tmp);
7788 break;
7789 case 0x08: /* rev */
7790 tcg_gen_bswap32_i32(tmp, tmp);
7791 break;
7792 case 0x09: /* rev16 */
7793 gen_rev16(tmp);
7794 break;
7795 case 0x0b: /* revsh */
7796 gen_revsh(tmp);
7797 break;
7798 case 0x10: /* sel */
7799 tmp2 = load_reg(s, rm);
7800 tmp3 = new_tmp();
7801 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7802 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7803 dead_tmp(tmp3);
7804 dead_tmp(tmp2);
7805 break;
7806 case 0x18: /* clz */
7807 gen_helper_clz(tmp, tmp);
7808 break;
7809 default:
7810 goto illegal_op;
7811 }
7812 }
7813 store_reg(s, rd, tmp);
7814 break;
7815 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7816 op = (insn >> 4) & 0xf;
7817 tmp = load_reg(s, rn);
7818 tmp2 = load_reg(s, rm);
7819 switch ((insn >> 20) & 7) {
7820 case 0: /* 32 x 32 -> 32 */
7821 tcg_gen_mul_i32(tmp, tmp, tmp2);
7822 dead_tmp(tmp2);
7823 if (rs != 15) {
7824 tmp2 = load_reg(s, rs);
7825 if (op)
7826 tcg_gen_sub_i32(tmp, tmp2, tmp);
7827 else
7828 tcg_gen_add_i32(tmp, tmp, tmp2);
7829 dead_tmp(tmp2);
7830 }
7831 break;
7832 case 1: /* 16 x 16 -> 32 */
7833 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7834 dead_tmp(tmp2);
7835 if (rs != 15) {
7836 tmp2 = load_reg(s, rs);
7837 gen_helper_add_setq(tmp, tmp, tmp2);
7838 dead_tmp(tmp2);
7839 }
7840 break;
7841 case 2: /* Dual multiply add. */
7842 case 4: /* Dual multiply subtract. */
7843 if (op)
7844 gen_swap_half(tmp2);
7845 gen_smul_dual(tmp, tmp2);
7846 /* This addition cannot overflow. */
7847 if (insn & (1 << 22)) {
7848 tcg_gen_sub_i32(tmp, tmp, tmp2);
7849 } else {
7850 tcg_gen_add_i32(tmp, tmp, tmp2);
7851 }
7852 dead_tmp(tmp2);
7853 if (rs != 15)
7854 {
7855 tmp2 = load_reg(s, rs);
7856 gen_helper_add_setq(tmp, tmp, tmp2);
7857 dead_tmp(tmp2);
7858 }
7859 break;
7860 case 3: /* 32 * 16 -> 32msb */
7861 if (op)
7862 tcg_gen_sari_i32(tmp2, tmp2, 16);
7863 else
7864 gen_sxth(tmp2);
7865 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7866 tcg_gen_shri_i64(tmp64, tmp64, 16);
7867 tmp = new_tmp();
7868 tcg_gen_trunc_i64_i32(tmp, tmp64);
7869 tcg_temp_free_i64(tmp64);
7870 if (rs != 15)
7871 {
7872 tmp2 = load_reg(s, rs);
7873 gen_helper_add_setq(tmp, tmp, tmp2);
7874 dead_tmp(tmp2);
7875 }
7876 break;
7877 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7878 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7879 if (rs != 15) {
7880 tmp = load_reg(s, rs);
7881 if (insn & (1 << 20)) {
7882 tmp64 = gen_addq_msw(tmp64, tmp);
7883 } else {
7884 tmp64 = gen_subq_msw(tmp64, tmp);
7885 }
7886 }
7887 if (insn & (1 << 4)) {
7888 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7889 }
7890 tcg_gen_shri_i64(tmp64, tmp64, 32);
7891 tmp = new_tmp();
7892 tcg_gen_trunc_i64_i32(tmp, tmp64);
7893 tcg_temp_free_i64(tmp64);
7894 break;
7895 case 7: /* Unsigned sum of absolute differences. */
7896 gen_helper_usad8(tmp, tmp, tmp2);
7897 dead_tmp(tmp2);
7898 if (rs != 15) {
7899 tmp2 = load_reg(s, rs);
7900 tcg_gen_add_i32(tmp, tmp, tmp2);
7901 dead_tmp(tmp2);
7902 }
7903 break;
7904 }
7905 store_reg(s, rd, tmp);
7906 break;
7907 case 6: case 7: /* 64-bit multiply, Divide. */
7908 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7909 tmp = load_reg(s, rn);
7910 tmp2 = load_reg(s, rm);
7911 if ((op & 0x50) == 0x10) {
7912 /* sdiv, udiv */
7913 if (!arm_feature(env, ARM_FEATURE_DIV))
7914 goto illegal_op;
7915 if (op & 0x20)
7916 gen_helper_udiv(tmp, tmp, tmp2);
7917 else
7918 gen_helper_sdiv(tmp, tmp, tmp2);
7919 dead_tmp(tmp2);
7920 store_reg(s, rd, tmp);
7921 } else if ((op & 0xe) == 0xc) {
7922 /* Dual multiply accumulate long. */
7923 if (op & 1)
7924 gen_swap_half(tmp2);
7925 gen_smul_dual(tmp, tmp2);
7926 if (op & 0x10) {
7927 tcg_gen_sub_i32(tmp, tmp, tmp2);
7928 } else {
7929 tcg_gen_add_i32(tmp, tmp, tmp2);
7930 }
7931 dead_tmp(tmp2);
7932 /* BUGFIX */
7933 tmp64 = tcg_temp_new_i64();
7934 tcg_gen_ext_i32_i64(tmp64, tmp);
7935 dead_tmp(tmp);
7936 gen_addq(s, tmp64, rs, rd);
7937 gen_storeq_reg(s, rs, rd, tmp64);
7938 tcg_temp_free_i64(tmp64);
7939 } else {
7940 if (op & 0x20) {
7941 /* Unsigned 64-bit multiply */
7942 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7943 } else {
7944 if (op & 8) {
7945 /* smlalxy */
7946 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7947 dead_tmp(tmp2);
7948 tmp64 = tcg_temp_new_i64();
7949 tcg_gen_ext_i32_i64(tmp64, tmp);
7950 dead_tmp(tmp);
7951 } else {
7952 /* Signed 64-bit multiply */
7953 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7954 }
7955 }
7956 if (op & 4) {
7957 /* umaal */
7958 gen_addq_lo(s, tmp64, rs);
7959 gen_addq_lo(s, tmp64, rd);
7960 } else if (op & 0x40) {
7961 /* 64-bit accumulate. */
7962 gen_addq(s, tmp64, rs, rd);
7963 }
7964 gen_storeq_reg(s, rs, rd, tmp64);
7965 tcg_temp_free_i64(tmp64);
7966 }
7967 break;
7968 }
7969 break;
7970 case 6: case 7: case 14: case 15:
7971 /* Coprocessor. */
7972 if (((insn >> 24) & 3) == 3) {
7973 /* Translate into the equivalent ARM encoding. */
7974 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7975 if (disas_neon_data_insn(env, s, insn))
7976 goto illegal_op;
7977 } else {
7978 if (insn & (1 << 28))
7979 goto illegal_op;
7980 if (disas_coproc_insn (env, s, insn))
7981 goto illegal_op;
7982 }
7983 break;
7984 case 8: case 9: case 10: case 11:
7985 if (insn & (1 << 15)) {
7986 /* Branches, misc control. */
7987 if (insn & 0x5000) {
7988 /* Unconditional branch. */
7989 /* signextend(hw1[10:0]) -> offset[:12]. */
7990 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7991 /* hw1[10:0] -> offset[11:1]. */
7992 offset |= (insn & 0x7ff) << 1;
7993 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7994 offset[24:22] already have the same value because of the
7995 sign extension above. */
7996 offset ^= ((~insn) & (1 << 13)) << 10;
7997 offset ^= ((~insn) & (1 << 11)) << 11;
7998
7999 if (insn & (1 << 14)) {
8000 /* Branch and link. */
8001 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
8002 }
8003
8004 offset += s->pc;
8005 if (insn & (1 << 12)) {
8006 /* b/bl */
8007 gen_jmp(s, offset);
8008 } else {
8009 /* blx */
8010 offset &= ~(uint32_t)2;
8011 gen_bx_im(s, offset);
8012 }
8013 } else if (((insn >> 23) & 7) == 7) {
8014 /* Misc control */
8015 if (insn & (1 << 13))
8016 goto illegal_op;
8017
8018 if (insn & (1 << 26)) {
8019 /* Secure monitor call (v6Z) */
8020 goto illegal_op; /* not implemented. */
8021 } else {
8022 op = (insn >> 20) & 7;
8023 switch (op) {
8024 case 0: /* msr cpsr. */
8025 if (IS_M(env)) {
8026 tmp = load_reg(s, rn);
8027 addr = tcg_const_i32(insn & 0xff);
8028 gen_helper_v7m_msr(cpu_env, addr, tmp);
8029 tcg_temp_free_i32(addr);
8030 dead_tmp(tmp);
8031 gen_lookup_tb(s);
8032 break;
8033 }
8034 /* fall through */
8035 case 1: /* msr spsr. */
8036 if (IS_M(env))
8037 goto illegal_op;
8038 tmp = load_reg(s, rn);
8039 if (gen_set_psr(s,
8040 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8041 op == 1, tmp))
8042 goto illegal_op;
8043 break;
8044 case 2: /* cps, nop-hint. */
8045 if (((insn >> 8) & 7) == 0) {
8046 gen_nop_hint(s, insn & 0xff);
8047 }
8048 /* Implemented as NOP in user mode. */
8049 if (IS_USER(s))
8050 break;
8051 offset = 0;
8052 imm = 0;
8053 if (insn & (1 << 10)) {
8054 if (insn & (1 << 7))
8055 offset |= CPSR_A;
8056 if (insn & (1 << 6))
8057 offset |= CPSR_I;
8058 if (insn & (1 << 5))
8059 offset |= CPSR_F;
8060 if (insn & (1 << 9))
8061 imm = CPSR_A | CPSR_I | CPSR_F;
8062 }
8063 if (insn & (1 << 8)) {
8064 offset |= 0x1f;
8065 imm |= (insn & 0x1f);
8066 }
8067 if (offset) {
8068 gen_set_psr_im(s, offset, 0, imm);
8069 }
8070 break;
8071 case 3: /* Special control operations. */
8072 ARCH(7);
8073 op = (insn >> 4) & 0xf;
8074 switch (op) {
8075 case 2: /* clrex */
8076 gen_clrex(s);
8077 break;
8078 case 4: /* dsb */
8079 case 5: /* dmb */
8080 case 6: /* isb */
8081 /* These execute as NOPs. */
8082 break;
8083 default:
8084 goto illegal_op;
8085 }
8086 break;
8087 case 4: /* bxj */
8088 /* Trivial implementation equivalent to bx. */
8089 tmp = load_reg(s, rn);
8090 gen_bx(s, tmp);
8091 break;
8092 case 5: /* Exception return. */
8093 if (IS_USER(s)) {
8094 goto illegal_op;
8095 }
8096 if (rn != 14 || rd != 15) {
8097 goto illegal_op;
8098 }
8099 tmp = load_reg(s, rn);
8100 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8101 gen_exception_return(s, tmp);
8102 break;
8103 case 6: /* mrs cpsr. */
8104 tmp = new_tmp();
8105 if (IS_M(env)) {
8106 addr = tcg_const_i32(insn & 0xff);
8107 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8108 tcg_temp_free_i32(addr);
8109 } else {
8110 gen_helper_cpsr_read(tmp);
8111 }
8112 store_reg(s, rd, tmp);
8113 break;
8114 case 7: /* mrs spsr. */
8115 /* Not accessible in user mode. */
8116 if (IS_USER(s) || IS_M(env))
8117 goto illegal_op;
8118 tmp = load_cpu_field(spsr);
8119 store_reg(s, rd, tmp);
8120 break;
8121 }
8122 }
8123 } else {
8124 /* Conditional branch. */
8125 op = (insn >> 22) & 0xf;
8126 /* Generate a conditional jump to next instruction. */
8127 s->condlabel = gen_new_label();
8128 gen_test_cc(op ^ 1, s->condlabel);
8129 s->condjmp = 1;
8130
8131 /* offset[11:1] = insn[10:0] */
8132 offset = (insn & 0x7ff) << 1;
8133 /* offset[17:12] = insn[21:16]. */
8134 offset |= (insn & 0x003f0000) >> 4;
8135 /* offset[31:20] = insn[26]. */
8136 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8137 /* offset[18] = insn[13]. */
8138 offset |= (insn & (1 << 13)) << 5;
8139 /* offset[19] = insn[11]. */
8140 offset |= (insn & (1 << 11)) << 8;
8141
8142 /* jump to the offset */
8143 gen_jmp(s, s->pc + offset);
8144 }
8145 } else {
8146 /* Data processing immediate. */
8147 if (insn & (1 << 25)) {
8148 if (insn & (1 << 24)) {
8149 if (insn & (1 << 20))
8150 goto illegal_op;
8151 /* Bitfield/Saturate. */
8152 op = (insn >> 21) & 7;
8153 imm = insn & 0x1f;
8154 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8155 if (rn == 15) {
8156 tmp = new_tmp();
8157 tcg_gen_movi_i32(tmp, 0);
8158 } else {
8159 tmp = load_reg(s, rn);
8160 }
8161 switch (op) {
8162 case 2: /* Signed bitfield extract. */
8163 imm++;
8164 if (shift + imm > 32)
8165 goto illegal_op;
8166 if (imm < 32)
8167 gen_sbfx(tmp, shift, imm);
8168 break;
8169 case 6: /* Unsigned bitfield extract. */
8170 imm++;
8171 if (shift + imm > 32)
8172 goto illegal_op;
8173 if (imm < 32)
8174 gen_ubfx(tmp, shift, (1u << imm) - 1);
8175 break;
8176 case 3: /* Bitfield insert/clear. */
8177 if (imm < shift)
8178 goto illegal_op;
8179 imm = imm + 1 - shift;
8180 if (imm != 32) {
8181 tmp2 = load_reg(s, rd);
8182 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8183 dead_tmp(tmp2);
8184 }
8185 break;
8186 case 7:
8187 goto illegal_op;
8188 default: /* Saturate. */
8189 if (shift) {
8190 if (op & 1)
8191 tcg_gen_sari_i32(tmp, tmp, shift);
8192 else
8193 tcg_gen_shli_i32(tmp, tmp, shift);
8194 }
8195 tmp2 = tcg_const_i32(imm);
8196 if (op & 4) {
8197 /* Unsigned. */
8198 if ((op & 1) && shift == 0)
8199 gen_helper_usat16(tmp, tmp, tmp2);
8200 else
8201 gen_helper_usat(tmp, tmp, tmp2);
8202 } else {
8203 /* Signed. */
8204 if ((op & 1) && shift == 0)
8205 gen_helper_ssat16(tmp, tmp, tmp2);
8206 else
8207 gen_helper_ssat(tmp, tmp, tmp2);
8208 }
8209 tcg_temp_free_i32(tmp2);
8210 break;
8211 }
8212 store_reg(s, rd, tmp);
8213 } else {
8214 imm = ((insn & 0x04000000) >> 15)
8215 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8216 if (insn & (1 << 22)) {
8217 /* 16-bit immediate. */
8218 imm |= (insn >> 4) & 0xf000;
8219 if (insn & (1 << 23)) {
8220 /* movt */
8221 tmp = load_reg(s, rd);
8222 tcg_gen_ext16u_i32(tmp, tmp);
8223 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8224 } else {
8225 /* movw */
8226 tmp = new_tmp();
8227 tcg_gen_movi_i32(tmp, imm);
8228 }
8229 } else {
8230 /* Add/sub 12-bit immediate. */
8231 if (rn == 15) {
8232 offset = s->pc & ~(uint32_t)3;
8233 if (insn & (1 << 23))
8234 offset -= imm;
8235 else
8236 offset += imm;
8237 tmp = new_tmp();
8238 tcg_gen_movi_i32(tmp, offset);
8239 } else {
8240 tmp = load_reg(s, rn);
8241 if (insn & (1 << 23))
8242 tcg_gen_subi_i32(tmp, tmp, imm);
8243 else
8244 tcg_gen_addi_i32(tmp, tmp, imm);
8245 }
8246 }
8247 store_reg(s, rd, tmp);
8248 }
8249 } else {
8250 int shifter_out = 0;
8251 /* modified 12-bit immediate. */
8252 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8253 imm = (insn & 0xff);
8254 switch (shift) {
8255 case 0: /* XY */
8256 /* Nothing to do. */
8257 break;
8258 case 1: /* 00XY00XY */
8259 imm |= imm << 16;
8260 break;
8261 case 2: /* XY00XY00 */
8262 imm |= imm << 16;
8263 imm <<= 8;
8264 break;
8265 case 3: /* XYXYXYXY */
8266 imm |= imm << 16;
8267 imm |= imm << 8;
8268 break;
8269 default: /* Rotated constant. */
8270 shift = (shift << 1) | (imm >> 7);
8271 imm |= 0x80;
8272 imm = imm << (32 - shift);
8273 shifter_out = 1;
8274 break;
8275 }
8276 tmp2 = new_tmp();
8277 tcg_gen_movi_i32(tmp2, imm);
8278 rn = (insn >> 16) & 0xf;
8279 if (rn == 15) {
8280 tmp = new_tmp();
8281 tcg_gen_movi_i32(tmp, 0);
8282 } else {
8283 tmp = load_reg(s, rn);
8284 }
8285 op = (insn >> 21) & 0xf;
8286 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8287 shifter_out, tmp, tmp2))
8288 goto illegal_op;
8289 dead_tmp(tmp2);
8290 rd = (insn >> 8) & 0xf;
8291 if (rd != 15) {
8292 store_reg(s, rd, tmp);
8293 } else {
8294 dead_tmp(tmp);
8295 }
8296 }
8297 }
8298 break;
8299 case 12: /* Load/store single data item. */
8300 {
8301 int postinc = 0;
8302 int writeback = 0;
8303 int user;
8304 if ((insn & 0x01100000) == 0x01000000) {
8305 if (disas_neon_ls_insn(env, s, insn))
8306 goto illegal_op;
8307 break;
8308 }
8309 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8310 if (rs == 15) {
8311 if (!(insn & (1 << 20))) {
8312 goto illegal_op;
8313 }
8314 if (op != 2) {
8315 /* Byte or halfword load space with dest == r15 : memory hints.
8316 * Catch them early so we don't emit pointless addressing code.
8317 * This space is a mix of:
8318 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8319 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8320 * cores)
8321 * unallocated hints, which must be treated as NOPs
8322 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8323 * which is easiest for the decoding logic
8324 * Some space which must UNDEF
8325 */
8326 int op1 = (insn >> 23) & 3;
8327 int op2 = (insn >> 6) & 0x3f;
8328 if (op & 2) {
8329 goto illegal_op;
8330 }
8331 if (rn == 15) {
8332 /* UNPREDICTABLE or unallocated hint */
8333 return 0;
8334 }
8335 if (op1 & 1) {
8336 return 0; /* PLD* or unallocated hint */
8337 }
8338 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8339 return 0; /* PLD* or unallocated hint */
8340 }
8341 /* UNDEF space, or an UNPREDICTABLE */
8342 return 1;
8343 }
8344 }
8345 user = IS_USER(s);
8346 if (rn == 15) {
8347 addr = new_tmp();
8348 /* PC relative. */
8349 /* s->pc has already been incremented by 4. */
8350 imm = s->pc & 0xfffffffc;
8351 if (insn & (1 << 23))
8352 imm += insn & 0xfff;
8353 else
8354 imm -= insn & 0xfff;
8355 tcg_gen_movi_i32(addr, imm);
8356 } else {
8357 addr = load_reg(s, rn);
8358 if (insn & (1 << 23)) {
8359 /* Positive offset. */
8360 imm = insn & 0xfff;
8361 tcg_gen_addi_i32(addr, addr, imm);
8362 } else {
8363 imm = insn & 0xff;
8364 switch ((insn >> 8) & 7) {
8365 case 0: case 8: /* Shifted Register. */
8366 shift = (insn >> 4) & 0xf;
8367 if (shift > 3)
8368 goto illegal_op;
8369 tmp = load_reg(s, rm);
8370 if (shift)
8371 tcg_gen_shli_i32(tmp, tmp, shift);
8372 tcg_gen_add_i32(addr, addr, tmp);
8373 dead_tmp(tmp);
8374 break;
8375 case 4: /* Negative offset. */
8376 tcg_gen_addi_i32(addr, addr, -imm);
8377 break;
8378 case 6: /* User privilege. */
8379 tcg_gen_addi_i32(addr, addr, imm);
8380 user = 1;
8381 break;
8382 case 1: /* Post-decrement. */
8383 imm = -imm;
8384 /* Fall through. */
8385 case 3: /* Post-increment. */
8386 postinc = 1;
8387 writeback = 1;
8388 break;
8389 case 5: /* Pre-decrement. */
8390 imm = -imm;
8391 /* Fall through. */
8392 case 7: /* Pre-increment. */
8393 tcg_gen_addi_i32(addr, addr, imm);
8394 writeback = 1;
8395 break;
8396 default:
8397 goto illegal_op;
8398 }
8399 }
8400 }
8401 if (insn & (1 << 20)) {
8402 /* Load. */
8403 switch (op) {
8404 case 0: tmp = gen_ld8u(addr, user); break;
8405 case 4: tmp = gen_ld8s(addr, user); break;
8406 case 1: tmp = gen_ld16u(addr, user); break;
8407 case 5: tmp = gen_ld16s(addr, user); break;
8408 case 2: tmp = gen_ld32(addr, user); break;
8409 default: goto illegal_op;
8410 }
8411 if (rs == 15) {
8412 gen_bx(s, tmp);
8413 } else {
8414 store_reg(s, rs, tmp);
8415 }
8416 } else {
8417 /* Store. */
8418 tmp = load_reg(s, rs);
8419 switch (op) {
8420 case 0: gen_st8(tmp, addr, user); break;
8421 case 1: gen_st16(tmp, addr, user); break;
8422 case 2: gen_st32(tmp, addr, user); break;
8423 default: goto illegal_op;
8424 }
8425 }
8426 if (postinc)
8427 tcg_gen_addi_i32(addr, addr, imm);
8428 if (writeback) {
8429 store_reg(s, rn, addr);
8430 } else {
8431 dead_tmp(addr);
8432 }
8433 }
8434 break;
8435 default:
8436 goto illegal_op;
8437 }
8438 return 0;
8439 illegal_op:
8440 return 1;
8441 }
8442
8443 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8444 {
8445 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8446 int32_t offset;
8447 int i;
8448 TCGv tmp;
8449 TCGv tmp2;
8450 TCGv addr;
8451
8452 if (s->condexec_mask) {
8453 cond = s->condexec_cond;
8454 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8455 s->condlabel = gen_new_label();
8456 gen_test_cc(cond ^ 1, s->condlabel);
8457 s->condjmp = 1;
8458 }
8459 }
8460
8461 insn = lduw_code(s->pc);
8462 s->pc += 2;
8463
8464 switch (insn >> 12) {
8465 case 0: case 1:
8466
8467 rd = insn & 7;
8468 op = (insn >> 11) & 3;
8469 if (op == 3) {
8470 /* add/subtract */
8471 rn = (insn >> 3) & 7;
8472 tmp = load_reg(s, rn);
8473 if (insn & (1 << 10)) {
8474 /* immediate */
8475 tmp2 = new_tmp();
8476 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8477 } else {
8478 /* reg */
8479 rm = (insn >> 6) & 7;
8480 tmp2 = load_reg(s, rm);
8481 }
8482 if (insn & (1 << 9)) {
8483 if (s->condexec_mask)
8484 tcg_gen_sub_i32(tmp, tmp, tmp2);
8485 else
8486 gen_helper_sub_cc(tmp, tmp, tmp2);
8487 } else {
8488 if (s->condexec_mask)
8489 tcg_gen_add_i32(tmp, tmp, tmp2);
8490 else
8491 gen_helper_add_cc(tmp, tmp, tmp2);
8492 }
8493 dead_tmp(tmp2);
8494 store_reg(s, rd, tmp);
8495 } else {
8496 /* shift immediate */
8497 rm = (insn >> 3) & 7;
8498 shift = (insn >> 6) & 0x1f;
8499 tmp = load_reg(s, rm);
8500 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8501 if (!s->condexec_mask)
8502 gen_logic_CC(tmp);
8503 store_reg(s, rd, tmp);
8504 }
8505 break;
8506 case 2: case 3:
8507 /* arithmetic large immediate */
8508 op = (insn >> 11) & 3;
8509 rd = (insn >> 8) & 0x7;
8510 if (op == 0) { /* mov */
8511 tmp = new_tmp();
8512 tcg_gen_movi_i32(tmp, insn & 0xff);
8513 if (!s->condexec_mask)
8514 gen_logic_CC(tmp);
8515 store_reg(s, rd, tmp);
8516 } else {
8517 tmp = load_reg(s, rd);
8518 tmp2 = new_tmp();
8519 tcg_gen_movi_i32(tmp2, insn & 0xff);
8520 switch (op) {
8521 case 1: /* cmp */
8522 gen_helper_sub_cc(tmp, tmp, tmp2);
8523 dead_tmp(tmp);
8524 dead_tmp(tmp2);
8525 break;
8526 case 2: /* add */
8527 if (s->condexec_mask)
8528 tcg_gen_add_i32(tmp, tmp, tmp2);
8529 else
8530 gen_helper_add_cc(tmp, tmp, tmp2);
8531 dead_tmp(tmp2);
8532 store_reg(s, rd, tmp);
8533 break;
8534 case 3: /* sub */
8535 if (s->condexec_mask)
8536 tcg_gen_sub_i32(tmp, tmp, tmp2);
8537 else
8538 gen_helper_sub_cc(tmp, tmp, tmp2);
8539 dead_tmp(tmp2);
8540 store_reg(s, rd, tmp);
8541 break;
8542 }
8543 }
8544 break;
8545 case 4:
8546 if (insn & (1 << 11)) {
8547 rd = (insn >> 8) & 7;
8548 /* load pc-relative. Bit 1 of PC is ignored. */
8549 val = s->pc + 2 + ((insn & 0xff) * 4);
8550 val &= ~(uint32_t)2;
8551 addr = new_tmp();
8552 tcg_gen_movi_i32(addr, val);
8553 tmp = gen_ld32(addr, IS_USER(s));
8554 dead_tmp(addr);
8555 store_reg(s, rd, tmp);
8556 break;
8557 }
8558 if (insn & (1 << 10)) {
8559 /* data processing extended or blx */
8560 rd = (insn & 7) | ((insn >> 4) & 8);
8561 rm = (insn >> 3) & 0xf;
8562 op = (insn >> 8) & 3;
8563 switch (op) {
8564 case 0: /* add */
8565 tmp = load_reg(s, rd);
8566 tmp2 = load_reg(s, rm);
8567 tcg_gen_add_i32(tmp, tmp, tmp2);
8568 dead_tmp(tmp2);
8569 store_reg(s, rd, tmp);
8570 break;
8571 case 1: /* cmp */
8572 tmp = load_reg(s, rd);
8573 tmp2 = load_reg(s, rm);
8574 gen_helper_sub_cc(tmp, tmp, tmp2);
8575 dead_tmp(tmp2);
8576 dead_tmp(tmp);
8577 break;
8578 case 2: /* mov/cpy */
8579 tmp = load_reg(s, rm);
8580 store_reg(s, rd, tmp);
8581 break;
8582 case 3:/* branch [and link] exchange thumb register */
8583 tmp = load_reg(s, rm);
8584 if (insn & (1 << 7)) {
8585 val = (uint32_t)s->pc | 1;
8586 tmp2 = new_tmp();
8587 tcg_gen_movi_i32(tmp2, val);
8588 store_reg(s, 14, tmp2);
8589 }
8590 gen_bx(s, tmp);
8591 break;
8592 }
8593 break;
8594 }
8595
8596 /* data processing register */
8597 rd = insn & 7;
8598 rm = (insn >> 3) & 7;
8599 op = (insn >> 6) & 0xf;
8600 if (op == 2 || op == 3 || op == 4 || op == 7) {
8601 /* the shift/rotate ops want the operands backwards */
8602 val = rm;
8603 rm = rd;
8604 rd = val;
8605 val = 1;
8606 } else {
8607 val = 0;
8608 }
8609
8610 if (op == 9) { /* neg */
8611 tmp = new_tmp();
8612 tcg_gen_movi_i32(tmp, 0);
8613 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8614 tmp = load_reg(s, rd);
8615 } else {
8616 TCGV_UNUSED(tmp);
8617 }
8618
8619 tmp2 = load_reg(s, rm);
8620 switch (op) {
8621 case 0x0: /* and */
8622 tcg_gen_and_i32(tmp, tmp, tmp2);
8623 if (!s->condexec_mask)
8624 gen_logic_CC(tmp);
8625 break;
8626 case 0x1: /* eor */
8627 tcg_gen_xor_i32(tmp, tmp, tmp2);
8628 if (!s->condexec_mask)
8629 gen_logic_CC(tmp);
8630 break;
8631 case 0x2: /* lsl */
8632 if (s->condexec_mask) {
8633 gen_helper_shl(tmp2, tmp2, tmp);
8634 } else {
8635 gen_helper_shl_cc(tmp2, tmp2, tmp);
8636 gen_logic_CC(tmp2);
8637 }
8638 break;
8639 case 0x3: /* lsr */
8640 if (s->condexec_mask) {
8641 gen_helper_shr(tmp2, tmp2, tmp);
8642 } else {
8643 gen_helper_shr_cc(tmp2, tmp2, tmp);
8644 gen_logic_CC(tmp2);
8645 }
8646 break;
8647 case 0x4: /* asr */
8648 if (s->condexec_mask) {
8649 gen_helper_sar(tmp2, tmp2, tmp);
8650 } else {
8651 gen_helper_sar_cc(tmp2, tmp2, tmp);
8652 gen_logic_CC(tmp2);
8653 }
8654 break;
8655 case 0x5: /* adc */
8656 if (s->condexec_mask)
8657 gen_adc(tmp, tmp2);
8658 else
8659 gen_helper_adc_cc(tmp, tmp, tmp2);
8660 break;
8661 case 0x6: /* sbc */
8662 if (s->condexec_mask)
8663 gen_sub_carry(tmp, tmp, tmp2);
8664 else
8665 gen_helper_sbc_cc(tmp, tmp, tmp2);
8666 break;
8667 case 0x7: /* ror */
8668 if (s->condexec_mask) {
8669 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8670 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
8671 } else {
8672 gen_helper_ror_cc(tmp2, tmp2, tmp);
8673 gen_logic_CC(tmp2);
8674 }
8675 break;
8676 case 0x8: /* tst */
8677 tcg_gen_and_i32(tmp, tmp, tmp2);
8678 gen_logic_CC(tmp);
8679 rd = 16;
8680 break;
8681 case 0x9: /* neg */
8682 if (s->condexec_mask)
8683 tcg_gen_neg_i32(tmp, tmp2);
8684 else
8685 gen_helper_sub_cc(tmp, tmp, tmp2);
8686 break;
8687 case 0xa: /* cmp */
8688 gen_helper_sub_cc(tmp, tmp, tmp2);
8689 rd = 16;
8690 break;
8691 case 0xb: /* cmn */
8692 gen_helper_add_cc(tmp, tmp, tmp2);
8693 rd = 16;
8694 break;
8695 case 0xc: /* orr */
8696 tcg_gen_or_i32(tmp, tmp, tmp2);
8697 if (!s->condexec_mask)
8698 gen_logic_CC(tmp);
8699 break;
8700 case 0xd: /* mul */
8701 tcg_gen_mul_i32(tmp, tmp, tmp2);
8702 if (!s->condexec_mask)
8703 gen_logic_CC(tmp);
8704 break;
8705 case 0xe: /* bic */
8706 tcg_gen_andc_i32(tmp, tmp, tmp2);
8707 if (!s->condexec_mask)
8708 gen_logic_CC(tmp);
8709 break;
8710 case 0xf: /* mvn */
8711 tcg_gen_not_i32(tmp2, tmp2);
8712 if (!s->condexec_mask)
8713 gen_logic_CC(tmp2);
8714 val = 1;
8715 rm = rd;
8716 break;
8717 }
8718 if (rd != 16) {
8719 if (val) {
8720 store_reg(s, rm, tmp2);
8721 if (op != 0xf)
8722 dead_tmp(tmp);
8723 } else {
8724 store_reg(s, rd, tmp);
8725 dead_tmp(tmp2);
8726 }
8727 } else {
8728 dead_tmp(tmp);
8729 dead_tmp(tmp2);
8730 }
8731 break;
8732
8733 case 5:
8734 /* load/store register offset. */
8735 rd = insn & 7;
8736 rn = (insn >> 3) & 7;
8737 rm = (insn >> 6) & 7;
8738 op = (insn >> 9) & 7;
8739 addr = load_reg(s, rn);
8740 tmp = load_reg(s, rm);
8741 tcg_gen_add_i32(addr, addr, tmp);
8742 dead_tmp(tmp);
8743
8744 if (op < 3) /* store */
8745 tmp = load_reg(s, rd);
8746
8747 switch (op) {
8748 case 0: /* str */
8749 gen_st32(tmp, addr, IS_USER(s));
8750 break;
8751 case 1: /* strh */
8752 gen_st16(tmp, addr, IS_USER(s));
8753 break;
8754 case 2: /* strb */
8755 gen_st8(tmp, addr, IS_USER(s));
8756 break;
8757 case 3: /* ldrsb */
8758 tmp = gen_ld8s(addr, IS_USER(s));
8759 break;
8760 case 4: /* ldr */
8761 tmp = gen_ld32(addr, IS_USER(s));
8762 break;
8763 case 5: /* ldrh */
8764 tmp = gen_ld16u(addr, IS_USER(s));
8765 break;
8766 case 6: /* ldrb */
8767 tmp = gen_ld8u(addr, IS_USER(s));
8768 break;
8769 case 7: /* ldrsh */
8770 tmp = gen_ld16s(addr, IS_USER(s));
8771 break;
8772 }
8773 if (op >= 3) /* load */
8774 store_reg(s, rd, tmp);
8775 dead_tmp(addr);
8776 break;
8777
8778 case 6:
8779 /* load/store word immediate offset */
8780 rd = insn & 7;
8781 rn = (insn >> 3) & 7;
8782 addr = load_reg(s, rn);
8783 val = (insn >> 4) & 0x7c;
8784 tcg_gen_addi_i32(addr, addr, val);
8785
8786 if (insn & (1 << 11)) {
8787 /* load */
8788 tmp = gen_ld32(addr, IS_USER(s));
8789 store_reg(s, rd, tmp);
8790 } else {
8791 /* store */
8792 tmp = load_reg(s, rd);
8793 gen_st32(tmp, addr, IS_USER(s));
8794 }
8795 dead_tmp(addr);
8796 break;
8797
8798 case 7:
8799 /* load/store byte immediate offset */
8800 rd = insn & 7;
8801 rn = (insn >> 3) & 7;
8802 addr = load_reg(s, rn);
8803 val = (insn >> 6) & 0x1f;
8804 tcg_gen_addi_i32(addr, addr, val);
8805
8806 if (insn & (1 << 11)) {
8807 /* load */
8808 tmp = gen_ld8u(addr, IS_USER(s));
8809 store_reg(s, rd, tmp);
8810 } else {
8811 /* store */
8812 tmp = load_reg(s, rd);
8813 gen_st8(tmp, addr, IS_USER(s));
8814 }
8815 dead_tmp(addr);
8816 break;
8817
8818 case 8:
8819 /* load/store halfword immediate offset */
8820 rd = insn & 7;
8821 rn = (insn >> 3) & 7;
8822 addr = load_reg(s, rn);
8823 val = (insn >> 5) & 0x3e;
8824 tcg_gen_addi_i32(addr, addr, val);
8825
8826 if (insn & (1 << 11)) {
8827 /* load */
8828 tmp = gen_ld16u(addr, IS_USER(s));
8829 store_reg(s, rd, tmp);
8830 } else {
8831 /* store */
8832 tmp = load_reg(s, rd);
8833 gen_st16(tmp, addr, IS_USER(s));
8834 }
8835 dead_tmp(addr);
8836 break;
8837
8838 case 9:
8839 /* load/store from stack */
8840 rd = (insn >> 8) & 7;
8841 addr = load_reg(s, 13);
8842 val = (insn & 0xff) * 4;
8843 tcg_gen_addi_i32(addr, addr, val);
8844
8845 if (insn & (1 << 11)) {
8846 /* load */
8847 tmp = gen_ld32(addr, IS_USER(s));
8848 store_reg(s, rd, tmp);
8849 } else {
8850 /* store */
8851 tmp = load_reg(s, rd);
8852 gen_st32(tmp, addr, IS_USER(s));
8853 }
8854 dead_tmp(addr);
8855 break;
8856
8857 case 10:
8858 /* add to high reg */
8859 rd = (insn >> 8) & 7;
8860 if (insn & (1 << 11)) {
8861 /* SP */
8862 tmp = load_reg(s, 13);
8863 } else {
8864 /* PC. bit 1 is ignored. */
8865 tmp = new_tmp();
8866 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
8867 }
8868 val = (insn & 0xff) * 4;
8869 tcg_gen_addi_i32(tmp, tmp, val);
8870 store_reg(s, rd, tmp);
8871 break;
8872
8873 case 11:
8874 /* misc */
8875 op = (insn >> 8) & 0xf;
8876 switch (op) {
8877 case 0:
8878 /* adjust stack pointer */
8879 tmp = load_reg(s, 13);
8880 val = (insn & 0x7f) * 4;
8881 if (insn & (1 << 7))
8882 val = -(int32_t)val;
8883 tcg_gen_addi_i32(tmp, tmp, val);
8884 store_reg(s, 13, tmp);
8885 break;
8886
8887 case 2: /* sign/zero extend. */
8888 ARCH(6);
8889 rd = insn & 7;
8890 rm = (insn >> 3) & 7;
8891 tmp = load_reg(s, rm);
8892 switch ((insn >> 6) & 3) {
8893 case 0: gen_sxth(tmp); break;
8894 case 1: gen_sxtb(tmp); break;
8895 case 2: gen_uxth(tmp); break;
8896 case 3: gen_uxtb(tmp); break;
8897 }
8898 store_reg(s, rd, tmp);
8899 break;
8900 case 4: case 5: case 0xc: case 0xd:
8901 /* push/pop */
8902 addr = load_reg(s, 13);
8903 if (insn & (1 << 8))
8904 offset = 4;
8905 else
8906 offset = 0;
8907 for (i = 0; i < 8; i++) {
8908 if (insn & (1 << i))
8909 offset += 4;
8910 }
8911 if ((insn & (1 << 11)) == 0) {
8912 tcg_gen_addi_i32(addr, addr, -offset);
8913 }
8914 for (i = 0; i < 8; i++) {
8915 if (insn & (1 << i)) {
8916 if (insn & (1 << 11)) {
8917 /* pop */
8918 tmp = gen_ld32(addr, IS_USER(s));
8919 store_reg(s, i, tmp);
8920 } else {
8921 /* push */
8922 tmp = load_reg(s, i);
8923 gen_st32(tmp, addr, IS_USER(s));
8924 }
8925 /* advance to the next address. */
8926 tcg_gen_addi_i32(addr, addr, 4);
8927 }
8928 }
8929 TCGV_UNUSED(tmp);
8930 if (insn & (1 << 8)) {
8931 if (insn & (1 << 11)) {
8932 /* pop pc */
8933 tmp = gen_ld32(addr, IS_USER(s));
8934 /* don't set the pc until the rest of the instruction
8935 has completed */
8936 } else {
8937 /* push lr */
8938 tmp = load_reg(s, 14);
8939 gen_st32(tmp, addr, IS_USER(s));
8940 }
8941 tcg_gen_addi_i32(addr, addr, 4);
8942 }
8943 if ((insn & (1 << 11)) == 0) {
8944 tcg_gen_addi_i32(addr, addr, -offset);
8945 }
8946 /* write back the new stack pointer */
8947 store_reg(s, 13, addr);
8948 /* set the new PC value */
8949 if ((insn & 0x0900) == 0x0900)
8950 gen_bx(s, tmp);
8951 break;
8952
8953 case 1: case 3: case 9: case 11: /* czb */
8954 rm = insn & 7;
8955 tmp = load_reg(s, rm);
8956 s->condlabel = gen_new_label();
8957 s->condjmp = 1;
8958 if (insn & (1 << 11))
8959 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
8960 else
8961 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
8962 dead_tmp(tmp);
8963 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8964 val = (uint32_t)s->pc + 2;
8965 val += offset;
8966 gen_jmp(s, val);
8967 break;
8968
8969 case 15: /* IT, nop-hint. */
8970 if ((insn & 0xf) == 0) {
8971 gen_nop_hint(s, (insn >> 4) & 0xf);
8972 break;
8973 }
8974 /* If Then. */
8975 s->condexec_cond = (insn >> 4) & 0xe;
8976 s->condexec_mask = insn & 0x1f;
8977 /* No actual code generated for this insn, just setup state. */
8978 break;
8979
8980 case 0xe: /* bkpt */
8981 gen_exception_insn(s, 2, EXCP_BKPT);
8982 break;
8983
8984 case 0xa: /* rev */
8985 ARCH(6);
8986 rn = (insn >> 3) & 0x7;
8987 rd = insn & 0x7;
8988 tmp = load_reg(s, rn);
8989 switch ((insn >> 6) & 3) {
8990 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
8991 case 1: gen_rev16(tmp); break;
8992 case 3: gen_revsh(tmp); break;
8993 default: goto illegal_op;
8994 }
8995 store_reg(s, rd, tmp);
8996 break;
8997
8998 case 6: /* cps */
8999 ARCH(6);
9000 if (IS_USER(s))
9001 break;
9002 if (IS_M(env)) {
9003 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9004 /* PRIMASK */
9005 if (insn & 1) {
9006 addr = tcg_const_i32(16);
9007 gen_helper_v7m_msr(cpu_env, addr, tmp);
9008 tcg_temp_free_i32(addr);
9009 }
9010 /* FAULTMASK */
9011 if (insn & 2) {
9012 addr = tcg_const_i32(17);
9013 gen_helper_v7m_msr(cpu_env, addr, tmp);
9014 tcg_temp_free_i32(addr);
9015 }
9016 tcg_temp_free_i32(tmp);
9017 gen_lookup_tb(s);
9018 } else {
9019 if (insn & (1 << 4))
9020 shift = CPSR_A | CPSR_I | CPSR_F;
9021 else
9022 shift = 0;
9023 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9024 }
9025 break;
9026
9027 default:
9028 goto undef;
9029 }
9030 break;
9031
9032 case 12:
9033 /* load/store multiple */
9034 rn = (insn >> 8) & 0x7;
9035 addr = load_reg(s, rn);
9036 for (i = 0; i < 8; i++) {
9037 if (insn & (1 << i)) {
9038 if (insn & (1 << 11)) {
9039 /* load */
9040 tmp = gen_ld32(addr, IS_USER(s));
9041 store_reg(s, i, tmp);
9042 } else {
9043 /* store */
9044 tmp = load_reg(s, i);
9045 gen_st32(tmp, addr, IS_USER(s));
9046 }
9047 /* advance to the next address */
9048 tcg_gen_addi_i32(addr, addr, 4);
9049 }
9050 }
9051 /* Base register writeback. */
9052 if ((insn & (1 << rn)) == 0) {
9053 store_reg(s, rn, addr);
9054 } else {
9055 dead_tmp(addr);
9056 }
9057 break;
9058
9059 case 13:
9060 /* conditional branch or swi */
9061 cond = (insn >> 8) & 0xf;
9062 if (cond == 0xe)
9063 goto undef;
9064
9065 if (cond == 0xf) {
9066 /* swi */
9067 gen_set_pc_im(s->pc);
9068 s->is_jmp = DISAS_SWI;
9069 break;
9070 }
9071 /* generate a conditional jump to next instruction */
9072 s->condlabel = gen_new_label();
9073 gen_test_cc(cond ^ 1, s->condlabel);
9074 s->condjmp = 1;
9075
9076 /* jump to the offset */
9077 val = (uint32_t)s->pc + 2;
9078 offset = ((int32_t)insn << 24) >> 24;
9079 val += offset << 1;
9080 gen_jmp(s, val);
9081 break;
9082
9083 case 14:
9084 if (insn & (1 << 11)) {
9085 if (disas_thumb2_insn(env, s, insn))
9086 goto undef32;
9087 break;
9088 }
9089 /* unconditional branch */
9090 val = (uint32_t)s->pc;
9091 offset = ((int32_t)insn << 21) >> 21;
9092 val += (offset << 1) + 2;
9093 gen_jmp(s, val);
9094 break;
9095
9096 case 15:
9097 if (disas_thumb2_insn(env, s, insn))
9098 goto undef32;
9099 break;
9100 }
9101 return;
9102 undef32:
9103 gen_exception_insn(s, 4, EXCP_UDEF);
9104 return;
9105 illegal_op:
9106 undef:
9107 gen_exception_insn(s, 2, EXCP_UDEF);
9108 }
9109
9110 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9111 basic block 'tb'. If search_pc is TRUE, also generate PC
9112 information for each intermediate instruction. */
9113 static inline void gen_intermediate_code_internal(CPUState *env,
9114 TranslationBlock *tb,
9115 int search_pc)
9116 {
9117 DisasContext dc1, *dc = &dc1;
9118 CPUBreakpoint *bp;
9119 uint16_t *gen_opc_end;
9120 int j, lj;
9121 target_ulong pc_start;
9122 uint32_t next_page_start;
9123 int num_insns;
9124 int max_insns;
9125
9126 /* generate intermediate code */
9127 num_temps = 0;
9128
9129 pc_start = tb->pc;
9130
9131 dc->tb = tb;
9132
9133 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9134
9135 dc->is_jmp = DISAS_NEXT;
9136 dc->pc = pc_start;
9137 dc->singlestep_enabled = env->singlestep_enabled;
9138 dc->condjmp = 0;
9139 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9140 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9141 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9142 #if !defined(CONFIG_USER_ONLY)
9143 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9144 #endif
9145 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9146 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9147 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9148 cpu_F0s = tcg_temp_new_i32();
9149 cpu_F1s = tcg_temp_new_i32();
9150 cpu_F0d = tcg_temp_new_i64();
9151 cpu_F1d = tcg_temp_new_i64();
9152 cpu_V0 = cpu_F0d;
9153 cpu_V1 = cpu_F1d;
9154 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9155 cpu_M0 = tcg_temp_new_i64();
9156 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9157 lj = -1;
9158 num_insns = 0;
9159 max_insns = tb->cflags & CF_COUNT_MASK;
9160 if (max_insns == 0)
9161 max_insns = CF_COUNT_MASK;
9162
9163 gen_icount_start();
9164
9165 /* A note on handling of the condexec (IT) bits:
9166 *
9167 * We want to avoid the overhead of having to write the updated condexec
9168 * bits back to the CPUState for every instruction in an IT block. So:
9169 * (1) if the condexec bits are not already zero then we write
9170 * zero back into the CPUState now. This avoids complications trying
9171 * to do it at the end of the block. (For example if we don't do this
9172 * it's hard to identify whether we can safely skip writing condexec
9173 * at the end of the TB, which we definitely want to do for the case
9174 * where a TB doesn't do anything with the IT state at all.)
9175 * (2) if we are going to leave the TB then we call gen_set_condexec()
9176 * which will write the correct value into CPUState if zero is wrong.
9177 * This is done both for leaving the TB at the end, and for leaving
9178 * it because of an exception we know will happen, which is done in
9179 * gen_exception_insn(). The latter is necessary because we need to
9180 * leave the TB with the PC/IT state just prior to execution of the
9181 * instruction which caused the exception.
9182 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9183 * then the CPUState will be wrong and we need to reset it.
9184 * This is handled in the same way as restoration of the
9185 * PC in these situations: we will be called again with search_pc=1
9186 * and generate a mapping of the condexec bits for each PC in
9187 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9188 * the condexec bits.
9189 *
9190 * Note that there are no instructions which can read the condexec
9191 * bits, and none which can write non-static values to them, so
9192 * we don't need to care about whether CPUState is correct in the
9193 * middle of a TB.
9194 */
9195
9196 /* Reset the conditional execution bits immediately. This avoids
9197 complications trying to do it at the end of the block. */
9198 if (dc->condexec_mask || dc->condexec_cond)
9199 {
9200 TCGv tmp = new_tmp();
9201 tcg_gen_movi_i32(tmp, 0);
9202 store_cpu_field(tmp, condexec_bits);
9203 }
9204 do {
9205 #ifdef CONFIG_USER_ONLY
9206 /* Intercept jump to the magic kernel page. */
9207 if (dc->pc >= 0xffff0000) {
9208 /* We always get here via a jump, so know we are not in a
9209 conditional execution block. */
9210 gen_exception(EXCP_KERNEL_TRAP);
9211 dc->is_jmp = DISAS_UPDATE;
9212 break;
9213 }
9214 #else
9215 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9216 /* We always get here via a jump, so know we are not in a
9217 conditional execution block. */
9218 gen_exception(EXCP_EXCEPTION_EXIT);
9219 dc->is_jmp = DISAS_UPDATE;
9220 break;
9221 }
9222 #endif
9223
9224 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9225 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9226 if (bp->pc == dc->pc) {
9227 gen_exception_insn(dc, 0, EXCP_DEBUG);
9228 /* Advance PC so that clearing the breakpoint will
9229 invalidate this TB. */
9230 dc->pc += 2;
9231 goto done_generating;
9232 break;
9233 }
9234 }
9235 }
9236 if (search_pc) {
9237 j = gen_opc_ptr - gen_opc_buf;
9238 if (lj < j) {
9239 lj++;
9240 while (lj < j)
9241 gen_opc_instr_start[lj++] = 0;
9242 }
9243 gen_opc_pc[lj] = dc->pc;
9244 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9245 gen_opc_instr_start[lj] = 1;
9246 gen_opc_icount[lj] = num_insns;
9247 }
9248
9249 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9250 gen_io_start();
9251
9252 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9253 tcg_gen_debug_insn_start(dc->pc);
9254 }
9255
9256 if (dc->thumb) {
9257 disas_thumb_insn(env, dc);
9258 if (dc->condexec_mask) {
9259 dc->condexec_cond = (dc->condexec_cond & 0xe)
9260 | ((dc->condexec_mask >> 4) & 1);
9261 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9262 if (dc->condexec_mask == 0) {
9263 dc->condexec_cond = 0;
9264 }
9265 }
9266 } else {
9267 disas_arm_insn(env, dc);
9268 }
9269 if (num_temps) {
9270 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9271 num_temps = 0;
9272 }
9273
9274 if (dc->condjmp && !dc->is_jmp) {
9275 gen_set_label(dc->condlabel);
9276 dc->condjmp = 0;
9277 }
9278 /* Translation stops when a conditional branch is encountered.
9279 * Otherwise the subsequent code could get translated several times.
9280 * Also stop translation when a page boundary is reached. This
9281 * ensures prefetch aborts occur at the right place. */
9282 num_insns ++;
9283 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9284 !env->singlestep_enabled &&
9285 !singlestep &&
9286 dc->pc < next_page_start &&
9287 num_insns < max_insns);
9288
9289 if (tb->cflags & CF_LAST_IO) {
9290 if (dc->condjmp) {
9291 /* FIXME: This can theoretically happen with self-modifying
9292 code. */
9293 cpu_abort(env, "IO on conditional branch instruction");
9294 }
9295 gen_io_end();
9296 }
9297
9298 /* At this stage dc->condjmp will only be set when the skipped
9299 instruction was a conditional branch or trap, and the PC has
9300 already been written. */
9301 if (unlikely(env->singlestep_enabled)) {
9302 /* Make sure the pc is updated, and raise a debug exception. */
9303 if (dc->condjmp) {
9304 gen_set_condexec(dc);
9305 if (dc->is_jmp == DISAS_SWI) {
9306 gen_exception(EXCP_SWI);
9307 } else {
9308 gen_exception(EXCP_DEBUG);
9309 }
9310 gen_set_label(dc->condlabel);
9311 }
9312 if (dc->condjmp || !dc->is_jmp) {
9313 gen_set_pc_im(dc->pc);
9314 dc->condjmp = 0;
9315 }
9316 gen_set_condexec(dc);
9317 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9318 gen_exception(EXCP_SWI);
9319 } else {
9320 /* FIXME: Single stepping a WFI insn will not halt
9321 the CPU. */
9322 gen_exception(EXCP_DEBUG);
9323 }
9324 } else {
9325 /* While branches must always occur at the end of an IT block,
9326 there are a few other things that can cause us to terminate
9327 the TB in the middel of an IT block:
9328 - Exception generating instructions (bkpt, swi, undefined).
9329 - Page boundaries.
9330 - Hardware watchpoints.
9331 Hardware breakpoints have already been handled and skip this code.
9332 */
9333 gen_set_condexec(dc);
9334 switch(dc->is_jmp) {
9335 case DISAS_NEXT:
9336 gen_goto_tb(dc, 1, dc->pc);
9337 break;
9338 default:
9339 case DISAS_JUMP:
9340 case DISAS_UPDATE:
9341 /* indicate that the hash table must be used to find the next TB */
9342 tcg_gen_exit_tb(0);
9343 break;
9344 case DISAS_TB_JUMP:
9345 /* nothing more to generate */
9346 break;
9347 case DISAS_WFI:
9348 gen_helper_wfi();
9349 break;
9350 case DISAS_SWI:
9351 gen_exception(EXCP_SWI);
9352 break;
9353 }
9354 if (dc->condjmp) {
9355 gen_set_label(dc->condlabel);
9356 gen_set_condexec(dc);
9357 gen_goto_tb(dc, 1, dc->pc);
9358 dc->condjmp = 0;
9359 }
9360 }
9361
9362 done_generating:
9363 gen_icount_end(tb, num_insns);
9364 *gen_opc_ptr = INDEX_op_end;
9365
9366 #ifdef DEBUG_DISAS
9367 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9368 qemu_log("----------------\n");
9369 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9370 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9371 qemu_log("\n");
9372 }
9373 #endif
9374 if (search_pc) {
9375 j = gen_opc_ptr - gen_opc_buf;
9376 lj++;
9377 while (lj <= j)
9378 gen_opc_instr_start[lj++] = 0;
9379 } else {
9380 tb->size = dc->pc - pc_start;
9381 tb->icount = num_insns;
9382 }
9383 }
9384
9385 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9386 {
9387 gen_intermediate_code_internal(env, tb, 0);
9388 }
9389
9390 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9391 {
9392 gen_intermediate_code_internal(env, tb, 1);
9393 }
9394
9395 static const char *cpu_mode_names[16] = {
9396 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9397 "???", "???", "???", "und", "???", "???", "???", "sys"
9398 };
9399
9400 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9401 int flags)
9402 {
9403 int i;
9404 #if 0
9405 union {
9406 uint32_t i;
9407 float s;
9408 } s0, s1;
9409 CPU_DoubleU d;
9410 /* ??? This assumes float64 and double have the same layout.
9411 Oh well, it's only debug dumps. */
9412 union {
9413 float64 f64;
9414 double d;
9415 } d0;
9416 #endif
9417 uint32_t psr;
9418
9419 for(i=0;i<16;i++) {
9420 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9421 if ((i % 4) == 3)
9422 cpu_fprintf(f, "\n");
9423 else
9424 cpu_fprintf(f, " ");
9425 }
9426 psr = cpsr_read(env);
9427 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9428 psr,
9429 psr & (1 << 31) ? 'N' : '-',
9430 psr & (1 << 30) ? 'Z' : '-',
9431 psr & (1 << 29) ? 'C' : '-',
9432 psr & (1 << 28) ? 'V' : '-',
9433 psr & CPSR_T ? 'T' : 'A',
9434 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9435
9436 #if 0
9437 for (i = 0; i < 16; i++) {
9438 d.d = env->vfp.regs[i];
9439 s0.i = d.l.lower;
9440 s1.i = d.l.upper;
9441 d0.f64 = d.d;
9442 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9443 i * 2, (int)s0.i, s0.s,
9444 i * 2 + 1, (int)s1.i, s1.s,
9445 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9446 d0.d);
9447 }
9448 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9449 #endif
9450 }
9451
9452 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9453 unsigned long searched_pc, int pc_pos, void *puc)
9454 {
9455 env->regs[15] = gen_opc_pc[pc_pos];
9456 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9457 }
Qemu copy for testing