target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #ifndef CPU_CRIS_H
  22 #define CPU_CRIS_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #include "cpu-defs.h"
  27
  28 #define TARGET_HAS_ICE 1
  29
  30 #define ELF_MACHINE     EM_CRIS
  31
  32 #define EXCP_MMU_EXEC    0
  33 #define EXCP_MMU_READ    1
  34 #define EXCP_MMU_WRITE   2
  35 #define EXCP_MMU_FLUSH   3
  36 #define EXCP_MMU_FAULT   4
  37 #define EXCP_BREAK      16 /* trap.  */
  38
  39 /* Register aliases. R0 - R15 */
  40 #define R_FP  8
  41 #define R_SP  14
  42 #define R_ACR 15
  43
  44 /* Support regs, P0 - P15  */
  45 #define PR_BZ  0
  46 #define PR_VR  1
  47 #define PR_PID 2
  48 #define PR_SRS 3
  49 #define PR_WZ  4
  50 #define PR_EXS 5
  51 #define PR_EDA 6
  52 #define PR_MOF 7
  53 #define PR_DZ  8
  54 #define PR_EBP 9
  55 #define PR_ERP 10
  56 #define PR_SRP 11
  57 #define PR_CCS 13
  58 #define PR_USP 14
  59 #define PR_SPC 15
  60
  61 /* CPU flags.  */
  62 #define S_FLAG 0x200
  63 #define R_FLAG 0x100
  64 #define P_FLAG 0x80
  65 #define U_FLAG 0x40
  66 #define P_FLAG 0x80
  67 #define U_FLAG 0x40
  68 #define I_FLAG 0x20
  69 #define X_FLAG 0x10
  70 #define N_FLAG 0x08
  71 #define Z_FLAG 0x04
  72 #define V_FLAG 0x02
  73 #define C_FLAG 0x01
  74 #define ALU_FLAGS 0x1F
  75
  76 /* Condition codes.  */
  77 #define CC_CC   0
  78 #define CC_CS   1
  79 #define CC_NE   2
  80 #define CC_EQ   3
  81 #define CC_VC   4
  82 #define CC_VS   5
  83 #define CC_PL   6
  84 #define CC_MI   7
  85 #define CC_LS   8
  86 #define CC_HI   9
  87 #define CC_GE  10
  88 #define CC_LT  11
  89 #define CC_GT  12
  90 #define CC_LE  13
  91 #define CC_A   14
  92 #define CC_P   15
  93
  94 /* Internal flags for the implementation.  */
  95 #define F_DELAYSLOT 1
  96
  97 #define NB_MMU_MODES 2
  98
  99 typedef struct CPUCRISState {
 100         uint32_t regs[16];
 101         /* P0 - P15 are referred to as special registers in the docs.  */
 102         uint32_t pregs[16];
 103
 104         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 105         uint32_t pc;
 106
 107         /* Pseudo register for the kernel stack.  */
 108         uint32_t ksp;
 109
 110         /* These are setup up by the guest code just before transfering the
 111            control back to the host.  */
 112         int jmp;
 113         uint32_t btarget;
 114         int btaken;
 115
 116         /* Condition flag tracking.  */
 117         uint32_t cc_op;
 118         uint32_t cc_mask;
 119         uint32_t cc_dest;
 120         uint32_t cc_src;
 121         uint32_t cc_result;
 122
 123         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 124         int cc_size;
 125
 126         /* Extended arithmetics.  */
 127         int cc_x_live;
 128         int cc_x;
 129
 130         int exception_index;
 131         int interrupt_request;
 132         int interrupt_vector;
 133         int fault_vector;
 134         int trap_vector;
 135
 136         uint32_t debug1;
 137         uint32_t debug2;
 138         uint32_t debug3;
 139
 140         struct
 141         {
 142                 int exec_insns;
 143                 int exec_loads;
 144                 int exec_stores;
 145         } stats;
 146
 147         /* FIXME: add a check in the translator to avoid writing to support
 148            register sets beyond the 4th. The ISA allows up to 256! but in
 149            practice there is no core that implements more than 4.
 150
 151            Support function registers are used to control units close to the
 152            core. Accesses do not pass down the normal hierarchy.
 153         */
 154         uint32_t sregs[4][16];
 155
 156         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 157            randomness for the 'hint' the mmu gives to sw for chosing valid
 158            sets on TLB refills.  */
 159         uint32_t mmu_rand_lfsr;
 160
 161         /*
 162          * We just store the stores to the tlbset here for later evaluation
 163          * when the hw needs access to them.
 164          *
 165          * One for I and another for D.
 166          */
 167         struct
 168         {
 169                 uint32_t hi;
 170                 uint32_t lo;
 171         } tlbsets[2][4][16];
 172
 173         int features;
 174         int user_mode_only;
 175         int halted;
 176
 177         jmp_buf jmp_env;
 178         CPU_COMMON
 179 } CPUCRISState;
 180
 181 CPUCRISState *cpu_cris_init(const char *cpu_model);
 182 int cpu_cris_exec(CPUCRISState *s);
 183 void cpu_cris_close(CPUCRISState *s);
 184 void do_interrupt(CPUCRISState *env);
 185 /* you can call this signal handler from your SIGBUS and SIGSEGV
 186    signal handlers to inform the virtual CPU of exceptions. non zero
 187    is returned if the signal was handled by the virtual CPU.  */
 188 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 189                            void *puc);
 190 void cpu_cris_flush_flags(CPUCRISState *, int);
 191
 192
 193 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 194                           int is_asi);
 195
 196 enum {
 197     CC_OP_DYNAMIC, /* Use env->cc_op  */
 198     CC_OP_FLAGS,
 199     CC_OP_LOGIC,
 200     CC_OP_CMP,
 201     CC_OP_MOVE,
 202     CC_OP_MOVE_PD,
 203     CC_OP_MOVE_SD,
 204     CC_OP_ADD,
 205     CC_OP_ADDC,
 206     CC_OP_MCP,
 207     CC_OP_ADDU,
 208     CC_OP_SUB,
 209     CC_OP_SUBU,
 210     CC_OP_NEG,
 211     CC_OP_BTST,
 212     CC_OP_MULS,
 213     CC_OP_MULU,
 214     CC_OP_DSTEP,
 215     CC_OP_BOUND,
 216
 217     CC_OP_OR,
 218     CC_OP_AND,
 219     CC_OP_XOR,
 220     CC_OP_LSL,
 221     CC_OP_LSR,
 222     CC_OP_ASR,
 223     CC_OP_LZ
 224 };
 225
 226 #define CCF_C 0x01
 227 #define CCF_V 0x02
 228 #define CCF_Z 0x04
 229 #define CCF_N 0x08
 230 #define CCF_X 0x10
 231
 232 #define CRIS_SSP    0
 233 #define CRIS_USP    1
 234
 235 void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
 236 void cris_set_macsr(CPUCRISState *env, uint32_t val);
 237 void cris_switch_sp(CPUCRISState *env);
 238
 239 void do_cris_semihosting(CPUCRISState *env, int nr);
 240
 241 enum cris_features {
 242     CRIS_FEATURE_CF_ISA_MUL,
 243 };
 244
 245 static inline int cris_feature(CPUCRISState *env, int feature)
 246 {
 247     return (env->features & (1u << feature)) != 0;
 248 }
 249
 250 void register_cris_insns (CPUCRISState *env);
 251
 252 /* CRIS uses 8k pages.  */
 253 #define TARGET_PAGE_BITS 13
 254 #define MMAP_SHIFT TARGET_PAGE_BITS
 255
 256 #define CPUState CPUCRISState
 257 #define cpu_init cpu_cris_init
 258 #define cpu_exec cpu_cris_exec
 259 #define cpu_gen_code cpu_cris_gen_code
 260 #define cpu_signal_handler cpu_cris_signal_handler
 261
 262 /* MMU modes definitions */
 263 #define MMU_MODE0_SUFFIX _kernel
 264 #define MMU_MODE1_SUFFIX _user
 265 #define MMU_USER_IDX 1
 266 static inline int cpu_mmu_index (CPUState *env)
 267 {
 268         return !!(env->pregs[PR_CCS] & U_FLAG);
 269 }
 270
 271 /* Support function regs.  */
 272 #define SFR_RW_GC_CFG      0][0
 273 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 274 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 275 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 276 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 277 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 278 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 279 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 280
 281 #include "cpu-all.h"
 282 #endif