target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #ifndef CPU_CRIS_H
  21 #define CPU_CRIS_H
  22
  23 #include "config.h"
  24 #include "qemu-common.h"
  25
  26 #define TARGET_LONG_BITS 32
  27
  28 #define CPUArchState struct CPUCRISState
  29
  30 #include "cpu-defs.h"
  31
  32 #define TARGET_HAS_ICE 1
  33
  34 #define ELF_MACHINE     EM_CRIS
  35
  36 #define EXCP_NMI        1
  37 #define EXCP_GURU       2
  38 #define EXCP_BUSFAULT   3
  39 #define EXCP_IRQ        4
  40 #define EXCP_BREAK      5
  41
  42 /* CRIS-specific interrupt pending bits.  */
  43 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  44
  45 /* Register aliases. R0 - R15 */
  46 #define R_FP  8
  47 #define R_SP  14
  48 #define R_ACR 15
  49
  50 /* Support regs, P0 - P15  */
  51 #define PR_BZ  0
  52 #define PR_VR  1
  53 #define PR_PID 2
  54 #define PR_SRS 3
  55 #define PR_WZ  4
  56 #define PR_EXS 5
  57 #define PR_EDA 6
  58 #define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
  59 #define PR_MOF 7
  60 #define PR_DZ  8
  61 #define PR_EBP 9
  62 #define PR_ERP 10
  63 #define PR_SRP 11
  64 #define PR_NRP 12
  65 #define PR_CCS 13
  66 #define PR_USP 14
  67 #define PRV10_BRP 14
  68 #define PR_SPC 15
  69
  70 /* CPU flags.  */
  71 #define Q_FLAG 0x80000000
  72 #define M_FLAG 0x40000000
  73 #define PFIX_FLAG 0x800      /* CRISv10 Only.  */
  74 #define F_FLAG_V10 0x400
  75 #define P_FLAG_V10 0x200
  76 #define S_FLAG 0x200
  77 #define R_FLAG 0x100
  78 #define P_FLAG 0x80
  79 #define U_FLAG 0x40
  80 #define I_FLAG 0x20
  81 #define X_FLAG 0x10
  82 #define N_FLAG 0x08
  83 #define Z_FLAG 0x04
  84 #define V_FLAG 0x02
  85 #define C_FLAG 0x01
  86 #define ALU_FLAGS 0x1F
  87
  88 /* Condition codes.  */
  89 #define CC_CC   0
  90 #define CC_CS   1
  91 #define CC_NE   2
  92 #define CC_EQ   3
  93 #define CC_VC   4
  94 #define CC_VS   5
  95 #define CC_PL   6
  96 #define CC_MI   7
  97 #define CC_LS   8
  98 #define CC_HI   9
  99 #define CC_GE  10
 100 #define CC_LT  11
 101 #define CC_GT  12
 102 #define CC_LE  13
 103 #define CC_A   14
 104 #define CC_P   15
 105
 106 #define NB_MMU_MODES 2
 107
 108 typedef struct CPUCRISState {
 109         uint32_t regs[16];
 110         /* P0 - P15 are referred to as special registers in the docs.  */
 111         uint32_t pregs[16];
 112
 113         /* Pseudo register for the PC. Not directly accessible on CRIS.  */
 114         uint32_t pc;
 115
 116         /* Pseudo register for the kernel stack.  */
 117         uint32_t ksp;
 118
 119         /* Branch.  */
 120         int dslot;
 121         int btaken;
 122         uint32_t btarget;
 123
 124         /* Condition flag tracking.  */
 125         uint32_t cc_op;
 126         uint32_t cc_mask;
 127         uint32_t cc_dest;
 128         uint32_t cc_src;
 129         uint32_t cc_result;
 130         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 131         int cc_size;
 132         /* X flag at the time of cc snapshot.  */
 133         int cc_x;
 134
 135         /* CRIS has certain insns that lockout interrupts.  */
 136         int locked_irq;
 137         int interrupt_vector;
 138         int fault_vector;
 139         int trap_vector;
 140
 141         /* FIXME: add a check in the translator to avoid writing to support
 142            register sets beyond the 4th. The ISA allows up to 256! but in
 143            practice there is no core that implements more than 4.
 144
 145            Support function registers are used to control units close to the
 146            core. Accesses do not pass down the normal hierarchy.
 147         */
 148         uint32_t sregs[4][16];
 149
 150         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 151            randomness for the 'hint' the mmu gives to sw for chosing valid
 152            sets on TLB refills.  */
 153         uint32_t mmu_rand_lfsr;
 154
 155         /*
 156          * We just store the stores to the tlbset here for later evaluation
 157          * when the hw needs access to them.
 158          *
 159          * One for I and another for D.
 160          */
 161         struct
 162         {
 163                 uint32_t hi;
 164                 uint32_t lo;
 165         } tlbsets[2][4][16];
 166
 167         CPU_COMMON
 168
 169         /* Members after CPU_COMMON are preserved across resets.  */
 170         void *load_info;
 171 } CPUCRISState;
 172
 173 #include "cpu-qom.h"
 174
 175 CRISCPU *cpu_cris_init(const char *cpu_model);
 176 int cpu_cris_exec(CPUCRISState *s);
 177 void cpu_cris_close(CPUCRISState *s);
 178 void do_interrupt(CPUCRISState *env);
 179 /* you can call this signal handler from your SIGBUS and SIGSEGV
 180    signal handlers to inform the virtual CPU of exceptions. non zero
 181    is returned if the signal was handled by the virtual CPU.  */
 182 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 183                            void *puc);
 184
 185 enum {
 186     CC_OP_DYNAMIC, /* Use env->cc_op  */
 187     CC_OP_FLAGS,
 188     CC_OP_CMP,
 189     CC_OP_MOVE,
 190     CC_OP_ADD,
 191     CC_OP_ADDC,
 192     CC_OP_MCP,
 193     CC_OP_ADDU,
 194     CC_OP_SUB,
 195     CC_OP_SUBU,
 196     CC_OP_NEG,
 197     CC_OP_BTST,
 198     CC_OP_MULS,
 199     CC_OP_MULU,
 200     CC_OP_DSTEP,
 201     CC_OP_MSTEP,
 202     CC_OP_BOUND,
 203
 204     CC_OP_OR,
 205     CC_OP_AND,
 206     CC_OP_XOR,
 207     CC_OP_LSL,
 208     CC_OP_LSR,
 209     CC_OP_ASR,
 210     CC_OP_LZ
 211 };
 212
 213 /* CRIS uses 8k pages.  */
 214 #define TARGET_PAGE_BITS 13
 215 #define MMAP_SHIFT TARGET_PAGE_BITS
 216
 217 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 218 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 219
 220 static inline CPUCRISState *cpu_init(const char *cpu_model)
 221 {
 222     CRISCPU *cpu = cpu_cris_init(cpu_model);
 223     if (cpu == NULL) {
 224         return NULL;
 225     }
 226     return &cpu->env;
 227 }
 228
 229 #define cpu_exec cpu_cris_exec
 230 #define cpu_gen_code cpu_cris_gen_code
 231 #define cpu_signal_handler cpu_cris_signal_handler
 232
 233 #define CPU_SAVE_VERSION 1
 234
 235 /* MMU modes definitions */
 236 #define MMU_MODE0_SUFFIX _kernel
 237 #define MMU_MODE1_SUFFIX _user
 238 #define MMU_USER_IDX 1
 239 static inline int cpu_mmu_index (CPUCRISState *env)
 240 {
 241         return !!(env->pregs[PR_CCS] & U_FLAG);
 242 }
 243
 244 int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
 245                               int mmu_idx);
 246 #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
 247
 248 #if defined(CONFIG_USER_ONLY)
 249 static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
 250 {
 251     if (newsp)
 252         env->regs[14] = newsp;
 253     env->regs[10] = 0;
 254 }
 255 #endif
 256
 257 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
 258 {
 259         env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
 260 }
 261
 262 /* Support function regs.  */
 263 #define SFR_RW_GC_CFG      0][0
 264 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 265 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 266 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 267 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 268 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 269 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 270 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 271
 272 #include "cpu-all.h"
 273
 274 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
 275                                         target_ulong *cs_base, int *flags)
 276 {
 277     *pc = env->pc;
 278     *cs_base = 0;
 279     *flags = env->dslot |
 280             (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
 281                                      | X_FLAG | PFIX_FLAG));
 282 }
 283
 284 #define cpu_list cris_cpu_list
 285 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 286
 287 static inline bool cpu_has_work(CPUCRISState *env)
 288 {
 289     return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 290 }
 291
 292 #include "exec-all.h"
 293
 294 static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
 295 {
 296     env->pc = tb->pc;
 297 }
 298 #endif