target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdio.h>
  23 #include <string.h>
  24
  25 #include "config.h"
  26 #include "cpu.h"
  27 #include "mmu.h"
  28 #include "exec-all.h"
  29 #include "host-utils.h"
  30
  31 #define D(x)
  32
  33 #if defined(CONFIG_USER_ONLY)
  34
  35 void do_interrupt (CPUState *env)
  36 {
  37         env->exception_index = -1;
  38         env->pregs[PR_ERP] = env->pc;
  39 }
  40
  41 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  42                              int mmu_idx, int is_softmmu)
  43 {
  44         env->exception_index = 0xaa;
  45         env->debug1 = address;
  46         cpu_dump_state(env, stderr, fprintf, 0);
  47         env->pregs[PR_ERP] = env->pc;
  48         return 1;
  49 }
  50
  51 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
  52 {
  53         return addr;
  54 }
  55
  56 #else /* !CONFIG_USER_ONLY */
  57
  58
  59 static void cris_shift_ccs(CPUState *env)
  60 {
  61         uint32_t ccs;
  62         /* Apply the ccs shift.  */
  63         ccs = env->pregs[PR_CCS];
  64         ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  65         env->pregs[PR_CCS] = ccs;
  66 }
  67
  68 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
  69                                int mmu_idx, int is_softmmu)
  70 {
  71         struct cris_mmu_result_t res;
  72         int prot, miss;
  73         int r = -1;
  74         target_ulong phy;
  75
  76         D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
  77         address &= TARGET_PAGE_MASK;
  78         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  79         miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
  80         if (miss)
  81         {
  82                 if (env->exception_index == EXCP_MMU_FAULT)
  83                         cpu_abort(env,
  84                                   "CRIS: Illegal recursive bus fault."
  85                                   "addr=%x rw=%d\n",
  86                                   address, rw);
  87
  88                 env->exception_index = EXCP_MMU_FAULT;
  89                 env->fault_vector = res.bf_vec;
  90                 r = 1;
  91         }
  92         else
  93         {
  94                 phy = res.phy;
  95                 prot = res.prot;
  96                 address &= TARGET_PAGE_MASK;
  97                 r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
  98         }
  99         if (r > 0)
 100                 D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x"
 101                           " phy=%x ismmu=%d vec=%x pc=%x\n",
 102                           __func__, r, env->interrupt_request,
 103                           address, res.phy, is_softmmu, res.bf_vec, env->pc));
 104         return r;
 105 }
 106
 107 void do_interrupt(CPUState *env)
 108 {
 109         int ex_vec = -1;
 110
 111         D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
 112                    env->exception_index,
 113                    env->interrupt_request));
 114
 115         switch (env->exception_index)
 116         {
 117                 case EXCP_BREAK:
 118                         /* These exceptions are genereated by the core itself.
 119                            ERP should point to the insn following the brk.  */
 120                         ex_vec = env->trap_vector;
 121                         env->pregs[PR_ERP] = env->pc + 2;
 122                         break;
 123
 124                 case EXCP_MMU_FAULT:
 125                         ex_vec = env->fault_vector;
 126                         env->pregs[PR_ERP] = env->pc;
 127                         break;
 128
 129                 default:
 130                         /* Is the core accepting interrupts?  */
 131                         if (!(env->pregs[PR_CCS] & I_FLAG))
 132                                 return;
 133                         /* The interrupt controller gives us the
 134                            vector.  */
 135                         ex_vec = env->interrupt_vector;
 136                         /* Normal interrupts are taken between
 137                            TB's.  env->pc is valid here.  */
 138                         env->pregs[PR_ERP] = env->pc;
 139                         break;
 140         }
 141
 142         if (env->dslot) {
 143                 D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x"
 144                           " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 145                           ex_vec, env->pc, env->dslot,
 146                           env->regs[R_SP],
 147                           env->pregs[PR_ERP], env->pregs[PR_PID],
 148                           env->pregs[PR_CCS],
 149                           env->cc_op, env->cc_mask));
 150                 /* We loose the btarget, btaken state here so rexec the
 151                    branch.  */
 152                 env->pregs[PR_ERP] -= env->dslot;
 153                 /* Exception starts with dslot cleared.  */
 154                 env->dslot = 0;
 155         }
 156
 157         env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
 158
 159         if (env->pregs[PR_CCS] & U_FLAG) {
 160                 /* Swap stack pointers.  */
 161                 env->pregs[PR_USP] = env->regs[R_SP];
 162                 env->regs[R_SP] = env->ksp;
 163         }
 164
 165         /* Apply the CRIS CCS shift. Clears U if set.  */
 166         cris_shift_ccs(env);
 167         D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 168                    __func__, env->pc, ex_vec,
 169                    env->pregs[PR_CCS],
 170                    env->pregs[PR_PID],
 171                    env->pregs[PR_ERP]));
 172 }
 173
 174 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 175 {
 176         uint32_t phy = addr;
 177         struct cris_mmu_result_t res;
 178         int miss;
 179         miss = cris_mmu_translate(&res, env, addr, 0, 0);
 180         if (!miss)
 181                 phy = res.phy;
 182         D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 183         return phy;
 184 }
 185 #endif