]> git.proxmox.com Git - qemu.git/blob - target-cris/translate.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
CRIS updates:
[qemu.git] / target-cris / translate.c
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
26 */
27
28 #include <stdarg.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <assert.h>
34
35 #include "cpu.h"
36 #include "exec-all.h"
37 #include "disas.h"
38 #include "tcg-op.h"
39 #include "helper.h"
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
42
43 #define CRIS_STATS 0
44 #if CRIS_STATS
45 #define STATS(x) x
46 #else
47 #define STATS(x)
48 #endif
49
50 #define DISAS_CRIS 0
51 #if DISAS_CRIS
52 #define DIS(x) x
53 #else
54 #define DIS(x)
55 #endif
56
57 #define D(x)
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
60
61 #define DISAS_SWI 5
62
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
71
72 TCGv cpu_env;
73 TCGv cpu_T[2];
74 TCGv cpu_R[16];
75 TCGv cpu_PR[16];
76 TCGv cc_src;
77 TCGv cc_dest;
78 TCGv cc_result;
79 TCGv cc_op;
80 TCGv cc_size;
81 TCGv cc_mask;
82
83 TCGv env_btarget;
84 TCGv env_pc;
85
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
88 CPUState *env;
89 target_ulong pc, ppc;
90
91 /* Decoder. */
92 uint32_t ir;
93 uint32_t opcode;
94 unsigned int op1;
95 unsigned int op2;
96 unsigned int zsize, zzsize;
97 unsigned int mode;
98 unsigned int postinc;
99
100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
106 translation time. */
107 int flags_x;
108 int clear_x; /* Clear x after this insn? */
109
110 int user; /* user or kernel mode. */
111 int is_jmp;
112 int dyn_jmp;
113
114 uint32_t delayed_pc;
115 int delayed_branch;
116 int bcc;
117 uint32_t condlabel;
118
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121 } DisasContext;
122
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
125 {
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
129 fflush(NULL);
130 cris_prepare_jmp (dc, 0x70000000 + line);
131 }
132
133 const char *regnames[] =
134 {
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139 };
140 const char *pregnames[] =
141 {
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146 };
147
148 /* We need this table to handle preg-moves with implicit width. */
149 int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158 };
159
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
164
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166 {
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170 }
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172 {
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176 }
177
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179 {
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
183 }
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185 {
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
189 }
190
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192 {
193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
197 else if (r == PR_VR)
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
207 else
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
209 }
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
211 {
212 if (r < 0 || r > 15)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
215 return;
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 else {
219 if (r == PR_PID) {
220 tcg_gen_helper_0_0(helper_tlb_flush);
221 }
222 tcg_gen_mov_tl(cpu_PR[r], tn);
223 }
224 }
225
226 static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
227 {
228 tcg_gen_movi_tl(tn, val);
229 }
230
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
232 {
233 int l1;
234
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
241 gen_set_label(l1);
242 }
243
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
245 {
246 int l1;
247
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
254 gen_set_label(l1);
255 }
256
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
258 {
259 int l1;
260
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
267 gen_set_label(l1);
268 }
269
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
272 {
273 TCGv t0, t1;
274
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
277
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
281
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
285
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
288 }
289
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
292 {
293 TCGv t0, t1;
294
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
297
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
301
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
305
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
308 }
309
310 /* Extended arithmetics on CRIS. */
311 static inline void t_gen_add_flag(TCGv d, int flag)
312 {
313 TCGv c;
314
315 c = tcg_temp_new(TCG_TYPE_TL);
316 t_gen_mov_TN_preg(c, PR_CCS);
317 /* Propagate carry into d. */
318 tcg_gen_andi_tl(c, c, 1 << flag);
319 if (flag)
320 tcg_gen_shri_tl(c, c, flag);
321 tcg_gen_add_tl(d, d, c);
322 tcg_gen_discard_tl(c);
323 }
324
325 static inline void t_gen_addx_carry(TCGv d)
326 {
327 TCGv x, c;
328
329 x = tcg_temp_new(TCG_TYPE_TL);
330 c = tcg_temp_new(TCG_TYPE_TL);
331 t_gen_mov_TN_preg(x, PR_CCS);
332 tcg_gen_mov_tl(c, x);
333
334 /* Propagate carry into d if X is set. Branch free. */
335 tcg_gen_andi_tl(c, c, C_FLAG);
336 tcg_gen_andi_tl(x, x, X_FLAG);
337 tcg_gen_shri_tl(x, x, 4);
338
339 tcg_gen_and_tl(x, x, c);
340 tcg_gen_add_tl(d, d, x);
341 tcg_gen_discard_tl(x);
342 tcg_gen_discard_tl(c);
343 }
344
345 static inline void t_gen_subx_carry(TCGv d)
346 {
347 TCGv x, c;
348
349 x = tcg_temp_new(TCG_TYPE_TL);
350 c = tcg_temp_new(TCG_TYPE_TL);
351 t_gen_mov_TN_preg(x, PR_CCS);
352 tcg_gen_mov_tl(c, x);
353
354 /* Propagate carry into d if X is set. Branch free. */
355 tcg_gen_andi_tl(c, c, C_FLAG);
356 tcg_gen_andi_tl(x, x, X_FLAG);
357 tcg_gen_shri_tl(x, x, 4);
358
359 tcg_gen_and_tl(x, x, c);
360 tcg_gen_sub_tl(d, d, x);
361 tcg_gen_discard_tl(x);
362 tcg_gen_discard_tl(c);
363 }
364
365 /* Swap the two bytes within each half word of the s operand.
366 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
367 static inline void t_gen_swapb(TCGv d, TCGv s)
368 {
369 TCGv t, org_s;
370
371 t = tcg_temp_new(TCG_TYPE_TL);
372 org_s = tcg_temp_new(TCG_TYPE_TL);
373
374 /* d and s may refer to the same object. */
375 tcg_gen_mov_tl(org_s, s);
376 tcg_gen_shli_tl(t, org_s, 8);
377 tcg_gen_andi_tl(d, t, 0xff00ff00);
378 tcg_gen_shri_tl(t, org_s, 8);
379 tcg_gen_andi_tl(t, t, 0x00ff00ff);
380 tcg_gen_or_tl(d, d, t);
381 tcg_gen_discard_tl(t);
382 tcg_gen_discard_tl(org_s);
383 }
384
385 /* Swap the halfwords of the s operand. */
386 static inline void t_gen_swapw(TCGv d, TCGv s)
387 {
388 TCGv t;
389 /* d and s refer the same object. */
390 t = tcg_temp_new(TCG_TYPE_TL);
391 tcg_gen_mov_tl(t, s);
392 tcg_gen_shli_tl(d, t, 16);
393 tcg_gen_shri_tl(t, t, 16);
394 tcg_gen_or_tl(d, d, t);
395 tcg_gen_discard_tl(t);
396 }
397
398 /* Reverse the within each byte.
399 T0 = (((T0 << 7) & 0x80808080) |
400 ((T0 << 5) & 0x40404040) |
401 ((T0 << 3) & 0x20202020) |
402 ((T0 << 1) & 0x10101010) |
403 ((T0 >> 1) & 0x08080808) |
404 ((T0 >> 3) & 0x04040404) |
405 ((T0 >> 5) & 0x02020202) |
406 ((T0 >> 7) & 0x01010101));
407 */
408 static inline void t_gen_swapr(TCGv d, TCGv s)
409 {
410 struct {
411 int shift; /* LSL when positive, LSR when negative. */
412 uint32_t mask;
413 } bitrev [] = {
414 {7, 0x80808080},
415 {5, 0x40404040},
416 {3, 0x20202020},
417 {1, 0x10101010},
418 {-1, 0x08080808},
419 {-3, 0x04040404},
420 {-5, 0x02020202},
421 {-7, 0x01010101}
422 };
423 int i;
424 TCGv t, org_s;
425
426 /* d and s refer the same object. */
427 t = tcg_temp_new(TCG_TYPE_TL);
428 org_s = tcg_temp_new(TCG_TYPE_TL);
429 tcg_gen_mov_tl(org_s, s);
430
431 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
432 tcg_gen_andi_tl(d, t, bitrev[0].mask);
433 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
434 if (bitrev[i].shift >= 0) {
435 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
436 } else {
437 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
438 }
439 tcg_gen_andi_tl(t, t, bitrev[i].mask);
440 tcg_gen_or_tl(d, d, t);
441 }
442 tcg_gen_discard_tl(t);
443 tcg_gen_discard_tl(org_s);
444 }
445
446 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
447 {
448 TranslationBlock *tb;
449 tb = dc->tb;
450 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
451 tcg_gen_goto_tb(n);
452 tcg_gen_movi_tl(cpu_T[0], dest);
453 t_gen_mov_env_TN(pc, cpu_T[0]);
454 tcg_gen_exit_tb((long)tb + n);
455 } else {
456 t_gen_mov_env_TN(pc, cpu_T[0]);
457 tcg_gen_exit_tb(0);
458 }
459 }
460
461 /* Sign extend at translation time. */
462 static int sign_extend(unsigned int val, unsigned int width)
463 {
464 int sval;
465
466 /* LSL. */
467 val <<= 31 - width;
468 sval = val;
469 /* ASR. */
470 sval >>= 31 - width;
471 return sval;
472 }
473
474 static inline void cris_clear_x_flag(DisasContext *dc)
475 {
476 if (!dc->flagx_live
477 || (dc->flagx_live && dc->flags_x)
478 || dc->cc_op != CC_OP_FLAGS)
479 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
480 dc->flagx_live = 1;
481 dc->flags_x = 0;
482 }
483
484 static void cris_evaluate_flags(DisasContext *dc)
485 {
486 if (!dc->flags_live) {
487 tcg_gen_movi_tl(cc_op, dc->cc_op);
488 tcg_gen_movi_tl(cc_size, dc->cc_size);
489 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
490
491 switch (dc->cc_op)
492 {
493 case CC_OP_MCP:
494 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
495 break;
496 case CC_OP_MULS:
497 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
498 break;
499 case CC_OP_MULU:
500 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
501 break;
502 case CC_OP_MOVE:
503 switch (dc->cc_size)
504 {
505 case 4:
506 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
507 break;
508 case 2:
509 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
510 break;
511 default:
512 tcg_gen_helper_0_0(helper_evaluate_flags);
513 break;
514 }
515 break;
516 case CC_OP_FLAGS:
517 /* live. */
518 break;
519 default:
520 {
521 switch (dc->cc_size)
522 {
523 case 4:
524 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
525 break;
526 default:
527 tcg_gen_helper_0_0(helper_evaluate_flags);
528 break;
529 }
530 }
531 break;
532 }
533 dc->flags_live = 1;
534 }
535 }
536
537 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
538 {
539 uint32_t ovl;
540
541 /* Check if we need to evaluate the condition codes due to
542 CC overlaying. */
543 ovl = (dc->cc_mask ^ mask) & ~mask;
544 if (ovl) {
545 /* TODO: optimize this case. It trigs all the time. */
546 cris_evaluate_flags (dc);
547 }
548 dc->cc_mask = mask;
549 dc->update_cc = 1;
550
551 if (mask == 0)
552 dc->update_cc = 0;
553 else
554 dc->flags_live = 0;
555 }
556
557 static void cris_update_cc_op(DisasContext *dc, int op, int size)
558 {
559 dc->cc_op = op;
560 dc->cc_size = size;
561 dc->flags_live = 0;
562 }
563
564 /* op is the operation.
565 T0, T1 are the operands.
566 dst is the destination reg.
567 */
568 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
569 {
570 int writeback = 1;
571 if (dc->update_cc) {
572 cris_update_cc_op(dc, op, size);
573 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
574
575 /* FIXME: This shouldn't be needed. But we don't pass the
576 tests without it. Investigate. */
577 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
578 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
579 }
580
581 /* Emit the ALU insns. */
582 switch (op)
583 {
584 case CC_OP_ADD:
585 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
586 /* Extended arithmetics. */
587 t_gen_addx_carry(cpu_T[0]);
588 break;
589 case CC_OP_ADDC:
590 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
591 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
592 break;
593 case CC_OP_MCP:
594 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
595 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
596 break;
597 case CC_OP_SUB:
598 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
599 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
600 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
601 /* CRIS flag evaluation needs ~src. */
602 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
603
604 /* Extended arithmetics. */
605 t_gen_subx_carry(cpu_T[0]);
606 break;
607 case CC_OP_MOVE:
608 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
609 break;
610 case CC_OP_OR:
611 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
612 break;
613 case CC_OP_AND:
614 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
615 break;
616 case CC_OP_XOR:
617 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
618 break;
619 case CC_OP_LSL:
620 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
621 break;
622 case CC_OP_LSR:
623 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
624 break;
625 case CC_OP_ASR:
626 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
627 break;
628 case CC_OP_NEG:
629 /* Hopefully the TCG backend recognizes this pattern
630 and makes a real neg out of it. */
631 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
632 /* Extended arithmetics. */
633 t_gen_subx_carry(cpu_T[0]);
634 break;
635 case CC_OP_LZ:
636 gen_op_lz_T0_T1();
637 break;
638 case CC_OP_BTST:
639 gen_op_btst_T0_T1();
640 writeback = 0;
641 break;
642 case CC_OP_MULS:
643 {
644 TCGv mof;
645 mof = tcg_temp_new(TCG_TYPE_TL);
646 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
647 t_gen_mov_preg_TN(PR_MOF, mof);
648 tcg_gen_discard_tl(mof);
649 }
650 break;
651 case CC_OP_MULU:
652 {
653 TCGv mof;
654 mof = tcg_temp_new(TCG_TYPE_TL);
655 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
656 t_gen_mov_preg_TN(PR_MOF, mof);
657 tcg_gen_discard_tl(mof);
658 }
659 break;
660 case CC_OP_DSTEP:
661 gen_op_dstep_T0_T1();
662 break;
663 case CC_OP_BOUND:
664 {
665 int l1;
666 l1 = gen_new_label();
667 tcg_gen_brcond_tl(TCG_COND_LEU,
668 cpu_T[0], cpu_T[1], l1);
669 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
670 gen_set_label(l1);
671 }
672 break;
673 case CC_OP_CMP:
674 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
675 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
676 /* CRIS flag evaluation needs ~src. */
677 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
678 /* CRIS flag evaluation needs ~src. */
679 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
680
681 /* Extended arithmetics. */
682 t_gen_subx_carry(cpu_T[0]);
683 writeback = 0;
684 break;
685 default:
686 fprintf (logfile, "illegal ALU op.\n");
687 BUG();
688 break;
689 }
690
691 if (dc->update_cc)
692 tcg_gen_mov_tl(cc_src, cpu_T[1]);
693
694 if (size == 1)
695 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
696 else if (size == 2)
697 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
698
699 /* Writeback. */
700 if (writeback) {
701 if (size == 4)
702 t_gen_mov_reg_TN(rd, cpu_T[0]);
703 else {
704 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
705 t_gen_mov_TN_reg(cpu_T[0], rd);
706 if (size == 1)
707 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
708 else
709 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
710 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
711 t_gen_mov_reg_TN(rd, cpu_T[0]);
712 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
713 }
714 }
715 if (dc->update_cc)
716 tcg_gen_mov_tl(cc_result, cpu_T[0]);
717
718 {
719 /* TODO: Optimize this. */
720 if (!dc->flagx_live)
721 cris_evaluate_flags(dc);
722 }
723 }
724
725 static int arith_cc(DisasContext *dc)
726 {
727 if (dc->update_cc) {
728 switch (dc->cc_op) {
729 case CC_OP_ADD: return 1;
730 case CC_OP_SUB: return 1;
731 case CC_OP_LSL: return 1;
732 case CC_OP_LSR: return 1;
733 case CC_OP_ASR: return 1;
734 case CC_OP_CMP: return 1;
735 default:
736 return 0;
737 }
738 }
739 return 0;
740 }
741
742 static void gen_tst_cc (DisasContext *dc, int cond)
743 {
744 int arith_opt;
745
746 /* TODO: optimize more condition codes. */
747 arith_opt = arith_cc(dc) && !dc->flags_live;
748 switch (cond) {
749 case CC_EQ:
750 if (arith_opt)
751 gen_op_tst_cc_eq_fast ();
752 else {
753 cris_evaluate_flags(dc);
754 gen_op_tst_cc_eq ();
755 }
756 break;
757 case CC_NE:
758 if (arith_opt)
759 gen_op_tst_cc_ne_fast ();
760 else {
761 cris_evaluate_flags(dc);
762 gen_op_tst_cc_ne ();
763 }
764 break;
765 case CC_CS:
766 cris_evaluate_flags(dc);
767 gen_op_tst_cc_cs ();
768 break;
769 case CC_CC:
770 cris_evaluate_flags(dc);
771 gen_op_tst_cc_cc ();
772 break;
773 case CC_VS:
774 cris_evaluate_flags(dc);
775 gen_op_tst_cc_vs ();
776 break;
777 case CC_VC:
778 cris_evaluate_flags(dc);
779 gen_op_tst_cc_vc ();
780 break;
781 case CC_PL:
782 if (arith_opt)
783 gen_op_tst_cc_pl_fast ();
784 else {
785 cris_evaluate_flags(dc);
786 gen_op_tst_cc_pl ();
787 }
788 break;
789 case CC_MI:
790 if (arith_opt)
791 gen_op_tst_cc_mi_fast ();
792 else {
793 cris_evaluate_flags(dc);
794 gen_op_tst_cc_mi ();
795 }
796 break;
797 case CC_LS:
798 cris_evaluate_flags(dc);
799 gen_op_tst_cc_ls ();
800 break;
801 case CC_HI:
802 cris_evaluate_flags(dc);
803 gen_op_tst_cc_hi ();
804 break;
805 case CC_GE:
806 cris_evaluate_flags(dc);
807 gen_op_tst_cc_ge ();
808 break;
809 case CC_LT:
810 cris_evaluate_flags(dc);
811 gen_op_tst_cc_lt ();
812 break;
813 case CC_GT:
814 cris_evaluate_flags(dc);
815 gen_op_tst_cc_gt ();
816 break;
817 case CC_LE:
818 cris_evaluate_flags(dc);
819 gen_op_tst_cc_le ();
820 break;
821 case CC_P:
822 cris_evaluate_flags(dc);
823 gen_op_tst_cc_p ();
824 break;
825 case CC_A:
826 cris_evaluate_flags(dc);
827 gen_op_movl_T0_im (1);
828 break;
829 default:
830 BUG();
831 break;
832 };
833 }
834
835 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
836 {
837 /* This helps us re-schedule the micro-code to insns in delay-slots
838 before the actual jump. */
839 dc->delayed_branch = 2;
840 dc->delayed_pc = dc->pc + offset;
841 dc->bcc = cond;
842 if (cond != CC_A)
843 {
844 gen_tst_cc (dc, cond);
845 gen_op_evaluate_bcc ();
846 }
847 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
848 }
849
850
851 /* Dynamic jumps, when the dest is in a live reg for example. */
852 void cris_prepare_dyn_jmp (DisasContext *dc)
853 {
854 /* This helps us re-schedule the micro-code to insns in delay-slots
855 before the actual jump. */
856 dc->delayed_branch = 2;
857 dc->dyn_jmp = 1;
858 dc->bcc = CC_A;
859 }
860
861 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
862 {
863 /* This helps us re-schedule the micro-code to insns in delay-slots
864 before the actual jump. */
865 dc->delayed_branch = 2;
866 dc->delayed_pc = dst;
867 dc->dyn_jmp = 0;
868 dc->bcc = CC_A;
869 }
870
871 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
872 unsigned int size, int sign)
873 {
874 int mem_index = cpu_mmu_index(dc->env);
875
876 /* FIXME: qemu_ld does not act as a barrier? */
877 tcg_gen_helper_0_0(helper_dummy);
878 cris_evaluate_flags(dc);
879 if (size == 1) {
880 if (sign)
881 tcg_gen_qemu_ld8s(dst, addr, mem_index);
882 else
883 tcg_gen_qemu_ld8u(dst, addr, mem_index);
884 }
885 else if (size == 2) {
886 if (sign)
887 tcg_gen_qemu_ld16s(dst, addr, mem_index);
888 else
889 tcg_gen_qemu_ld16u(dst, addr, mem_index);
890 }
891 else {
892 tcg_gen_qemu_ld32s(dst, addr, mem_index);
893 }
894 }
895
896 void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
897 {
898 int mem_index = cpu_mmu_index(dc->env);
899
900 /* FIXME: qemu_st does not act as a barrier? */
901 tcg_gen_helper_0_0(helper_dummy);
902 cris_evaluate_flags(dc);
903
904 /* Remember, operands are flipped. CRIS has reversed order. */
905 if (size == 1)
906 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
907 else if (size == 2)
908 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
909 else
910 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
911 }
912
913 static inline void t_gen_sext(TCGv d, TCGv s, int size)
914 {
915 if (size == 1)
916 tcg_gen_ext8s_i32(d, s);
917 else if (size == 2)
918 tcg_gen_ext16s_i32(d, s);
919 }
920
921 static inline void t_gen_zext(TCGv d, TCGv s, int size)
922 {
923 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
924 if (size == 1)
925 tcg_gen_andi_i32(d, s, 0xff);
926 else if (size == 2)
927 tcg_gen_andi_i32(d, s, 0xffff);
928 }
929
930 #if DISAS_CRIS
931 static char memsize_char(int size)
932 {
933 switch (size)
934 {
935 case 1: return 'b'; break;
936 case 2: return 'w'; break;
937 case 4: return 'd'; break;
938 default:
939 return 'x';
940 break;
941 }
942 }
943 #endif
944
945 static unsigned int memsize_z(DisasContext *dc)
946 {
947 return dc->zsize + 1;
948 }
949
950 static unsigned int memsize_zz(DisasContext *dc)
951 {
952 switch (dc->zzsize)
953 {
954 case 0: return 1;
955 case 1: return 2;
956 default:
957 return 4;
958 }
959 }
960
961 static void do_postinc (DisasContext *dc, int size)
962 {
963 if (!dc->postinc)
964 return;
965 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
966 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], size);
967 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
968 }
969
970
971 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
972 int size, int s_ext)
973 {
974 t_gen_mov_TN_reg(cpu_T[1], rs);
975 if (s_ext)
976 t_gen_sext(cpu_T[1], cpu_T[1], size);
977 else
978 t_gen_zext(cpu_T[1], cpu_T[1], size);
979 }
980
981 /* Prepare T0 and T1 for a register alu operation.
982 s_ext decides if the operand1 should be sign-extended or zero-extended when
983 needed. */
984 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
985 int size, int s_ext)
986 {
987 dec_prep_move_r(dc, rs, rd, size, s_ext);
988
989 t_gen_mov_TN_reg(cpu_T[0], rd);
990 if (s_ext)
991 t_gen_sext(cpu_T[0], cpu_T[0], size);
992 else
993 t_gen_zext(cpu_T[0], cpu_T[0], size);
994 }
995
996 /* Prepare T0 and T1 for a memory + alu operation.
997 s_ext decides if the operand1 should be sign-extended or zero-extended when
998 needed. */
999 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1000 {
1001 unsigned int rs, rd;
1002 uint32_t imm;
1003 int is_imm;
1004 int insn_len = 2;
1005
1006 rs = dc->op1;
1007 rd = dc->op2;
1008 is_imm = rs == 15 && dc->postinc;
1009
1010 /* Load [$rs] onto T1. */
1011 if (is_imm) {
1012 insn_len = 2 + memsize;
1013 if (memsize == 1)
1014 insn_len++;
1015
1016 imm = ldl_code(dc->pc + 2);
1017 if (memsize != 4) {
1018 if (s_ext) {
1019 imm = sign_extend(imm, (memsize * 8) - 1);
1020 } else {
1021 if (memsize == 1)
1022 imm &= 0xff;
1023 else
1024 imm &= 0xffff;
1025 }
1026 }
1027 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1028 imm, rd, s_ext, memsize));
1029 tcg_gen_movi_tl(cpu_T[1], imm);
1030 dc->postinc = 0;
1031 } else {
1032 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1033 if (s_ext)
1034 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1035 else
1036 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1037 }
1038
1039 /* put dest in T0. */
1040 t_gen_mov_TN_reg(cpu_T[0], rd);
1041 return insn_len;
1042 }
1043
1044 #if DISAS_CRIS
1045 static const char *cc_name(int cc)
1046 {
1047 static char *cc_names[16] = {
1048 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1049 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1050 };
1051 assert(cc < 16);
1052 return cc_names[cc];
1053 }
1054 #endif
1055
1056 /* Start of insn decoders. */
1057
1058 static unsigned int dec_bccq(DisasContext *dc)
1059 {
1060 int32_t offset;
1061 int sign;
1062 uint32_t cond = dc->op2;
1063 int tmp;
1064
1065 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1066 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1067
1068 offset *= 2;
1069 offset |= sign << 8;
1070 tmp = offset;
1071 offset = sign_extend(offset, 8);
1072
1073 /* op2 holds the condition-code. */
1074 cris_cc_mask(dc, 0);
1075 cris_prepare_cc_branch (dc, offset, cond);
1076 return 2;
1077 }
1078 static unsigned int dec_addoq(DisasContext *dc)
1079 {
1080 int32_t imm;
1081
1082 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1083 imm = sign_extend(dc->op1, 7);
1084
1085 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1086 cris_cc_mask(dc, 0);
1087 /* Fetch register operand, */
1088 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1089 return 2;
1090 }
1091 static unsigned int dec_addq(DisasContext *dc)
1092 {
1093 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1094
1095 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1096
1097 cris_cc_mask(dc, CC_MASK_NZVC);
1098 /* Fetch register operand, */
1099 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1100 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1101 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1102 return 2;
1103 }
1104 static unsigned int dec_moveq(DisasContext *dc)
1105 {
1106 uint32_t imm;
1107
1108 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1109 imm = sign_extend(dc->op1, 5);
1110 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1111
1112 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1113 return 2;
1114 }
1115 static unsigned int dec_subq(DisasContext *dc)
1116 {
1117 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1118
1119 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1120
1121 cris_cc_mask(dc, CC_MASK_NZVC);
1122 /* Fetch register operand, */
1123 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1124 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1125 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1126 return 2;
1127 }
1128 static unsigned int dec_cmpq(DisasContext *dc)
1129 {
1130 uint32_t imm;
1131 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1132 imm = sign_extend(dc->op1, 5);
1133
1134 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1135 cris_cc_mask(dc, CC_MASK_NZVC);
1136 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1137 t_gen_mov_TN_im(cpu_T[1], imm);
1138 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1139 return 2;
1140 }
1141 static unsigned int dec_andq(DisasContext *dc)
1142 {
1143 uint32_t imm;
1144 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1145 imm = sign_extend(dc->op1, 5);
1146
1147 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1148 cris_cc_mask(dc, CC_MASK_NZ);
1149 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1150 t_gen_mov_TN_im(cpu_T[1], imm);
1151 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1152 return 2;
1153 }
1154 static unsigned int dec_orq(DisasContext *dc)
1155 {
1156 uint32_t imm;
1157 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1158 imm = sign_extend(dc->op1, 5);
1159 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1160 cris_cc_mask(dc, CC_MASK_NZ);
1161 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1162 t_gen_mov_TN_im(cpu_T[1], imm);
1163 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1164 return 2;
1165 }
1166 static unsigned int dec_btstq(DisasContext *dc)
1167 {
1168 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1169 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1170 cris_cc_mask(dc, CC_MASK_NZ);
1171 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1172 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1173 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1174
1175 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1176 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1177 dc->flags_live = 1;
1178 return 2;
1179 }
1180 static unsigned int dec_asrq(DisasContext *dc)
1181 {
1182 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1183 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1184 cris_cc_mask(dc, CC_MASK_NZ);
1185 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1186 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1187 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1188 return 2;
1189 }
1190 static unsigned int dec_lslq(DisasContext *dc)
1191 {
1192 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1193 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1194
1195 cris_cc_mask(dc, CC_MASK_NZ);
1196 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1197 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1198 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1199 return 2;
1200 }
1201 static unsigned int dec_lsrq(DisasContext *dc)
1202 {
1203 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1204 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1205
1206 cris_cc_mask(dc, CC_MASK_NZ);
1207 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1208 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1209 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1210 return 2;
1211 }
1212
1213 static unsigned int dec_move_r(DisasContext *dc)
1214 {
1215 int size = memsize_zz(dc);
1216
1217 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1218 memsize_char(size), dc->op1, dc->op2));
1219
1220 cris_cc_mask(dc, CC_MASK_NZ);
1221 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1222 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1223 return 2;
1224 }
1225
1226 static unsigned int dec_scc_r(DisasContext *dc)
1227 {
1228 int cond = dc->op2;
1229
1230 DIS(fprintf (logfile, "s%s $r%u\n",
1231 cc_name(cond), dc->op1));
1232
1233 if (cond != CC_A)
1234 {
1235 gen_tst_cc (dc, cond);
1236 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1237 }
1238 else
1239 tcg_gen_movi_tl(cpu_T[1], 1);
1240
1241 cris_cc_mask(dc, 0);
1242 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1243 return 2;
1244 }
1245
1246 static unsigned int dec_and_r(DisasContext *dc)
1247 {
1248 int size = memsize_zz(dc);
1249
1250 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1251 memsize_char(size), dc->op1, dc->op2));
1252 cris_cc_mask(dc, CC_MASK_NZ);
1253 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1254 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1255 return 2;
1256 }
1257
1258 static unsigned int dec_lz_r(DisasContext *dc)
1259 {
1260 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1261 dc->op1, dc->op2));
1262 cris_cc_mask(dc, CC_MASK_NZ);
1263 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1264 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1265 return 2;
1266 }
1267
1268 static unsigned int dec_lsl_r(DisasContext *dc)
1269 {
1270 int size = memsize_zz(dc);
1271
1272 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1273 memsize_char(size), dc->op1, dc->op2));
1274 cris_cc_mask(dc, CC_MASK_NZ);
1275 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1276 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1277 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1278 return 2;
1279 }
1280
1281 static unsigned int dec_lsr_r(DisasContext *dc)
1282 {
1283 int size = memsize_zz(dc);
1284
1285 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1286 memsize_char(size), dc->op1, dc->op2));
1287 cris_cc_mask(dc, CC_MASK_NZ);
1288 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1289 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1290 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1291 return 2;
1292 }
1293
1294 static unsigned int dec_asr_r(DisasContext *dc)
1295 {
1296 int size = memsize_zz(dc);
1297
1298 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1299 memsize_char(size), dc->op1, dc->op2));
1300 cris_cc_mask(dc, CC_MASK_NZ);
1301 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1302 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1303 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1304 return 2;
1305 }
1306
1307 static unsigned int dec_muls_r(DisasContext *dc)
1308 {
1309 int size = memsize_zz(dc);
1310
1311 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1312 memsize_char(size), dc->op1, dc->op2));
1313 cris_cc_mask(dc, CC_MASK_NZV);
1314 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1315 t_gen_sext(cpu_T[0], cpu_T[0], size);
1316 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1317 return 2;
1318 }
1319
1320 static unsigned int dec_mulu_r(DisasContext *dc)
1321 {
1322 int size = memsize_zz(dc);
1323
1324 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1325 memsize_char(size), dc->op1, dc->op2));
1326 cris_cc_mask(dc, CC_MASK_NZV);
1327 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1328 t_gen_zext(cpu_T[0], cpu_T[0], size);
1329 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1330 return 2;
1331 }
1332
1333
1334 static unsigned int dec_dstep_r(DisasContext *dc)
1335 {
1336 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1337 cris_cc_mask(dc, CC_MASK_NZ);
1338 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1339 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1340 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1341 return 2;
1342 }
1343
1344 static unsigned int dec_xor_r(DisasContext *dc)
1345 {
1346 int size = memsize_zz(dc);
1347 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1348 memsize_char(size), dc->op1, dc->op2));
1349 BUG_ON(size != 4); /* xor is dword. */
1350 cris_cc_mask(dc, CC_MASK_NZ);
1351 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1352 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1353 return 2;
1354 }
1355
1356 static unsigned int dec_bound_r(DisasContext *dc)
1357 {
1358 int size = memsize_zz(dc);
1359 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1360 memsize_char(size), dc->op1, dc->op2));
1361 cris_cc_mask(dc, CC_MASK_NZ);
1362 /* TODO: needs optmimization. */
1363 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1364 /* rd should be 4. */
1365 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1366 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1367 return 2;
1368 }
1369
1370 static unsigned int dec_cmp_r(DisasContext *dc)
1371 {
1372 int size = memsize_zz(dc);
1373 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1374 memsize_char(size), dc->op1, dc->op2));
1375 cris_cc_mask(dc, CC_MASK_NZVC);
1376 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1377 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1378 return 2;
1379 }
1380
1381 static unsigned int dec_abs_r(DisasContext *dc)
1382 {
1383 int l1;
1384
1385 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1386 dc->op1, dc->op2));
1387 cris_cc_mask(dc, CC_MASK_NZ);
1388 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1389
1390 /* TODO: consider a branch free approach. */
1391 l1 = gen_new_label();
1392 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1393 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1394 gen_set_label(l1);
1395 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1396 return 2;
1397 }
1398
1399 static unsigned int dec_add_r(DisasContext *dc)
1400 {
1401 int size = memsize_zz(dc);
1402 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1403 memsize_char(size), dc->op1, dc->op2));
1404 cris_cc_mask(dc, CC_MASK_NZVC);
1405 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1406 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1407 return 2;
1408 }
1409
1410 static unsigned int dec_addc_r(DisasContext *dc)
1411 {
1412 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1413 dc->op1, dc->op2));
1414 cris_evaluate_flags(dc);
1415 cris_cc_mask(dc, CC_MASK_NZVC);
1416 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1417 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1418 return 2;
1419 }
1420
1421 static unsigned int dec_mcp_r(DisasContext *dc)
1422 {
1423 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1424 dc->op2, dc->op1));
1425 cris_evaluate_flags(dc);
1426 cris_cc_mask(dc, CC_MASK_RNZV);
1427 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1428 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1429 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1430 return 2;
1431 }
1432
1433 #if DISAS_CRIS
1434 static char * swapmode_name(int mode, char *modename) {
1435 int i = 0;
1436 if (mode & 8)
1437 modename[i++] = 'n';
1438 if (mode & 4)
1439 modename[i++] = 'w';
1440 if (mode & 2)
1441 modename[i++] = 'b';
1442 if (mode & 1)
1443 modename[i++] = 'r';
1444 modename[i++] = 0;
1445 return modename;
1446 }
1447 #endif
1448
1449 static unsigned int dec_swap_r(DisasContext *dc)
1450 {
1451 DIS(char modename[4]);
1452 DIS(fprintf (logfile, "swap%s $r%u\n",
1453 swapmode_name(dc->op2, modename), dc->op1));
1454
1455 cris_cc_mask(dc, CC_MASK_NZ);
1456 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1457 if (dc->op2 & 8)
1458 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1459 if (dc->op2 & 4)
1460 t_gen_swapw(cpu_T[0], cpu_T[0]);
1461 if (dc->op2 & 2)
1462 t_gen_swapb(cpu_T[0], cpu_T[0]);
1463 if (dc->op2 & 1)
1464 t_gen_swapr(cpu_T[0], cpu_T[0]);
1465 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1466 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1467 return 2;
1468 }
1469
1470 static unsigned int dec_or_r(DisasContext *dc)
1471 {
1472 int size = memsize_zz(dc);
1473 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1474 memsize_char(size), dc->op1, dc->op2));
1475 cris_cc_mask(dc, CC_MASK_NZ);
1476 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1477 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1478 return 2;
1479 }
1480
1481 static unsigned int dec_addi_r(DisasContext *dc)
1482 {
1483 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1484 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1485 cris_cc_mask(dc, 0);
1486 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1487 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1488 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1489 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1490 return 2;
1491 }
1492
1493 static unsigned int dec_addi_acr(DisasContext *dc)
1494 {
1495 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1496 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1497 cris_cc_mask(dc, 0);
1498 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1499 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1500
1501 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1502 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1503 return 2;
1504 }
1505
1506 static unsigned int dec_neg_r(DisasContext *dc)
1507 {
1508 int size = memsize_zz(dc);
1509 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1510 memsize_char(size), dc->op1, dc->op2));
1511 cris_cc_mask(dc, CC_MASK_NZVC);
1512 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1513 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1514 return 2;
1515 }
1516
1517 static unsigned int dec_btst_r(DisasContext *dc)
1518 {
1519 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1520 dc->op1, dc->op2));
1521 cris_cc_mask(dc, CC_MASK_NZ);
1522 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1523 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1524
1525 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1526 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1527 dc->flags_live = 1;
1528 return 2;
1529 }
1530
1531 static unsigned int dec_sub_r(DisasContext *dc)
1532 {
1533 int size = memsize_zz(dc);
1534 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1535 memsize_char(size), dc->op1, dc->op2));
1536 cris_cc_mask(dc, CC_MASK_NZVC);
1537 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1538 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1539 return 2;
1540 }
1541
1542 /* Zero extension. From size to dword. */
1543 static unsigned int dec_movu_r(DisasContext *dc)
1544 {
1545 int size = memsize_z(dc);
1546 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1547 memsize_char(size),
1548 dc->op1, dc->op2));
1549
1550 cris_cc_mask(dc, CC_MASK_NZ);
1551 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1552 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1553 return 2;
1554 }
1555
1556 /* Sign extension. From size to dword. */
1557 static unsigned int dec_movs_r(DisasContext *dc)
1558 {
1559 int size = memsize_z(dc);
1560 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1561 memsize_char(size),
1562 dc->op1, dc->op2));
1563
1564 cris_cc_mask(dc, CC_MASK_NZ);
1565 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1566 /* Size can only be qi or hi. */
1567 t_gen_sext(cpu_T[1], cpu_T[0], size);
1568 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1569 return 2;
1570 }
1571
1572 /* zero extension. From size to dword. */
1573 static unsigned int dec_addu_r(DisasContext *dc)
1574 {
1575 int size = memsize_z(dc);
1576 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1577 memsize_char(size),
1578 dc->op1, dc->op2));
1579
1580 cris_cc_mask(dc, CC_MASK_NZVC);
1581 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1582 /* Size can only be qi or hi. */
1583 t_gen_zext(cpu_T[1], cpu_T[1], size);
1584 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1585 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1586 return 2;
1587 }
1588
1589 /* Sign extension. From size to dword. */
1590 static unsigned int dec_adds_r(DisasContext *dc)
1591 {
1592 int size = memsize_z(dc);
1593 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1594 memsize_char(size),
1595 dc->op1, dc->op2));
1596
1597 cris_cc_mask(dc, CC_MASK_NZVC);
1598 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1599 /* Size can only be qi or hi. */
1600 t_gen_sext(cpu_T[1], cpu_T[1], size);
1601 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1602
1603 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1604 return 2;
1605 }
1606
1607 /* Zero extension. From size to dword. */
1608 static unsigned int dec_subu_r(DisasContext *dc)
1609 {
1610 int size = memsize_z(dc);
1611 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1612 memsize_char(size),
1613 dc->op1, dc->op2));
1614
1615 cris_cc_mask(dc, CC_MASK_NZVC);
1616 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1617 /* Size can only be qi or hi. */
1618 t_gen_zext(cpu_T[1], cpu_T[1], size);
1619 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1620 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1621 return 2;
1622 }
1623
1624 /* Sign extension. From size to dword. */
1625 static unsigned int dec_subs_r(DisasContext *dc)
1626 {
1627 int size = memsize_z(dc);
1628 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1629 memsize_char(size),
1630 dc->op1, dc->op2));
1631
1632 cris_cc_mask(dc, CC_MASK_NZVC);
1633 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1634 /* Size can only be qi or hi. */
1635 t_gen_sext(cpu_T[1], cpu_T[1], size);
1636 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1637 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1638 return 2;
1639 }
1640
1641 static unsigned int dec_setclrf(DisasContext *dc)
1642 {
1643 uint32_t flags;
1644 int set = (~dc->opcode >> 2) & 1;
1645
1646 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1647 | EXTRACT_FIELD(dc->ir, 0, 3);
1648 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1649 if (set && flags == 0)
1650 DIS(fprintf (logfile, "nop\n"));
1651 else if (!set && (flags & 0x20))
1652 DIS(fprintf (logfile, "di\n"));
1653 else
1654 DIS(fprintf (logfile, "%sf %x\n",
1655 set ? "set" : "clr",
1656 flags));
1657
1658 if (set && (flags & X_FLAG)) {
1659 dc->flagx_live = 1;
1660 dc->flags_x = 1;
1661 }
1662
1663 /* Simply decode the flags. */
1664 cris_evaluate_flags (dc);
1665 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1666 tcg_gen_movi_tl(cc_op, dc->cc_op);
1667
1668 if (set)
1669 gen_op_setf(flags);
1670 else
1671 gen_op_clrf(flags);
1672 dc->flags_live = 1;
1673 dc->clear_x = 0;
1674 return 2;
1675 }
1676
1677 static unsigned int dec_move_rs(DisasContext *dc)
1678 {
1679 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1680 cris_cc_mask(dc, 0);
1681 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1682 gen_op_movl_sreg_T0(dc->op2);
1683
1684 #if !defined(CONFIG_USER_ONLY)
1685 if (dc->op2 == 6)
1686 gen_op_movl_tlb_hi_T0();
1687 else if (dc->op2 == 5) { /* srs is checked at runtime. */
1688 tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
1689 gen_op_movl_tlb_lo_T0();
1690 }
1691 #endif
1692 return 2;
1693 }
1694 static unsigned int dec_move_sr(DisasContext *dc)
1695 {
1696 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1697 cris_cc_mask(dc, 0);
1698 gen_op_movl_T0_sreg(dc->op2);
1699 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1700 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1701 return 2;
1702 }
1703 static unsigned int dec_move_rp(DisasContext *dc)
1704 {
1705 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1706 cris_cc_mask(dc, 0);
1707
1708 if (dc->op2 == PR_CCS) {
1709 cris_evaluate_flags(dc);
1710 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1711 if (dc->user) {
1712 /* User space is not allowed to touch all flags. */
1713 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1714 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1715 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1716 }
1717 }
1718 else
1719 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1720
1721 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1722 if (dc->op2 == PR_CCS) {
1723 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1724 dc->flags_live = 1;
1725 }
1726 return 2;
1727 }
1728 static unsigned int dec_move_pr(DisasContext *dc)
1729 {
1730 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1731 cris_cc_mask(dc, 0);
1732 /* Support register 0 is hardwired to zero.
1733 Treat it specially. */
1734 if (dc->op2 == 0)
1735 tcg_gen_movi_tl(cpu_T[1], 0);
1736 else if (dc->op2 == PR_CCS) {
1737 cris_evaluate_flags(dc);
1738 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1739 } else
1740 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1741 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1742 return 2;
1743 }
1744
1745 static unsigned int dec_move_mr(DisasContext *dc)
1746 {
1747 int memsize = memsize_zz(dc);
1748 int insn_len;
1749 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1750 memsize_char(memsize),
1751 dc->op1, dc->postinc ? "+]" : "]",
1752 dc->op2));
1753
1754 insn_len = dec_prep_alu_m(dc, 0, memsize);
1755 cris_cc_mask(dc, CC_MASK_NZ);
1756 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1757 do_postinc(dc, memsize);
1758 return insn_len;
1759 }
1760
1761 static unsigned int dec_movs_m(DisasContext *dc)
1762 {
1763 int memsize = memsize_z(dc);
1764 int insn_len;
1765 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1766 memsize_char(memsize),
1767 dc->op1, dc->postinc ? "+]" : "]",
1768 dc->op2));
1769
1770 /* sign extend. */
1771 insn_len = dec_prep_alu_m(dc, 1, memsize);
1772 cris_cc_mask(dc, CC_MASK_NZ);
1773 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1774 do_postinc(dc, memsize);
1775 return insn_len;
1776 }
1777
1778 static unsigned int dec_addu_m(DisasContext *dc)
1779 {
1780 int memsize = memsize_z(dc);
1781 int insn_len;
1782 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
1783 memsize_char(memsize),
1784 dc->op1, dc->postinc ? "+]" : "]",
1785 dc->op2));
1786
1787 /* sign extend. */
1788 insn_len = dec_prep_alu_m(dc, 0, memsize);
1789 cris_cc_mask(dc, CC_MASK_NZVC);
1790 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1791 do_postinc(dc, memsize);
1792 return insn_len;
1793 }
1794
1795 static unsigned int dec_adds_m(DisasContext *dc)
1796 {
1797 int memsize = memsize_z(dc);
1798 int insn_len;
1799 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
1800 memsize_char(memsize),
1801 dc->op1, dc->postinc ? "+]" : "]",
1802 dc->op2));
1803
1804 /* sign extend. */
1805 insn_len = dec_prep_alu_m(dc, 1, memsize);
1806 cris_cc_mask(dc, CC_MASK_NZVC);
1807 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1808 do_postinc(dc, memsize);
1809 return insn_len;
1810 }
1811
1812 static unsigned int dec_subu_m(DisasContext *dc)
1813 {
1814 int memsize = memsize_z(dc);
1815 int insn_len;
1816 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
1817 memsize_char(memsize),
1818 dc->op1, dc->postinc ? "+]" : "]",
1819 dc->op2));
1820
1821 /* sign extend. */
1822 insn_len = dec_prep_alu_m(dc, 0, memsize);
1823 cris_cc_mask(dc, CC_MASK_NZVC);
1824 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1825 do_postinc(dc, memsize);
1826 return insn_len;
1827 }
1828
1829 static unsigned int dec_subs_m(DisasContext *dc)
1830 {
1831 int memsize = memsize_z(dc);
1832 int insn_len;
1833 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
1834 memsize_char(memsize),
1835 dc->op1, dc->postinc ? "+]" : "]",
1836 dc->op2));
1837
1838 /* sign extend. */
1839 insn_len = dec_prep_alu_m(dc, 1, memsize);
1840 cris_cc_mask(dc, CC_MASK_NZVC);
1841 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1842 do_postinc(dc, memsize);
1843 return insn_len;
1844 }
1845
1846 static unsigned int dec_movu_m(DisasContext *dc)
1847 {
1848 int memsize = memsize_z(dc);
1849 int insn_len;
1850
1851 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
1852 memsize_char(memsize),
1853 dc->op1, dc->postinc ? "+]" : "]",
1854 dc->op2));
1855
1856 insn_len = dec_prep_alu_m(dc, 0, memsize);
1857 cris_cc_mask(dc, CC_MASK_NZ);
1858 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1859 do_postinc(dc, memsize);
1860 return insn_len;
1861 }
1862
1863 static unsigned int dec_cmpu_m(DisasContext *dc)
1864 {
1865 int memsize = memsize_z(dc);
1866 int insn_len;
1867 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
1868 memsize_char(memsize),
1869 dc->op1, dc->postinc ? "+]" : "]",
1870 dc->op2));
1871
1872 insn_len = dec_prep_alu_m(dc, 0, memsize);
1873 cris_cc_mask(dc, CC_MASK_NZVC);
1874 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1875 do_postinc(dc, memsize);
1876 return insn_len;
1877 }
1878
1879 static unsigned int dec_cmps_m(DisasContext *dc)
1880 {
1881 int memsize = memsize_z(dc);
1882 int insn_len;
1883 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
1884 memsize_char(memsize),
1885 dc->op1, dc->postinc ? "+]" : "]",
1886 dc->op2));
1887
1888 insn_len = dec_prep_alu_m(dc, 1, memsize);
1889 cris_cc_mask(dc, CC_MASK_NZVC);
1890 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1891 do_postinc(dc, memsize);
1892 return insn_len;
1893 }
1894
1895 static unsigned int dec_cmp_m(DisasContext *dc)
1896 {
1897 int memsize = memsize_zz(dc);
1898 int insn_len;
1899 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
1900 memsize_char(memsize),
1901 dc->op1, dc->postinc ? "+]" : "]",
1902 dc->op2));
1903
1904 insn_len = dec_prep_alu_m(dc, 0, memsize);
1905 cris_cc_mask(dc, CC_MASK_NZVC);
1906 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1907 do_postinc(dc, memsize);
1908 return insn_len;
1909 }
1910
1911 static unsigned int dec_test_m(DisasContext *dc)
1912 {
1913 int memsize = memsize_zz(dc);
1914 int insn_len;
1915 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
1916 memsize_char(memsize),
1917 dc->op1, dc->postinc ? "+]" : "]",
1918 dc->op2));
1919
1920 insn_len = dec_prep_alu_m(dc, 0, memsize);
1921 cris_cc_mask(dc, CC_MASK_NZ);
1922 gen_op_clrf(3);
1923
1924 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1925 tcg_gen_movi_tl(cpu_T[1], 0);
1926 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1927 do_postinc(dc, memsize);
1928 return insn_len;
1929 }
1930
1931 static unsigned int dec_and_m(DisasContext *dc)
1932 {
1933 int memsize = memsize_zz(dc);
1934 int insn_len;
1935 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
1936 memsize_char(memsize),
1937 dc->op1, dc->postinc ? "+]" : "]",
1938 dc->op2));
1939
1940 insn_len = dec_prep_alu_m(dc, 0, memsize);
1941 cris_cc_mask(dc, CC_MASK_NZ);
1942 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
1943 do_postinc(dc, memsize);
1944 return insn_len;
1945 }
1946
1947 static unsigned int dec_add_m(DisasContext *dc)
1948 {
1949 int memsize = memsize_zz(dc);
1950 int insn_len;
1951 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1952 memsize_char(memsize),
1953 dc->op1, dc->postinc ? "+]" : "]",
1954 dc->op2));
1955
1956 insn_len = dec_prep_alu_m(dc, 0, memsize);
1957 cris_cc_mask(dc, CC_MASK_NZVC);
1958 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
1959 do_postinc(dc, memsize);
1960 return insn_len;
1961 }
1962
1963 static unsigned int dec_addo_m(DisasContext *dc)
1964 {
1965 int memsize = memsize_zz(dc);
1966 int insn_len;
1967 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1968 memsize_char(memsize),
1969 dc->op1, dc->postinc ? "+]" : "]",
1970 dc->op2));
1971
1972 insn_len = dec_prep_alu_m(dc, 1, memsize);
1973 cris_cc_mask(dc, 0);
1974 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
1975 do_postinc(dc, memsize);
1976 return insn_len;
1977 }
1978
1979 static unsigned int dec_bound_m(DisasContext *dc)
1980 {
1981 int memsize = memsize_zz(dc);
1982 int insn_len;
1983 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
1984 memsize_char(memsize),
1985 dc->op1, dc->postinc ? "+]" : "]",
1986 dc->op2));
1987
1988 insn_len = dec_prep_alu_m(dc, 0, memsize);
1989 cris_cc_mask(dc, CC_MASK_NZ);
1990 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1991 do_postinc(dc, memsize);
1992 return insn_len;
1993 }
1994
1995 static unsigned int dec_addc_mr(DisasContext *dc)
1996 {
1997 int insn_len = 2;
1998 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
1999 dc->op1, dc->postinc ? "+]" : "]",
2000 dc->op2));
2001
2002 cris_evaluate_flags(dc);
2003 insn_len = dec_prep_alu_m(dc, 0, 4);
2004 cris_cc_mask(dc, CC_MASK_NZVC);
2005 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2006 do_postinc(dc, 4);
2007 return insn_len;
2008 }
2009
2010 static unsigned int dec_sub_m(DisasContext *dc)
2011 {
2012 int memsize = memsize_zz(dc);
2013 int insn_len;
2014 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2015 memsize_char(memsize),
2016 dc->op1, dc->postinc ? "+]" : "]",
2017 dc->op2, dc->ir, dc->zzsize));
2018
2019 insn_len = dec_prep_alu_m(dc, 0, memsize);
2020 cris_cc_mask(dc, CC_MASK_NZVC);
2021 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2022 do_postinc(dc, memsize);
2023 return insn_len;
2024 }
2025
2026 static unsigned int dec_or_m(DisasContext *dc)
2027 {
2028 int memsize = memsize_zz(dc);
2029 int insn_len;
2030 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2031 memsize_char(memsize),
2032 dc->op1, dc->postinc ? "+]" : "]",
2033 dc->op2, dc->pc));
2034
2035 insn_len = dec_prep_alu_m(dc, 0, memsize);
2036 cris_cc_mask(dc, CC_MASK_NZ);
2037 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2038 do_postinc(dc, memsize);
2039 return insn_len;
2040 }
2041
2042 static unsigned int dec_move_mp(DisasContext *dc)
2043 {
2044 int memsize = memsize_zz(dc);
2045 int insn_len = 2;
2046
2047 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2048 memsize_char(memsize),
2049 dc->op1,
2050 dc->postinc ? "+]" : "]",
2051 dc->op2));
2052
2053 insn_len = dec_prep_alu_m(dc, 0, memsize);
2054 cris_cc_mask(dc, 0);
2055 if (dc->op2 == PR_CCS) {
2056 cris_evaluate_flags(dc);
2057 if (dc->user) {
2058 /* User space is not allowed to touch all flags. */
2059 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2060 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2061 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2062 }
2063 }
2064
2065 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2066
2067 do_postinc(dc, memsize);
2068 return insn_len;
2069 }
2070
2071 static unsigned int dec_move_pm(DisasContext *dc)
2072 {
2073 int memsize;
2074
2075 memsize = preg_sizes[dc->op2];
2076
2077 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2078 memsize_char(memsize),
2079 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2080
2081 /* prepare store. Address in T0, value in T1. */
2082 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2083 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2084 gen_store_T0_T1(dc, memsize);
2085 cris_cc_mask(dc, 0);
2086 if (dc->postinc)
2087 {
2088 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2089 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2090 }
2091 return 2;
2092 }
2093
2094 static unsigned int dec_movem_mr(DisasContext *dc)
2095 {
2096 int i;
2097
2098 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2099 dc->postinc ? "+]" : "]", dc->op2));
2100
2101 /* fetch the address into T0 and T1. */
2102 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
2103 for (i = 0; i <= dc->op2; i++) {
2104 /* Perform the load onto regnum i. Always dword wide. */
2105 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2106 gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
2107 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
2108 }
2109 /* writeback the updated pointer value. */
2110 if (dc->postinc)
2111 t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
2112
2113 /* gen_load might want to evaluate the previous insns flags. */
2114 cris_cc_mask(dc, 0);
2115 return 2;
2116 }
2117
2118 static unsigned int dec_movem_rm(DisasContext *dc)
2119 {
2120 int i;
2121
2122 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2123 dc->postinc ? "+]" : "]"));
2124
2125 for (i = 0; i <= dc->op2; i++) {
2126 /* Fetch register i into T1. */
2127 t_gen_mov_TN_reg(cpu_T[1], i);
2128 /* Fetch the address into T0. */
2129 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2130 /* Displace it. */
2131 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
2132 /* Perform the store. */
2133 gen_store_T0_T1(dc, 4);
2134 }
2135 if (dc->postinc) {
2136 /* T0 should point to the last written addr, advance one more
2137 step. */
2138 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
2139 /* writeback the updated pointer value. */
2140 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2141 }
2142 cris_cc_mask(dc, 0);
2143 return 2;
2144 }
2145
2146 static unsigned int dec_move_rm(DisasContext *dc)
2147 {
2148 int memsize;
2149
2150 memsize = memsize_zz(dc);
2151
2152 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2153 memsize, dc->op2, dc->op1));
2154
2155 /* prepare store. */
2156 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2157 t_gen_mov_TN_reg(cpu_T[1], dc->op2);
2158 gen_store_T0_T1(dc, memsize);
2159 if (dc->postinc)
2160 {
2161 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2162 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2163 }
2164 cris_cc_mask(dc, 0);
2165 return 2;
2166 }
2167
2168 static unsigned int dec_lapcq(DisasContext *dc)
2169 {
2170 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2171 dc->pc + dc->op1*2, dc->op2));
2172 cris_cc_mask(dc, 0);
2173 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2174 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2175 return 2;
2176 }
2177
2178 static unsigned int dec_lapc_im(DisasContext *dc)
2179 {
2180 unsigned int rd;
2181 int32_t imm;
2182 int32_t pc;
2183
2184 rd = dc->op2;
2185
2186 cris_cc_mask(dc, 0);
2187 imm = ldl_code(dc->pc + 2);
2188 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2189
2190 pc = dc->pc;
2191 pc += imm;
2192 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2193 return 6;
2194 }
2195
2196 /* Jump to special reg. */
2197 static unsigned int dec_jump_p(DisasContext *dc)
2198 {
2199 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2200 cris_cc_mask(dc, 0);
2201
2202 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2203 /* rete will often have low bit set to indicate delayslot. */
2204 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2205 cris_prepare_dyn_jmp(dc);
2206 return 2;
2207 }
2208
2209 /* Jump and save. */
2210 static unsigned int dec_jas_r(DisasContext *dc)
2211 {
2212 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2213 cris_cc_mask(dc, 0);
2214 /* Store the return address in Pd. */
2215 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2216 if (dc->op2 > 15)
2217 abort();
2218 tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
2219
2220 cris_prepare_dyn_jmp(dc);
2221 return 2;
2222 }
2223
2224 static unsigned int dec_jas_im(DisasContext *dc)
2225 {
2226 uint32_t imm;
2227
2228 imm = ldl_code(dc->pc + 2);
2229
2230 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2231 cris_cc_mask(dc, 0);
2232 /* Stor the return address in Pd. */
2233 tcg_gen_movi_tl(env_btarget, imm);
2234 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2235 cris_prepare_dyn_jmp(dc);
2236 return 6;
2237 }
2238
2239 static unsigned int dec_jasc_im(DisasContext *dc)
2240 {
2241 uint32_t imm;
2242
2243 imm = ldl_code(dc->pc + 2);
2244
2245 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2246 cris_cc_mask(dc, 0);
2247 /* Stor the return address in Pd. */
2248 tcg_gen_movi_tl(cpu_T[0], imm);
2249 t_gen_mov_env_TN(btarget, cpu_T[0]);
2250 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2251 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2252 cris_prepare_dyn_jmp(dc);
2253 return 6;
2254 }
2255
2256 static unsigned int dec_jasc_r(DisasContext *dc)
2257 {
2258 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2259 cris_cc_mask(dc, 0);
2260 /* Stor the return address in Pd. */
2261 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2262 t_gen_mov_env_TN(btarget, cpu_T[0]);
2263 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2264 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2265 cris_prepare_dyn_jmp(dc);
2266 return 2;
2267 }
2268
2269 static unsigned int dec_bcc_im(DisasContext *dc)
2270 {
2271 int32_t offset;
2272 uint32_t cond = dc->op2;
2273
2274 offset = ldl_code(dc->pc + 2);
2275 offset = sign_extend(offset, 15);
2276
2277 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2278 cc_name(cond), offset,
2279 dc->pc, dc->pc + offset));
2280
2281 cris_cc_mask(dc, 0);
2282 /* op2 holds the condition-code. */
2283 cris_prepare_cc_branch (dc, offset, cond);
2284 return 4;
2285 }
2286
2287 static unsigned int dec_bas_im(DisasContext *dc)
2288 {
2289 int32_t simm;
2290
2291
2292 simm = ldl_code(dc->pc + 2);
2293
2294 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2295 cris_cc_mask(dc, 0);
2296 /* Stor the return address in Pd. */
2297 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2298 t_gen_mov_env_TN(btarget, cpu_T[0]);
2299 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2300 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2301 cris_prepare_dyn_jmp(dc);
2302 return 6;
2303 }
2304
2305 static unsigned int dec_basc_im(DisasContext *dc)
2306 {
2307 int32_t simm;
2308 simm = ldl_code(dc->pc + 2);
2309
2310 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2311 cris_cc_mask(dc, 0);
2312 /* Stor the return address in Pd. */
2313 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2314 t_gen_mov_env_TN(btarget, cpu_T[0]);
2315 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2316 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2317 cris_prepare_dyn_jmp(dc);
2318 return 6;
2319 }
2320
2321 static unsigned int dec_rfe_etc(DisasContext *dc)
2322 {
2323 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2324 dc->opcode, dc->pc, dc->op1, dc->op2));
2325
2326 cris_cc_mask(dc, 0);
2327
2328 if (dc->op2 == 15) /* ignore halt. */
2329 return 2;
2330
2331 switch (dc->op2 & 7) {
2332 case 2:
2333 /* rfe. */
2334 cris_evaluate_flags(dc);
2335 gen_op_ccs_rshift();
2336 /* FIXME: don't set the P-FLAG if R is set. */
2337 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
2338 /* Debug helper. */
2339 tcg_gen_helper_0_0(helper_rfe);
2340 dc->is_jmp = DISAS_UPDATE;
2341 break;
2342 case 5:
2343 /* rfn. */
2344 BUG();
2345 break;
2346 case 6:
2347 /* break. */
2348 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2349 t_gen_mov_env_TN(pc, cpu_T[0]);
2350 /* Breaks start at 16 in the exception vector. */
2351 gen_op_break_im(dc->op1 + 16);
2352 dc->is_jmp = DISAS_UPDATE;
2353 break;
2354 default:
2355 printf ("op2=%x\n", dc->op2);
2356 BUG();
2357 break;
2358
2359 }
2360 return 2;
2361 }
2362
2363 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2364 {
2365 /* Ignore D-cache flushes. */
2366 return 2;
2367 }
2368
2369 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2370 {
2371 /* Ignore I-cache flushes. */
2372 return 2;
2373 }
2374
2375 static unsigned int dec_null(DisasContext *dc)
2376 {
2377 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2378 dc->pc, dc->opcode, dc->op1, dc->op2);
2379 fflush(NULL);
2380 BUG();
2381 return 2;
2382 }
2383
2384 struct decoder_info {
2385 struct {
2386 uint32_t bits;
2387 uint32_t mask;
2388 };
2389 unsigned int (*dec)(DisasContext *dc);
2390 } decinfo[] = {
2391 /* Order matters here. */
2392 {DEC_MOVEQ, dec_moveq},
2393 {DEC_BTSTQ, dec_btstq},
2394 {DEC_CMPQ, dec_cmpq},
2395 {DEC_ADDOQ, dec_addoq},
2396 {DEC_ADDQ, dec_addq},
2397 {DEC_SUBQ, dec_subq},
2398 {DEC_ANDQ, dec_andq},
2399 {DEC_ORQ, dec_orq},
2400 {DEC_ASRQ, dec_asrq},
2401 {DEC_LSLQ, dec_lslq},
2402 {DEC_LSRQ, dec_lsrq},
2403 {DEC_BCCQ, dec_bccq},
2404
2405 {DEC_BCC_IM, dec_bcc_im},
2406 {DEC_JAS_IM, dec_jas_im},
2407 {DEC_JAS_R, dec_jas_r},
2408 {DEC_JASC_IM, dec_jasc_im},
2409 {DEC_JASC_R, dec_jasc_r},
2410 {DEC_BAS_IM, dec_bas_im},
2411 {DEC_BASC_IM, dec_basc_im},
2412 {DEC_JUMP_P, dec_jump_p},
2413 {DEC_LAPC_IM, dec_lapc_im},
2414 {DEC_LAPCQ, dec_lapcq},
2415
2416 {DEC_RFE_ETC, dec_rfe_etc},
2417 {DEC_ADDC_MR, dec_addc_mr},
2418
2419 {DEC_MOVE_MP, dec_move_mp},
2420 {DEC_MOVE_PM, dec_move_pm},
2421 {DEC_MOVEM_MR, dec_movem_mr},
2422 {DEC_MOVEM_RM, dec_movem_rm},
2423 {DEC_MOVE_PR, dec_move_pr},
2424 {DEC_SCC_R, dec_scc_r},
2425 {DEC_SETF, dec_setclrf},
2426 {DEC_CLEARF, dec_setclrf},
2427
2428 {DEC_MOVE_SR, dec_move_sr},
2429 {DEC_MOVE_RP, dec_move_rp},
2430 {DEC_SWAP_R, dec_swap_r},
2431 {DEC_ABS_R, dec_abs_r},
2432 {DEC_LZ_R, dec_lz_r},
2433 {DEC_MOVE_RS, dec_move_rs},
2434 {DEC_BTST_R, dec_btst_r},
2435 {DEC_ADDC_R, dec_addc_r},
2436
2437 {DEC_DSTEP_R, dec_dstep_r},
2438 {DEC_XOR_R, dec_xor_r},
2439 {DEC_MCP_R, dec_mcp_r},
2440 {DEC_CMP_R, dec_cmp_r},
2441
2442 {DEC_ADDI_R, dec_addi_r},
2443 {DEC_ADDI_ACR, dec_addi_acr},
2444
2445 {DEC_ADD_R, dec_add_r},
2446 {DEC_SUB_R, dec_sub_r},
2447
2448 {DEC_ADDU_R, dec_addu_r},
2449 {DEC_ADDS_R, dec_adds_r},
2450 {DEC_SUBU_R, dec_subu_r},
2451 {DEC_SUBS_R, dec_subs_r},
2452 {DEC_LSL_R, dec_lsl_r},
2453
2454 {DEC_AND_R, dec_and_r},
2455 {DEC_OR_R, dec_or_r},
2456 {DEC_BOUND_R, dec_bound_r},
2457 {DEC_ASR_R, dec_asr_r},
2458 {DEC_LSR_R, dec_lsr_r},
2459
2460 {DEC_MOVU_R, dec_movu_r},
2461 {DEC_MOVS_R, dec_movs_r},
2462 {DEC_NEG_R, dec_neg_r},
2463 {DEC_MOVE_R, dec_move_r},
2464
2465 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2466 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2467
2468 {DEC_MULS_R, dec_muls_r},
2469 {DEC_MULU_R, dec_mulu_r},
2470
2471 {DEC_ADDU_M, dec_addu_m},
2472 {DEC_ADDS_M, dec_adds_m},
2473 {DEC_SUBU_M, dec_subu_m},
2474 {DEC_SUBS_M, dec_subs_m},
2475
2476 {DEC_CMPU_M, dec_cmpu_m},
2477 {DEC_CMPS_M, dec_cmps_m},
2478 {DEC_MOVU_M, dec_movu_m},
2479 {DEC_MOVS_M, dec_movs_m},
2480
2481 {DEC_CMP_M, dec_cmp_m},
2482 {DEC_ADDO_M, dec_addo_m},
2483 {DEC_BOUND_M, dec_bound_m},
2484 {DEC_ADD_M, dec_add_m},
2485 {DEC_SUB_M, dec_sub_m},
2486 {DEC_AND_M, dec_and_m},
2487 {DEC_OR_M, dec_or_m},
2488 {DEC_MOVE_RM, dec_move_rm},
2489 {DEC_TEST_M, dec_test_m},
2490 {DEC_MOVE_MR, dec_move_mr},
2491
2492 {{0, 0}, dec_null}
2493 };
2494
2495 static inline unsigned int
2496 cris_decoder(DisasContext *dc)
2497 {
2498 unsigned int insn_len = 2;
2499 uint32_t tmp;
2500 int i;
2501
2502 /* Load a halfword onto the instruction register. */
2503 tmp = ldl_code(dc->pc);
2504 dc->ir = tmp & 0xffff;
2505
2506 /* Now decode it. */
2507 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2508 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2509 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2510 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2511 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2512 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2513
2514 /* Large switch for all insns. */
2515 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2516 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2517 {
2518 insn_len = decinfo[i].dec(dc);
2519 break;
2520 }
2521 }
2522
2523 return insn_len;
2524 }
2525
2526 static void check_breakpoint(CPUState *env, DisasContext *dc)
2527 {
2528 int j;
2529 if (env->nb_breakpoints > 0) {
2530 for(j = 0; j < env->nb_breakpoints; j++) {
2531 if (env->breakpoints[j] == dc->pc) {
2532 cris_evaluate_flags (dc);
2533 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2534 t_gen_mov_env_TN(pc, cpu_T[0]);
2535 gen_op_debug();
2536 dc->is_jmp = DISAS_UPDATE;
2537 }
2538 }
2539 }
2540 }
2541
2542 /* generate intermediate code for basic block 'tb'. */
2543 struct DisasContext ctx;
2544 static int
2545 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2546 int search_pc)
2547 {
2548 uint16_t *gen_opc_end;
2549 uint32_t pc_start;
2550 unsigned int insn_len;
2551 int j, lj;
2552 struct DisasContext *dc = &ctx;
2553 uint32_t next_page_start;
2554
2555 if (!logfile)
2556 logfile = stderr;
2557
2558 if (tb->pc & 1)
2559 cpu_abort(env, "unaligned pc=%x erp=%x\n",
2560 env->pc, env->pregs[PR_ERP]);
2561 pc_start = tb->pc;
2562 dc->env = env;
2563 dc->tb = tb;
2564
2565 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2566
2567 dc->is_jmp = DISAS_NEXT;
2568 dc->ppc = pc_start;
2569 dc->pc = pc_start;
2570 dc->singlestep_enabled = env->singlestep_enabled;
2571 dc->flags_live = 1;
2572 dc->flagx_live = 0;
2573 dc->flags_x = 0;
2574 dc->cc_mask = 0;
2575 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2576
2577 dc->user = env->pregs[PR_CCS] & U_FLAG;
2578 dc->delayed_branch = 0;
2579
2580 if (loglevel & CPU_LOG_TB_IN_ASM) {
2581 fprintf(logfile,
2582 "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
2583 "%x.%x.%x.%x\n"
2584 "%x.%x.%x.%x\n"
2585 "%x.%x.%x.%x\n"
2586 "%x.%x.%x.%x\n",
2587 search_pc, env->pc, env->pregs[PR_CCS],
2588 env->pregs[PR_PID], env->pregs[PR_USP],
2589 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2590 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2591 env->regs[8], env->regs[9],
2592 env->regs[10], env->regs[11],
2593 env->regs[12], env->regs[13],
2594 env->regs[14], env->regs[15]);
2595
2596 }
2597
2598 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2599 lj = -1;
2600 do
2601 {
2602 check_breakpoint(env, dc);
2603 if (dc->is_jmp == DISAS_JUMP
2604 || dc->is_jmp == DISAS_SWI)
2605 goto done;
2606
2607 if (search_pc) {
2608 j = gen_opc_ptr - gen_opc_buf;
2609 if (lj < j) {
2610 lj++;
2611 while (lj < j)
2612 gen_opc_instr_start[lj++] = 0;
2613 }
2614 if (dc->delayed_branch == 1) {
2615 gen_opc_pc[lj] = dc->ppc | 1;
2616 gen_opc_instr_start[lj] = 0;
2617 }
2618 else {
2619 gen_opc_pc[lj] = dc->pc;
2620 gen_opc_instr_start[lj] = 1;
2621 }
2622 }
2623
2624 dc->clear_x = 1;
2625 insn_len = cris_decoder(dc);
2626 STATS(gen_op_exec_insn());
2627 dc->ppc = dc->pc;
2628 dc->pc += insn_len;
2629 if (dc->clear_x)
2630 cris_clear_x_flag(dc);
2631
2632 /* Check for delayed branches here. If we do it before
2633 actually genereating any host code, the simulator will just
2634 loop doing nothing for on this program location. */
2635 if (dc->delayed_branch) {
2636 dc->delayed_branch--;
2637 if (dc->delayed_branch == 0)
2638 {
2639 if (dc->bcc == CC_A) {
2640 gen_op_jmp1 ();
2641 dc->is_jmp = DISAS_JUMP;
2642 }
2643 else {
2644 /* Conditional jmp. */
2645 gen_op_cc_jmp (dc->delayed_pc, dc->pc);
2646 dc->is_jmp = DISAS_JUMP;
2647 }
2648 }
2649 }
2650
2651 if (env->singlestep_enabled)
2652 break;
2653 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2654 && ((dc->pc < next_page_start) || dc->delayed_branch));
2655
2656 if (dc->delayed_branch == 1) {
2657 /* Reexecute the last insn. */
2658 dc->pc = dc->ppc;
2659 }
2660
2661 if (!dc->is_jmp) {
2662 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2663 dc->is_jmp, dc->delayed_branch));
2664 /* T0 and env_pc should hold the new pc. */
2665 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2666 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2667 }
2668
2669 cris_evaluate_flags (dc);
2670 done:
2671 if (__builtin_expect(env->singlestep_enabled, 0)) {
2672 gen_op_debug();
2673 } else {
2674 switch(dc->is_jmp) {
2675 case DISAS_NEXT:
2676 gen_goto_tb(dc, 1, dc->pc);
2677 break;
2678 default:
2679 case DISAS_JUMP:
2680 case DISAS_UPDATE:
2681 /* indicate that the hash table must be used
2682 to find the next TB */
2683 tcg_gen_exit_tb(0);
2684 break;
2685 case DISAS_SWI:
2686 case DISAS_TB_JUMP:
2687 /* nothing more to generate */
2688 break;
2689 }
2690 }
2691 *gen_opc_ptr = INDEX_op_end;
2692 if (search_pc) {
2693 j = gen_opc_ptr - gen_opc_buf;
2694 lj++;
2695 while (lj <= j)
2696 gen_opc_instr_start[lj++] = 0;
2697 } else {
2698 tb->size = dc->pc - pc_start;
2699 }
2700
2701 #ifdef DEBUG_DISAS
2702 if (loglevel & CPU_LOG_TB_IN_ASM) {
2703 fprintf(logfile, "--------------\n");
2704 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2705 target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
2706 fprintf(logfile, "\nisize=%d osize=%d\n",
2707 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2708 }
2709 #endif
2710 return 0;
2711 }
2712
2713 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2714 {
2715 return gen_intermediate_code_internal(env, tb, 0);
2716 }
2717
2718 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2719 {
2720 return gen_intermediate_code_internal(env, tb, 1);
2721 }
2722
2723 void cpu_dump_state (CPUState *env, FILE *f,
2724 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2725 int flags)
2726 {
2727 int i;
2728 uint32_t srs;
2729
2730 if (!env || !f)
2731 return;
2732
2733 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2734 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2735 "debug=%x %x %x\n",
2736 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2737 env->cc_op,
2738 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2739 env->debug1, env->debug2, env->debug3);
2740
2741 for (i = 0; i < 16; i++) {
2742 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2743 if ((i + 1) % 4 == 0)
2744 cpu_fprintf(f, "\n");
2745 }
2746 cpu_fprintf(f, "\nspecial regs:\n");
2747 for (i = 0; i < 16; i++) {
2748 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2749 if ((i + 1) % 4 == 0)
2750 cpu_fprintf(f, "\n");
2751 }
2752 srs = env->pregs[PR_SRS];
2753 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
2754 if (srs < 256) {
2755 for (i = 0; i < 16; i++) {
2756 cpu_fprintf(f, "s%2.2d=%8.8x ",
2757 i, env->sregs[srs][i]);
2758 if ((i + 1) % 4 == 0)
2759 cpu_fprintf(f, "\n");
2760 }
2761 }
2762 cpu_fprintf(f, "\n\n");
2763
2764 }
2765
2766 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
2767 {
2768 }
2769
2770 CPUCRISState *cpu_cris_init (const char *cpu_model)
2771 {
2772 CPUCRISState *env;
2773 int i;
2774
2775 env = qemu_mallocz(sizeof(CPUCRISState));
2776 if (!env)
2777 return NULL;
2778 cpu_exec_init(env);
2779
2780 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
2781 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
2782 #if TARGET_LONG_BITS > HOST_LONG_BITS
2783 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
2784 TCG_AREG0, offsetof(CPUState, t0), "T0");
2785 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
2786 TCG_AREG0, offsetof(CPUState, t1), "T1");
2787 #else
2788 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
2789 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
2790 #endif
2791
2792 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2793 offsetof(CPUState, cc_src), "cc_src");
2794 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2795 offsetof(CPUState, cc_dest),
2796 "cc_dest");
2797 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2798 offsetof(CPUState, cc_result),
2799 "cc_result");
2800 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2801 offsetof(CPUState, cc_op), "cc_op");
2802 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2803 offsetof(CPUState, cc_size),
2804 "cc_size");
2805 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2806 offsetof(CPUState, cc_mask),
2807 "cc_mask");
2808
2809 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2810 offsetof(CPUState, pc),
2811 "pc");
2812 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2813 offsetof(CPUState, btarget),
2814 "btarget");
2815
2816 for (i = 0; i < 16; i++) {
2817 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2818 offsetof(CPUState, regs[i]),
2819 regnames[i]);
2820 }
2821 for (i = 0; i < 16; i++) {
2822 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2823 offsetof(CPUState, pregs[i]),
2824 pregnames[i]);
2825 }
2826
2827 TCG_HELPER(helper_tlb_update);
2828 TCG_HELPER(helper_tlb_flush);
2829 TCG_HELPER(helper_rfe);
2830 TCG_HELPER(helper_store);
2831 TCG_HELPER(helper_dump);
2832 TCG_HELPER(helper_dummy);
2833
2834 TCG_HELPER(helper_evaluate_flags_muls);
2835 TCG_HELPER(helper_evaluate_flags_mulu);
2836 TCG_HELPER(helper_evaluate_flags_mcp);
2837 TCG_HELPER(helper_evaluate_flags_alu_4);
2838 TCG_HELPER(helper_evaluate_flags_move_4);
2839 TCG_HELPER(helper_evaluate_flags_move_2);
2840 TCG_HELPER(helper_evaluate_flags);
2841
2842 cpu_reset(env);
2843 return env;
2844 }
2845
2846 void cpu_reset (CPUCRISState *env)
2847 {
2848 memset(env, 0, offsetof(CPUCRISState, breakpoints));
2849 tlb_flush(env, 1);
2850
2851 #if defined(CONFIG_USER_ONLY)
2852 /* start in user mode with interrupts enabled. */
2853 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
2854 #else
2855 env->pregs[PR_CCS] = 0;
2856 #endif
2857 }
2858
2859 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
2860 unsigned long searched_pc, int pc_pos, void *puc)
2861 {
2862 env->pc = gen_opc_pc[pc_pos];
2863 }
Qemu copy for testing