2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
44 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
65 static TCGv cpu_R
[16];
66 static TCGv cpu_PR
[16];
70 static TCGv cc_result
;
75 static TCGv env_btaken
;
76 static TCGv env_btarget
;
79 #include "gen-icount.h"
81 /* This is the state at translation time. */
82 typedef struct DisasContext
{
91 unsigned int zsize
, zzsize
;
100 int cc_size_uptodate
; /* -1 invalid or last written value. */
102 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate
; /* Wether or not $ccs is uptodate. */
104 int flagx_known
; /* Wether or not flags_x has the x flag known at
108 int clear_x
; /* Clear x after this insn? */
109 int cpustate_changed
;
110 unsigned int tb_flags
; /* tb dependent flags. */
115 #define JMP_INDIRECT 2
116 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
121 struct TranslationBlock
*tb
;
122 int singlestep_enabled
;
125 static void gen_BUG(DisasContext
*dc
, const char *file
, int line
)
127 printf ("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
128 fprintf (logfile
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
129 cpu_abort(dc
->env
, "%s:%d\n", file
, line
);
132 static const char *regnames
[] =
134 "$r0", "$r1", "$r2", "$r3",
135 "$r4", "$r5", "$r6", "$r7",
136 "$r8", "$r9", "$r10", "$r11",
137 "$r12", "$r13", "$sp", "$acr",
139 static const char *pregnames
[] =
141 "$bz", "$vr", "$pid", "$srs",
142 "$wz", "$exs", "$eda", "$mof",
143 "$dz", "$ebp", "$erp", "$srp",
144 "$nrp", "$ccs", "$usp", "$spc",
147 /* We need this table to handle preg-moves with implicit width. */
148 static int preg_sizes
[] = {
159 #define t_gen_mov_TN_env(tn, member) \
160 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
161 #define t_gen_mov_env_TN(member, tn) \
162 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
164 static inline void t_gen_mov_TN_reg(TCGv tn
, int r
)
167 fprintf(stderr
, "wrong register read $r%d\n", r
);
168 tcg_gen_mov_tl(tn
, cpu_R
[r
]);
170 static inline void t_gen_mov_reg_TN(int r
, TCGv tn
)
173 fprintf(stderr
, "wrong register write $r%d\n", r
);
174 tcg_gen_mov_tl(cpu_R
[r
], tn
);
177 static inline void _t_gen_mov_TN_env(TCGv tn
, int offset
)
179 if (offset
> sizeof (CPUState
))
180 fprintf(stderr
, "wrong load from env from off=%d\n", offset
);
181 tcg_gen_ld_tl(tn
, cpu_env
, offset
);
183 static inline void _t_gen_mov_env_TN(int offset
, TCGv tn
)
185 if (offset
> sizeof (CPUState
))
186 fprintf(stderr
, "wrong store to env at off=%d\n", offset
);
187 tcg_gen_st_tl(tn
, cpu_env
, offset
);
190 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
193 fprintf(stderr
, "wrong register read $p%d\n", r
);
194 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
195 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
197 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
198 else if (r
== PR_EDA
) {
199 printf("read from EDA!\n");
200 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
203 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
205 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
208 fprintf(stderr
, "wrong register write $p%d\n", r
);
209 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
211 else if (r
== PR_SRS
)
212 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
215 tcg_gen_helper_0_1(helper_tlb_flush_pid
, tn
);
216 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
)
217 tcg_gen_helper_0_1(helper_spc_write
, tn
);
218 else if (r
== PR_CCS
)
219 dc
->cpustate_changed
= 1;
220 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
224 static inline void t_gen_raise_exception(uint32_t index
)
226 tcg_gen_helper_0_1(helper_raise_exception
, tcg_const_tl(index
));
229 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
233 t0
= tcg_temp_new(TCG_TYPE_TL
);
234 t_31
= tcg_const_tl(31);
235 tcg_gen_shl_tl(d
, a
, b
);
237 tcg_gen_sub_tl(t0
, t_31
, b
);
238 tcg_gen_sar_tl(t0
, t0
, t_31
);
239 tcg_gen_and_tl(t0
, t0
, d
);
240 tcg_gen_xor_tl(d
, d
, t0
);
245 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
249 t0
= tcg_temp_new(TCG_TYPE_TL
);
250 t_31
= tcg_temp_new(TCG_TYPE_TL
);
251 tcg_gen_shr_tl(d
, a
, b
);
253 tcg_gen_movi_tl(t_31
, 31);
254 tcg_gen_sub_tl(t0
, t_31
, b
);
255 tcg_gen_sar_tl(t0
, t0
, t_31
);
256 tcg_gen_and_tl(t0
, t0
, d
);
257 tcg_gen_xor_tl(d
, d
, t0
);
262 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
266 t0
= tcg_temp_new(TCG_TYPE_TL
);
267 t_31
= tcg_temp_new(TCG_TYPE_TL
);
268 tcg_gen_sar_tl(d
, a
, b
);
270 tcg_gen_movi_tl(t_31
, 31);
271 tcg_gen_sub_tl(t0
, t_31
, b
);
272 tcg_gen_sar_tl(t0
, t0
, t_31
);
273 tcg_gen_or_tl(d
, d
, t0
);
278 /* 64-bit signed mul, lower result in d and upper in d2. */
279 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
283 t0
= tcg_temp_new(TCG_TYPE_I64
);
284 t1
= tcg_temp_new(TCG_TYPE_I64
);
286 tcg_gen_ext32s_i64(t0
, a
);
287 tcg_gen_ext32s_i64(t1
, b
);
288 tcg_gen_mul_i64(t0
, t0
, t1
);
290 tcg_gen_trunc_i64_i32(d
, t0
);
291 tcg_gen_shri_i64(t0
, t0
, 32);
292 tcg_gen_trunc_i64_i32(d2
, t0
);
298 /* 64-bit unsigned muls, lower result in d and upper in d2. */
299 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
303 t0
= tcg_temp_new(TCG_TYPE_I64
);
304 t1
= tcg_temp_new(TCG_TYPE_I64
);
306 tcg_gen_extu_i32_i64(t0
, a
);
307 tcg_gen_extu_i32_i64(t1
, b
);
308 tcg_gen_mul_i64(t0
, t0
, t1
);
310 tcg_gen_trunc_i64_i32(d
, t0
);
311 tcg_gen_shri_i64(t0
, t0
, 32);
312 tcg_gen_trunc_i64_i32(d2
, t0
);
318 /* 32bit branch-free binary search for counting leading zeros. */
319 static void t_gen_lz_i32(TCGv d
, TCGv x
)
323 y
= tcg_temp_new(TCG_TYPE_I32
);
324 m
= tcg_temp_new(TCG_TYPE_I32
);
325 n
= tcg_temp_new(TCG_TYPE_I32
);
328 tcg_gen_shri_i32(y
, x
, 16);
329 tcg_gen_neg_i32(y
, y
);
331 /* m = (y >> 16) & 16 */
332 tcg_gen_sari_i32(m
, y
, 16);
333 tcg_gen_andi_i32(m
, m
, 16);
336 tcg_gen_sub_i32(n
, tcg_const_i32(16), m
);
338 tcg_gen_shr_i32(x
, x
, m
);
341 tcg_gen_subi_i32(y
, x
, 0x100);
342 /* m = (y >> 16) & 8 */
343 tcg_gen_sari_i32(m
, y
, 16);
344 tcg_gen_andi_i32(m
, m
, 8);
346 tcg_gen_add_i32(n
, n
, m
);
348 tcg_gen_shl_i32(x
, x
, m
);
351 tcg_gen_subi_i32(y
, x
, 0x1000);
352 /* m = (y >> 16) & 4 */
353 tcg_gen_sari_i32(m
, y
, 16);
354 tcg_gen_andi_i32(m
, m
, 4);
356 tcg_gen_add_i32(n
, n
, m
);
358 tcg_gen_shl_i32(x
, x
, m
);
361 tcg_gen_subi_i32(y
, x
, 0x4000);
362 /* m = (y >> 16) & 2 */
363 tcg_gen_sari_i32(m
, y
, 16);
364 tcg_gen_andi_i32(m
, m
, 2);
366 tcg_gen_add_i32(n
, n
, m
);
368 tcg_gen_shl_i32(x
, x
, m
);
371 tcg_gen_shri_i32(y
, x
, 14);
372 /* m = y & ~(y >> 1) */
373 tcg_gen_sari_i32(m
, y
, 1);
374 tcg_gen_not_i32(m
, m
);
375 tcg_gen_and_i32(m
, m
, y
);
378 tcg_gen_addi_i32(d
, n
, 2);
379 tcg_gen_sub_i32(d
, d
, m
);
386 static void t_gen_btst(TCGv d
, TCGv a
, TCGv b
)
394 The N flag is set according to the selected bit in the dest reg.
395 The Z flag is set if the selected bit and all bits to the right are
397 The X flag is cleared.
398 Other flags are left untouched.
399 The destination reg is not affected.
401 unsigned int fz, sbit, bset, mask, masked_t0;
404 bset = !!(T0 & (1 << sbit));
405 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
406 masked_t0 = T0 & mask;
407 fz = !(masked_t0 | bset);
409 // Clear the X, N and Z flags.
410 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
411 // Set the N and Z flags accordingly.
412 T0 |= (bset << 3) | (fz << 2);
415 l1
= gen_new_label();
416 sbit
= tcg_temp_new(TCG_TYPE_TL
);
417 bset
= tcg_temp_new(TCG_TYPE_TL
);
418 t0
= tcg_temp_new(TCG_TYPE_TL
);
420 /* Compute bset and sbit. */
421 tcg_gen_andi_tl(sbit
, b
, 31);
422 tcg_gen_shl_tl(t0
, tcg_const_tl(1), sbit
);
423 tcg_gen_and_tl(bset
, a
, t0
);
424 tcg_gen_shr_tl(bset
, bset
, sbit
);
425 /* Displace to N_FLAG. */
426 tcg_gen_shli_tl(bset
, bset
, 3);
428 tcg_gen_shl_tl(sbit
, tcg_const_tl(2), sbit
);
429 tcg_gen_subi_tl(sbit
, sbit
, 1);
430 tcg_gen_and_tl(sbit
, a
, sbit
);
432 tcg_gen_andi_tl(d
, cpu_PR
[PR_CCS
], ~(X_FLAG
| N_FLAG
| Z_FLAG
));
433 /* or in the N_FLAG. */
434 tcg_gen_or_tl(d
, d
, bset
);
435 tcg_gen_brcondi_tl(TCG_COND_NE
, sbit
, 0, l1
);
436 /* or in the Z_FLAG. */
437 tcg_gen_ori_tl(d
, d
, Z_FLAG
);
444 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
448 l1
= gen_new_label();
455 tcg_gen_shli_tl(d
, a
, 1);
456 tcg_gen_brcond_tl(TCG_COND_LTU
, d
, b
, l1
);
457 tcg_gen_sub_tl(d
, d
, b
);
461 /* Extended arithmetics on CRIS. */
462 static inline void t_gen_add_flag(TCGv d
, int flag
)
466 c
= tcg_temp_new(TCG_TYPE_TL
);
467 t_gen_mov_TN_preg(c
, PR_CCS
);
468 /* Propagate carry into d. */
469 tcg_gen_andi_tl(c
, c
, 1 << flag
);
471 tcg_gen_shri_tl(c
, c
, flag
);
472 tcg_gen_add_tl(d
, d
, c
);
476 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
478 if (dc
->flagx_known
) {
482 c
= tcg_temp_new(TCG_TYPE_TL
);
483 t_gen_mov_TN_preg(c
, PR_CCS
);
484 /* C flag is already at bit 0. */
485 tcg_gen_andi_tl(c
, c
, C_FLAG
);
486 tcg_gen_add_tl(d
, d
, c
);
492 x
= tcg_temp_new(TCG_TYPE_TL
);
493 c
= tcg_temp_new(TCG_TYPE_TL
);
494 t_gen_mov_TN_preg(x
, PR_CCS
);
495 tcg_gen_mov_tl(c
, x
);
497 /* Propagate carry into d if X is set. Branch free. */
498 tcg_gen_andi_tl(c
, c
, C_FLAG
);
499 tcg_gen_andi_tl(x
, x
, X_FLAG
);
500 tcg_gen_shri_tl(x
, x
, 4);
502 tcg_gen_and_tl(x
, x
, c
);
503 tcg_gen_add_tl(d
, d
, x
);
509 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
511 if (dc
->flagx_known
) {
515 c
= tcg_temp_new(TCG_TYPE_TL
);
516 t_gen_mov_TN_preg(c
, PR_CCS
);
517 /* C flag is already at bit 0. */
518 tcg_gen_andi_tl(c
, c
, C_FLAG
);
519 tcg_gen_sub_tl(d
, d
, c
);
525 x
= tcg_temp_new(TCG_TYPE_TL
);
526 c
= tcg_temp_new(TCG_TYPE_TL
);
527 t_gen_mov_TN_preg(x
, PR_CCS
);
528 tcg_gen_mov_tl(c
, x
);
530 /* Propagate carry into d if X is set. Branch free. */
531 tcg_gen_andi_tl(c
, c
, C_FLAG
);
532 tcg_gen_andi_tl(x
, x
, X_FLAG
);
533 tcg_gen_shri_tl(x
, x
, 4);
535 tcg_gen_and_tl(x
, x
, c
);
536 tcg_gen_sub_tl(d
, d
, x
);
542 /* Swap the two bytes within each half word of the s operand.
543 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
544 static inline void t_gen_swapb(TCGv d
, TCGv s
)
548 t
= tcg_temp_new(TCG_TYPE_TL
);
549 org_s
= tcg_temp_new(TCG_TYPE_TL
);
551 /* d and s may refer to the same object. */
552 tcg_gen_mov_tl(org_s
, s
);
553 tcg_gen_shli_tl(t
, org_s
, 8);
554 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
555 tcg_gen_shri_tl(t
, org_s
, 8);
556 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
557 tcg_gen_or_tl(d
, d
, t
);
559 tcg_temp_free(org_s
);
562 /* Swap the halfwords of the s operand. */
563 static inline void t_gen_swapw(TCGv d
, TCGv s
)
566 /* d and s refer the same object. */
567 t
= tcg_temp_new(TCG_TYPE_TL
);
568 tcg_gen_mov_tl(t
, s
);
569 tcg_gen_shli_tl(d
, t
, 16);
570 tcg_gen_shri_tl(t
, t
, 16);
571 tcg_gen_or_tl(d
, d
, t
);
575 /* Reverse the within each byte.
576 T0 = (((T0 << 7) & 0x80808080) |
577 ((T0 << 5) & 0x40404040) |
578 ((T0 << 3) & 0x20202020) |
579 ((T0 << 1) & 0x10101010) |
580 ((T0 >> 1) & 0x08080808) |
581 ((T0 >> 3) & 0x04040404) |
582 ((T0 >> 5) & 0x02020202) |
583 ((T0 >> 7) & 0x01010101));
585 static inline void t_gen_swapr(TCGv d
, TCGv s
)
588 int shift
; /* LSL when positive, LSR when negative. */
603 /* d and s refer the same object. */
604 t
= tcg_temp_new(TCG_TYPE_TL
);
605 org_s
= tcg_temp_new(TCG_TYPE_TL
);
606 tcg_gen_mov_tl(org_s
, s
);
608 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
609 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
610 for (i
= 1; i
< sizeof bitrev
/ sizeof bitrev
[0]; i
++) {
611 if (bitrev
[i
].shift
>= 0) {
612 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
614 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
616 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
617 tcg_gen_or_tl(d
, d
, t
);
620 tcg_temp_free(org_s
);
623 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
628 l1
= gen_new_label();
629 btaken
= tcg_temp_new(TCG_TYPE_TL
);
631 /* Conditional jmp. */
632 tcg_gen_mov_tl(btaken
, env_btaken
);
633 tcg_gen_mov_tl(env_pc
, pc_false
);
634 tcg_gen_brcondi_tl(TCG_COND_EQ
, btaken
, 0, l1
);
635 tcg_gen_mov_tl(env_pc
, pc_true
);
638 tcg_temp_free(btaken
);
641 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
643 TranslationBlock
*tb
;
645 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
647 tcg_gen_movi_tl(env_pc
, dest
);
648 tcg_gen_exit_tb((long)tb
+ n
);
650 tcg_gen_movi_tl(env_pc
, dest
);
655 /* Sign extend at translation time. */
656 static int sign_extend(unsigned int val
, unsigned int width
)
668 static inline void cris_clear_x_flag(DisasContext
*dc
)
670 if (dc
->flagx_known
&& dc
->flags_x
)
671 dc
->flags_uptodate
= 0;
677 static void cris_flush_cc_state(DisasContext
*dc
)
679 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
680 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
681 dc
->cc_size_uptodate
= dc
->cc_size
;
683 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
684 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
687 static void cris_evaluate_flags(DisasContext
*dc
)
689 if (!dc
->flags_uptodate
) {
690 cris_flush_cc_state(dc
);
695 tcg_gen_helper_0_0(helper_evaluate_flags_mcp
);
698 tcg_gen_helper_0_0(helper_evaluate_flags_muls
);
701 tcg_gen_helper_0_0(helper_evaluate_flags_mulu
);
713 tcg_gen_helper_0_0(helper_evaluate_flags_move_4
);
716 tcg_gen_helper_0_0(helper_evaluate_flags_move_2
);
719 tcg_gen_helper_0_0(helper_evaluate_flags
);
731 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4
);
734 tcg_gen_helper_0_0(helper_evaluate_flags
);
740 if (dc
->flagx_known
) {
742 tcg_gen_ori_tl(cpu_PR
[PR_CCS
],
743 cpu_PR
[PR_CCS
], X_FLAG
);
745 tcg_gen_andi_tl(cpu_PR
[PR_CCS
],
746 cpu_PR
[PR_CCS
], ~X_FLAG
);
749 dc
->flags_uptodate
= 1;
753 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
762 /* Check if we need to evaluate the condition codes due to
764 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
766 /* TODO: optimize this case. It trigs all the time. */
767 cris_evaluate_flags (dc
);
773 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
777 dc
->flags_uptodate
= 0;
780 static inline void cris_update_cc_x(DisasContext
*dc
)
782 /* Save the x flag state at the time of the cc snapshot. */
783 if (dc
->flagx_known
) {
784 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
))
786 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
787 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
790 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
791 dc
->cc_x_uptodate
= 1;
795 /* Update cc prior to executing ALU op. Needs source operands untouched. */
796 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
797 TCGv dst
, TCGv src
, int size
)
800 cris_update_cc_op(dc
, op
, size
);
801 tcg_gen_mov_tl(cc_src
, src
);
810 tcg_gen_mov_tl(cc_dest
, dst
);
812 cris_update_cc_x(dc
);
816 /* Update cc after executing ALU op. needs the result. */
817 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
820 if (dc
->cc_size
== 4 &&
821 (dc
->cc_op
== CC_OP_SUB
822 || dc
->cc_op
== CC_OP_ADD
))
824 tcg_gen_mov_tl(cc_result
, res
);
828 /* Returns one if the write back stage should execute. */
829 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
830 TCGv dst
, TCGv a
, TCGv b
, int size
)
832 /* Emit the ALU insns. */
836 tcg_gen_add_tl(dst
, a
, b
);
837 /* Extended arithmetics. */
838 t_gen_addx_carry(dc
, dst
);
841 tcg_gen_add_tl(dst
, a
, b
);
842 t_gen_add_flag(dst
, 0); /* C_FLAG. */
845 tcg_gen_add_tl(dst
, a
, b
);
846 t_gen_add_flag(dst
, 8); /* R_FLAG. */
849 tcg_gen_sub_tl(dst
, a
, b
);
850 /* Extended arithmetics. */
851 t_gen_subx_carry(dc
, dst
);
854 tcg_gen_mov_tl(dst
, b
);
857 tcg_gen_or_tl(dst
, a
, b
);
860 tcg_gen_and_tl(dst
, a
, b
);
863 tcg_gen_xor_tl(dst
, a
, b
);
866 t_gen_lsl(dst
, a
, b
);
869 t_gen_lsr(dst
, a
, b
);
872 t_gen_asr(dst
, a
, b
);
875 tcg_gen_neg_tl(dst
, b
);
876 /* Extended arithmetics. */
877 t_gen_subx_carry(dc
, dst
);
880 t_gen_lz_i32(dst
, b
);
883 t_gen_btst(dst
, a
, b
);
886 t_gen_muls(dst
, cpu_PR
[PR_MOF
], a
, b
);
889 t_gen_mulu(dst
, cpu_PR
[PR_MOF
], a
, b
);
892 t_gen_cris_dstep(dst
, a
, b
);
897 l1
= gen_new_label();
898 tcg_gen_mov_tl(dst
, a
);
899 tcg_gen_brcond_tl(TCG_COND_LEU
, a
, b
, l1
);
900 tcg_gen_mov_tl(dst
, b
);
905 tcg_gen_sub_tl(dst
, a
, b
);
906 /* Extended arithmetics. */
907 t_gen_subx_carry(dc
, dst
);
910 fprintf (logfile
, "illegal ALU op.\n");
916 tcg_gen_andi_tl(dst
, dst
, 0xff);
918 tcg_gen_andi_tl(dst
, dst
, 0xffff);
921 static void cris_alu(DisasContext
*dc
, int op
,
922 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
929 if (op
== CC_OP_BOUND
|| op
== CC_OP_BTST
)
930 tmp
= tcg_temp_local_new(TCG_TYPE_TL
);
932 if (op
== CC_OP_CMP
) {
933 tmp
= tcg_temp_new(TCG_TYPE_TL
);
935 } else if (size
== 4) {
939 tmp
= tcg_temp_new(TCG_TYPE_TL
);
942 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
943 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
944 cris_update_result(dc
, tmp
);
949 tcg_gen_andi_tl(d
, d
, ~0xff);
951 tcg_gen_andi_tl(d
, d
, ~0xffff);
952 tcg_gen_or_tl(d
, d
, tmp
);
958 static int arith_cc(DisasContext
*dc
)
962 case CC_OP_ADDC
: return 1;
963 case CC_OP_ADD
: return 1;
964 case CC_OP_SUB
: return 1;
965 case CC_OP_DSTEP
: return 1;
966 case CC_OP_LSL
: return 1;
967 case CC_OP_LSR
: return 1;
968 case CC_OP_ASR
: return 1;
969 case CC_OP_CMP
: return 1;
970 case CC_OP_NEG
: return 1;
971 case CC_OP_OR
: return 1;
972 case CC_OP_XOR
: return 1;
973 case CC_OP_MULU
: return 1;
974 case CC_OP_MULS
: return 1;
982 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
984 int arith_opt
, move_opt
;
986 /* TODO: optimize more condition codes. */
989 * If the flags are live, we've gotta look into the bits of CCS.
990 * Otherwise, if we just did an arithmetic operation we try to
991 * evaluate the condition code faster.
993 * When this function is done, T0 should be non-zero if the condition
996 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
997 move_opt
= (dc
->cc_op
== CC_OP_MOVE
) && dc
->flags_uptodate
;
1000 if (arith_opt
|| move_opt
) {
1001 /* If cc_result is zero, T0 should be
1002 non-zero otherwise T0 should be zero. */
1004 l1
= gen_new_label();
1005 tcg_gen_movi_tl(cc
, 0);
1006 tcg_gen_brcondi_tl(TCG_COND_NE
, cc_result
,
1008 tcg_gen_movi_tl(cc
, 1);
1012 cris_evaluate_flags(dc
);
1014 cpu_PR
[PR_CCS
], Z_FLAG
);
1018 if (arith_opt
|| move_opt
)
1019 tcg_gen_mov_tl(cc
, cc_result
);
1021 cris_evaluate_flags(dc
);
1022 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
1024 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
1028 cris_evaluate_flags(dc
);
1029 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
1032 cris_evaluate_flags(dc
);
1033 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
1034 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
1037 cris_evaluate_flags(dc
);
1038 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
1041 cris_evaluate_flags(dc
);
1042 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
1044 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
1047 if (arith_opt
|| move_opt
) {
1050 if (dc
->cc_size
== 1)
1052 else if (dc
->cc_size
== 2)
1055 tcg_gen_shri_tl(cc
, cc_result
, bits
);
1056 tcg_gen_xori_tl(cc
, cc
, 1);
1058 cris_evaluate_flags(dc
);
1059 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
1061 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1065 if (arith_opt
|| move_opt
) {
1068 if (dc
->cc_size
== 1)
1070 else if (dc
->cc_size
== 2)
1073 tcg_gen_shri_tl(cc
, cc_result
, 31);
1076 cris_evaluate_flags(dc
);
1077 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
1082 cris_evaluate_flags(dc
);
1083 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
1087 cris_evaluate_flags(dc
);
1091 tmp
= tcg_temp_new(TCG_TYPE_TL
);
1092 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
1094 /* Overlay the C flag on top of the Z. */
1095 tcg_gen_shli_tl(cc
, tmp
, 2);
1096 tcg_gen_and_tl(cc
, tmp
, cc
);
1097 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
1103 cris_evaluate_flags(dc
);
1104 /* Overlay the V flag on top of the N. */
1105 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1107 cpu_PR
[PR_CCS
], cc
);
1108 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1109 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
1112 cris_evaluate_flags(dc
);
1113 /* Overlay the V flag on top of the N. */
1114 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1116 cpu_PR
[PR_CCS
], cc
);
1117 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1120 cris_evaluate_flags(dc
);
1124 n
= tcg_temp_new(TCG_TYPE_TL
);
1125 z
= tcg_temp_new(TCG_TYPE_TL
);
1127 /* To avoid a shift we overlay everything on
1129 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1130 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1132 tcg_gen_xori_tl(z
, z
, 2);
1134 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1135 tcg_gen_xori_tl(n
, n
, 2);
1136 tcg_gen_and_tl(cc
, z
, n
);
1137 tcg_gen_andi_tl(cc
, cc
, 2);
1144 cris_evaluate_flags(dc
);
1148 n
= tcg_temp_new(TCG_TYPE_TL
);
1149 z
= tcg_temp_new(TCG_TYPE_TL
);
1151 /* To avoid a shift we overlay everything on
1153 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1154 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1156 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1157 tcg_gen_or_tl(cc
, z
, n
);
1158 tcg_gen_andi_tl(cc
, cc
, 2);
1165 cris_evaluate_flags(dc
);
1166 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1169 tcg_gen_movi_tl(cc
, 1);
1177 static void cris_store_direct_jmp(DisasContext
*dc
)
1179 /* Store the direct jmp state into the cpu-state. */
1180 if (dc
->jmp
== JMP_DIRECT
) {
1181 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1182 tcg_gen_movi_tl(env_btaken
, 1);
1186 static void cris_prepare_cc_branch (DisasContext
*dc
,
1187 int offset
, int cond
)
1189 /* This helps us re-schedule the micro-code to insns in delay-slots
1190 before the actual jump. */
1191 dc
->delayed_branch
= 2;
1192 dc
->jmp_pc
= dc
->pc
+ offset
;
1196 dc
->jmp
= JMP_INDIRECT
;
1197 gen_tst_cc (dc
, env_btaken
, cond
);
1198 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1200 /* Allow chaining. */
1201 dc
->jmp
= JMP_DIRECT
;
1206 /* jumps, when the dest is in a live reg for example. Direct should be set
1207 when the dest addr is constant to allow tb chaining. */
1208 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1210 /* This helps us re-schedule the micro-code to insns in delay-slots
1211 before the actual jump. */
1212 dc
->delayed_branch
= 2;
1214 if (type
== JMP_INDIRECT
)
1215 tcg_gen_movi_tl(env_btaken
, 1);
1218 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1219 unsigned int size
, int sign
)
1221 int mem_index
= cpu_mmu_index(dc
->env
);
1223 /* If we get a fault on a delayslot we must keep the jmp state in
1224 the cpu-state to be able to re-execute the jmp. */
1225 if (dc
->delayed_branch
== 1)
1226 cris_store_direct_jmp(dc
);
1230 tcg_gen_qemu_ld8s(dst
, addr
, mem_index
);
1232 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
1234 else if (size
== 2) {
1236 tcg_gen_qemu_ld16s(dst
, addr
, mem_index
);
1238 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
1240 else if (size
== 4) {
1241 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
1243 else if (size
== 8) {
1244 tcg_gen_qemu_ld64(dst
, addr
, mem_index
);
1248 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1251 int mem_index
= cpu_mmu_index(dc
->env
);
1253 /* If we get a fault on a delayslot we must keep the jmp state in
1254 the cpu-state to be able to re-execute the jmp. */
1255 if (dc
->delayed_branch
== 1)
1256 cris_store_direct_jmp(dc
);
1259 /* Conditional writes. We only support the kind were X and P are known
1260 at translation time. */
1261 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1263 cris_evaluate_flags(dc
);
1264 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1269 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1271 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1273 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1275 if (dc
->flagx_known
&& dc
->flags_x
) {
1276 cris_evaluate_flags(dc
);
1277 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1281 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1284 tcg_gen_ext8s_i32(d
, s
);
1286 tcg_gen_ext16s_i32(d
, s
);
1287 else if(GET_TCGV(d
) != GET_TCGV(s
))
1288 tcg_gen_mov_tl(d
, s
);
1291 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1294 tcg_gen_ext8u_i32(d
, s
);
1296 tcg_gen_ext16u_i32(d
, s
);
1297 else if (GET_TCGV(d
) != GET_TCGV(s
))
1298 tcg_gen_mov_tl(d
, s
);
1302 static char memsize_char(int size
)
1306 case 1: return 'b'; break;
1307 case 2: return 'w'; break;
1308 case 4: return 'd'; break;
1316 static inline unsigned int memsize_z(DisasContext
*dc
)
1318 return dc
->zsize
+ 1;
1321 static inline unsigned int memsize_zz(DisasContext
*dc
)
1332 static inline void do_postinc (DisasContext
*dc
, int size
)
1335 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1338 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1339 int size
, int s_ext
, TCGv dst
)
1342 t_gen_sext(dst
, cpu_R
[rs
], size
);
1344 t_gen_zext(dst
, cpu_R
[rs
], size
);
1347 /* Prepare T0 and T1 for a register alu operation.
1348 s_ext decides if the operand1 should be sign-extended or zero-extended when
1350 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1351 int size
, int s_ext
, TCGv dst
, TCGv src
)
1353 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1356 t_gen_sext(dst
, cpu_R
[rd
], size
);
1358 t_gen_zext(dst
, cpu_R
[rd
], size
);
1361 static int dec_prep_move_m(DisasContext
*dc
, int s_ext
, int memsize
,
1364 unsigned int rs
, rd
;
1371 is_imm
= rs
== 15 && dc
->postinc
;
1373 /* Load [$rs] onto T1. */
1375 insn_len
= 2 + memsize
;
1382 imm
= ldsb_code(dc
->pc
+ 2);
1384 imm
= ldsw_code(dc
->pc
+ 2);
1387 imm
= ldub_code(dc
->pc
+ 2);
1389 imm
= lduw_code(dc
->pc
+ 2);
1392 imm
= ldl_code(dc
->pc
+ 2);
1394 tcg_gen_movi_tl(dst
, imm
);
1397 cris_flush_cc_state(dc
);
1398 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1400 t_gen_sext(dst
, dst
, memsize
);
1402 t_gen_zext(dst
, dst
, memsize
);
1407 /* Prepare T0 and T1 for a memory + alu operation.
1408 s_ext decides if the operand1 should be sign-extended or zero-extended when
1410 static int dec_prep_alu_m(DisasContext
*dc
, int s_ext
, int memsize
,
1415 insn_len
= dec_prep_move_m(dc
, s_ext
, memsize
, src
);
1416 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1421 static const char *cc_name(int cc
)
1423 static const char *cc_names
[16] = {
1424 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1425 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1428 return cc_names
[cc
];
1432 /* Start of insn decoders. */
1434 static unsigned int dec_bccq(DisasContext
*dc
)
1438 uint32_t cond
= dc
->op2
;
1441 offset
= EXTRACT_FIELD (dc
->ir
, 1, 7);
1442 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1445 offset
|= sign
<< 8;
1447 offset
= sign_extend(offset
, 8);
1449 DIS(fprintf (logfile
, "b%s %x\n", cc_name(cond
), dc
->pc
+ offset
));
1451 /* op2 holds the condition-code. */
1452 cris_cc_mask(dc
, 0);
1453 cris_prepare_cc_branch (dc
, offset
, cond
);
1456 static unsigned int dec_addoq(DisasContext
*dc
)
1460 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1461 imm
= sign_extend(dc
->op1
, 7);
1463 DIS(fprintf (logfile
, "addoq %d, $r%u\n", imm
, dc
->op2
));
1464 cris_cc_mask(dc
, 0);
1465 /* Fetch register operand, */
1466 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1470 static unsigned int dec_addq(DisasContext
*dc
)
1472 DIS(fprintf (logfile
, "addq %u, $r%u\n", dc
->op1
, dc
->op2
));
1474 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1476 cris_cc_mask(dc
, CC_MASK_NZVC
);
1478 cris_alu(dc
, CC_OP_ADD
,
1479 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1482 static unsigned int dec_moveq(DisasContext
*dc
)
1486 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1487 imm
= sign_extend(dc
->op1
, 5);
1488 DIS(fprintf (logfile
, "moveq %d, $r%u\n", imm
, dc
->op2
));
1490 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tcg_const_tl(imm
));
1493 static unsigned int dec_subq(DisasContext
*dc
)
1495 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1497 DIS(fprintf (logfile
, "subq %u, $r%u\n", dc
->op1
, dc
->op2
));
1499 cris_cc_mask(dc
, CC_MASK_NZVC
);
1500 cris_alu(dc
, CC_OP_SUB
,
1501 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1504 static unsigned int dec_cmpq(DisasContext
*dc
)
1507 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1508 imm
= sign_extend(dc
->op1
, 5);
1510 DIS(fprintf (logfile
, "cmpq %d, $r%d\n", imm
, dc
->op2
));
1511 cris_cc_mask(dc
, CC_MASK_NZVC
);
1513 cris_alu(dc
, CC_OP_CMP
,
1514 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1517 static unsigned int dec_andq(DisasContext
*dc
)
1520 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1521 imm
= sign_extend(dc
->op1
, 5);
1523 DIS(fprintf (logfile
, "andq %d, $r%d\n", imm
, dc
->op2
));
1524 cris_cc_mask(dc
, CC_MASK_NZ
);
1526 cris_alu(dc
, CC_OP_AND
,
1527 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1530 static unsigned int dec_orq(DisasContext
*dc
)
1533 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1534 imm
= sign_extend(dc
->op1
, 5);
1535 DIS(fprintf (logfile
, "orq %d, $r%d\n", imm
, dc
->op2
));
1536 cris_cc_mask(dc
, CC_MASK_NZ
);
1538 cris_alu(dc
, CC_OP_OR
,
1539 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1542 static unsigned int dec_btstq(DisasContext
*dc
)
1545 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1546 DIS(fprintf (logfile
, "btstq %u, $r%d\n", dc
->op1
, dc
->op2
));
1548 cris_cc_mask(dc
, CC_MASK_NZ
);
1549 l0
= tcg_temp_local_new(TCG_TYPE_TL
);
1550 cris_alu(dc
, CC_OP_BTST
,
1551 l0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1552 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1553 t_gen_mov_preg_TN(dc
, PR_CCS
, l0
);
1554 dc
->flags_uptodate
= 1;
1558 static unsigned int dec_asrq(DisasContext
*dc
)
1560 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1561 DIS(fprintf (logfile
, "asrq %u, $r%d\n", dc
->op1
, dc
->op2
));
1562 cris_cc_mask(dc
, CC_MASK_NZ
);
1564 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1565 cris_alu(dc
, CC_OP_MOVE
,
1567 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1570 static unsigned int dec_lslq(DisasContext
*dc
)
1572 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1573 DIS(fprintf (logfile
, "lslq %u, $r%d\n", dc
->op1
, dc
->op2
));
1575 cris_cc_mask(dc
, CC_MASK_NZ
);
1577 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1579 cris_alu(dc
, CC_OP_MOVE
,
1581 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1584 static unsigned int dec_lsrq(DisasContext
*dc
)
1586 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1587 DIS(fprintf (logfile
, "lsrq %u, $r%d\n", dc
->op1
, dc
->op2
));
1589 cris_cc_mask(dc
, CC_MASK_NZ
);
1591 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1592 cris_alu(dc
, CC_OP_MOVE
,
1594 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1598 static unsigned int dec_move_r(DisasContext
*dc
)
1600 int size
= memsize_zz(dc
);
1602 DIS(fprintf (logfile
, "move.%c $r%u, $r%u\n",
1603 memsize_char(size
), dc
->op1
, dc
->op2
));
1605 cris_cc_mask(dc
, CC_MASK_NZ
);
1607 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1608 cris_cc_mask(dc
, CC_MASK_NZ
);
1609 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1610 cris_update_cc_x(dc
);
1611 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1616 t0
= tcg_temp_new(TCG_TYPE_TL
);
1617 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1618 cris_alu(dc
, CC_OP_MOVE
,
1620 cpu_R
[dc
->op2
], t0
, size
);
1626 static unsigned int dec_scc_r(DisasContext
*dc
)
1630 DIS(fprintf (logfile
, "s%s $r%u\n",
1631 cc_name(cond
), dc
->op1
));
1637 gen_tst_cc (dc
, cpu_R
[dc
->op1
], cond
);
1638 l1
= gen_new_label();
1639 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_R
[dc
->op1
], 0, l1
);
1640 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1644 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1646 cris_cc_mask(dc
, 0);
1650 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1653 t
[0] = cpu_R
[dc
->op2
];
1654 t
[1] = cpu_R
[dc
->op1
];
1656 t
[0] = tcg_temp_new(TCG_TYPE_TL
);
1657 t
[1] = tcg_temp_new(TCG_TYPE_TL
);
1661 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1664 tcg_temp_free(t
[0]);
1665 tcg_temp_free(t
[1]);
1669 static unsigned int dec_and_r(DisasContext
*dc
)
1672 int size
= memsize_zz(dc
);
1674 DIS(fprintf (logfile
, "and.%c $r%u, $r%u\n",
1675 memsize_char(size
), dc
->op1
, dc
->op2
));
1677 cris_cc_mask(dc
, CC_MASK_NZ
);
1679 cris_alu_alloc_temps(dc
, size
, t
);
1680 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1681 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1682 cris_alu_free_temps(dc
, size
, t
);
1686 static unsigned int dec_lz_r(DisasContext
*dc
)
1689 DIS(fprintf (logfile
, "lz $r%u, $r%u\n",
1691 cris_cc_mask(dc
, CC_MASK_NZ
);
1692 t0
= tcg_temp_new(TCG_TYPE_TL
);
1693 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1694 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1699 static unsigned int dec_lsl_r(DisasContext
*dc
)
1702 int size
= memsize_zz(dc
);
1704 DIS(fprintf (logfile
, "lsl.%c $r%u, $r%u\n",
1705 memsize_char(size
), dc
->op1
, dc
->op2
));
1707 cris_cc_mask(dc
, CC_MASK_NZ
);
1708 cris_alu_alloc_temps(dc
, size
, t
);
1709 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1710 tcg_gen_andi_tl(t
[1], t
[1], 63);
1711 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1712 cris_alu_alloc_temps(dc
, size
, t
);
1716 static unsigned int dec_lsr_r(DisasContext
*dc
)
1719 int size
= memsize_zz(dc
);
1721 DIS(fprintf (logfile
, "lsr.%c $r%u, $r%u\n",
1722 memsize_char(size
), dc
->op1
, dc
->op2
));
1724 cris_cc_mask(dc
, CC_MASK_NZ
);
1725 cris_alu_alloc_temps(dc
, size
, t
);
1726 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1727 tcg_gen_andi_tl(t
[1], t
[1], 63);
1728 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1729 cris_alu_free_temps(dc
, size
, t
);
1733 static unsigned int dec_asr_r(DisasContext
*dc
)
1736 int size
= memsize_zz(dc
);
1738 DIS(fprintf (logfile
, "asr.%c $r%u, $r%u\n",
1739 memsize_char(size
), dc
->op1
, dc
->op2
));
1741 cris_cc_mask(dc
, CC_MASK_NZ
);
1742 cris_alu_alloc_temps(dc
, size
, t
);
1743 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1744 tcg_gen_andi_tl(t
[1], t
[1], 63);
1745 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1746 cris_alu_free_temps(dc
, size
, t
);
1750 static unsigned int dec_muls_r(DisasContext
*dc
)
1753 int size
= memsize_zz(dc
);
1755 DIS(fprintf (logfile
, "muls.%c $r%u, $r%u\n",
1756 memsize_char(size
), dc
->op1
, dc
->op2
));
1757 cris_cc_mask(dc
, CC_MASK_NZV
);
1758 cris_alu_alloc_temps(dc
, size
, t
);
1759 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1761 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1762 cris_alu_free_temps(dc
, size
, t
);
1766 static unsigned int dec_mulu_r(DisasContext
*dc
)
1769 int size
= memsize_zz(dc
);
1771 DIS(fprintf (logfile
, "mulu.%c $r%u, $r%u\n",
1772 memsize_char(size
), dc
->op1
, dc
->op2
));
1773 cris_cc_mask(dc
, CC_MASK_NZV
);
1774 cris_alu_alloc_temps(dc
, size
, t
);
1775 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1777 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1778 cris_alu_alloc_temps(dc
, size
, t
);
1783 static unsigned int dec_dstep_r(DisasContext
*dc
)
1785 DIS(fprintf (logfile
, "dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
));
1786 cris_cc_mask(dc
, CC_MASK_NZ
);
1787 cris_alu(dc
, CC_OP_DSTEP
,
1788 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1792 static unsigned int dec_xor_r(DisasContext
*dc
)
1795 int size
= memsize_zz(dc
);
1796 DIS(fprintf (logfile
, "xor.%c $r%u, $r%u\n",
1797 memsize_char(size
), dc
->op1
, dc
->op2
));
1798 BUG_ON(size
!= 4); /* xor is dword. */
1799 cris_cc_mask(dc
, CC_MASK_NZ
);
1800 cris_alu_alloc_temps(dc
, size
, t
);
1801 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1803 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1804 cris_alu_free_temps(dc
, size
, t
);
1808 static unsigned int dec_bound_r(DisasContext
*dc
)
1811 int size
= memsize_zz(dc
);
1812 DIS(fprintf (logfile
, "bound.%c $r%u, $r%u\n",
1813 memsize_char(size
), dc
->op1
, dc
->op2
));
1814 cris_cc_mask(dc
, CC_MASK_NZ
);
1815 l0
= tcg_temp_local_new(TCG_TYPE_TL
);
1816 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1817 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1822 static unsigned int dec_cmp_r(DisasContext
*dc
)
1825 int size
= memsize_zz(dc
);
1826 DIS(fprintf (logfile
, "cmp.%c $r%u, $r%u\n",
1827 memsize_char(size
), dc
->op1
, dc
->op2
));
1828 cris_cc_mask(dc
, CC_MASK_NZVC
);
1829 cris_alu_alloc_temps(dc
, size
, t
);
1830 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1832 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1833 cris_alu_free_temps(dc
, size
, t
);
1837 static unsigned int dec_abs_r(DisasContext
*dc
)
1841 DIS(fprintf (logfile
, "abs $r%u, $r%u\n",
1843 cris_cc_mask(dc
, CC_MASK_NZ
);
1845 t0
= tcg_temp_new(TCG_TYPE_TL
);
1846 tcg_gen_sari_tl(t0
, cpu_R
[dc
->op1
], 31);
1847 tcg_gen_xor_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
);
1848 tcg_gen_sub_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
);
1851 cris_alu(dc
, CC_OP_MOVE
,
1852 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1856 static unsigned int dec_add_r(DisasContext
*dc
)
1859 int size
= memsize_zz(dc
);
1860 DIS(fprintf (logfile
, "add.%c $r%u, $r%u\n",
1861 memsize_char(size
), dc
->op1
, dc
->op2
));
1862 cris_cc_mask(dc
, CC_MASK_NZVC
);
1863 cris_alu_alloc_temps(dc
, size
, t
);
1864 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1866 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1867 cris_alu_free_temps(dc
, size
, t
);
1871 static unsigned int dec_addc_r(DisasContext
*dc
)
1873 DIS(fprintf (logfile
, "addc $r%u, $r%u\n",
1875 cris_evaluate_flags(dc
);
1876 cris_cc_mask(dc
, CC_MASK_NZVC
);
1877 cris_alu(dc
, CC_OP_ADDC
,
1878 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1882 static unsigned int dec_mcp_r(DisasContext
*dc
)
1884 DIS(fprintf (logfile
, "mcp $p%u, $r%u\n",
1886 cris_evaluate_flags(dc
);
1887 cris_cc_mask(dc
, CC_MASK_RNZV
);
1888 cris_alu(dc
, CC_OP_MCP
,
1889 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1894 static char * swapmode_name(int mode
, char *modename
) {
1897 modename
[i
++] = 'n';
1899 modename
[i
++] = 'w';
1901 modename
[i
++] = 'b';
1903 modename
[i
++] = 'r';
1909 static unsigned int dec_swap_r(DisasContext
*dc
)
1915 DIS(fprintf (logfile
, "swap%s $r%u\n",
1916 swapmode_name(dc
->op2
, modename
), dc
->op1
));
1918 cris_cc_mask(dc
, CC_MASK_NZ
);
1919 t0
= tcg_temp_new(TCG_TYPE_TL
);
1920 t_gen_mov_TN_reg(t0
, dc
->op1
);
1922 tcg_gen_not_tl(t0
, t0
);
1924 t_gen_swapw(t0
, t0
);
1926 t_gen_swapb(t0
, t0
);
1928 t_gen_swapr(t0
, t0
);
1929 cris_alu(dc
, CC_OP_MOVE
,
1930 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1935 static unsigned int dec_or_r(DisasContext
*dc
)
1938 int size
= memsize_zz(dc
);
1939 DIS(fprintf (logfile
, "or.%c $r%u, $r%u\n",
1940 memsize_char(size
), dc
->op1
, dc
->op2
));
1941 cris_cc_mask(dc
, CC_MASK_NZ
);
1942 cris_alu_alloc_temps(dc
, size
, t
);
1943 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1944 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1945 cris_alu_free_temps(dc
, size
, t
);
1949 static unsigned int dec_addi_r(DisasContext
*dc
)
1952 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u\n",
1953 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1954 cris_cc_mask(dc
, 0);
1955 t0
= tcg_temp_new(TCG_TYPE_TL
);
1956 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1957 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1962 static unsigned int dec_addi_acr(DisasContext
*dc
)
1965 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u, $acr\n",
1966 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1967 cris_cc_mask(dc
, 0);
1968 t0
= tcg_temp_new(TCG_TYPE_TL
);
1969 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1970 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1975 static unsigned int dec_neg_r(DisasContext
*dc
)
1978 int size
= memsize_zz(dc
);
1979 DIS(fprintf (logfile
, "neg.%c $r%u, $r%u\n",
1980 memsize_char(size
), dc
->op1
, dc
->op2
));
1981 cris_cc_mask(dc
, CC_MASK_NZVC
);
1982 cris_alu_alloc_temps(dc
, size
, t
);
1983 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1985 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1986 cris_alu_free_temps(dc
, size
, t
);
1990 static unsigned int dec_btst_r(DisasContext
*dc
)
1993 DIS(fprintf (logfile
, "btst $r%u, $r%u\n",
1995 cris_cc_mask(dc
, CC_MASK_NZ
);
1997 l0
= tcg_temp_local_new(TCG_TYPE_TL
);
1998 cris_alu(dc
, CC_OP_BTST
, l0
, cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1999 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2000 t_gen_mov_preg_TN(dc
, PR_CCS
, l0
);
2001 dc
->flags_uptodate
= 1;
2006 static unsigned int dec_sub_r(DisasContext
*dc
)
2009 int size
= memsize_zz(dc
);
2010 DIS(fprintf (logfile
, "sub.%c $r%u, $r%u\n",
2011 memsize_char(size
), dc
->op1
, dc
->op2
));
2012 cris_cc_mask(dc
, CC_MASK_NZVC
);
2013 cris_alu_alloc_temps(dc
, size
, t
);
2014 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
2015 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
2016 cris_alu_free_temps(dc
, size
, t
);
2020 /* Zero extension. From size to dword. */
2021 static unsigned int dec_movu_r(DisasContext
*dc
)
2024 int size
= memsize_z(dc
);
2025 DIS(fprintf (logfile
, "movu.%c $r%u, $r%u\n",
2029 cris_cc_mask(dc
, CC_MASK_NZ
);
2030 t0
= tcg_temp_new(TCG_TYPE_TL
);
2031 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
2032 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2037 /* Sign extension. From size to dword. */
2038 static unsigned int dec_movs_r(DisasContext
*dc
)
2041 int size
= memsize_z(dc
);
2042 DIS(fprintf (logfile
, "movs.%c $r%u, $r%u\n",
2046 cris_cc_mask(dc
, CC_MASK_NZ
);
2047 t0
= tcg_temp_new(TCG_TYPE_TL
);
2048 /* Size can only be qi or hi. */
2049 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2050 cris_alu(dc
, CC_OP_MOVE
,
2051 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
2056 /* zero extension. From size to dword. */
2057 static unsigned int dec_addu_r(DisasContext
*dc
)
2060 int size
= memsize_z(dc
);
2061 DIS(fprintf (logfile
, "addu.%c $r%u, $r%u\n",
2065 cris_cc_mask(dc
, CC_MASK_NZVC
);
2066 t0
= tcg_temp_new(TCG_TYPE_TL
);
2067 /* Size can only be qi or hi. */
2068 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
2069 cris_alu(dc
, CC_OP_ADD
,
2070 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2075 /* Sign extension. From size to dword. */
2076 static unsigned int dec_adds_r(DisasContext
*dc
)
2079 int size
= memsize_z(dc
);
2080 DIS(fprintf (logfile
, "adds.%c $r%u, $r%u\n",
2084 cris_cc_mask(dc
, CC_MASK_NZVC
);
2085 t0
= tcg_temp_new(TCG_TYPE_TL
);
2086 /* Size can only be qi or hi. */
2087 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2088 cris_alu(dc
, CC_OP_ADD
,
2089 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2094 /* Zero extension. From size to dword. */
2095 static unsigned int dec_subu_r(DisasContext
*dc
)
2098 int size
= memsize_z(dc
);
2099 DIS(fprintf (logfile
, "subu.%c $r%u, $r%u\n",
2103 cris_cc_mask(dc
, CC_MASK_NZVC
);
2104 t0
= tcg_temp_new(TCG_TYPE_TL
);
2105 /* Size can only be qi or hi. */
2106 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
2107 cris_alu(dc
, CC_OP_SUB
,
2108 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2113 /* Sign extension. From size to dword. */
2114 static unsigned int dec_subs_r(DisasContext
*dc
)
2117 int size
= memsize_z(dc
);
2118 DIS(fprintf (logfile
, "subs.%c $r%u, $r%u\n",
2122 cris_cc_mask(dc
, CC_MASK_NZVC
);
2123 t0
= tcg_temp_new(TCG_TYPE_TL
);
2124 /* Size can only be qi or hi. */
2125 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2126 cris_alu(dc
, CC_OP_SUB
,
2127 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2132 static unsigned int dec_setclrf(DisasContext
*dc
)
2135 int set
= (~dc
->opcode
>> 2) & 1;
2138 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
2139 | EXTRACT_FIELD(dc
->ir
, 0, 3);
2140 if (set
&& flags
== 0) {
2141 DIS(fprintf (logfile
, "nop\n"));
2143 } else if (!set
&& (flags
& 0x20)) {
2144 DIS(fprintf (logfile
, "di\n"));
2147 DIS(fprintf (logfile
, "%sf %x\n",
2148 set
? "set" : "clr",
2152 /* User space is not allowed to touch these. Silently ignore. */
2153 if (dc
->tb_flags
& U_FLAG
) {
2154 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
2157 if (flags
& X_FLAG
) {
2158 dc
->flagx_known
= 1;
2160 dc
->flags_x
= X_FLAG
;
2165 /* Break the TB if the P flag changes. */
2166 if (flags
& P_FLAG
) {
2167 if ((set
&& !(dc
->tb_flags
& P_FLAG
))
2168 || (!set
&& (dc
->tb_flags
& P_FLAG
))) {
2169 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2170 dc
->is_jmp
= DISAS_UPDATE
;
2171 dc
->cpustate_changed
= 1;
2174 if (flags
& S_FLAG
) {
2175 dc
->cpustate_changed
= 1;
2179 /* Simply decode the flags. */
2180 cris_evaluate_flags (dc
);
2181 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2182 cris_update_cc_x(dc
);
2183 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2186 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2187 /* Enter user mode. */
2188 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2189 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2190 dc
->cpustate_changed
= 1;
2192 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2195 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2197 dc
->flags_uptodate
= 1;
2202 static unsigned int dec_move_rs(DisasContext
*dc
)
2204 DIS(fprintf (logfile
, "move $r%u, $s%u\n", dc
->op1
, dc
->op2
));
2205 cris_cc_mask(dc
, 0);
2206 tcg_gen_helper_0_2(helper_movl_sreg_reg
,
2207 tcg_const_tl(dc
->op2
), tcg_const_tl(dc
->op1
));
2210 static unsigned int dec_move_sr(DisasContext
*dc
)
2212 DIS(fprintf (logfile
, "move $s%u, $r%u\n", dc
->op2
, dc
->op1
));
2213 cris_cc_mask(dc
, 0);
2214 tcg_gen_helper_0_2(helper_movl_reg_sreg
,
2215 tcg_const_tl(dc
->op1
), tcg_const_tl(dc
->op2
));
2219 static unsigned int dec_move_rp(DisasContext
*dc
)
2222 DIS(fprintf (logfile
, "move $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2223 cris_cc_mask(dc
, 0);
2225 t
[0] = tcg_temp_new(TCG_TYPE_TL
);
2226 if (dc
->op2
== PR_CCS
) {
2227 cris_evaluate_flags(dc
);
2228 t_gen_mov_TN_reg(t
[0], dc
->op1
);
2229 if (dc
->tb_flags
& U_FLAG
) {
2230 t
[1] = tcg_temp_new(TCG_TYPE_TL
);
2231 /* User space is not allowed to touch all flags. */
2232 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2233 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2234 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2235 tcg_temp_free(t
[1]);
2239 t_gen_mov_TN_reg(t
[0], dc
->op1
);
2241 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2242 if (dc
->op2
== PR_CCS
) {
2243 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2244 dc
->flags_uptodate
= 1;
2246 tcg_temp_free(t
[0]);
2249 static unsigned int dec_move_pr(DisasContext
*dc
)
2252 DIS(fprintf (logfile
, "move $p%u, $r%u\n", dc
->op1
, dc
->op2
));
2253 cris_cc_mask(dc
, 0);
2255 if (dc
->op2
== PR_CCS
)
2256 cris_evaluate_flags(dc
);
2258 t0
= tcg_temp_new(TCG_TYPE_TL
);
2259 t_gen_mov_TN_preg(t0
, dc
->op2
);
2260 cris_alu(dc
, CC_OP_MOVE
,
2261 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, preg_sizes
[dc
->op2
]);
2266 static unsigned int dec_move_mr(DisasContext
*dc
)
2268 int memsize
= memsize_zz(dc
);
2270 DIS(fprintf (logfile
, "move.%c [$r%u%s, $r%u\n",
2271 memsize_char(memsize
),
2272 dc
->op1
, dc
->postinc
? "+]" : "]",
2276 insn_len
= dec_prep_move_m(dc
, 0, 4, cpu_R
[dc
->op2
]);
2277 cris_cc_mask(dc
, CC_MASK_NZ
);
2278 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2279 cris_update_cc_x(dc
);
2280 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2285 t0
= tcg_temp_new(TCG_TYPE_TL
);
2286 insn_len
= dec_prep_move_m(dc
, 0, memsize
, t0
);
2287 cris_cc_mask(dc
, CC_MASK_NZ
);
2288 cris_alu(dc
, CC_OP_MOVE
,
2289 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2292 do_postinc(dc
, memsize
);
2296 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2298 t
[0] = tcg_temp_new(TCG_TYPE_TL
);
2299 t
[1] = tcg_temp_new(TCG_TYPE_TL
);
2302 static inline void cris_alu_m_free_temps(TCGv
*t
)
2304 tcg_temp_free(t
[0]);
2305 tcg_temp_free(t
[1]);
2308 static unsigned int dec_movs_m(DisasContext
*dc
)
2311 int memsize
= memsize_z(dc
);
2313 DIS(fprintf (logfile
, "movs.%c [$r%u%s, $r%u\n",
2314 memsize_char(memsize
),
2315 dc
->op1
, dc
->postinc
? "+]" : "]",
2318 cris_alu_m_alloc_temps(t
);
2320 insn_len
= dec_prep_alu_m(dc
, 1, memsize
, t
[0], t
[1]);
2321 cris_cc_mask(dc
, CC_MASK_NZ
);
2322 cris_alu(dc
, CC_OP_MOVE
,
2323 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2324 do_postinc(dc
, memsize
);
2325 cris_alu_m_free_temps(t
);
2329 static unsigned int dec_addu_m(DisasContext
*dc
)
2332 int memsize
= memsize_z(dc
);
2334 DIS(fprintf (logfile
, "addu.%c [$r%u%s, $r%u\n",
2335 memsize_char(memsize
),
2336 dc
->op1
, dc
->postinc
? "+]" : "]",
2339 cris_alu_m_alloc_temps(t
);
2341 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2342 cris_cc_mask(dc
, CC_MASK_NZVC
);
2343 cris_alu(dc
, CC_OP_ADD
,
2344 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2345 do_postinc(dc
, memsize
);
2346 cris_alu_m_free_temps(t
);
2350 static unsigned int dec_adds_m(DisasContext
*dc
)
2353 int memsize
= memsize_z(dc
);
2355 DIS(fprintf (logfile
, "adds.%c [$r%u%s, $r%u\n",
2356 memsize_char(memsize
),
2357 dc
->op1
, dc
->postinc
? "+]" : "]",
2360 cris_alu_m_alloc_temps(t
);
2362 insn_len
= dec_prep_alu_m(dc
, 1, memsize
, t
[0], t
[1]);
2363 cris_cc_mask(dc
, CC_MASK_NZVC
);
2364 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2365 do_postinc(dc
, memsize
);
2366 cris_alu_m_free_temps(t
);
2370 static unsigned int dec_subu_m(DisasContext
*dc
)
2373 int memsize
= memsize_z(dc
);
2375 DIS(fprintf (logfile
, "subu.%c [$r%u%s, $r%u\n",
2376 memsize_char(memsize
),
2377 dc
->op1
, dc
->postinc
? "+]" : "]",
2380 cris_alu_m_alloc_temps(t
);
2382 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2383 cris_cc_mask(dc
, CC_MASK_NZVC
);
2384 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2385 do_postinc(dc
, memsize
);
2386 cris_alu_m_free_temps(t
);
2390 static unsigned int dec_subs_m(DisasContext
*dc
)
2393 int memsize
= memsize_z(dc
);
2395 DIS(fprintf (logfile
, "subs.%c [$r%u%s, $r%u\n",
2396 memsize_char(memsize
),
2397 dc
->op1
, dc
->postinc
? "+]" : "]",
2400 cris_alu_m_alloc_temps(t
);
2402 insn_len
= dec_prep_alu_m(dc
, 1, memsize
, t
[0], t
[1]);
2403 cris_cc_mask(dc
, CC_MASK_NZVC
);
2404 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2405 do_postinc(dc
, memsize
);
2406 cris_alu_m_free_temps(t
);
2410 static unsigned int dec_movu_m(DisasContext
*dc
)
2413 int memsize
= memsize_z(dc
);
2416 DIS(fprintf (logfile
, "movu.%c [$r%u%s, $r%u\n",
2417 memsize_char(memsize
),
2418 dc
->op1
, dc
->postinc
? "+]" : "]",
2421 cris_alu_m_alloc_temps(t
);
2422 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2423 cris_cc_mask(dc
, CC_MASK_NZ
);
2424 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2425 do_postinc(dc
, memsize
);
2426 cris_alu_m_free_temps(t
);
2430 static unsigned int dec_cmpu_m(DisasContext
*dc
)
2433 int memsize
= memsize_z(dc
);
2435 DIS(fprintf (logfile
, "cmpu.%c [$r%u%s, $r%u\n",
2436 memsize_char(memsize
),
2437 dc
->op1
, dc
->postinc
? "+]" : "]",
2440 cris_alu_m_alloc_temps(t
);
2441 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2442 cris_cc_mask(dc
, CC_MASK_NZVC
);
2443 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2444 do_postinc(dc
, memsize
);
2445 cris_alu_m_free_temps(t
);
2449 static unsigned int dec_cmps_m(DisasContext
*dc
)
2452 int memsize
= memsize_z(dc
);
2454 DIS(fprintf (logfile
, "cmps.%c [$r%u%s, $r%u\n",
2455 memsize_char(memsize
),
2456 dc
->op1
, dc
->postinc
? "+]" : "]",
2459 cris_alu_m_alloc_temps(t
);
2460 insn_len
= dec_prep_alu_m(dc
, 1, memsize
, t
[0], t
[1]);
2461 cris_cc_mask(dc
, CC_MASK_NZVC
);
2462 cris_alu(dc
, CC_OP_CMP
,
2463 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2465 do_postinc(dc
, memsize
);
2466 cris_alu_m_free_temps(t
);
2470 static unsigned int dec_cmp_m(DisasContext
*dc
)
2473 int memsize
= memsize_zz(dc
);
2475 DIS(fprintf (logfile
, "cmp.%c [$r%u%s, $r%u\n",
2476 memsize_char(memsize
),
2477 dc
->op1
, dc
->postinc
? "+]" : "]",
2480 cris_alu_m_alloc_temps(t
);
2481 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2482 cris_cc_mask(dc
, CC_MASK_NZVC
);
2483 cris_alu(dc
, CC_OP_CMP
,
2484 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2486 do_postinc(dc
, memsize
);
2487 cris_alu_m_free_temps(t
);
2491 static unsigned int dec_test_m(DisasContext
*dc
)
2494 int memsize
= memsize_zz(dc
);
2496 DIS(fprintf (logfile
, "test.%d [$r%u%s] op2=%x\n",
2497 memsize_char(memsize
),
2498 dc
->op1
, dc
->postinc
? "+]" : "]",
2501 cris_evaluate_flags(dc
);
2503 cris_alu_m_alloc_temps(t
);
2504 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2505 cris_cc_mask(dc
, CC_MASK_NZ
);
2506 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2508 cris_alu(dc
, CC_OP_CMP
,
2509 cpu_R
[dc
->op2
], t
[1], tcg_const_tl(0), memsize_zz(dc
));
2510 do_postinc(dc
, memsize
);
2511 cris_alu_m_free_temps(t
);
2515 static unsigned int dec_and_m(DisasContext
*dc
)
2518 int memsize
= memsize_zz(dc
);
2520 DIS(fprintf (logfile
, "and.%d [$r%u%s, $r%u\n",
2521 memsize_char(memsize
),
2522 dc
->op1
, dc
->postinc
? "+]" : "]",
2525 cris_alu_m_alloc_temps(t
);
2526 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2527 cris_cc_mask(dc
, CC_MASK_NZ
);
2528 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2529 do_postinc(dc
, memsize
);
2530 cris_alu_m_free_temps(t
);
2534 static unsigned int dec_add_m(DisasContext
*dc
)
2537 int memsize
= memsize_zz(dc
);
2539 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
2540 memsize_char(memsize
),
2541 dc
->op1
, dc
->postinc
? "+]" : "]",
2544 cris_alu_m_alloc_temps(t
);
2545 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2546 cris_cc_mask(dc
, CC_MASK_NZVC
);
2547 cris_alu(dc
, CC_OP_ADD
,
2548 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2549 do_postinc(dc
, memsize
);
2550 cris_alu_m_free_temps(t
);
2554 static unsigned int dec_addo_m(DisasContext
*dc
)
2557 int memsize
= memsize_zz(dc
);
2559 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
2560 memsize_char(memsize
),
2561 dc
->op1
, dc
->postinc
? "+]" : "]",
2564 cris_alu_m_alloc_temps(t
);
2565 insn_len
= dec_prep_alu_m(dc
, 1, memsize
, t
[0], t
[1]);
2566 cris_cc_mask(dc
, 0);
2567 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2568 do_postinc(dc
, memsize
);
2569 cris_alu_m_free_temps(t
);
2573 static unsigned int dec_bound_m(DisasContext
*dc
)
2576 int memsize
= memsize_zz(dc
);
2578 DIS(fprintf (logfile
, "bound.%d [$r%u%s, $r%u\n",
2579 memsize_char(memsize
),
2580 dc
->op1
, dc
->postinc
? "+]" : "]",
2583 l
[0] = tcg_temp_local_new(TCG_TYPE_TL
);
2584 l
[1] = tcg_temp_local_new(TCG_TYPE_TL
);
2585 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, l
[0], l
[1]);
2586 cris_cc_mask(dc
, CC_MASK_NZ
);
2587 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2588 do_postinc(dc
, memsize
);
2589 tcg_temp_free(l
[0]);
2590 tcg_temp_free(l
[1]);
2594 static unsigned int dec_addc_mr(DisasContext
*dc
)
2598 DIS(fprintf (logfile
, "addc [$r%u%s, $r%u\n",
2599 dc
->op1
, dc
->postinc
? "+]" : "]",
2602 cris_evaluate_flags(dc
);
2603 cris_alu_m_alloc_temps(t
);
2604 insn_len
= dec_prep_alu_m(dc
, 0, 4, t
[0], t
[1]);
2605 cris_cc_mask(dc
, CC_MASK_NZVC
);
2606 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2608 cris_alu_m_free_temps(t
);
2612 static unsigned int dec_sub_m(DisasContext
*dc
)
2615 int memsize
= memsize_zz(dc
);
2617 DIS(fprintf (logfile
, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2618 memsize_char(memsize
),
2619 dc
->op1
, dc
->postinc
? "+]" : "]",
2620 dc
->op2
, dc
->ir
, dc
->zzsize
));
2622 cris_alu_m_alloc_temps(t
);
2623 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2624 cris_cc_mask(dc
, CC_MASK_NZVC
);
2625 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2626 do_postinc(dc
, memsize
);
2627 cris_alu_m_free_temps(t
);
2631 static unsigned int dec_or_m(DisasContext
*dc
)
2634 int memsize
= memsize_zz(dc
);
2636 DIS(fprintf (logfile
, "or.%d [$r%u%s, $r%u pc=%x\n",
2637 memsize_char(memsize
),
2638 dc
->op1
, dc
->postinc
? "+]" : "]",
2641 cris_alu_m_alloc_temps(t
);
2642 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2643 cris_cc_mask(dc
, CC_MASK_NZ
);
2644 cris_alu(dc
, CC_OP_OR
,
2645 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2646 do_postinc(dc
, memsize
);
2647 cris_alu_m_free_temps(t
);
2651 static unsigned int dec_move_mp(DisasContext
*dc
)
2654 int memsize
= memsize_zz(dc
);
2657 DIS(fprintf (logfile
, "move.%c [$r%u%s, $p%u\n",
2658 memsize_char(memsize
),
2660 dc
->postinc
? "+]" : "]",
2663 cris_alu_m_alloc_temps(t
);
2664 insn_len
= dec_prep_alu_m(dc
, 0, memsize
, t
[0], t
[1]);
2665 cris_cc_mask(dc
, 0);
2666 if (dc
->op2
== PR_CCS
) {
2667 cris_evaluate_flags(dc
);
2668 if (dc
->tb_flags
& U_FLAG
) {
2669 /* User space is not allowed to touch all flags. */
2670 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2671 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2672 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2676 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2678 do_postinc(dc
, memsize
);
2679 cris_alu_m_free_temps(t
);
2683 static unsigned int dec_move_pm(DisasContext
*dc
)
2688 memsize
= preg_sizes
[dc
->op2
];
2690 DIS(fprintf (logfile
, "move.%c $p%u, [$r%u%s\n",
2691 memsize_char(memsize
),
2692 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]"));
2694 /* prepare store. Address in T0, value in T1. */
2695 if (dc
->op2
== PR_CCS
)
2696 cris_evaluate_flags(dc
);
2697 t0
= tcg_temp_new(TCG_TYPE_TL
);
2698 t_gen_mov_TN_preg(t0
, dc
->op2
);
2699 cris_flush_cc_state(dc
);
2700 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2703 cris_cc_mask(dc
, 0);
2705 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2709 static unsigned int dec_movem_mr(DisasContext
*dc
)
2714 int nr
= dc
->op2
+ 1;
2716 DIS(fprintf (logfile
, "movem [$r%u%s, $r%u\n", dc
->op1
,
2717 dc
->postinc
? "+]" : "]", dc
->op2
));
2719 addr
= tcg_temp_new(TCG_TYPE_TL
);
2720 /* There are probably better ways of doing this. */
2721 cris_flush_cc_state(dc
);
2722 for (i
= 0; i
< (nr
>> 1); i
++) {
2723 tmp
[i
] = tcg_temp_new(TCG_TYPE_I64
);
2724 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2725 gen_load(dc
, tmp
[i
], addr
, 8, 0);
2728 tmp
[i
] = tcg_temp_new(TCG_TYPE_I32
);
2729 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2730 gen_load(dc
, tmp
[i
], addr
, 4, 0);
2732 tcg_temp_free(addr
);
2734 for (i
= 0; i
< (nr
>> 1); i
++) {
2735 tcg_gen_trunc_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2736 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2737 tcg_gen_trunc_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2738 tcg_temp_free(tmp
[i
]);
2741 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp
[i
]);
2742 tcg_temp_free(tmp
[i
]);
2745 /* writeback the updated pointer value. */
2747 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2749 /* gen_load might want to evaluate the previous insns flags. */
2750 cris_cc_mask(dc
, 0);
2754 static unsigned int dec_movem_rm(DisasContext
*dc
)
2760 DIS(fprintf (logfile
, "movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2761 dc
->postinc
? "+]" : "]"));
2763 cris_flush_cc_state(dc
);
2765 tmp
= tcg_temp_new(TCG_TYPE_TL
);
2766 addr
= tcg_temp_new(TCG_TYPE_TL
);
2767 tcg_gen_movi_tl(tmp
, 4);
2768 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2769 for (i
= 0; i
<= dc
->op2
; i
++) {
2770 /* Displace addr. */
2771 /* Perform the store. */
2772 gen_store(dc
, addr
, cpu_R
[i
], 4);
2773 tcg_gen_add_tl(addr
, addr
, tmp
);
2776 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2777 cris_cc_mask(dc
, 0);
2779 tcg_temp_free(addr
);
2783 static unsigned int dec_move_rm(DisasContext
*dc
)
2787 memsize
= memsize_zz(dc
);
2789 DIS(fprintf (logfile
, "move.%d $r%u, [$r%u]\n",
2790 memsize
, dc
->op2
, dc
->op1
));
2792 /* prepare store. */
2793 cris_flush_cc_state(dc
);
2794 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2797 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2798 cris_cc_mask(dc
, 0);
2802 static unsigned int dec_lapcq(DisasContext
*dc
)
2804 DIS(fprintf (logfile
, "lapcq %x, $r%u\n",
2805 dc
->pc
+ dc
->op1
*2, dc
->op2
));
2806 cris_cc_mask(dc
, 0);
2807 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2811 static unsigned int dec_lapc_im(DisasContext
*dc
)
2819 cris_cc_mask(dc
, 0);
2820 imm
= ldl_code(dc
->pc
+ 2);
2821 DIS(fprintf (logfile
, "lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
));
2825 t_gen_mov_reg_TN(rd
, tcg_const_tl(pc
));
2829 /* Jump to special reg. */
2830 static unsigned int dec_jump_p(DisasContext
*dc
)
2832 DIS(fprintf (logfile
, "jump $p%u\n", dc
->op2
));
2834 if (dc
->op2
== PR_CCS
)
2835 cris_evaluate_flags(dc
);
2836 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2837 /* rete will often have low bit set to indicate delayslot. */
2838 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2839 cris_cc_mask(dc
, 0);
2840 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2844 /* Jump and save. */
2845 static unsigned int dec_jas_r(DisasContext
*dc
)
2847 DIS(fprintf (logfile
, "jas $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2848 cris_cc_mask(dc
, 0);
2849 /* Store the return address in Pd. */
2850 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2853 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4));
2855 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2859 static unsigned int dec_jas_im(DisasContext
*dc
)
2863 imm
= ldl_code(dc
->pc
+ 2);
2865 DIS(fprintf (logfile
, "jas 0x%x\n", imm
));
2866 cris_cc_mask(dc
, 0);
2867 /* Store the return address in Pd. */
2868 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2871 cris_prepare_jmp(dc
, JMP_DIRECT
);
2875 static unsigned int dec_jasc_im(DisasContext
*dc
)
2879 imm
= ldl_code(dc
->pc
+ 2);
2881 DIS(fprintf (logfile
, "jasc 0x%x\n", imm
));
2882 cris_cc_mask(dc
, 0);
2883 /* Store the return address in Pd. */
2884 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8 + 4));
2887 cris_prepare_jmp(dc
, JMP_DIRECT
);
2891 static unsigned int dec_jasc_r(DisasContext
*dc
)
2893 DIS(fprintf (logfile
, "jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2894 cris_cc_mask(dc
, 0);
2895 /* Store the return address in Pd. */
2896 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2897 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4 + 4));
2898 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2902 static unsigned int dec_bcc_im(DisasContext
*dc
)
2905 uint32_t cond
= dc
->op2
;
2907 offset
= ldsw_code(dc
->pc
+ 2);
2909 DIS(fprintf (logfile
, "b%s %d pc=%x dst=%x\n",
2910 cc_name(cond
), offset
,
2911 dc
->pc
, dc
->pc
+ offset
));
2913 cris_cc_mask(dc
, 0);
2914 /* op2 holds the condition-code. */
2915 cris_prepare_cc_branch (dc
, offset
, cond
);
2919 static unsigned int dec_bas_im(DisasContext
*dc
)
2924 simm
= ldl_code(dc
->pc
+ 2);
2926 DIS(fprintf (logfile
, "bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2927 cris_cc_mask(dc
, 0);
2928 /* Store the return address in Pd. */
2929 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2931 dc
->jmp_pc
= dc
->pc
+ simm
;
2932 cris_prepare_jmp(dc
, JMP_DIRECT
);
2936 static unsigned int dec_basc_im(DisasContext
*dc
)
2939 simm
= ldl_code(dc
->pc
+ 2);
2941 DIS(fprintf (logfile
, "basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2942 cris_cc_mask(dc
, 0);
2943 /* Store the return address in Pd. */
2944 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 12));
2946 dc
->jmp_pc
= dc
->pc
+ simm
;
2947 cris_prepare_jmp(dc
, JMP_DIRECT
);
2951 static unsigned int dec_rfe_etc(DisasContext
*dc
)
2953 cris_cc_mask(dc
, 0);
2955 if (dc
->op2
== 15) /* ignore halt. */
2958 switch (dc
->op2
& 7) {
2961 DIS(fprintf(logfile
, "rfe\n"));
2962 cris_evaluate_flags(dc
);
2963 tcg_gen_helper_0_0(helper_rfe
);
2964 dc
->is_jmp
= DISAS_UPDATE
;
2968 DIS(fprintf(logfile
, "rfn\n"));
2969 cris_evaluate_flags(dc
);
2970 tcg_gen_helper_0_0(helper_rfn
);
2971 dc
->is_jmp
= DISAS_UPDATE
;
2974 DIS(fprintf(logfile
, "break %d\n", dc
->op1
));
2975 cris_evaluate_flags (dc
);
2977 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2979 /* Breaks start at 16 in the exception vector. */
2980 t_gen_mov_env_TN(trap_vector
,
2981 tcg_const_tl(dc
->op1
+ 16));
2982 t_gen_raise_exception(EXCP_BREAK
);
2983 dc
->is_jmp
= DISAS_UPDATE
;
2986 printf ("op2=%x\n", dc
->op2
);
2994 static unsigned int dec_ftag_fidx_d_m(DisasContext
*dc
)
2999 static unsigned int dec_ftag_fidx_i_m(DisasContext
*dc
)
3004 static unsigned int dec_null(DisasContext
*dc
)
3006 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
3007 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
3013 static struct decoder_info
{
3018 unsigned int (*dec
)(DisasContext
*dc
);
3020 /* Order matters here. */
3021 {DEC_MOVEQ
, dec_moveq
},
3022 {DEC_BTSTQ
, dec_btstq
},
3023 {DEC_CMPQ
, dec_cmpq
},
3024 {DEC_ADDOQ
, dec_addoq
},
3025 {DEC_ADDQ
, dec_addq
},
3026 {DEC_SUBQ
, dec_subq
},
3027 {DEC_ANDQ
, dec_andq
},
3029 {DEC_ASRQ
, dec_asrq
},
3030 {DEC_LSLQ
, dec_lslq
},
3031 {DEC_LSRQ
, dec_lsrq
},
3032 {DEC_BCCQ
, dec_bccq
},
3034 {DEC_BCC_IM
, dec_bcc_im
},
3035 {DEC_JAS_IM
, dec_jas_im
},
3036 {DEC_JAS_R
, dec_jas_r
},
3037 {DEC_JASC_IM
, dec_jasc_im
},
3038 {DEC_JASC_R
, dec_jasc_r
},
3039 {DEC_BAS_IM
, dec_bas_im
},
3040 {DEC_BASC_IM
, dec_basc_im
},
3041 {DEC_JUMP_P
, dec_jump_p
},
3042 {DEC_LAPC_IM
, dec_lapc_im
},
3043 {DEC_LAPCQ
, dec_lapcq
},
3045 {DEC_RFE_ETC
, dec_rfe_etc
},
3046 {DEC_ADDC_MR
, dec_addc_mr
},
3048 {DEC_MOVE_MP
, dec_move_mp
},
3049 {DEC_MOVE_PM
, dec_move_pm
},
3050 {DEC_MOVEM_MR
, dec_movem_mr
},
3051 {DEC_MOVEM_RM
, dec_movem_rm
},
3052 {DEC_MOVE_PR
, dec_move_pr
},
3053 {DEC_SCC_R
, dec_scc_r
},
3054 {DEC_SETF
, dec_setclrf
},
3055 {DEC_CLEARF
, dec_setclrf
},
3057 {DEC_MOVE_SR
, dec_move_sr
},
3058 {DEC_MOVE_RP
, dec_move_rp
},
3059 {DEC_SWAP_R
, dec_swap_r
},
3060 {DEC_ABS_R
, dec_abs_r
},
3061 {DEC_LZ_R
, dec_lz_r
},
3062 {DEC_MOVE_RS
, dec_move_rs
},
3063 {DEC_BTST_R
, dec_btst_r
},
3064 {DEC_ADDC_R
, dec_addc_r
},
3066 {DEC_DSTEP_R
, dec_dstep_r
},
3067 {DEC_XOR_R
, dec_xor_r
},
3068 {DEC_MCP_R
, dec_mcp_r
},
3069 {DEC_CMP_R
, dec_cmp_r
},
3071 {DEC_ADDI_R
, dec_addi_r
},
3072 {DEC_ADDI_ACR
, dec_addi_acr
},
3074 {DEC_ADD_R
, dec_add_r
},
3075 {DEC_SUB_R
, dec_sub_r
},
3077 {DEC_ADDU_R
, dec_addu_r
},
3078 {DEC_ADDS_R
, dec_adds_r
},
3079 {DEC_SUBU_R
, dec_subu_r
},
3080 {DEC_SUBS_R
, dec_subs_r
},
3081 {DEC_LSL_R
, dec_lsl_r
},
3083 {DEC_AND_R
, dec_and_r
},
3084 {DEC_OR_R
, dec_or_r
},
3085 {DEC_BOUND_R
, dec_bound_r
},
3086 {DEC_ASR_R
, dec_asr_r
},
3087 {DEC_LSR_R
, dec_lsr_r
},
3089 {DEC_MOVU_R
, dec_movu_r
},
3090 {DEC_MOVS_R
, dec_movs_r
},
3091 {DEC_NEG_R
, dec_neg_r
},
3092 {DEC_MOVE_R
, dec_move_r
},
3094 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
3095 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
3097 {DEC_MULS_R
, dec_muls_r
},
3098 {DEC_MULU_R
, dec_mulu_r
},
3100 {DEC_ADDU_M
, dec_addu_m
},
3101 {DEC_ADDS_M
, dec_adds_m
},
3102 {DEC_SUBU_M
, dec_subu_m
},
3103 {DEC_SUBS_M
, dec_subs_m
},
3105 {DEC_CMPU_M
, dec_cmpu_m
},
3106 {DEC_CMPS_M
, dec_cmps_m
},
3107 {DEC_MOVU_M
, dec_movu_m
},
3108 {DEC_MOVS_M
, dec_movs_m
},
3110 {DEC_CMP_M
, dec_cmp_m
},
3111 {DEC_ADDO_M
, dec_addo_m
},
3112 {DEC_BOUND_M
, dec_bound_m
},
3113 {DEC_ADD_M
, dec_add_m
},
3114 {DEC_SUB_M
, dec_sub_m
},
3115 {DEC_AND_M
, dec_and_m
},
3116 {DEC_OR_M
, dec_or_m
},
3117 {DEC_MOVE_RM
, dec_move_rm
},
3118 {DEC_TEST_M
, dec_test_m
},
3119 {DEC_MOVE_MR
, dec_move_mr
},
3124 static inline unsigned int
3125 cris_decoder(DisasContext
*dc
)
3127 unsigned int insn_len
= 2;
3130 if (unlikely(loglevel
& CPU_LOG_TB_OP
))
3131 tcg_gen_debug_insn_start(dc
->pc
);
3133 /* Load a halfword onto the instruction register. */
3134 dc
->ir
= lduw_code(dc
->pc
);
3136 /* Now decode it. */
3137 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3138 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3139 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3140 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3141 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3142 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3144 /* Large switch for all insns. */
3145 for (i
= 0; i
< sizeof decinfo
/ sizeof decinfo
[0]; i
++) {
3146 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
)
3148 insn_len
= decinfo
[i
].dec(dc
);
3153 #if !defined(CONFIG_USER_ONLY)
3154 /* Single-stepping ? */
3155 if (dc
->tb_flags
& S_FLAG
) {
3158 l1
= gen_new_label();
3159 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3160 /* We treat SPC as a break with an odd trap vector. */
3161 cris_evaluate_flags (dc
);
3162 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(3));
3163 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3164 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3165 t_gen_raise_exception(EXCP_BREAK
);
3172 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
3175 if (env
->nb_breakpoints
> 0) {
3176 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
3177 if (env
->breakpoints
[j
] == dc
->pc
) {
3178 cris_evaluate_flags (dc
);
3179 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3180 t_gen_raise_exception(EXCP_DEBUG
);
3181 dc
->is_jmp
= DISAS_UPDATE
;
3189 * Delay slots on QEMU/CRIS.
3191 * If an exception hits on a delayslot, the core will let ERP (the Exception
3192 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3193 * to give SW a hint that the exception actually hit on the dslot.
3195 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3196 * the core and any jmp to an odd addresses will mask off that lsb. It is
3197 * simply there to let sw know there was an exception on a dslot.
3199 * When the software returns from an exception, the branch will re-execute.
3200 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3201 * and the branch and delayslot dont share pages.
3203 * The TB contaning the branch insn will set up env->btarget and evaluate
3204 * env->btaken. When the translation loop exits we will note that the branch
3205 * sequence is broken and let env->dslot be the size of the branch insn (those
3208 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3209 * set). It will also expect to have env->dslot setup with the size of the
3210 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3211 * will execute the dslot and take the branch, either to btarget or just one
3214 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3215 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3216 * branch and set lsb). Then env->dslot gets cleared so that the exception
3217 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3218 * masked off and we will reexecute the branch insn.
3222 /* generate intermediate code for basic block 'tb'. */
3224 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
3227 uint16_t *gen_opc_end
;
3229 unsigned int insn_len
;
3231 struct DisasContext ctx
;
3232 struct DisasContext
*dc
= &ctx
;
3233 uint32_t next_page_start
;
3241 /* Odd PC indicates that branch is rexecuting due to exception in the
3242 * delayslot, like in real hw.
3244 pc_start
= tb
->pc
& ~1;
3248 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
3250 dc
->is_jmp
= DISAS_NEXT
;
3253 dc
->singlestep_enabled
= env
->singlestep_enabled
;
3254 dc
->flags_uptodate
= 1;
3255 dc
->flagx_known
= 1;
3256 dc
->flags_x
= tb
->flags
& X_FLAG
;
3257 dc
->cc_x_uptodate
= 0;
3261 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3262 dc
->cc_size_uptodate
= -1;
3264 /* Decode TB flags. */
3265 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG
| X_FLAG
);
3266 dc
->delayed_branch
= !!(tb
->flags
& 7);
3267 if (dc
->delayed_branch
)
3268 dc
->jmp
= JMP_INDIRECT
;
3270 dc
->jmp
= JMP_NOJMP
;
3272 dc
->cpustate_changed
= 0;
3274 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3276 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3282 search_pc
, dc
->pc
, dc
->ppc
,
3283 (unsigned long long)tb
->flags
,
3284 env
->btarget
, (unsigned)tb
->flags
& 7,
3286 env
->pregs
[PR_PID
], env
->pregs
[PR_USP
],
3287 env
->regs
[0], env
->regs
[1], env
->regs
[2], env
->regs
[3],
3288 env
->regs
[4], env
->regs
[5], env
->regs
[6], env
->regs
[7],
3289 env
->regs
[8], env
->regs
[9],
3290 env
->regs
[10], env
->regs
[11],
3291 env
->regs
[12], env
->regs
[13],
3292 env
->regs
[14], env
->regs
[15]);
3293 fprintf(logfile
, "--------------\n");
3294 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
3297 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3300 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3302 max_insns
= CF_COUNT_MASK
;
3307 check_breakpoint(env
, dc
);
3310 j
= gen_opc_ptr
- gen_opc_buf
;
3314 gen_opc_instr_start
[lj
++] = 0;
3316 if (dc
->delayed_branch
== 1)
3317 gen_opc_pc
[lj
] = dc
->ppc
| 1;
3319 gen_opc_pc
[lj
] = dc
->pc
;
3320 gen_opc_instr_start
[lj
] = 1;
3321 gen_opc_icount
[lj
] = num_insns
;
3325 DIS(fprintf(logfile
, "%8.8x:\t", dc
->pc
));
3327 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
3331 insn_len
= cris_decoder(dc
);
3335 cris_clear_x_flag(dc
);
3338 /* Check for delayed branches here. If we do it before
3339 actually generating any host code, the simulator will just
3340 loop doing nothing for on this program location. */
3341 if (dc
->delayed_branch
) {
3342 dc
->delayed_branch
--;
3343 if (dc
->delayed_branch
== 0)
3346 t_gen_mov_env_TN(dslot
,
3348 if (dc
->jmp
== JMP_DIRECT
) {
3349 dc
->is_jmp
= DISAS_NEXT
;
3351 t_gen_cc_jmp(env_btarget
,
3352 tcg_const_tl(dc
->pc
));
3353 dc
->is_jmp
= DISAS_JUMP
;
3359 /* If we are rexecuting a branch due to exceptions on
3360 delay slots dont break. */
3361 if (!(tb
->pc
& 1) && env
->singlestep_enabled
)
3363 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3364 && gen_opc_ptr
< gen_opc_end
3365 && (dc
->pc
< next_page_start
)
3366 && num_insns
< max_insns
);
3369 if (dc
->jmp
== JMP_DIRECT
&& !dc
->delayed_branch
)
3372 if (tb
->cflags
& CF_LAST_IO
)
3374 /* Force an update if the per-tb cpu state has changed. */
3375 if (dc
->is_jmp
== DISAS_NEXT
3376 && (dc
->cpustate_changed
|| !dc
->flagx_known
3377 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3378 dc
->is_jmp
= DISAS_UPDATE
;
3379 tcg_gen_movi_tl(env_pc
, npc
);
3381 /* Broken branch+delayslot sequence. */
3382 if (dc
->delayed_branch
== 1) {
3383 /* Set env->dslot to the size of the branch insn. */
3384 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
3385 cris_store_direct_jmp(dc
);
3388 cris_evaluate_flags (dc
);
3390 if (unlikely(env
->singlestep_enabled
)) {
3391 if (dc
->is_jmp
== DISAS_NEXT
)
3392 tcg_gen_movi_tl(env_pc
, npc
);
3393 t_gen_raise_exception(EXCP_DEBUG
);
3395 switch(dc
->is_jmp
) {
3397 gen_goto_tb(dc
, 1, npc
);
3402 /* indicate that the hash table must be used
3403 to find the next TB */
3408 /* nothing more to generate */
3412 gen_icount_end(tb
, num_insns
);
3413 *gen_opc_ptr
= INDEX_op_end
;
3415 j
= gen_opc_ptr
- gen_opc_buf
;
3418 gen_opc_instr_start
[lj
++] = 0;
3420 tb
->size
= dc
->pc
- pc_start
;
3421 tb
->icount
= num_insns
;
3426 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3427 target_disas(logfile
, pc_start
, dc
->pc
- pc_start
, 0);
3428 fprintf(logfile
, "\nisize=%d osize=%zd\n",
3429 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
3435 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
3437 gen_intermediate_code_internal(env
, tb
, 0);
3440 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
3442 gen_intermediate_code_internal(env
, tb
, 1);
3445 void cpu_dump_state (CPUState
*env
, FILE *f
,
3446 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
3455 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3456 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3457 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3459 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3462 for (i
= 0; i
< 16; i
++) {
3463 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
3464 if ((i
+ 1) % 4 == 0)
3465 cpu_fprintf(f
, "\n");
3467 cpu_fprintf(f
, "\nspecial regs:\n");
3468 for (i
= 0; i
< 16; i
++) {
3469 cpu_fprintf(f
, "p%2.2d=%8.8x ", i
, env
->pregs
[i
]);
3470 if ((i
+ 1) % 4 == 0)
3471 cpu_fprintf(f
, "\n");
3473 srs
= env
->pregs
[PR_SRS
];
3474 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3476 for (i
= 0; i
< 16; i
++) {
3477 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3478 i
, env
->sregs
[srs
][i
]);
3479 if ((i
+ 1) % 4 == 0)
3480 cpu_fprintf(f
, "\n");
3483 cpu_fprintf(f
, "\n\n");
3487 CPUCRISState
*cpu_cris_init (const char *cpu_model
)
3490 static int tcg_initialized
= 0;
3493 env
= qemu_mallocz(sizeof(CPUCRISState
));
3500 if (tcg_initialized
)
3503 tcg_initialized
= 1;
3505 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
3506 cc_x
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3507 offsetof(CPUState
, cc_x
), "cc_x");
3508 cc_src
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3509 offsetof(CPUState
, cc_src
), "cc_src");
3510 cc_dest
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3511 offsetof(CPUState
, cc_dest
),
3513 cc_result
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3514 offsetof(CPUState
, cc_result
),
3516 cc_op
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3517 offsetof(CPUState
, cc_op
), "cc_op");
3518 cc_size
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3519 offsetof(CPUState
, cc_size
),
3521 cc_mask
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3522 offsetof(CPUState
, cc_mask
),
3525 env_pc
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3526 offsetof(CPUState
, pc
),
3528 env_btarget
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3529 offsetof(CPUState
, btarget
),
3531 env_btaken
= tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3532 offsetof(CPUState
, btaken
),
3534 for (i
= 0; i
< 16; i
++) {
3535 cpu_R
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3536 offsetof(CPUState
, regs
[i
]),
3539 for (i
= 0; i
< 16; i
++) {
3540 cpu_PR
[i
] = tcg_global_mem_new(TCG_TYPE_TL
, TCG_AREG0
,
3541 offsetof(CPUState
, pregs
[i
]),
3545 TCG_HELPER(helper_raise_exception
);
3546 TCG_HELPER(helper_dump
);
3548 TCG_HELPER(helper_tlb_flush_pid
);
3549 TCG_HELPER(helper_movl_sreg_reg
);
3550 TCG_HELPER(helper_movl_reg_sreg
);
3551 TCG_HELPER(helper_rfe
);
3552 TCG_HELPER(helper_rfn
);
3554 TCG_HELPER(helper_evaluate_flags_muls
);
3555 TCG_HELPER(helper_evaluate_flags_mulu
);
3556 TCG_HELPER(helper_evaluate_flags_mcp
);
3557 TCG_HELPER(helper_evaluate_flags_alu_4
);
3558 TCG_HELPER(helper_evaluate_flags_move_4
);
3559 TCG_HELPER(helper_evaluate_flags_move_2
);
3560 TCG_HELPER(helper_evaluate_flags
);
3561 TCG_HELPER(helper_top_evaluate_flags
);
3565 void cpu_reset (CPUCRISState
*env
)
3567 memset(env
, 0, offsetof(CPUCRISState
, breakpoints
));
3570 env
->pregs
[PR_VR
] = 32;
3571 #if defined(CONFIG_USER_ONLY)
3572 /* start in user mode with interrupts enabled. */
3573 env
->pregs
[PR_CCS
] |= U_FLAG
| I_FLAG
;
3575 env
->pregs
[PR_CCS
] = 0;
3579 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
3580 unsigned long searched_pc
, int pc_pos
, void *puc
)
3582 env
->pc
= gen_opc_pc
[pc_pos
];