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1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29 #include "helper.h"
30 #include "mmu.h"
31 #include "crisv32-decode.h"
32
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define DISAS_CRIS 0
37 #if DISAS_CRIS
38 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
39 #else
40 # define LOG_DIS(...) do { } while (0)
41 #endif
42
43 #define D(x)
44 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
45 #define BUG_ON(x) ({if (x) BUG();})
46
47 #define DISAS_SWI 5
48
49 /* Used by the decoder. */
50 #define EXTRACT_FIELD(src, start, end) \
51 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52
53 #define CC_MASK_NZ 0xc
54 #define CC_MASK_NZV 0xe
55 #define CC_MASK_NZVC 0xf
56 #define CC_MASK_RNZV 0x10e
57
58 static TCGv_ptr cpu_env;
59 static TCGv cpu_R[16];
60 static TCGv cpu_PR[16];
61 static TCGv cc_x;
62 static TCGv cc_src;
63 static TCGv cc_dest;
64 static TCGv cc_result;
65 static TCGv cc_op;
66 static TCGv cc_size;
67 static TCGv cc_mask;
68
69 static TCGv env_btaken;
70 static TCGv env_btarget;
71 static TCGv env_pc;
72
73 #include "gen-icount.h"
74
75 /* This is the state at translation time. */
76 typedef struct DisasContext {
77 CPUCRISState *env;
78 target_ulong pc, ppc;
79
80 /* Decoder. */
81 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
82 uint32_t ir;
83 uint32_t opcode;
84 unsigned int op1;
85 unsigned int op2;
86 unsigned int zsize, zzsize;
87 unsigned int mode;
88 unsigned int postinc;
89
90 unsigned int size;
91 unsigned int src;
92 unsigned int dst;
93 unsigned int cond;
94
95 int update_cc;
96 int cc_op;
97 int cc_size;
98 uint32_t cc_mask;
99
100 int cc_size_uptodate; /* -1 invalid or last written value. */
101
102 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate; /* Wether or not $ccs is uptodate. */
104 int flagx_known; /* Wether or not flags_x has the x flag known at
105 translation time. */
106 int flags_x;
107
108 int clear_x; /* Clear x after this insn? */
109 int clear_prefix; /* Clear prefix after this insn? */
110 int clear_locked_irq; /* Clear the irq lockout. */
111 int cpustate_changed;
112 unsigned int tb_flags; /* tb dependent flags. */
113 int is_jmp;
114
115 #define JMP_NOJMP 0
116 #define JMP_DIRECT 1
117 #define JMP_DIRECT_CC 2
118 #define JMP_INDIRECT 3
119 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
120 uint32_t jmp_pc;
121
122 int delayed_branch;
123
124 struct TranslationBlock *tb;
125 int singlestep_enabled;
126 } DisasContext;
127
128 static void gen_BUG(DisasContext *dc, const char *file, int line)
129 {
130 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
132 cpu_abort(dc->env, "%s:%d\n", file, line);
133 }
134
135 static const char *regnames[] =
136 {
137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
141 };
142 static const char *pregnames[] =
143 {
144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
148 };
149
150 /* We need this table to handle preg-moves with implicit width. */
151 static int preg_sizes[] = {
152 1, /* bz. */
153 1, /* vr. */
154 4, /* pid. */
155 1, /* srs. */
156 2, /* wz. */
157 4, 4, 4,
158 4, 4, 4, 4,
159 4, 4, 4, 4,
160 };
161
162 #define t_gen_mov_TN_env(tn, member) \
163 _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))
164 #define t_gen_mov_env_TN(member, tn) \
165 _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
166
167 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 {
169 if (r < 0 || r > 15)
170 fprintf(stderr, "wrong register read $r%d\n", r);
171 tcg_gen_mov_tl(tn, cpu_R[r]);
172 }
173 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 {
175 if (r < 0 || r > 15)
176 fprintf(stderr, "wrong register write $r%d\n", r);
177 tcg_gen_mov_tl(cpu_R[r], tn);
178 }
179
180 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
181 {
182 if (offset > sizeof (CPUCRISState))
183 fprintf(stderr, "wrong load from env from off=%d\n", offset);
184 tcg_gen_ld_tl(tn, cpu_env, offset);
185 }
186 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
187 {
188 if (offset > sizeof (CPUCRISState))
189 fprintf(stderr, "wrong store to env at off=%d\n", offset);
190 tcg_gen_st_tl(tn, cpu_env, offset);
191 }
192
193 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 {
195 if (r < 0 || r > 15)
196 fprintf(stderr, "wrong register read $p%d\n", r);
197 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
198 tcg_gen_mov_tl(tn, tcg_const_tl(0));
199 else if (r == PR_VR)
200 tcg_gen_mov_tl(tn, tcg_const_tl(32));
201 else
202 tcg_gen_mov_tl(tn, cpu_PR[r]);
203 }
204 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
205 {
206 if (r < 0 || r > 15)
207 fprintf(stderr, "wrong register write $p%d\n", r);
208 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
209 return;
210 else if (r == PR_SRS)
211 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
212 else {
213 if (r == PR_PID)
214 gen_helper_tlb_flush_pid(cpu_env, tn);
215 if (dc->tb_flags & S_FLAG && r == PR_SPC)
216 gen_helper_spc_write(cpu_env, tn);
217 else if (r == PR_CCS)
218 dc->cpustate_changed = 1;
219 tcg_gen_mov_tl(cpu_PR[r], tn);
220 }
221 }
222
223 /* Sign extend at translation time. */
224 static int sign_extend(unsigned int val, unsigned int width)
225 {
226 int sval;
227
228 /* LSL. */
229 val <<= 31 - width;
230 sval = val;
231 /* ASR. */
232 sval >>= 31 - width;
233 return sval;
234 }
235
236 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
237 unsigned int size, unsigned int sign)
238 {
239 int r;
240
241 switch (size) {
242 case 4:
243 {
244 r = cpu_ldl_code(env, addr);
245 break;
246 }
247 case 2:
248 {
249 if (sign) {
250 r = cpu_ldsw_code(env, addr);
251 } else {
252 r = cpu_lduw_code(env, addr);
253 }
254 break;
255 }
256 case 1:
257 {
258 if (sign) {
259 r = cpu_ldsb_code(env, addr);
260 } else {
261 r = cpu_ldub_code(env, addr);
262 }
263 break;
264 }
265 default:
266 cpu_abort(dc->env, "Invalid fetch size %d\n", size);
267 break;
268 }
269 return r;
270 }
271
272 static void cris_lock_irq(DisasContext *dc)
273 {
274 dc->clear_locked_irq = 0;
275 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
276 }
277
278 static inline void t_gen_raise_exception(uint32_t index)
279 {
280 TCGv_i32 tmp = tcg_const_i32(index);
281 gen_helper_raise_exception(cpu_env, tmp);
282 tcg_temp_free_i32(tmp);
283 }
284
285 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
286 {
287 TCGv t0, t_31;
288
289 t0 = tcg_temp_new();
290 t_31 = tcg_const_tl(31);
291 tcg_gen_shl_tl(d, a, b);
292
293 tcg_gen_sub_tl(t0, t_31, b);
294 tcg_gen_sar_tl(t0, t0, t_31);
295 tcg_gen_and_tl(t0, t0, d);
296 tcg_gen_xor_tl(d, d, t0);
297 tcg_temp_free(t0);
298 tcg_temp_free(t_31);
299 }
300
301 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
302 {
303 TCGv t0, t_31;
304
305 t0 = tcg_temp_new();
306 t_31 = tcg_temp_new();
307 tcg_gen_shr_tl(d, a, b);
308
309 tcg_gen_movi_tl(t_31, 31);
310 tcg_gen_sub_tl(t0, t_31, b);
311 tcg_gen_sar_tl(t0, t0, t_31);
312 tcg_gen_and_tl(t0, t0, d);
313 tcg_gen_xor_tl(d, d, t0);
314 tcg_temp_free(t0);
315 tcg_temp_free(t_31);
316 }
317
318 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
319 {
320 TCGv t0, t_31;
321
322 t0 = tcg_temp_new();
323 t_31 = tcg_temp_new();
324 tcg_gen_sar_tl(d, a, b);
325
326 tcg_gen_movi_tl(t_31, 31);
327 tcg_gen_sub_tl(t0, t_31, b);
328 tcg_gen_sar_tl(t0, t0, t_31);
329 tcg_gen_or_tl(d, d, t0);
330 tcg_temp_free(t0);
331 tcg_temp_free(t_31);
332 }
333
334 /* 64-bit signed mul, lower result in d and upper in d2. */
335 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
336 {
337 TCGv_i64 t0, t1;
338
339 t0 = tcg_temp_new_i64();
340 t1 = tcg_temp_new_i64();
341
342 tcg_gen_ext_i32_i64(t0, a);
343 tcg_gen_ext_i32_i64(t1, b);
344 tcg_gen_mul_i64(t0, t0, t1);
345
346 tcg_gen_trunc_i64_i32(d, t0);
347 tcg_gen_shri_i64(t0, t0, 32);
348 tcg_gen_trunc_i64_i32(d2, t0);
349
350 tcg_temp_free_i64(t0);
351 tcg_temp_free_i64(t1);
352 }
353
354 /* 64-bit unsigned muls, lower result in d and upper in d2. */
355 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
356 {
357 TCGv_i64 t0, t1;
358
359 t0 = tcg_temp_new_i64();
360 t1 = tcg_temp_new_i64();
361
362 tcg_gen_extu_i32_i64(t0, a);
363 tcg_gen_extu_i32_i64(t1, b);
364 tcg_gen_mul_i64(t0, t0, t1);
365
366 tcg_gen_trunc_i64_i32(d, t0);
367 tcg_gen_shri_i64(t0, t0, 32);
368 tcg_gen_trunc_i64_i32(d2, t0);
369
370 tcg_temp_free_i64(t0);
371 tcg_temp_free_i64(t1);
372 }
373
374 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
375 {
376 int l1;
377
378 l1 = gen_new_label();
379
380 /*
381 * d <<= 1
382 * if (d >= s)
383 * d -= s;
384 */
385 tcg_gen_shli_tl(d, a, 1);
386 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
387 tcg_gen_sub_tl(d, d, b);
388 gen_set_label(l1);
389 }
390
391 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
392 {
393 TCGv t;
394
395 /*
396 * d <<= 1
397 * if (n)
398 * d += s;
399 */
400 t = tcg_temp_new();
401 tcg_gen_shli_tl(d, a, 1);
402 tcg_gen_shli_tl(t, ccs, 31 - 3);
403 tcg_gen_sari_tl(t, t, 31);
404 tcg_gen_and_tl(t, t, b);
405 tcg_gen_add_tl(d, d, t);
406 tcg_temp_free(t);
407 }
408
409 /* Extended arithmetics on CRIS. */
410 static inline void t_gen_add_flag(TCGv d, int flag)
411 {
412 TCGv c;
413
414 c = tcg_temp_new();
415 t_gen_mov_TN_preg(c, PR_CCS);
416 /* Propagate carry into d. */
417 tcg_gen_andi_tl(c, c, 1 << flag);
418 if (flag)
419 tcg_gen_shri_tl(c, c, flag);
420 tcg_gen_add_tl(d, d, c);
421 tcg_temp_free(c);
422 }
423
424 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
425 {
426 if (dc->flagx_known) {
427 if (dc->flags_x) {
428 TCGv c;
429
430 c = tcg_temp_new();
431 t_gen_mov_TN_preg(c, PR_CCS);
432 /* C flag is already at bit 0. */
433 tcg_gen_andi_tl(c, c, C_FLAG);
434 tcg_gen_add_tl(d, d, c);
435 tcg_temp_free(c);
436 }
437 } else {
438 TCGv x, c;
439
440 x = tcg_temp_new();
441 c = tcg_temp_new();
442 t_gen_mov_TN_preg(x, PR_CCS);
443 tcg_gen_mov_tl(c, x);
444
445 /* Propagate carry into d if X is set. Branch free. */
446 tcg_gen_andi_tl(c, c, C_FLAG);
447 tcg_gen_andi_tl(x, x, X_FLAG);
448 tcg_gen_shri_tl(x, x, 4);
449
450 tcg_gen_and_tl(x, x, c);
451 tcg_gen_add_tl(d, d, x);
452 tcg_temp_free(x);
453 tcg_temp_free(c);
454 }
455 }
456
457 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
458 {
459 if (dc->flagx_known) {
460 if (dc->flags_x) {
461 TCGv c;
462
463 c = tcg_temp_new();
464 t_gen_mov_TN_preg(c, PR_CCS);
465 /* C flag is already at bit 0. */
466 tcg_gen_andi_tl(c, c, C_FLAG);
467 tcg_gen_sub_tl(d, d, c);
468 tcg_temp_free(c);
469 }
470 } else {
471 TCGv x, c;
472
473 x = tcg_temp_new();
474 c = tcg_temp_new();
475 t_gen_mov_TN_preg(x, PR_CCS);
476 tcg_gen_mov_tl(c, x);
477
478 /* Propagate carry into d if X is set. Branch free. */
479 tcg_gen_andi_tl(c, c, C_FLAG);
480 tcg_gen_andi_tl(x, x, X_FLAG);
481 tcg_gen_shri_tl(x, x, 4);
482
483 tcg_gen_and_tl(x, x, c);
484 tcg_gen_sub_tl(d, d, x);
485 tcg_temp_free(x);
486 tcg_temp_free(c);
487 }
488 }
489
490 /* Swap the two bytes within each half word of the s operand.
491 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
492 static inline void t_gen_swapb(TCGv d, TCGv s)
493 {
494 TCGv t, org_s;
495
496 t = tcg_temp_new();
497 org_s = tcg_temp_new();
498
499 /* d and s may refer to the same object. */
500 tcg_gen_mov_tl(org_s, s);
501 tcg_gen_shli_tl(t, org_s, 8);
502 tcg_gen_andi_tl(d, t, 0xff00ff00);
503 tcg_gen_shri_tl(t, org_s, 8);
504 tcg_gen_andi_tl(t, t, 0x00ff00ff);
505 tcg_gen_or_tl(d, d, t);
506 tcg_temp_free(t);
507 tcg_temp_free(org_s);
508 }
509
510 /* Swap the halfwords of the s operand. */
511 static inline void t_gen_swapw(TCGv d, TCGv s)
512 {
513 TCGv t;
514 /* d and s refer the same object. */
515 t = tcg_temp_new();
516 tcg_gen_mov_tl(t, s);
517 tcg_gen_shli_tl(d, t, 16);
518 tcg_gen_shri_tl(t, t, 16);
519 tcg_gen_or_tl(d, d, t);
520 tcg_temp_free(t);
521 }
522
523 /* Reverse the within each byte.
524 T0 = (((T0 << 7) & 0x80808080) |
525 ((T0 << 5) & 0x40404040) |
526 ((T0 << 3) & 0x20202020) |
527 ((T0 << 1) & 0x10101010) |
528 ((T0 >> 1) & 0x08080808) |
529 ((T0 >> 3) & 0x04040404) |
530 ((T0 >> 5) & 0x02020202) |
531 ((T0 >> 7) & 0x01010101));
532 */
533 static inline void t_gen_swapr(TCGv d, TCGv s)
534 {
535 struct {
536 int shift; /* LSL when positive, LSR when negative. */
537 uint32_t mask;
538 } bitrev [] = {
539 {7, 0x80808080},
540 {5, 0x40404040},
541 {3, 0x20202020},
542 {1, 0x10101010},
543 {-1, 0x08080808},
544 {-3, 0x04040404},
545 {-5, 0x02020202},
546 {-7, 0x01010101}
547 };
548 int i;
549 TCGv t, org_s;
550
551 /* d and s refer the same object. */
552 t = tcg_temp_new();
553 org_s = tcg_temp_new();
554 tcg_gen_mov_tl(org_s, s);
555
556 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
557 tcg_gen_andi_tl(d, t, bitrev[0].mask);
558 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
559 if (bitrev[i].shift >= 0) {
560 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
561 } else {
562 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
563 }
564 tcg_gen_andi_tl(t, t, bitrev[i].mask);
565 tcg_gen_or_tl(d, d, t);
566 }
567 tcg_temp_free(t);
568 tcg_temp_free(org_s);
569 }
570
571 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
572 {
573 int l1;
574
575 l1 = gen_new_label();
576
577 /* Conditional jmp. */
578 tcg_gen_mov_tl(env_pc, pc_false);
579 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
580 tcg_gen_mov_tl(env_pc, pc_true);
581 gen_set_label(l1);
582 }
583
584 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
585 {
586 TranslationBlock *tb;
587 tb = dc->tb;
588 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
589 tcg_gen_goto_tb(n);
590 tcg_gen_movi_tl(env_pc, dest);
591 tcg_gen_exit_tb((tcg_target_long)tb + n);
592 } else {
593 tcg_gen_movi_tl(env_pc, dest);
594 tcg_gen_exit_tb(0);
595 }
596 }
597
598 static inline void cris_clear_x_flag(DisasContext *dc)
599 {
600 if (dc->flagx_known && dc->flags_x)
601 dc->flags_uptodate = 0;
602
603 dc->flagx_known = 1;
604 dc->flags_x = 0;
605 }
606
607 static void cris_flush_cc_state(DisasContext *dc)
608 {
609 if (dc->cc_size_uptodate != dc->cc_size) {
610 tcg_gen_movi_tl(cc_size, dc->cc_size);
611 dc->cc_size_uptodate = dc->cc_size;
612 }
613 tcg_gen_movi_tl(cc_op, dc->cc_op);
614 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
615 }
616
617 static void cris_evaluate_flags(DisasContext *dc)
618 {
619 if (dc->flags_uptodate)
620 return;
621
622 cris_flush_cc_state(dc);
623
624 switch (dc->cc_op)
625 {
626 case CC_OP_MCP:
627 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
628 cpu_PR[PR_CCS], cc_src,
629 cc_dest, cc_result);
630 break;
631 case CC_OP_MULS:
632 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
633 cpu_PR[PR_CCS], cc_result,
634 cpu_PR[PR_MOF]);
635 break;
636 case CC_OP_MULU:
637 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
638 cpu_PR[PR_CCS], cc_result,
639 cpu_PR[PR_MOF]);
640 break;
641 case CC_OP_MOVE:
642 case CC_OP_AND:
643 case CC_OP_OR:
644 case CC_OP_XOR:
645 case CC_OP_ASR:
646 case CC_OP_LSR:
647 case CC_OP_LSL:
648 switch (dc->cc_size)
649 {
650 case 4:
651 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
652 cpu_env, cpu_PR[PR_CCS], cc_result);
653 break;
654 case 2:
655 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
656 cpu_env, cpu_PR[PR_CCS], cc_result);
657 break;
658 default:
659 gen_helper_evaluate_flags(cpu_env);
660 break;
661 }
662 break;
663 case CC_OP_FLAGS:
664 /* live. */
665 break;
666 case CC_OP_SUB:
667 case CC_OP_CMP:
668 if (dc->cc_size == 4)
669 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
670 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
671 else
672 gen_helper_evaluate_flags(cpu_env);
673
674 break;
675 default:
676 switch (dc->cc_size)
677 {
678 case 4:
679 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
680 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
681 break;
682 default:
683 gen_helper_evaluate_flags(cpu_env);
684 break;
685 }
686 break;
687 }
688
689 if (dc->flagx_known) {
690 if (dc->flags_x)
691 tcg_gen_ori_tl(cpu_PR[PR_CCS],
692 cpu_PR[PR_CCS], X_FLAG);
693 else if (dc->cc_op == CC_OP_FLAGS)
694 tcg_gen_andi_tl(cpu_PR[PR_CCS],
695 cpu_PR[PR_CCS], ~X_FLAG);
696 }
697 dc->flags_uptodate = 1;
698 }
699
700 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
701 {
702 uint32_t ovl;
703
704 if (!mask) {
705 dc->update_cc = 0;
706 return;
707 }
708
709 /* Check if we need to evaluate the condition codes due to
710 CC overlaying. */
711 ovl = (dc->cc_mask ^ mask) & ~mask;
712 if (ovl) {
713 /* TODO: optimize this case. It trigs all the time. */
714 cris_evaluate_flags (dc);
715 }
716 dc->cc_mask = mask;
717 dc->update_cc = 1;
718 }
719
720 static void cris_update_cc_op(DisasContext *dc, int op, int size)
721 {
722 dc->cc_op = op;
723 dc->cc_size = size;
724 dc->flags_uptodate = 0;
725 }
726
727 static inline void cris_update_cc_x(DisasContext *dc)
728 {
729 /* Save the x flag state at the time of the cc snapshot. */
730 if (dc->flagx_known) {
731 if (dc->cc_x_uptodate == (2 | dc->flags_x))
732 return;
733 tcg_gen_movi_tl(cc_x, dc->flags_x);
734 dc->cc_x_uptodate = 2 | dc->flags_x;
735 }
736 else {
737 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
738 dc->cc_x_uptodate = 1;
739 }
740 }
741
742 /* Update cc prior to executing ALU op. Needs source operands untouched. */
743 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
744 TCGv dst, TCGv src, int size)
745 {
746 if (dc->update_cc) {
747 cris_update_cc_op(dc, op, size);
748 tcg_gen_mov_tl(cc_src, src);
749
750 if (op != CC_OP_MOVE
751 && op != CC_OP_AND
752 && op != CC_OP_OR
753 && op != CC_OP_XOR
754 && op != CC_OP_ASR
755 && op != CC_OP_LSR
756 && op != CC_OP_LSL)
757 tcg_gen_mov_tl(cc_dest, dst);
758
759 cris_update_cc_x(dc);
760 }
761 }
762
763 /* Update cc after executing ALU op. needs the result. */
764 static inline void cris_update_result(DisasContext *dc, TCGv res)
765 {
766 if (dc->update_cc)
767 tcg_gen_mov_tl(cc_result, res);
768 }
769
770 /* Returns one if the write back stage should execute. */
771 static void cris_alu_op_exec(DisasContext *dc, int op,
772 TCGv dst, TCGv a, TCGv b, int size)
773 {
774 /* Emit the ALU insns. */
775 switch (op)
776 {
777 case CC_OP_ADD:
778 tcg_gen_add_tl(dst, a, b);
779 /* Extended arithmetics. */
780 t_gen_addx_carry(dc, dst);
781 break;
782 case CC_OP_ADDC:
783 tcg_gen_add_tl(dst, a, b);
784 t_gen_add_flag(dst, 0); /* C_FLAG. */
785 break;
786 case CC_OP_MCP:
787 tcg_gen_add_tl(dst, a, b);
788 t_gen_add_flag(dst, 8); /* R_FLAG. */
789 break;
790 case CC_OP_SUB:
791 tcg_gen_sub_tl(dst, a, b);
792 /* Extended arithmetics. */
793 t_gen_subx_carry(dc, dst);
794 break;
795 case CC_OP_MOVE:
796 tcg_gen_mov_tl(dst, b);
797 break;
798 case CC_OP_OR:
799 tcg_gen_or_tl(dst, a, b);
800 break;
801 case CC_OP_AND:
802 tcg_gen_and_tl(dst, a, b);
803 break;
804 case CC_OP_XOR:
805 tcg_gen_xor_tl(dst, a, b);
806 break;
807 case CC_OP_LSL:
808 t_gen_lsl(dst, a, b);
809 break;
810 case CC_OP_LSR:
811 t_gen_lsr(dst, a, b);
812 break;
813 case CC_OP_ASR:
814 t_gen_asr(dst, a, b);
815 break;
816 case CC_OP_NEG:
817 tcg_gen_neg_tl(dst, b);
818 /* Extended arithmetics. */
819 t_gen_subx_carry(dc, dst);
820 break;
821 case CC_OP_LZ:
822 gen_helper_lz(dst, b);
823 break;
824 case CC_OP_MULS:
825 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
826 break;
827 case CC_OP_MULU:
828 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
829 break;
830 case CC_OP_DSTEP:
831 t_gen_cris_dstep(dst, a, b);
832 break;
833 case CC_OP_MSTEP:
834 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
835 break;
836 case CC_OP_BOUND:
837 {
838 int l1;
839 l1 = gen_new_label();
840 tcg_gen_mov_tl(dst, a);
841 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
842 tcg_gen_mov_tl(dst, b);
843 gen_set_label(l1);
844 }
845 break;
846 case CC_OP_CMP:
847 tcg_gen_sub_tl(dst, a, b);
848 /* Extended arithmetics. */
849 t_gen_subx_carry(dc, dst);
850 break;
851 default:
852 qemu_log("illegal ALU op.\n");
853 BUG();
854 break;
855 }
856
857 if (size == 1)
858 tcg_gen_andi_tl(dst, dst, 0xff);
859 else if (size == 2)
860 tcg_gen_andi_tl(dst, dst, 0xffff);
861 }
862
863 static void cris_alu(DisasContext *dc, int op,
864 TCGv d, TCGv op_a, TCGv op_b, int size)
865 {
866 TCGv tmp;
867 int writeback;
868
869 writeback = 1;
870
871 if (op == CC_OP_CMP) {
872 tmp = tcg_temp_new();
873 writeback = 0;
874 } else if (size == 4) {
875 tmp = d;
876 writeback = 0;
877 } else
878 tmp = tcg_temp_new();
879
880
881 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
882 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
883 cris_update_result(dc, tmp);
884
885 /* Writeback. */
886 if (writeback) {
887 if (size == 1)
888 tcg_gen_andi_tl(d, d, ~0xff);
889 else
890 tcg_gen_andi_tl(d, d, ~0xffff);
891 tcg_gen_or_tl(d, d, tmp);
892 }
893 if (!TCGV_EQUAL(tmp, d))
894 tcg_temp_free(tmp);
895 }
896
897 static int arith_cc(DisasContext *dc)
898 {
899 if (dc->update_cc) {
900 switch (dc->cc_op) {
901 case CC_OP_ADDC: return 1;
902 case CC_OP_ADD: return 1;
903 case CC_OP_SUB: return 1;
904 case CC_OP_DSTEP: return 1;
905 case CC_OP_LSL: return 1;
906 case CC_OP_LSR: return 1;
907 case CC_OP_ASR: return 1;
908 case CC_OP_CMP: return 1;
909 case CC_OP_NEG: return 1;
910 case CC_OP_OR: return 1;
911 case CC_OP_AND: return 1;
912 case CC_OP_XOR: return 1;
913 case CC_OP_MULU: return 1;
914 case CC_OP_MULS: return 1;
915 default:
916 return 0;
917 }
918 }
919 return 0;
920 }
921
922 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
923 {
924 int arith_opt, move_opt;
925
926 /* TODO: optimize more condition codes. */
927
928 /*
929 * If the flags are live, we've gotta look into the bits of CCS.
930 * Otherwise, if we just did an arithmetic operation we try to
931 * evaluate the condition code faster.
932 *
933 * When this function is done, T0 should be non-zero if the condition
934 * code is true.
935 */
936 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
937 move_opt = (dc->cc_op == CC_OP_MOVE);
938 switch (cond) {
939 case CC_EQ:
940 if ((arith_opt || move_opt)
941 && dc->cc_x_uptodate != (2 | X_FLAG)) {
942 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
943 cc_result, tcg_const_tl(0));
944 }
945 else {
946 cris_evaluate_flags(dc);
947 tcg_gen_andi_tl(cc,
948 cpu_PR[PR_CCS], Z_FLAG);
949 }
950 break;
951 case CC_NE:
952 if ((arith_opt || move_opt)
953 && dc->cc_x_uptodate != (2 | X_FLAG)) {
954 tcg_gen_mov_tl(cc, cc_result);
955 } else {
956 cris_evaluate_flags(dc);
957 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
958 Z_FLAG);
959 tcg_gen_andi_tl(cc, cc, Z_FLAG);
960 }
961 break;
962 case CC_CS:
963 cris_evaluate_flags(dc);
964 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
965 break;
966 case CC_CC:
967 cris_evaluate_flags(dc);
968 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
969 tcg_gen_andi_tl(cc, cc, C_FLAG);
970 break;
971 case CC_VS:
972 cris_evaluate_flags(dc);
973 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
974 break;
975 case CC_VC:
976 cris_evaluate_flags(dc);
977 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
978 V_FLAG);
979 tcg_gen_andi_tl(cc, cc, V_FLAG);
980 break;
981 case CC_PL:
982 if (arith_opt || move_opt) {
983 int bits = 31;
984
985 if (dc->cc_size == 1)
986 bits = 7;
987 else if (dc->cc_size == 2)
988 bits = 15;
989
990 tcg_gen_shri_tl(cc, cc_result, bits);
991 tcg_gen_xori_tl(cc, cc, 1);
992 } else {
993 cris_evaluate_flags(dc);
994 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
995 N_FLAG);
996 tcg_gen_andi_tl(cc, cc, N_FLAG);
997 }
998 break;
999 case CC_MI:
1000 if (arith_opt || move_opt) {
1001 int bits = 31;
1002
1003 if (dc->cc_size == 1)
1004 bits = 7;
1005 else if (dc->cc_size == 2)
1006 bits = 15;
1007
1008 tcg_gen_shri_tl(cc, cc_result, bits);
1009 tcg_gen_andi_tl(cc, cc, 1);
1010 }
1011 else {
1012 cris_evaluate_flags(dc);
1013 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1014 N_FLAG);
1015 }
1016 break;
1017 case CC_LS:
1018 cris_evaluate_flags(dc);
1019 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1020 C_FLAG | Z_FLAG);
1021 break;
1022 case CC_HI:
1023 cris_evaluate_flags(dc);
1024 {
1025 TCGv tmp;
1026
1027 tmp = tcg_temp_new();
1028 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1029 C_FLAG | Z_FLAG);
1030 /* Overlay the C flag on top of the Z. */
1031 tcg_gen_shli_tl(cc, tmp, 2);
1032 tcg_gen_and_tl(cc, tmp, cc);
1033 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1034
1035 tcg_temp_free(tmp);
1036 }
1037 break;
1038 case CC_GE:
1039 cris_evaluate_flags(dc);
1040 /* Overlay the V flag on top of the N. */
1041 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1042 tcg_gen_xor_tl(cc,
1043 cpu_PR[PR_CCS], cc);
1044 tcg_gen_andi_tl(cc, cc, N_FLAG);
1045 tcg_gen_xori_tl(cc, cc, N_FLAG);
1046 break;
1047 case CC_LT:
1048 cris_evaluate_flags(dc);
1049 /* Overlay the V flag on top of the N. */
1050 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1051 tcg_gen_xor_tl(cc,
1052 cpu_PR[PR_CCS], cc);
1053 tcg_gen_andi_tl(cc, cc, N_FLAG);
1054 break;
1055 case CC_GT:
1056 cris_evaluate_flags(dc);
1057 {
1058 TCGv n, z;
1059
1060 n = tcg_temp_new();
1061 z = tcg_temp_new();
1062
1063 /* To avoid a shift we overlay everything on
1064 the V flag. */
1065 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1066 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1067 /* invert Z. */
1068 tcg_gen_xori_tl(z, z, 2);
1069
1070 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1071 tcg_gen_xori_tl(n, n, 2);
1072 tcg_gen_and_tl(cc, z, n);
1073 tcg_gen_andi_tl(cc, cc, 2);
1074
1075 tcg_temp_free(n);
1076 tcg_temp_free(z);
1077 }
1078 break;
1079 case CC_LE:
1080 cris_evaluate_flags(dc);
1081 {
1082 TCGv n, z;
1083
1084 n = tcg_temp_new();
1085 z = tcg_temp_new();
1086
1087 /* To avoid a shift we overlay everything on
1088 the V flag. */
1089 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1090 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1091
1092 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1093 tcg_gen_or_tl(cc, z, n);
1094 tcg_gen_andi_tl(cc, cc, 2);
1095
1096 tcg_temp_free(n);
1097 tcg_temp_free(z);
1098 }
1099 break;
1100 case CC_P:
1101 cris_evaluate_flags(dc);
1102 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1103 break;
1104 case CC_A:
1105 tcg_gen_movi_tl(cc, 1);
1106 break;
1107 default:
1108 BUG();
1109 break;
1110 };
1111 }
1112
1113 static void cris_store_direct_jmp(DisasContext *dc)
1114 {
1115 /* Store the direct jmp state into the cpu-state. */
1116 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1117 if (dc->jmp == JMP_DIRECT) {
1118 tcg_gen_movi_tl(env_btaken, 1);
1119 }
1120 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1121 dc->jmp = JMP_INDIRECT;
1122 }
1123 }
1124
1125 static void cris_prepare_cc_branch (DisasContext *dc,
1126 int offset, int cond)
1127 {
1128 /* This helps us re-schedule the micro-code to insns in delay-slots
1129 before the actual jump. */
1130 dc->delayed_branch = 2;
1131 dc->jmp = JMP_DIRECT_CC;
1132 dc->jmp_pc = dc->pc + offset;
1133
1134 gen_tst_cc (dc, env_btaken, cond);
1135 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1136 }
1137
1138
1139 /* jumps, when the dest is in a live reg for example. Direct should be set
1140 when the dest addr is constant to allow tb chaining. */
1141 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1142 {
1143 /* This helps us re-schedule the micro-code to insns in delay-slots
1144 before the actual jump. */
1145 dc->delayed_branch = 2;
1146 dc->jmp = type;
1147 if (type == JMP_INDIRECT) {
1148 tcg_gen_movi_tl(env_btaken, 1);
1149 }
1150 }
1151
1152 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1153 {
1154 int mem_index = cpu_mmu_index(dc->env);
1155
1156 /* If we get a fault on a delayslot we must keep the jmp state in
1157 the cpu-state to be able to re-execute the jmp. */
1158 if (dc->delayed_branch == 1)
1159 cris_store_direct_jmp(dc);
1160
1161 tcg_gen_qemu_ld64(dst, addr, mem_index);
1162 }
1163
1164 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1165 unsigned int size, int sign)
1166 {
1167 int mem_index = cpu_mmu_index(dc->env);
1168
1169 /* If we get a fault on a delayslot we must keep the jmp state in
1170 the cpu-state to be able to re-execute the jmp. */
1171 if (dc->delayed_branch == 1)
1172 cris_store_direct_jmp(dc);
1173
1174 if (size == 1) {
1175 if (sign)
1176 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1177 else
1178 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1179 }
1180 else if (size == 2) {
1181 if (sign)
1182 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1183 else
1184 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1185 }
1186 else if (size == 4) {
1187 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1188 }
1189 else {
1190 abort();
1191 }
1192 }
1193
1194 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1195 unsigned int size)
1196 {
1197 int mem_index = cpu_mmu_index(dc->env);
1198
1199 /* If we get a fault on a delayslot we must keep the jmp state in
1200 the cpu-state to be able to re-execute the jmp. */
1201 if (dc->delayed_branch == 1)
1202 cris_store_direct_jmp(dc);
1203
1204
1205 /* Conditional writes. We only support the kind were X and P are known
1206 at translation time. */
1207 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1208 dc->postinc = 0;
1209 cris_evaluate_flags(dc);
1210 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1211 return;
1212 }
1213
1214 if (size == 1)
1215 tcg_gen_qemu_st8(val, addr, mem_index);
1216 else if (size == 2)
1217 tcg_gen_qemu_st16(val, addr, mem_index);
1218 else
1219 tcg_gen_qemu_st32(val, addr, mem_index);
1220
1221 if (dc->flagx_known && dc->flags_x) {
1222 cris_evaluate_flags(dc);
1223 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1224 }
1225 }
1226
1227 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1228 {
1229 if (size == 1)
1230 tcg_gen_ext8s_i32(d, s);
1231 else if (size == 2)
1232 tcg_gen_ext16s_i32(d, s);
1233 else if(!TCGV_EQUAL(d, s))
1234 tcg_gen_mov_tl(d, s);
1235 }
1236
1237 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1238 {
1239 if (size == 1)
1240 tcg_gen_ext8u_i32(d, s);
1241 else if (size == 2)
1242 tcg_gen_ext16u_i32(d, s);
1243 else if (!TCGV_EQUAL(d, s))
1244 tcg_gen_mov_tl(d, s);
1245 }
1246
1247 #if DISAS_CRIS
1248 static char memsize_char(int size)
1249 {
1250 switch (size)
1251 {
1252 case 1: return 'b'; break;
1253 case 2: return 'w'; break;
1254 case 4: return 'd'; break;
1255 default:
1256 return 'x';
1257 break;
1258 }
1259 }
1260 #endif
1261
1262 static inline unsigned int memsize_z(DisasContext *dc)
1263 {
1264 return dc->zsize + 1;
1265 }
1266
1267 static inline unsigned int memsize_zz(DisasContext *dc)
1268 {
1269 switch (dc->zzsize)
1270 {
1271 case 0: return 1;
1272 case 1: return 2;
1273 default:
1274 return 4;
1275 }
1276 }
1277
1278 static inline void do_postinc (DisasContext *dc, int size)
1279 {
1280 if (dc->postinc)
1281 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1282 }
1283
1284 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1285 int size, int s_ext, TCGv dst)
1286 {
1287 if (s_ext)
1288 t_gen_sext(dst, cpu_R[rs], size);
1289 else
1290 t_gen_zext(dst, cpu_R[rs], size);
1291 }
1292
1293 /* Prepare T0 and T1 for a register alu operation.
1294 s_ext decides if the operand1 should be sign-extended or zero-extended when
1295 needed. */
1296 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1297 int size, int s_ext, TCGv dst, TCGv src)
1298 {
1299 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1300
1301 if (s_ext)
1302 t_gen_sext(dst, cpu_R[rd], size);
1303 else
1304 t_gen_zext(dst, cpu_R[rd], size);
1305 }
1306
1307 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1308 int s_ext, int memsize, TCGv dst)
1309 {
1310 unsigned int rs;
1311 uint32_t imm;
1312 int is_imm;
1313 int insn_len = 2;
1314
1315 rs = dc->op1;
1316 is_imm = rs == 15 && dc->postinc;
1317
1318 /* Load [$rs] onto T1. */
1319 if (is_imm) {
1320 insn_len = 2 + memsize;
1321 if (memsize == 1)
1322 insn_len++;
1323
1324 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1325 tcg_gen_movi_tl(dst, imm);
1326 dc->postinc = 0;
1327 } else {
1328 cris_flush_cc_state(dc);
1329 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1330 if (s_ext)
1331 t_gen_sext(dst, dst, memsize);
1332 else
1333 t_gen_zext(dst, dst, memsize);
1334 }
1335 return insn_len;
1336 }
1337
1338 /* Prepare T0 and T1 for a memory + alu operation.
1339 s_ext decides if the operand1 should be sign-extended or zero-extended when
1340 needed. */
1341 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1342 int s_ext, int memsize, TCGv dst, TCGv src)
1343 {
1344 int insn_len;
1345
1346 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1347 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1348 return insn_len;
1349 }
1350
1351 #if DISAS_CRIS
1352 static const char *cc_name(int cc)
1353 {
1354 static const char *cc_names[16] = {
1355 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1356 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1357 };
1358 assert(cc < 16);
1359 return cc_names[cc];
1360 }
1361 #endif
1362
1363 /* Start of insn decoders. */
1364
1365 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1366 {
1367 int32_t offset;
1368 int sign;
1369 uint32_t cond = dc->op2;
1370
1371 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1372 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1373
1374 offset *= 2;
1375 offset |= sign << 8;
1376 offset = sign_extend(offset, 8);
1377
1378 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1379
1380 /* op2 holds the condition-code. */
1381 cris_cc_mask(dc, 0);
1382 cris_prepare_cc_branch (dc, offset, cond);
1383 return 2;
1384 }
1385 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1386 {
1387 int32_t imm;
1388
1389 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1390 imm = sign_extend(dc->op1, 7);
1391
1392 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1393 cris_cc_mask(dc, 0);
1394 /* Fetch register operand, */
1395 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1396
1397 return 2;
1398 }
1399 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1400 {
1401 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1402
1403 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1404
1405 cris_cc_mask(dc, CC_MASK_NZVC);
1406
1407 cris_alu(dc, CC_OP_ADD,
1408 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1409 return 2;
1410 }
1411 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1412 {
1413 uint32_t imm;
1414
1415 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1416 imm = sign_extend(dc->op1, 5);
1417 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1418
1419 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1420 return 2;
1421 }
1422 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1423 {
1424 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1425
1426 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1427
1428 cris_cc_mask(dc, CC_MASK_NZVC);
1429 cris_alu(dc, CC_OP_SUB,
1430 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1431 return 2;
1432 }
1433 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1434 {
1435 uint32_t imm;
1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1437 imm = sign_extend(dc->op1, 5);
1438
1439 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1440 cris_cc_mask(dc, CC_MASK_NZVC);
1441
1442 cris_alu(dc, CC_OP_CMP,
1443 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1444 return 2;
1445 }
1446 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1447 {
1448 uint32_t imm;
1449 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1450 imm = sign_extend(dc->op1, 5);
1451
1452 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1453 cris_cc_mask(dc, CC_MASK_NZ);
1454
1455 cris_alu(dc, CC_OP_AND,
1456 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1457 return 2;
1458 }
1459 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1460 {
1461 uint32_t imm;
1462 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1463 imm = sign_extend(dc->op1, 5);
1464 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1465 cris_cc_mask(dc, CC_MASK_NZ);
1466
1467 cris_alu(dc, CC_OP_OR,
1468 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1469 return 2;
1470 }
1471 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1472 {
1473 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1474 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1475
1476 cris_cc_mask(dc, CC_MASK_NZ);
1477 cris_evaluate_flags(dc);
1478 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1479 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1480 cris_alu(dc, CC_OP_MOVE,
1481 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1482 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1483 dc->flags_uptodate = 1;
1484 return 2;
1485 }
1486 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1487 {
1488 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1489 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1490 cris_cc_mask(dc, CC_MASK_NZ);
1491
1492 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1493 cris_alu(dc, CC_OP_MOVE,
1494 cpu_R[dc->op2],
1495 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1496 return 2;
1497 }
1498 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1499 {
1500 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1501 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1502
1503 cris_cc_mask(dc, CC_MASK_NZ);
1504
1505 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1506
1507 cris_alu(dc, CC_OP_MOVE,
1508 cpu_R[dc->op2],
1509 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1510 return 2;
1511 }
1512 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1513 {
1514 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1515 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1516
1517 cris_cc_mask(dc, CC_MASK_NZ);
1518
1519 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1520 cris_alu(dc, CC_OP_MOVE,
1521 cpu_R[dc->op2],
1522 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1523 return 2;
1524 }
1525
1526 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1527 {
1528 int size = memsize_zz(dc);
1529
1530 LOG_DIS("move.%c $r%u, $r%u\n",
1531 memsize_char(size), dc->op1, dc->op2);
1532
1533 cris_cc_mask(dc, CC_MASK_NZ);
1534 if (size == 4) {
1535 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1536 cris_cc_mask(dc, CC_MASK_NZ);
1537 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1538 cris_update_cc_x(dc);
1539 cris_update_result(dc, cpu_R[dc->op2]);
1540 }
1541 else {
1542 TCGv t0;
1543
1544 t0 = tcg_temp_new();
1545 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1546 cris_alu(dc, CC_OP_MOVE,
1547 cpu_R[dc->op2],
1548 cpu_R[dc->op2], t0, size);
1549 tcg_temp_free(t0);
1550 }
1551 return 2;
1552 }
1553
1554 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1555 {
1556 int cond = dc->op2;
1557
1558 LOG_DIS("s%s $r%u\n",
1559 cc_name(cond), dc->op1);
1560
1561 if (cond != CC_A)
1562 {
1563 int l1;
1564
1565 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1566 l1 = gen_new_label();
1567 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1568 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1569 gen_set_label(l1);
1570 }
1571 else
1572 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1573
1574 cris_cc_mask(dc, 0);
1575 return 2;
1576 }
1577
1578 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1579 {
1580 if (size == 4) {
1581 t[0] = cpu_R[dc->op2];
1582 t[1] = cpu_R[dc->op1];
1583 } else {
1584 t[0] = tcg_temp_new();
1585 t[1] = tcg_temp_new();
1586 }
1587 }
1588
1589 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1590 {
1591 if (size != 4) {
1592 tcg_temp_free(t[0]);
1593 tcg_temp_free(t[1]);
1594 }
1595 }
1596
1597 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1598 {
1599 TCGv t[2];
1600 int size = memsize_zz(dc);
1601
1602 LOG_DIS("and.%c $r%u, $r%u\n",
1603 memsize_char(size), dc->op1, dc->op2);
1604
1605 cris_cc_mask(dc, CC_MASK_NZ);
1606
1607 cris_alu_alloc_temps(dc, size, t);
1608 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1609 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1610 cris_alu_free_temps(dc, size, t);
1611 return 2;
1612 }
1613
1614 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1615 {
1616 TCGv t0;
1617 LOG_DIS("lz $r%u, $r%u\n",
1618 dc->op1, dc->op2);
1619 cris_cc_mask(dc, CC_MASK_NZ);
1620 t0 = tcg_temp_new();
1621 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1622 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1623 tcg_temp_free(t0);
1624 return 2;
1625 }
1626
1627 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1628 {
1629 TCGv t[2];
1630 int size = memsize_zz(dc);
1631
1632 LOG_DIS("lsl.%c $r%u, $r%u\n",
1633 memsize_char(size), dc->op1, dc->op2);
1634
1635 cris_cc_mask(dc, CC_MASK_NZ);
1636 cris_alu_alloc_temps(dc, size, t);
1637 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1638 tcg_gen_andi_tl(t[1], t[1], 63);
1639 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1640 cris_alu_alloc_temps(dc, size, t);
1641 return 2;
1642 }
1643
1644 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1645 {
1646 TCGv t[2];
1647 int size = memsize_zz(dc);
1648
1649 LOG_DIS("lsr.%c $r%u, $r%u\n",
1650 memsize_char(size), dc->op1, dc->op2);
1651
1652 cris_cc_mask(dc, CC_MASK_NZ);
1653 cris_alu_alloc_temps(dc, size, t);
1654 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1655 tcg_gen_andi_tl(t[1], t[1], 63);
1656 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1657 cris_alu_free_temps(dc, size, t);
1658 return 2;
1659 }
1660
1661 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1662 {
1663 TCGv t[2];
1664 int size = memsize_zz(dc);
1665
1666 LOG_DIS("asr.%c $r%u, $r%u\n",
1667 memsize_char(size), dc->op1, dc->op2);
1668
1669 cris_cc_mask(dc, CC_MASK_NZ);
1670 cris_alu_alloc_temps(dc, size, t);
1671 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1672 tcg_gen_andi_tl(t[1], t[1], 63);
1673 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1674 cris_alu_free_temps(dc, size, t);
1675 return 2;
1676 }
1677
1678 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1679 {
1680 TCGv t[2];
1681 int size = memsize_zz(dc);
1682
1683 LOG_DIS("muls.%c $r%u, $r%u\n",
1684 memsize_char(size), dc->op1, dc->op2);
1685 cris_cc_mask(dc, CC_MASK_NZV);
1686 cris_alu_alloc_temps(dc, size, t);
1687 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1688
1689 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1690 cris_alu_free_temps(dc, size, t);
1691 return 2;
1692 }
1693
1694 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1695 {
1696 TCGv t[2];
1697 int size = memsize_zz(dc);
1698
1699 LOG_DIS("mulu.%c $r%u, $r%u\n",
1700 memsize_char(size), dc->op1, dc->op2);
1701 cris_cc_mask(dc, CC_MASK_NZV);
1702 cris_alu_alloc_temps(dc, size, t);
1703 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1704
1705 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1706 cris_alu_alloc_temps(dc, size, t);
1707 return 2;
1708 }
1709
1710
1711 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1712 {
1713 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1714 cris_cc_mask(dc, CC_MASK_NZ);
1715 cris_alu(dc, CC_OP_DSTEP,
1716 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1717 return 2;
1718 }
1719
1720 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1721 {
1722 TCGv t[2];
1723 int size = memsize_zz(dc);
1724 LOG_DIS("xor.%c $r%u, $r%u\n",
1725 memsize_char(size), dc->op1, dc->op2);
1726 BUG_ON(size != 4); /* xor is dword. */
1727 cris_cc_mask(dc, CC_MASK_NZ);
1728 cris_alu_alloc_temps(dc, size, t);
1729 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1730
1731 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1732 cris_alu_free_temps(dc, size, t);
1733 return 2;
1734 }
1735
1736 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1737 {
1738 TCGv l0;
1739 int size = memsize_zz(dc);
1740 LOG_DIS("bound.%c $r%u, $r%u\n",
1741 memsize_char(size), dc->op1, dc->op2);
1742 cris_cc_mask(dc, CC_MASK_NZ);
1743 l0 = tcg_temp_local_new();
1744 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1745 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1746 tcg_temp_free(l0);
1747 return 2;
1748 }
1749
1750 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1751 {
1752 TCGv t[2];
1753 int size = memsize_zz(dc);
1754 LOG_DIS("cmp.%c $r%u, $r%u\n",
1755 memsize_char(size), dc->op1, dc->op2);
1756 cris_cc_mask(dc, CC_MASK_NZVC);
1757 cris_alu_alloc_temps(dc, size, t);
1758 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1759
1760 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1761 cris_alu_free_temps(dc, size, t);
1762 return 2;
1763 }
1764
1765 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1766 {
1767 TCGv t0;
1768
1769 LOG_DIS("abs $r%u, $r%u\n",
1770 dc->op1, dc->op2);
1771 cris_cc_mask(dc, CC_MASK_NZ);
1772
1773 t0 = tcg_temp_new();
1774 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1775 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1776 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1777 tcg_temp_free(t0);
1778
1779 cris_alu(dc, CC_OP_MOVE,
1780 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1781 return 2;
1782 }
1783
1784 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1785 {
1786 TCGv t[2];
1787 int size = memsize_zz(dc);
1788 LOG_DIS("add.%c $r%u, $r%u\n",
1789 memsize_char(size), dc->op1, dc->op2);
1790 cris_cc_mask(dc, CC_MASK_NZVC);
1791 cris_alu_alloc_temps(dc, size, t);
1792 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1793
1794 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1795 cris_alu_free_temps(dc, size, t);
1796 return 2;
1797 }
1798
1799 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1800 {
1801 LOG_DIS("addc $r%u, $r%u\n",
1802 dc->op1, dc->op2);
1803 cris_evaluate_flags(dc);
1804 /* Set for this insn. */
1805 dc->flagx_known = 1;
1806 dc->flags_x = X_FLAG;
1807
1808 cris_cc_mask(dc, CC_MASK_NZVC);
1809 cris_alu(dc, CC_OP_ADDC,
1810 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1811 return 2;
1812 }
1813
1814 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1815 {
1816 LOG_DIS("mcp $p%u, $r%u\n",
1817 dc->op2, dc->op1);
1818 cris_evaluate_flags(dc);
1819 cris_cc_mask(dc, CC_MASK_RNZV);
1820 cris_alu(dc, CC_OP_MCP,
1821 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1822 return 2;
1823 }
1824
1825 #if DISAS_CRIS
1826 static char * swapmode_name(int mode, char *modename) {
1827 int i = 0;
1828 if (mode & 8)
1829 modename[i++] = 'n';
1830 if (mode & 4)
1831 modename[i++] = 'w';
1832 if (mode & 2)
1833 modename[i++] = 'b';
1834 if (mode & 1)
1835 modename[i++] = 'r';
1836 modename[i++] = 0;
1837 return modename;
1838 }
1839 #endif
1840
1841 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1842 {
1843 TCGv t0;
1844 #if DISAS_CRIS
1845 char modename[4];
1846 #endif
1847 LOG_DIS("swap%s $r%u\n",
1848 swapmode_name(dc->op2, modename), dc->op1);
1849
1850 cris_cc_mask(dc, CC_MASK_NZ);
1851 t0 = tcg_temp_new();
1852 t_gen_mov_TN_reg(t0, dc->op1);
1853 if (dc->op2 & 8)
1854 tcg_gen_not_tl(t0, t0);
1855 if (dc->op2 & 4)
1856 t_gen_swapw(t0, t0);
1857 if (dc->op2 & 2)
1858 t_gen_swapb(t0, t0);
1859 if (dc->op2 & 1)
1860 t_gen_swapr(t0, t0);
1861 cris_alu(dc, CC_OP_MOVE,
1862 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1863 tcg_temp_free(t0);
1864 return 2;
1865 }
1866
1867 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1868 {
1869 TCGv t[2];
1870 int size = memsize_zz(dc);
1871 LOG_DIS("or.%c $r%u, $r%u\n",
1872 memsize_char(size), dc->op1, dc->op2);
1873 cris_cc_mask(dc, CC_MASK_NZ);
1874 cris_alu_alloc_temps(dc, size, t);
1875 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1876 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1877 cris_alu_free_temps(dc, size, t);
1878 return 2;
1879 }
1880
1881 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1882 {
1883 TCGv t0;
1884 LOG_DIS("addi.%c $r%u, $r%u\n",
1885 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1886 cris_cc_mask(dc, 0);
1887 t0 = tcg_temp_new();
1888 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1889 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1890 tcg_temp_free(t0);
1891 return 2;
1892 }
1893
1894 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1895 {
1896 TCGv t0;
1897 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1898 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1899 cris_cc_mask(dc, 0);
1900 t0 = tcg_temp_new();
1901 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1902 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1903 tcg_temp_free(t0);
1904 return 2;
1905 }
1906
1907 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1908 {
1909 TCGv t[2];
1910 int size = memsize_zz(dc);
1911 LOG_DIS("neg.%c $r%u, $r%u\n",
1912 memsize_char(size), dc->op1, dc->op2);
1913 cris_cc_mask(dc, CC_MASK_NZVC);
1914 cris_alu_alloc_temps(dc, size, t);
1915 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1916
1917 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1918 cris_alu_free_temps(dc, size, t);
1919 return 2;
1920 }
1921
1922 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1923 {
1924 LOG_DIS("btst $r%u, $r%u\n",
1925 dc->op1, dc->op2);
1926 cris_cc_mask(dc, CC_MASK_NZ);
1927 cris_evaluate_flags(dc);
1928 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1929 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1930 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1931 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1932 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1933 dc->flags_uptodate = 1;
1934 return 2;
1935 }
1936
1937 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1938 {
1939 TCGv t[2];
1940 int size = memsize_zz(dc);
1941 LOG_DIS("sub.%c $r%u, $r%u\n",
1942 memsize_char(size), dc->op1, dc->op2);
1943 cris_cc_mask(dc, CC_MASK_NZVC);
1944 cris_alu_alloc_temps(dc, size, t);
1945 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1946 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1947 cris_alu_free_temps(dc, size, t);
1948 return 2;
1949 }
1950
1951 /* Zero extension. From size to dword. */
1952 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1953 {
1954 TCGv t0;
1955 int size = memsize_z(dc);
1956 LOG_DIS("movu.%c $r%u, $r%u\n",
1957 memsize_char(size),
1958 dc->op1, dc->op2);
1959
1960 cris_cc_mask(dc, CC_MASK_NZ);
1961 t0 = tcg_temp_new();
1962 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1963 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1964 tcg_temp_free(t0);
1965 return 2;
1966 }
1967
1968 /* Sign extension. From size to dword. */
1969 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1970 {
1971 TCGv t0;
1972 int size = memsize_z(dc);
1973 LOG_DIS("movs.%c $r%u, $r%u\n",
1974 memsize_char(size),
1975 dc->op1, dc->op2);
1976
1977 cris_cc_mask(dc, CC_MASK_NZ);
1978 t0 = tcg_temp_new();
1979 /* Size can only be qi or hi. */
1980 t_gen_sext(t0, cpu_R[dc->op1], size);
1981 cris_alu(dc, CC_OP_MOVE,
1982 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1983 tcg_temp_free(t0);
1984 return 2;
1985 }
1986
1987 /* zero extension. From size to dword. */
1988 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1989 {
1990 TCGv t0;
1991 int size = memsize_z(dc);
1992 LOG_DIS("addu.%c $r%u, $r%u\n",
1993 memsize_char(size),
1994 dc->op1, dc->op2);
1995
1996 cris_cc_mask(dc, CC_MASK_NZVC);
1997 t0 = tcg_temp_new();
1998 /* Size can only be qi or hi. */
1999 t_gen_zext(t0, cpu_R[dc->op1], size);
2000 cris_alu(dc, CC_OP_ADD,
2001 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2002 tcg_temp_free(t0);
2003 return 2;
2004 }
2005
2006 /* Sign extension. From size to dword. */
2007 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
2008 {
2009 TCGv t0;
2010 int size = memsize_z(dc);
2011 LOG_DIS("adds.%c $r%u, $r%u\n",
2012 memsize_char(size),
2013 dc->op1, dc->op2);
2014
2015 cris_cc_mask(dc, CC_MASK_NZVC);
2016 t0 = tcg_temp_new();
2017 /* Size can only be qi or hi. */
2018 t_gen_sext(t0, cpu_R[dc->op1], size);
2019 cris_alu(dc, CC_OP_ADD,
2020 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2021 tcg_temp_free(t0);
2022 return 2;
2023 }
2024
2025 /* Zero extension. From size to dword. */
2026 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
2027 {
2028 TCGv t0;
2029 int size = memsize_z(dc);
2030 LOG_DIS("subu.%c $r%u, $r%u\n",
2031 memsize_char(size),
2032 dc->op1, dc->op2);
2033
2034 cris_cc_mask(dc, CC_MASK_NZVC);
2035 t0 = tcg_temp_new();
2036 /* Size can only be qi or hi. */
2037 t_gen_zext(t0, cpu_R[dc->op1], size);
2038 cris_alu(dc, CC_OP_SUB,
2039 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2040 tcg_temp_free(t0);
2041 return 2;
2042 }
2043
2044 /* Sign extension. From size to dword. */
2045 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
2046 {
2047 TCGv t0;
2048 int size = memsize_z(dc);
2049 LOG_DIS("subs.%c $r%u, $r%u\n",
2050 memsize_char(size),
2051 dc->op1, dc->op2);
2052
2053 cris_cc_mask(dc, CC_MASK_NZVC);
2054 t0 = tcg_temp_new();
2055 /* Size can only be qi or hi. */
2056 t_gen_sext(t0, cpu_R[dc->op1], size);
2057 cris_alu(dc, CC_OP_SUB,
2058 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2059 tcg_temp_free(t0);
2060 return 2;
2061 }
2062
2063 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
2064 {
2065 uint32_t flags;
2066 int set = (~dc->opcode >> 2) & 1;
2067
2068
2069 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2070 | EXTRACT_FIELD(dc->ir, 0, 3);
2071 if (set && flags == 0) {
2072 LOG_DIS("nop\n");
2073 return 2;
2074 } else if (!set && (flags & 0x20)) {
2075 LOG_DIS("di\n");
2076 }
2077 else {
2078 LOG_DIS("%sf %x\n",
2079 set ? "set" : "clr",
2080 flags);
2081 }
2082
2083 /* User space is not allowed to touch these. Silently ignore. */
2084 if (dc->tb_flags & U_FLAG) {
2085 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2086 }
2087
2088 if (flags & X_FLAG) {
2089 dc->flagx_known = 1;
2090 if (set)
2091 dc->flags_x = X_FLAG;
2092 else
2093 dc->flags_x = 0;
2094 }
2095
2096 /* Break the TB if any of the SPI flag changes. */
2097 if (flags & (P_FLAG | S_FLAG)) {
2098 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2099 dc->is_jmp = DISAS_UPDATE;
2100 dc->cpustate_changed = 1;
2101 }
2102
2103 /* For the I flag, only act on posedge. */
2104 if ((flags & I_FLAG)) {
2105 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2106 dc->is_jmp = DISAS_UPDATE;
2107 dc->cpustate_changed = 1;
2108 }
2109
2110
2111 /* Simply decode the flags. */
2112 cris_evaluate_flags (dc);
2113 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2114 cris_update_cc_x(dc);
2115 tcg_gen_movi_tl(cc_op, dc->cc_op);
2116
2117 if (set) {
2118 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2119 /* Enter user mode. */
2120 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2121 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2122 dc->cpustate_changed = 1;
2123 }
2124 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2125 }
2126 else
2127 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2128
2129 dc->flags_uptodate = 1;
2130 dc->clear_x = 0;
2131 return 2;
2132 }
2133
2134 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2135 {
2136 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2137 cris_cc_mask(dc, 0);
2138 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2139 tcg_const_tl(dc->op1));
2140 return 2;
2141 }
2142 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2143 {
2144 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2145 cris_cc_mask(dc, 0);
2146 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2147 tcg_const_tl(dc->op2));
2148 return 2;
2149 }
2150
2151 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2152 {
2153 TCGv t[2];
2154 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2155 cris_cc_mask(dc, 0);
2156
2157 t[0] = tcg_temp_new();
2158 if (dc->op2 == PR_CCS) {
2159 cris_evaluate_flags(dc);
2160 t_gen_mov_TN_reg(t[0], dc->op1);
2161 if (dc->tb_flags & U_FLAG) {
2162 t[1] = tcg_temp_new();
2163 /* User space is not allowed to touch all flags. */
2164 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2165 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2166 tcg_gen_or_tl(t[0], t[1], t[0]);
2167 tcg_temp_free(t[1]);
2168 }
2169 }
2170 else
2171 t_gen_mov_TN_reg(t[0], dc->op1);
2172
2173 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2174 if (dc->op2 == PR_CCS) {
2175 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2176 dc->flags_uptodate = 1;
2177 }
2178 tcg_temp_free(t[0]);
2179 return 2;
2180 }
2181 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2182 {
2183 TCGv t0;
2184 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2185 cris_cc_mask(dc, 0);
2186
2187 if (dc->op2 == PR_CCS)
2188 cris_evaluate_flags(dc);
2189
2190 if (dc->op2 == PR_DZ) {
2191 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2192 } else {
2193 t0 = tcg_temp_new();
2194 t_gen_mov_TN_preg(t0, dc->op2);
2195 cris_alu(dc, CC_OP_MOVE,
2196 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2197 preg_sizes[dc->op2]);
2198 tcg_temp_free(t0);
2199 }
2200 return 2;
2201 }
2202
2203 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2204 {
2205 int memsize = memsize_zz(dc);
2206 int insn_len;
2207 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2208 memsize_char(memsize),
2209 dc->op1, dc->postinc ? "+]" : "]",
2210 dc->op2);
2211
2212 if (memsize == 4) {
2213 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2214 cris_cc_mask(dc, CC_MASK_NZ);
2215 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2216 cris_update_cc_x(dc);
2217 cris_update_result(dc, cpu_R[dc->op2]);
2218 }
2219 else {
2220 TCGv t0;
2221
2222 t0 = tcg_temp_new();
2223 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2224 cris_cc_mask(dc, CC_MASK_NZ);
2225 cris_alu(dc, CC_OP_MOVE,
2226 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2227 tcg_temp_free(t0);
2228 }
2229 do_postinc(dc, memsize);
2230 return insn_len;
2231 }
2232
2233 static inline void cris_alu_m_alloc_temps(TCGv *t)
2234 {
2235 t[0] = tcg_temp_new();
2236 t[1] = tcg_temp_new();
2237 }
2238
2239 static inline void cris_alu_m_free_temps(TCGv *t)
2240 {
2241 tcg_temp_free(t[0]);
2242 tcg_temp_free(t[1]);
2243 }
2244
2245 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2246 {
2247 TCGv t[2];
2248 int memsize = memsize_z(dc);
2249 int insn_len;
2250 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2251 memsize_char(memsize),
2252 dc->op1, dc->postinc ? "+]" : "]",
2253 dc->op2);
2254
2255 cris_alu_m_alloc_temps(t);
2256 /* sign extend. */
2257 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2258 cris_cc_mask(dc, CC_MASK_NZ);
2259 cris_alu(dc, CC_OP_MOVE,
2260 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2261 do_postinc(dc, memsize);
2262 cris_alu_m_free_temps(t);
2263 return insn_len;
2264 }
2265
2266 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2267 {
2268 TCGv t[2];
2269 int memsize = memsize_z(dc);
2270 int insn_len;
2271 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2272 memsize_char(memsize),
2273 dc->op1, dc->postinc ? "+]" : "]",
2274 dc->op2);
2275
2276 cris_alu_m_alloc_temps(t);
2277 /* sign extend. */
2278 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2279 cris_cc_mask(dc, CC_MASK_NZVC);
2280 cris_alu(dc, CC_OP_ADD,
2281 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2282 do_postinc(dc, memsize);
2283 cris_alu_m_free_temps(t);
2284 return insn_len;
2285 }
2286
2287 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2288 {
2289 TCGv t[2];
2290 int memsize = memsize_z(dc);
2291 int insn_len;
2292 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2293 memsize_char(memsize),
2294 dc->op1, dc->postinc ? "+]" : "]",
2295 dc->op2);
2296
2297 cris_alu_m_alloc_temps(t);
2298 /* sign extend. */
2299 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2300 cris_cc_mask(dc, CC_MASK_NZVC);
2301 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2302 do_postinc(dc, memsize);
2303 cris_alu_m_free_temps(t);
2304 return insn_len;
2305 }
2306
2307 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2308 {
2309 TCGv t[2];
2310 int memsize = memsize_z(dc);
2311 int insn_len;
2312 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2313 memsize_char(memsize),
2314 dc->op1, dc->postinc ? "+]" : "]",
2315 dc->op2);
2316
2317 cris_alu_m_alloc_temps(t);
2318 /* sign extend. */
2319 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2320 cris_cc_mask(dc, CC_MASK_NZVC);
2321 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2322 do_postinc(dc, memsize);
2323 cris_alu_m_free_temps(t);
2324 return insn_len;
2325 }
2326
2327 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2328 {
2329 TCGv t[2];
2330 int memsize = memsize_z(dc);
2331 int insn_len;
2332 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2333 memsize_char(memsize),
2334 dc->op1, dc->postinc ? "+]" : "]",
2335 dc->op2);
2336
2337 cris_alu_m_alloc_temps(t);
2338 /* sign extend. */
2339 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2340 cris_cc_mask(dc, CC_MASK_NZVC);
2341 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2342 do_postinc(dc, memsize);
2343 cris_alu_m_free_temps(t);
2344 return insn_len;
2345 }
2346
2347 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2348 {
2349 TCGv t[2];
2350 int memsize = memsize_z(dc);
2351 int insn_len;
2352
2353 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2354 memsize_char(memsize),
2355 dc->op1, dc->postinc ? "+]" : "]",
2356 dc->op2);
2357
2358 cris_alu_m_alloc_temps(t);
2359 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2360 cris_cc_mask(dc, CC_MASK_NZ);
2361 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2362 do_postinc(dc, memsize);
2363 cris_alu_m_free_temps(t);
2364 return insn_len;
2365 }
2366
2367 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2368 {
2369 TCGv t[2];
2370 int memsize = memsize_z(dc);
2371 int insn_len;
2372 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2373 memsize_char(memsize),
2374 dc->op1, dc->postinc ? "+]" : "]",
2375 dc->op2);
2376
2377 cris_alu_m_alloc_temps(t);
2378 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2379 cris_cc_mask(dc, CC_MASK_NZVC);
2380 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2381 do_postinc(dc, memsize);
2382 cris_alu_m_free_temps(t);
2383 return insn_len;
2384 }
2385
2386 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2387 {
2388 TCGv t[2];
2389 int memsize = memsize_z(dc);
2390 int insn_len;
2391 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2392 memsize_char(memsize),
2393 dc->op1, dc->postinc ? "+]" : "]",
2394 dc->op2);
2395
2396 cris_alu_m_alloc_temps(t);
2397 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2398 cris_cc_mask(dc, CC_MASK_NZVC);
2399 cris_alu(dc, CC_OP_CMP,
2400 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2401 memsize_zz(dc));
2402 do_postinc(dc, memsize);
2403 cris_alu_m_free_temps(t);
2404 return insn_len;
2405 }
2406
2407 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2408 {
2409 TCGv t[2];
2410 int memsize = memsize_zz(dc);
2411 int insn_len;
2412 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2413 memsize_char(memsize),
2414 dc->op1, dc->postinc ? "+]" : "]",
2415 dc->op2);
2416
2417 cris_alu_m_alloc_temps(t);
2418 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2419 cris_cc_mask(dc, CC_MASK_NZVC);
2420 cris_alu(dc, CC_OP_CMP,
2421 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2422 memsize_zz(dc));
2423 do_postinc(dc, memsize);
2424 cris_alu_m_free_temps(t);
2425 return insn_len;
2426 }
2427
2428 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2429 {
2430 TCGv t[2];
2431 int memsize = memsize_zz(dc);
2432 int insn_len;
2433 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2434 memsize_char(memsize),
2435 dc->op1, dc->postinc ? "+]" : "]",
2436 dc->op2);
2437
2438 cris_evaluate_flags(dc);
2439
2440 cris_alu_m_alloc_temps(t);
2441 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2442 cris_cc_mask(dc, CC_MASK_NZ);
2443 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2444
2445 cris_alu(dc, CC_OP_CMP,
2446 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2447 do_postinc(dc, memsize);
2448 cris_alu_m_free_temps(t);
2449 return insn_len;
2450 }
2451
2452 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2453 {
2454 TCGv t[2];
2455 int memsize = memsize_zz(dc);
2456 int insn_len;
2457 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2458 memsize_char(memsize),
2459 dc->op1, dc->postinc ? "+]" : "]",
2460 dc->op2);
2461
2462 cris_alu_m_alloc_temps(t);
2463 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2464 cris_cc_mask(dc, CC_MASK_NZ);
2465 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2466 do_postinc(dc, memsize);
2467 cris_alu_m_free_temps(t);
2468 return insn_len;
2469 }
2470
2471 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2472 {
2473 TCGv t[2];
2474 int memsize = memsize_zz(dc);
2475 int insn_len;
2476 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2477 memsize_char(memsize),
2478 dc->op1, dc->postinc ? "+]" : "]",
2479 dc->op2);
2480
2481 cris_alu_m_alloc_temps(t);
2482 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2483 cris_cc_mask(dc, CC_MASK_NZVC);
2484 cris_alu(dc, CC_OP_ADD,
2485 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2486 do_postinc(dc, memsize);
2487 cris_alu_m_free_temps(t);
2488 return insn_len;
2489 }
2490
2491 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2492 {
2493 TCGv t[2];
2494 int memsize = memsize_zz(dc);
2495 int insn_len;
2496 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2497 memsize_char(memsize),
2498 dc->op1, dc->postinc ? "+]" : "]",
2499 dc->op2);
2500
2501 cris_alu_m_alloc_temps(t);
2502 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2503 cris_cc_mask(dc, 0);
2504 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2505 do_postinc(dc, memsize);
2506 cris_alu_m_free_temps(t);
2507 return insn_len;
2508 }
2509
2510 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2511 {
2512 TCGv l[2];
2513 int memsize = memsize_zz(dc);
2514 int insn_len;
2515 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2516 memsize_char(memsize),
2517 dc->op1, dc->postinc ? "+]" : "]",
2518 dc->op2);
2519
2520 l[0] = tcg_temp_local_new();
2521 l[1] = tcg_temp_local_new();
2522 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2523 cris_cc_mask(dc, CC_MASK_NZ);
2524 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2525 do_postinc(dc, memsize);
2526 tcg_temp_free(l[0]);
2527 tcg_temp_free(l[1]);
2528 return insn_len;
2529 }
2530
2531 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2532 {
2533 TCGv t[2];
2534 int insn_len = 2;
2535 LOG_DIS("addc [$r%u%s, $r%u\n",
2536 dc->op1, dc->postinc ? "+]" : "]",
2537 dc->op2);
2538
2539 cris_evaluate_flags(dc);
2540
2541 /* Set for this insn. */
2542 dc->flagx_known = 1;
2543 dc->flags_x = X_FLAG;
2544
2545 cris_alu_m_alloc_temps(t);
2546 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2547 cris_cc_mask(dc, CC_MASK_NZVC);
2548 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2549 do_postinc(dc, 4);
2550 cris_alu_m_free_temps(t);
2551 return insn_len;
2552 }
2553
2554 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2555 {
2556 TCGv t[2];
2557 int memsize = memsize_zz(dc);
2558 int insn_len;
2559 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2560 memsize_char(memsize),
2561 dc->op1, dc->postinc ? "+]" : "]",
2562 dc->op2, dc->ir, dc->zzsize);
2563
2564 cris_alu_m_alloc_temps(t);
2565 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2566 cris_cc_mask(dc, CC_MASK_NZVC);
2567 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2568 do_postinc(dc, memsize);
2569 cris_alu_m_free_temps(t);
2570 return insn_len;
2571 }
2572
2573 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2574 {
2575 TCGv t[2];
2576 int memsize = memsize_zz(dc);
2577 int insn_len;
2578 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2579 memsize_char(memsize),
2580 dc->op1, dc->postinc ? "+]" : "]",
2581 dc->op2, dc->pc);
2582
2583 cris_alu_m_alloc_temps(t);
2584 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2585 cris_cc_mask(dc, CC_MASK_NZ);
2586 cris_alu(dc, CC_OP_OR,
2587 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2588 do_postinc(dc, memsize);
2589 cris_alu_m_free_temps(t);
2590 return insn_len;
2591 }
2592
2593 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2594 {
2595 TCGv t[2];
2596 int memsize = memsize_zz(dc);
2597 int insn_len = 2;
2598
2599 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2600 memsize_char(memsize),
2601 dc->op1,
2602 dc->postinc ? "+]" : "]",
2603 dc->op2);
2604
2605 cris_alu_m_alloc_temps(t);
2606 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2607 cris_cc_mask(dc, 0);
2608 if (dc->op2 == PR_CCS) {
2609 cris_evaluate_flags(dc);
2610 if (dc->tb_flags & U_FLAG) {
2611 /* User space is not allowed to touch all flags. */
2612 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2613 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2614 tcg_gen_or_tl(t[1], t[0], t[1]);
2615 }
2616 }
2617
2618 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2619
2620 do_postinc(dc, memsize);
2621 cris_alu_m_free_temps(t);
2622 return insn_len;
2623 }
2624
2625 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2626 {
2627 TCGv t0;
2628 int memsize;
2629
2630 memsize = preg_sizes[dc->op2];
2631
2632 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2633 memsize_char(memsize),
2634 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2635
2636 /* prepare store. Address in T0, value in T1. */
2637 if (dc->op2 == PR_CCS)
2638 cris_evaluate_flags(dc);
2639 t0 = tcg_temp_new();
2640 t_gen_mov_TN_preg(t0, dc->op2);
2641 cris_flush_cc_state(dc);
2642 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2643 tcg_temp_free(t0);
2644
2645 cris_cc_mask(dc, 0);
2646 if (dc->postinc)
2647 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2648 return 2;
2649 }
2650
2651 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2652 {
2653 TCGv_i64 tmp[16];
2654 TCGv tmp32;
2655 TCGv addr;
2656 int i;
2657 int nr = dc->op2 + 1;
2658
2659 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2660 dc->postinc ? "+]" : "]", dc->op2);
2661
2662 addr = tcg_temp_new();
2663 /* There are probably better ways of doing this. */
2664 cris_flush_cc_state(dc);
2665 for (i = 0; i < (nr >> 1); i++) {
2666 tmp[i] = tcg_temp_new_i64();
2667 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2668 gen_load64(dc, tmp[i], addr);
2669 }
2670 if (nr & 1) {
2671 tmp32 = tcg_temp_new_i32();
2672 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2673 gen_load(dc, tmp32, addr, 4, 0);
2674 } else
2675 TCGV_UNUSED(tmp32);
2676 tcg_temp_free(addr);
2677
2678 for (i = 0; i < (nr >> 1); i++) {
2679 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2680 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2681 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2682 tcg_temp_free_i64(tmp[i]);
2683 }
2684 if (nr & 1) {
2685 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2686 tcg_temp_free(tmp32);
2687 }
2688
2689 /* writeback the updated pointer value. */
2690 if (dc->postinc)
2691 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2692
2693 /* gen_load might want to evaluate the previous insns flags. */
2694 cris_cc_mask(dc, 0);
2695 return 2;
2696 }
2697
2698 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2699 {
2700 TCGv tmp;
2701 TCGv addr;
2702 int i;
2703
2704 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2705 dc->postinc ? "+]" : "]");
2706
2707 cris_flush_cc_state(dc);
2708
2709 tmp = tcg_temp_new();
2710 addr = tcg_temp_new();
2711 tcg_gen_movi_tl(tmp, 4);
2712 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2713 for (i = 0; i <= dc->op2; i++) {
2714 /* Displace addr. */
2715 /* Perform the store. */
2716 gen_store(dc, addr, cpu_R[i], 4);
2717 tcg_gen_add_tl(addr, addr, tmp);
2718 }
2719 if (dc->postinc)
2720 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2721 cris_cc_mask(dc, 0);
2722 tcg_temp_free(tmp);
2723 tcg_temp_free(addr);
2724 return 2;
2725 }
2726
2727 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2728 {
2729 int memsize;
2730
2731 memsize = memsize_zz(dc);
2732
2733 LOG_DIS("move.%c $r%u, [$r%u]\n",
2734 memsize_char(memsize), dc->op2, dc->op1);
2735
2736 /* prepare store. */
2737 cris_flush_cc_state(dc);
2738 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2739
2740 if (dc->postinc)
2741 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2742 cris_cc_mask(dc, 0);
2743 return 2;
2744 }
2745
2746 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2747 {
2748 LOG_DIS("lapcq %x, $r%u\n",
2749 dc->pc + dc->op1*2, dc->op2);
2750 cris_cc_mask(dc, 0);
2751 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2752 return 2;
2753 }
2754
2755 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2756 {
2757 unsigned int rd;
2758 int32_t imm;
2759 int32_t pc;
2760
2761 rd = dc->op2;
2762
2763 cris_cc_mask(dc, 0);
2764 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2765 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2766
2767 pc = dc->pc;
2768 pc += imm;
2769 tcg_gen_movi_tl(cpu_R[rd], pc);
2770 return 6;
2771 }
2772
2773 /* Jump to special reg. */
2774 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2775 {
2776 LOG_DIS("jump $p%u\n", dc->op2);
2777
2778 if (dc->op2 == PR_CCS)
2779 cris_evaluate_flags(dc);
2780 t_gen_mov_TN_preg(env_btarget, dc->op2);
2781 /* rete will often have low bit set to indicate delayslot. */
2782 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2783 cris_cc_mask(dc, 0);
2784 cris_prepare_jmp(dc, JMP_INDIRECT);
2785 return 2;
2786 }
2787
2788 /* Jump and save. */
2789 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2790 {
2791 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2792 cris_cc_mask(dc, 0);
2793 /* Store the return address in Pd. */
2794 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2795 if (dc->op2 > 15)
2796 abort();
2797 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2798
2799 cris_prepare_jmp(dc, JMP_INDIRECT);
2800 return 2;
2801 }
2802
2803 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2804 {
2805 uint32_t imm;
2806
2807 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2808
2809 LOG_DIS("jas 0x%x\n", imm);
2810 cris_cc_mask(dc, 0);
2811 /* Store the return address in Pd. */
2812 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2813
2814 dc->jmp_pc = imm;
2815 cris_prepare_jmp(dc, JMP_DIRECT);
2816 return 6;
2817 }
2818
2819 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2820 {
2821 uint32_t imm;
2822
2823 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2824
2825 LOG_DIS("jasc 0x%x\n", imm);
2826 cris_cc_mask(dc, 0);
2827 /* Store the return address in Pd. */
2828 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2829
2830 dc->jmp_pc = imm;
2831 cris_prepare_jmp(dc, JMP_DIRECT);
2832 return 6;
2833 }
2834
2835 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2836 {
2837 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2838 cris_cc_mask(dc, 0);
2839 /* Store the return address in Pd. */
2840 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2841 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2842 cris_prepare_jmp(dc, JMP_INDIRECT);
2843 return 2;
2844 }
2845
2846 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2847 {
2848 int32_t offset;
2849 uint32_t cond = dc->op2;
2850
2851 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2852
2853 LOG_DIS("b%s %d pc=%x dst=%x\n",
2854 cc_name(cond), offset,
2855 dc->pc, dc->pc + offset);
2856
2857 cris_cc_mask(dc, 0);
2858 /* op2 holds the condition-code. */
2859 cris_prepare_cc_branch (dc, offset, cond);
2860 return 4;
2861 }
2862
2863 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2864 {
2865 int32_t simm;
2866
2867
2868 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2869
2870 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2871 cris_cc_mask(dc, 0);
2872 /* Store the return address in Pd. */
2873 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2874
2875 dc->jmp_pc = dc->pc + simm;
2876 cris_prepare_jmp(dc, JMP_DIRECT);
2877 return 6;
2878 }
2879
2880 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2881 {
2882 int32_t simm;
2883 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2884
2885 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2886 cris_cc_mask(dc, 0);
2887 /* Store the return address in Pd. */
2888 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2889
2890 dc->jmp_pc = dc->pc + simm;
2891 cris_prepare_jmp(dc, JMP_DIRECT);
2892 return 6;
2893 }
2894
2895 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2896 {
2897 cris_cc_mask(dc, 0);
2898
2899 if (dc->op2 == 15) {
2900 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2901 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2902 t_gen_raise_exception(EXCP_HLT);
2903 return 2;
2904 }
2905
2906 switch (dc->op2 & 7) {
2907 case 2:
2908 /* rfe. */
2909 LOG_DIS("rfe\n");
2910 cris_evaluate_flags(dc);
2911 gen_helper_rfe(cpu_env);
2912 dc->is_jmp = DISAS_UPDATE;
2913 break;
2914 case 5:
2915 /* rfn. */
2916 LOG_DIS("rfn\n");
2917 cris_evaluate_flags(dc);
2918 gen_helper_rfn(cpu_env);
2919 dc->is_jmp = DISAS_UPDATE;
2920 break;
2921 case 6:
2922 LOG_DIS("break %d\n", dc->op1);
2923 cris_evaluate_flags (dc);
2924 /* break. */
2925 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2926
2927 /* Breaks start at 16 in the exception vector. */
2928 t_gen_mov_env_TN(trap_vector,
2929 tcg_const_tl(dc->op1 + 16));
2930 t_gen_raise_exception(EXCP_BREAK);
2931 dc->is_jmp = DISAS_UPDATE;
2932 break;
2933 default:
2934 printf ("op2=%x\n", dc->op2);
2935 BUG();
2936 break;
2937
2938 }
2939 return 2;
2940 }
2941
2942 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2943 {
2944 return 2;
2945 }
2946
2947 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2948 {
2949 return 2;
2950 }
2951
2952 static int dec_null(CPUCRISState *env, DisasContext *dc)
2953 {
2954 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2955 dc->pc, dc->opcode, dc->op1, dc->op2);
2956 fflush(NULL);
2957 BUG();
2958 return 2;
2959 }
2960
2961 static struct decoder_info {
2962 struct {
2963 uint32_t bits;
2964 uint32_t mask;
2965 };
2966 int (*dec)(CPUCRISState *env, DisasContext *dc);
2967 } decinfo[] = {
2968 /* Order matters here. */
2969 {DEC_MOVEQ, dec_moveq},
2970 {DEC_BTSTQ, dec_btstq},
2971 {DEC_CMPQ, dec_cmpq},
2972 {DEC_ADDOQ, dec_addoq},
2973 {DEC_ADDQ, dec_addq},
2974 {DEC_SUBQ, dec_subq},
2975 {DEC_ANDQ, dec_andq},
2976 {DEC_ORQ, dec_orq},
2977 {DEC_ASRQ, dec_asrq},
2978 {DEC_LSLQ, dec_lslq},
2979 {DEC_LSRQ, dec_lsrq},
2980 {DEC_BCCQ, dec_bccq},
2981
2982 {DEC_BCC_IM, dec_bcc_im},
2983 {DEC_JAS_IM, dec_jas_im},
2984 {DEC_JAS_R, dec_jas_r},
2985 {DEC_JASC_IM, dec_jasc_im},
2986 {DEC_JASC_R, dec_jasc_r},
2987 {DEC_BAS_IM, dec_bas_im},
2988 {DEC_BASC_IM, dec_basc_im},
2989 {DEC_JUMP_P, dec_jump_p},
2990 {DEC_LAPC_IM, dec_lapc_im},
2991 {DEC_LAPCQ, dec_lapcq},
2992
2993 {DEC_RFE_ETC, dec_rfe_etc},
2994 {DEC_ADDC_MR, dec_addc_mr},
2995
2996 {DEC_MOVE_MP, dec_move_mp},
2997 {DEC_MOVE_PM, dec_move_pm},
2998 {DEC_MOVEM_MR, dec_movem_mr},
2999 {DEC_MOVEM_RM, dec_movem_rm},
3000 {DEC_MOVE_PR, dec_move_pr},
3001 {DEC_SCC_R, dec_scc_r},
3002 {DEC_SETF, dec_setclrf},
3003 {DEC_CLEARF, dec_setclrf},
3004
3005 {DEC_MOVE_SR, dec_move_sr},
3006 {DEC_MOVE_RP, dec_move_rp},
3007 {DEC_SWAP_R, dec_swap_r},
3008 {DEC_ABS_R, dec_abs_r},
3009 {DEC_LZ_R, dec_lz_r},
3010 {DEC_MOVE_RS, dec_move_rs},
3011 {DEC_BTST_R, dec_btst_r},
3012 {DEC_ADDC_R, dec_addc_r},
3013
3014 {DEC_DSTEP_R, dec_dstep_r},
3015 {DEC_XOR_R, dec_xor_r},
3016 {DEC_MCP_R, dec_mcp_r},
3017 {DEC_CMP_R, dec_cmp_r},
3018
3019 {DEC_ADDI_R, dec_addi_r},
3020 {DEC_ADDI_ACR, dec_addi_acr},
3021
3022 {DEC_ADD_R, dec_add_r},
3023 {DEC_SUB_R, dec_sub_r},
3024
3025 {DEC_ADDU_R, dec_addu_r},
3026 {DEC_ADDS_R, dec_adds_r},
3027 {DEC_SUBU_R, dec_subu_r},
3028 {DEC_SUBS_R, dec_subs_r},
3029 {DEC_LSL_R, dec_lsl_r},
3030
3031 {DEC_AND_R, dec_and_r},
3032 {DEC_OR_R, dec_or_r},
3033 {DEC_BOUND_R, dec_bound_r},
3034 {DEC_ASR_R, dec_asr_r},
3035 {DEC_LSR_R, dec_lsr_r},
3036
3037 {DEC_MOVU_R, dec_movu_r},
3038 {DEC_MOVS_R, dec_movs_r},
3039 {DEC_NEG_R, dec_neg_r},
3040 {DEC_MOVE_R, dec_move_r},
3041
3042 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3043 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3044
3045 {DEC_MULS_R, dec_muls_r},
3046 {DEC_MULU_R, dec_mulu_r},
3047
3048 {DEC_ADDU_M, dec_addu_m},
3049 {DEC_ADDS_M, dec_adds_m},
3050 {DEC_SUBU_M, dec_subu_m},
3051 {DEC_SUBS_M, dec_subs_m},
3052
3053 {DEC_CMPU_M, dec_cmpu_m},
3054 {DEC_CMPS_M, dec_cmps_m},
3055 {DEC_MOVU_M, dec_movu_m},
3056 {DEC_MOVS_M, dec_movs_m},
3057
3058 {DEC_CMP_M, dec_cmp_m},
3059 {DEC_ADDO_M, dec_addo_m},
3060 {DEC_BOUND_M, dec_bound_m},
3061 {DEC_ADD_M, dec_add_m},
3062 {DEC_SUB_M, dec_sub_m},
3063 {DEC_AND_M, dec_and_m},
3064 {DEC_OR_M, dec_or_m},
3065 {DEC_MOVE_RM, dec_move_rm},
3066 {DEC_TEST_M, dec_test_m},
3067 {DEC_MOVE_MR, dec_move_mr},
3068
3069 {{0, 0}, dec_null}
3070 };
3071
3072 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3073 {
3074 int insn_len = 2;
3075 int i;
3076
3077 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
3078 tcg_gen_debug_insn_start(dc->pc);
3079
3080 /* Load a halfword onto the instruction register. */
3081 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3082
3083 /* Now decode it. */
3084 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3085 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3086 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3087 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3088 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3089 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3090
3091 /* Large switch for all insns. */
3092 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3093 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3094 {
3095 insn_len = decinfo[i].dec(env, dc);
3096 break;
3097 }
3098 }
3099
3100 #if !defined(CONFIG_USER_ONLY)
3101 /* Single-stepping ? */
3102 if (dc->tb_flags & S_FLAG) {
3103 int l1;
3104
3105 l1 = gen_new_label();
3106 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3107 /* We treat SPC as a break with an odd trap vector. */
3108 cris_evaluate_flags (dc);
3109 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3110 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3111 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3112 t_gen_raise_exception(EXCP_BREAK);
3113 gen_set_label(l1);
3114 }
3115 #endif
3116 return insn_len;
3117 }
3118
3119 static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
3120 {
3121 CPUBreakpoint *bp;
3122
3123 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3124 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3125 if (bp->pc == dc->pc) {
3126 cris_evaluate_flags (dc);
3127 tcg_gen_movi_tl(env_pc, dc->pc);
3128 t_gen_raise_exception(EXCP_DEBUG);
3129 dc->is_jmp = DISAS_UPDATE;
3130 }
3131 }
3132 }
3133 }
3134
3135 #include "translate_v10.c"
3136
3137 /*
3138 * Delay slots on QEMU/CRIS.
3139 *
3140 * If an exception hits on a delayslot, the core will let ERP (the Exception
3141 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3142 * to give SW a hint that the exception actually hit on the dslot.
3143 *
3144 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3145 * the core and any jmp to an odd addresses will mask off that lsb. It is
3146 * simply there to let sw know there was an exception on a dslot.
3147 *
3148 * When the software returns from an exception, the branch will re-execute.
3149 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3150 * and the branch and delayslot dont share pages.
3151 *
3152 * The TB contaning the branch insn will set up env->btarget and evaluate
3153 * env->btaken. When the translation loop exits we will note that the branch
3154 * sequence is broken and let env->dslot be the size of the branch insn (those
3155 * vary in length).
3156 *
3157 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3158 * set). It will also expect to have env->dslot setup with the size of the
3159 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3160 * will execute the dslot and take the branch, either to btarget or just one
3161 * insn ahead.
3162 *
3163 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3164 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3165 * branch and set lsb). Then env->dslot gets cleared so that the exception
3166 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3167 * masked off and we will reexecute the branch insn.
3168 *
3169 */
3170
3171 /* generate intermediate code for basic block 'tb'. */
3172 static void
3173 gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb,
3174 int search_pc)
3175 {
3176 uint16_t *gen_opc_end;
3177 uint32_t pc_start;
3178 unsigned int insn_len;
3179 int j, lj;
3180 struct DisasContext ctx;
3181 struct DisasContext *dc = &ctx;
3182 uint32_t next_page_start;
3183 target_ulong npc;
3184 int num_insns;
3185 int max_insns;
3186
3187 qemu_log_try_set_file(stderr);
3188
3189 if (env->pregs[PR_VR] == 32) {
3190 dc->decoder = crisv32_decoder;
3191 dc->clear_locked_irq = 0;
3192 } else {
3193 dc->decoder = crisv10_decoder;
3194 dc->clear_locked_irq = 1;
3195 }
3196
3197 /* Odd PC indicates that branch is rexecuting due to exception in the
3198 * delayslot, like in real hw.
3199 */
3200 pc_start = tb->pc & ~1;
3201 dc->env = env;
3202 dc->tb = tb;
3203
3204 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3205
3206 dc->is_jmp = DISAS_NEXT;
3207 dc->ppc = pc_start;
3208 dc->pc = pc_start;
3209 dc->singlestep_enabled = env->singlestep_enabled;
3210 dc->flags_uptodate = 1;
3211 dc->flagx_known = 1;
3212 dc->flags_x = tb->flags & X_FLAG;
3213 dc->cc_x_uptodate = 0;
3214 dc->cc_mask = 0;
3215 dc->update_cc = 0;
3216 dc->clear_prefix = 0;
3217
3218 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3219 dc->cc_size_uptodate = -1;
3220
3221 /* Decode TB flags. */
3222 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3223 | X_FLAG | PFIX_FLAG);
3224 dc->delayed_branch = !!(tb->flags & 7);
3225 if (dc->delayed_branch)
3226 dc->jmp = JMP_INDIRECT;
3227 else
3228 dc->jmp = JMP_NOJMP;
3229
3230 dc->cpustate_changed = 0;
3231
3232 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3233 qemu_log(
3234 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3235 "pid=%x usp=%x\n"
3236 "%x.%x.%x.%x\n"
3237 "%x.%x.%x.%x\n"
3238 "%x.%x.%x.%x\n"
3239 "%x.%x.%x.%x\n",
3240 search_pc, dc->pc, dc->ppc,
3241 (uint64_t)tb->flags,
3242 env->btarget, (unsigned)tb->flags & 7,
3243 env->pregs[PR_CCS],
3244 env->pregs[PR_PID], env->pregs[PR_USP],
3245 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3246 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3247 env->regs[8], env->regs[9],
3248 env->regs[10], env->regs[11],
3249 env->regs[12], env->regs[13],
3250 env->regs[14], env->regs[15]);
3251 qemu_log("--------------\n");
3252 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3253 }
3254
3255 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3256 lj = -1;
3257 num_insns = 0;
3258 max_insns = tb->cflags & CF_COUNT_MASK;
3259 if (max_insns == 0)
3260 max_insns = CF_COUNT_MASK;
3261
3262 gen_icount_start();
3263 do
3264 {
3265 check_breakpoint(env, dc);
3266
3267 if (search_pc) {
3268 j = gen_opc_ptr - gen_opc_buf;
3269 if (lj < j) {
3270 lj++;
3271 while (lj < j)
3272 gen_opc_instr_start[lj++] = 0;
3273 }
3274 if (dc->delayed_branch == 1)
3275 gen_opc_pc[lj] = dc->ppc | 1;
3276 else
3277 gen_opc_pc[lj] = dc->pc;
3278 gen_opc_instr_start[lj] = 1;
3279 gen_opc_icount[lj] = num_insns;
3280 }
3281
3282 /* Pretty disas. */
3283 LOG_DIS("%8.8x:\t", dc->pc);
3284
3285 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3286 gen_io_start();
3287 dc->clear_x = 1;
3288
3289 insn_len = dc->decoder(env, dc);
3290 dc->ppc = dc->pc;
3291 dc->pc += insn_len;
3292 if (dc->clear_x)
3293 cris_clear_x_flag(dc);
3294
3295 num_insns++;
3296 /* Check for delayed branches here. If we do it before
3297 actually generating any host code, the simulator will just
3298 loop doing nothing for on this program location. */
3299 if (dc->delayed_branch) {
3300 dc->delayed_branch--;
3301 if (dc->delayed_branch == 0)
3302 {
3303 if (tb->flags & 7)
3304 t_gen_mov_env_TN(dslot,
3305 tcg_const_tl(0));
3306 if (dc->cpustate_changed || !dc->flagx_known
3307 || (dc->flags_x != (tb->flags & X_FLAG))) {
3308 cris_store_direct_jmp(dc);
3309 }
3310
3311 if (dc->clear_locked_irq) {
3312 dc->clear_locked_irq = 0;
3313 t_gen_mov_env_TN(locked_irq,
3314 tcg_const_tl(0));
3315 }
3316
3317 if (dc->jmp == JMP_DIRECT_CC) {
3318 int l1;
3319
3320 l1 = gen_new_label();
3321 cris_evaluate_flags(dc);
3322
3323 /* Conditional jmp. */
3324 tcg_gen_brcondi_tl(TCG_COND_EQ,
3325 env_btaken, 0, l1);
3326 gen_goto_tb(dc, 1, dc->jmp_pc);
3327 gen_set_label(l1);
3328 gen_goto_tb(dc, 0, dc->pc);
3329 dc->is_jmp = DISAS_TB_JUMP;
3330 dc->jmp = JMP_NOJMP;
3331 } else if (dc->jmp == JMP_DIRECT) {
3332 cris_evaluate_flags(dc);
3333 gen_goto_tb(dc, 0, dc->jmp_pc);
3334 dc->is_jmp = DISAS_TB_JUMP;
3335 dc->jmp = JMP_NOJMP;
3336 } else {
3337 t_gen_cc_jmp(env_btarget,
3338 tcg_const_tl(dc->pc));
3339 dc->is_jmp = DISAS_JUMP;
3340 }
3341 break;
3342 }
3343 }
3344
3345 /* If we are rexecuting a branch due to exceptions on
3346 delay slots dont break. */
3347 if (!(tb->pc & 1) && env->singlestep_enabled)
3348 break;
3349 } while (!dc->is_jmp && !dc->cpustate_changed
3350 && gen_opc_ptr < gen_opc_end
3351 && !singlestep
3352 && (dc->pc < next_page_start)
3353 && num_insns < max_insns);
3354
3355 if (dc->clear_locked_irq)
3356 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3357
3358 npc = dc->pc;
3359
3360 if (tb->cflags & CF_LAST_IO)
3361 gen_io_end();
3362 /* Force an update if the per-tb cpu state has changed. */
3363 if (dc->is_jmp == DISAS_NEXT
3364 && (dc->cpustate_changed || !dc->flagx_known
3365 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3366 dc->is_jmp = DISAS_UPDATE;
3367 tcg_gen_movi_tl(env_pc, npc);
3368 }
3369 /* Broken branch+delayslot sequence. */
3370 if (dc->delayed_branch == 1) {
3371 /* Set env->dslot to the size of the branch insn. */
3372 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3373 cris_store_direct_jmp(dc);
3374 }
3375
3376 cris_evaluate_flags (dc);
3377
3378 if (unlikely(env->singlestep_enabled)) {
3379 if (dc->is_jmp == DISAS_NEXT)
3380 tcg_gen_movi_tl(env_pc, npc);
3381 t_gen_raise_exception(EXCP_DEBUG);
3382 } else {
3383 switch(dc->is_jmp) {
3384 case DISAS_NEXT:
3385 gen_goto_tb(dc, 1, npc);
3386 break;
3387 default:
3388 case DISAS_JUMP:
3389 case DISAS_UPDATE:
3390 /* indicate that the hash table must be used
3391 to find the next TB */
3392 tcg_gen_exit_tb(0);
3393 break;
3394 case DISAS_SWI:
3395 case DISAS_TB_JUMP:
3396 /* nothing more to generate */
3397 break;
3398 }
3399 }
3400 gen_icount_end(tb, num_insns);
3401 *gen_opc_ptr = INDEX_op_end;
3402 if (search_pc) {
3403 j = gen_opc_ptr - gen_opc_buf;
3404 lj++;
3405 while (lj <= j)
3406 gen_opc_instr_start[lj++] = 0;
3407 } else {
3408 tb->size = dc->pc - pc_start;
3409 tb->icount = num_insns;
3410 }
3411
3412 #ifdef DEBUG_DISAS
3413 #if !DISAS_CRIS
3414 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3415 log_target_disas(pc_start, dc->pc - pc_start,
3416 dc->env->pregs[PR_VR]);
3417 qemu_log("\nisize=%d osize=%td\n",
3418 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3419 }
3420 #endif
3421 #endif
3422 }
3423
3424 void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
3425 {
3426 gen_intermediate_code_internal(env, tb, 0);
3427 }
3428
3429 void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
3430 {
3431 gen_intermediate_code_internal(env, tb, 1);
3432 }
3433
3434 void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf,
3435 int flags)
3436 {
3437 int i;
3438 uint32_t srs;
3439
3440 if (!env || !f)
3441 return;
3442
3443 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3444 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3445 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3446 env->cc_op,
3447 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3448
3449
3450 for (i = 0; i < 16; i++) {
3451 cpu_fprintf(f, "%s=%8.8x ",regnames[i], env->regs[i]);
3452 if ((i + 1) % 4 == 0)
3453 cpu_fprintf(f, "\n");
3454 }
3455 cpu_fprintf(f, "\nspecial regs:\n");
3456 for (i = 0; i < 16; i++) {
3457 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3458 if ((i + 1) % 4 == 0)
3459 cpu_fprintf(f, "\n");
3460 }
3461 srs = env->pregs[PR_SRS];
3462 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3463 if (srs < ARRAY_SIZE(env->sregs)) {
3464 for (i = 0; i < 16; i++) {
3465 cpu_fprintf(f, "s%2.2d=%8.8x ",
3466 i, env->sregs[srs][i]);
3467 if ((i + 1) % 4 == 0)
3468 cpu_fprintf(f, "\n");
3469 }
3470 }
3471 cpu_fprintf(f, "\n\n");
3472
3473 }
3474
3475 struct
3476 {
3477 uint32_t vr;
3478 const char *name;
3479 } cris_cores[] = {
3480 {8, "crisv8"},
3481 {9, "crisv9"},
3482 {10, "crisv10"},
3483 {11, "crisv11"},
3484 {32, "crisv32"},
3485 };
3486
3487 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3488 {
3489 unsigned int i;
3490
3491 (*cpu_fprintf)(f, "Available CPUs:\n");
3492 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3493 (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
3494 }
3495 }
3496
3497 static uint32_t vr_by_name(const char *name)
3498 {
3499 unsigned int i;
3500 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3501 if (strcmp(name, cris_cores[i].name) == 0) {
3502 return cris_cores[i].vr;
3503 }
3504 }
3505 return 32;
3506 }
3507
3508 CRISCPU *cpu_cris_init(const char *cpu_model)
3509 {
3510 CRISCPU *cpu;
3511 CPUCRISState *env;
3512 static int tcg_initialized = 0;
3513 int i;
3514
3515 cpu = CRIS_CPU(object_new(TYPE_CRIS_CPU));
3516 env = &cpu->env;
3517
3518 env->pregs[PR_VR] = vr_by_name(cpu_model);
3519
3520 cpu_reset(CPU(cpu));
3521 qemu_init_vcpu(env);
3522
3523 if (tcg_initialized) {
3524 return cpu;
3525 }
3526
3527 tcg_initialized = 1;
3528
3529 #define GEN_HELPER 2
3530 #include "helper.h"
3531
3532 if (env->pregs[PR_VR] < 32) {
3533 cpu_crisv10_init(env);
3534 return cpu;
3535 }
3536
3537
3538 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3539 cc_x = tcg_global_mem_new(TCG_AREG0,
3540 offsetof(CPUCRISState, cc_x), "cc_x");
3541 cc_src = tcg_global_mem_new(TCG_AREG0,
3542 offsetof(CPUCRISState, cc_src), "cc_src");
3543 cc_dest = tcg_global_mem_new(TCG_AREG0,
3544 offsetof(CPUCRISState, cc_dest),
3545 "cc_dest");
3546 cc_result = tcg_global_mem_new(TCG_AREG0,
3547 offsetof(CPUCRISState, cc_result),
3548 "cc_result");
3549 cc_op = tcg_global_mem_new(TCG_AREG0,
3550 offsetof(CPUCRISState, cc_op), "cc_op");
3551 cc_size = tcg_global_mem_new(TCG_AREG0,
3552 offsetof(CPUCRISState, cc_size),
3553 "cc_size");
3554 cc_mask = tcg_global_mem_new(TCG_AREG0,
3555 offsetof(CPUCRISState, cc_mask),
3556 "cc_mask");
3557
3558 env_pc = tcg_global_mem_new(TCG_AREG0,
3559 offsetof(CPUCRISState, pc),
3560 "pc");
3561 env_btarget = tcg_global_mem_new(TCG_AREG0,
3562 offsetof(CPUCRISState, btarget),
3563 "btarget");
3564 env_btaken = tcg_global_mem_new(TCG_AREG0,
3565 offsetof(CPUCRISState, btaken),
3566 "btaken");
3567 for (i = 0; i < 16; i++) {
3568 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3569 offsetof(CPUCRISState, regs[i]),
3570 regnames[i]);
3571 }
3572 for (i = 0; i < 16; i++) {
3573 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3574 offsetof(CPUCRISState, pregs[i]),
3575 pregnames[i]);
3576 }
3577
3578 return cpu;
3579 }
3580
3581 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
3582 {
3583 env->pc = gen_opc_pc[pc_pos];
3584 }
Qemu copy for testing