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Update to a hopefully more future proof FSF address
[qemu.git] / target-cris / translate_v10.c
1 /*
2 * CRISv10 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2010 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "crisv10-decode.h"
22
23 static const char *regnames_v10[] =
24 {
25 "$r0", "$r1", "$r2", "$r3",
26 "$r4", "$r5", "$r6", "$r7",
27 "$r8", "$r9", "$r10", "$r11",
28 "$r12", "$r13", "$sp", "$pc",
29 };
30
31 static const char *pregnames_v10[] =
32 {
33 "$bz", "$vr", "$p2", "$p3",
34 "$wz", "$ccr", "$p6-prefix", "$mof",
35 "$dz", "$ibr", "$irp", "$srp",
36 "$bar", "$dccr", "$brp", "$usp",
37 };
38
39 /* We need this table to handle preg-moves with implicit width. */
40 static int preg_sizes_v10[] = {
41 1, /* bz. */
42 1, /* vr. */
43 1, /* pid. */
44 1, /* srs. */
45 2, /* wz. */
46 2, 2, 4,
47 4, 4, 4, 4,
48 4, 4, 4, 4,
49 };
50
51 static inline int dec10_size(unsigned int size)
52 {
53 size++;
54 if (size == 3)
55 size++;
56 return size;
57 }
58
59 static inline void cris_illegal_insn(DisasContext *dc)
60 {
61 qemu_log("illegal insn at pc=%x\n", dc->pc);
62 t_gen_raise_exception(EXCP_BREAK);
63 }
64
65 /* Prefix flag and register are used to handle the more complex
66 addressing modes. */
67 static void cris_set_prefix(DisasContext *dc)
68 {
69 dc->clear_prefix = 0;
70 dc->tb_flags |= PFIX_FLAG;
71 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
72
73 /* prefix insns dont clear the x flag. */
74 dc->clear_x = 0;
75 cris_lock_irq(dc);
76 }
77
78 static void crisv10_prepare_memaddr(DisasContext *dc,
79 TCGv addr, unsigned int size)
80 {
81 if (dc->tb_flags & PFIX_FLAG) {
82 tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
83 } else {
84 tcg_gen_mov_tl(addr, cpu_R[dc->src]);
85 }
86 }
87
88 static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
89 {
90 unsigned int insn_len = 0;
91
92 if (dc->tb_flags & PFIX_FLAG) {
93 if (dc->mode == CRISV10_MODE_AUTOINC) {
94 tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
95 }
96 } else {
97 if (dc->mode == CRISV10_MODE_AUTOINC) {
98 if (dc->src == 15) {
99 insn_len += size & ~1;
100 } else {
101 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
102 }
103 }
104 }
105 return insn_len;
106 }
107
108 static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
109 TCGv dst)
110 {
111 unsigned int rs, rd;
112 uint32_t imm;
113 int is_imm;
114 int insn_len = 0;
115
116 rs = dc->src;
117 rd = dc->dst;
118 is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
119 LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
120 rs, rd, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
121
122 /* Load [$rs] onto T1. */
123 if (is_imm) {
124 if (memsize != 4) {
125 if (s_ext) {
126 if (memsize == 1)
127 imm = ldsb_code(dc->pc + 2);
128 else
129 imm = ldsw_code(dc->pc + 2);
130 } else {
131 if (memsize == 1)
132 imm = ldub_code(dc->pc + 2);
133 else
134 imm = lduw_code(dc->pc + 2);
135 }
136 } else
137 imm = ldl_code(dc->pc + 2);
138
139 tcg_gen_movi_tl(dst, imm);
140
141 if (dc->mode == CRISV10_MODE_AUTOINC) {
142 insn_len += memsize;
143 if (memsize == 1)
144 insn_len++;
145 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
146 }
147 } else {
148 TCGv addr;
149
150 addr = tcg_temp_new();
151 cris_flush_cc_state(dc);
152 crisv10_prepare_memaddr(dc, addr, memsize);
153 gen_load(dc, dst, addr, memsize, 0);
154 if (s_ext)
155 t_gen_sext(dst, dst, memsize);
156 else
157 t_gen_zext(dst, dst, memsize);
158 insn_len += crisv10_post_memaddr(dc, memsize);
159 tcg_temp_free(addr);
160 }
161
162 if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
163 dc->dst = dc->src;
164 }
165 return insn_len;
166 }
167
168 static unsigned int dec10_quick_imm(DisasContext *dc)
169 {
170 int32_t imm, simm;
171 int op;
172
173 /* sign extend. */
174 imm = dc->ir & ((1 << 6) - 1);
175 simm = (int8_t) (imm << 2);
176 simm >>= 2;
177 switch (dc->opcode) {
178 case CRISV10_QIMM_BDAP_R0:
179 case CRISV10_QIMM_BDAP_R1:
180 case CRISV10_QIMM_BDAP_R2:
181 case CRISV10_QIMM_BDAP_R3:
182 simm = (int8_t)dc->ir;
183 LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
184 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
185 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
186 cris_set_prefix(dc);
187 if (dc->dst == 15) {
188 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
189 } else {
190 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
191 }
192 break;
193
194 case CRISV10_QIMM_MOVEQ:
195 LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
196
197 cris_cc_mask(dc, CC_MASK_NZVC);
198 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
199 cpu_R[dc->dst], tcg_const_tl(simm), 4);
200 break;
201 case CRISV10_QIMM_CMPQ:
202 LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
203
204 cris_cc_mask(dc, CC_MASK_NZVC);
205 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
206 cpu_R[dc->dst], tcg_const_tl(simm), 4);
207 break;
208 case CRISV10_QIMM_ADDQ:
209 LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
210
211 cris_cc_mask(dc, CC_MASK_NZVC);
212 cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
213 cpu_R[dc->dst], tcg_const_tl(imm), 4);
214 break;
215 case CRISV10_QIMM_ANDQ:
216 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
217
218 cris_cc_mask(dc, CC_MASK_NZVC);
219 cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
220 cpu_R[dc->dst], tcg_const_tl(simm), 4);
221 break;
222 case CRISV10_QIMM_ASHQ:
223 LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
224
225 cris_cc_mask(dc, CC_MASK_NZVC);
226 op = imm & (1 << 5);
227 imm &= 0x1f;
228 if (op) {
229 cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
230 cpu_R[dc->dst], tcg_const_tl(imm), 4);
231 } else {
232 /* BTST */
233 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
234 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
235 tcg_const_tl(imm), cpu_PR[PR_CCS]);
236 }
237 break;
238 case CRISV10_QIMM_LSHQ:
239 LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
240
241 op = CC_OP_LSL;
242 if (imm & (1 << 5)) {
243 op = CC_OP_LSR;
244 }
245 imm &= 0x1f;
246 cris_cc_mask(dc, CC_MASK_NZVC);
247 cris_alu(dc, op, cpu_R[dc->dst],
248 cpu_R[dc->dst], tcg_const_tl(imm), 4);
249 break;
250 case CRISV10_QIMM_SUBQ:
251 LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
252
253 cris_cc_mask(dc, CC_MASK_NZVC);
254 cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
255 cpu_R[dc->dst], tcg_const_tl(imm), 4);
256 break;
257 case CRISV10_QIMM_ORQ:
258 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
259
260 cris_cc_mask(dc, CC_MASK_NZVC);
261 cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
262 cpu_R[dc->dst], tcg_const_tl(simm), 4);
263 break;
264
265 case CRISV10_QIMM_BCC_R0:
266 if (!dc->ir) {
267 cpu_abort(dc->env, "opcode zero\n");
268 }
269 case CRISV10_QIMM_BCC_R1:
270 case CRISV10_QIMM_BCC_R2:
271 case CRISV10_QIMM_BCC_R3:
272 imm = dc->ir & 0xff;
273 /* bit 0 is a sign bit. */
274 if (imm & 1) {
275 imm |= 0xffffff00; /* sign extend. */
276 imm &= ~1; /* get rid of the sign bit. */
277 }
278 imm += 2;
279 LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
280
281 cris_cc_mask(dc, 0);
282 cris_prepare_cc_branch(dc, imm, dc->cond);
283 break;
284
285 default:
286 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
287 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
288 assert(0);
289 break;
290 }
291 return 2;
292 }
293
294 static unsigned int dec10_setclrf(DisasContext *dc)
295 {
296 uint32_t flags;
297 unsigned int set = ~dc->opcode & 1;
298
299 flags = EXTRACT_FIELD(dc->ir, 0, 3)
300 | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
301 LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
302
303
304 if (flags & X_FLAG) {
305 dc->flagx_known = 1;
306 if (set)
307 dc->flags_x = X_FLAG;
308 else
309 dc->flags_x = 0;
310 }
311
312 cris_evaluate_flags (dc);
313 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
314 cris_update_cc_x(dc);
315 tcg_gen_movi_tl(cc_op, dc->cc_op);
316
317 if (set) {
318 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
319 } else {
320 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
321 }
322
323 dc->flags_uptodate = 1;
324 dc->clear_x = 0;
325 cris_lock_irq(dc);
326 return 2;
327 }
328
329 static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
330 TCGv dd, TCGv ds, TCGv sd, TCGv ss)
331 {
332 if (sext) {
333 t_gen_sext(dd, sd, size);
334 t_gen_sext(ds, ss, size);
335 } else {
336 t_gen_zext(dd, sd, size);
337 t_gen_zext(ds, ss, size);
338 }
339 }
340
341 static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
342 {
343 TCGv t[2];
344
345 t[0] = tcg_temp_new();
346 t[1] = tcg_temp_new();
347 dec10_reg_prep_sext(dc, size, sext,
348 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
349
350 if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
351 tcg_gen_andi_tl(t[1], t[1], 63);
352 }
353
354 assert(dc->dst != 15);
355 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
356 tcg_temp_free(t[0]);
357 tcg_temp_free(t[1]);
358 }
359
360 static void dec10_reg_bound(DisasContext *dc, int size)
361 {
362 TCGv t;
363
364 t = tcg_temp_local_new();
365 t_gen_zext(t, cpu_R[dc->src], size);
366 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
367 tcg_temp_free(t);
368 }
369
370 static void dec10_reg_mul(DisasContext *dc, int size, int sext)
371 {
372 int op = sext ? CC_OP_MULS : CC_OP_MULU;
373 TCGv t[2];
374
375 t[0] = tcg_temp_new();
376 t[1] = tcg_temp_new();
377 dec10_reg_prep_sext(dc, size, sext,
378 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
379
380 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
381
382 tcg_temp_free(t[0]);
383 tcg_temp_free(t[1]);
384 }
385
386
387 static void dec10_reg_movs(DisasContext *dc)
388 {
389 int size = (dc->size & 1) + 1;
390 TCGv t;
391
392 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
393 cris_cc_mask(dc, CC_MASK_NZVC);
394
395 t = tcg_temp_new();
396 if (dc->ir & 32)
397 t_gen_sext(t, cpu_R[dc->src], size);
398 else
399 t_gen_zext(t, cpu_R[dc->src], size);
400
401 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
402 tcg_temp_free(t);
403 }
404
405 static void dec10_reg_alux(DisasContext *dc, int op)
406 {
407 int size = (dc->size & 1) + 1;
408 TCGv t;
409
410 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
411 cris_cc_mask(dc, CC_MASK_NZVC);
412
413 t = tcg_temp_new();
414 if (dc->ir & 32)
415 t_gen_sext(t, cpu_R[dc->src], size);
416 else
417 t_gen_zext(t, cpu_R[dc->src], size);
418
419 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
420 tcg_temp_free(t);
421 }
422
423 static void dec10_reg_mov_pr(DisasContext *dc)
424 {
425 LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
426 cris_lock_irq(dc);
427 if (dc->src == 15) {
428 tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
429 cris_prepare_jmp(dc, JMP_INDIRECT);
430 return;
431 }
432 if (dc->dst == PR_CCS) {
433 cris_evaluate_flags(dc);
434 }
435 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
436 cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
437 }
438
439 static void dec10_reg_abs(DisasContext *dc)
440 {
441 TCGv t0;
442
443 LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
444
445 assert(dc->dst != 15);
446 t0 = tcg_temp_new();
447 tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
448 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
449 tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
450
451 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
452 tcg_temp_free(t0);
453 }
454
455 static void dec10_reg_swap(DisasContext *dc)
456 {
457 TCGv t0;
458
459 LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
460
461 cris_cc_mask(dc, CC_MASK_NZVC);
462 t0 = tcg_temp_new();
463 t_gen_mov_TN_reg(t0, dc->src);
464 if (dc->dst & 8)
465 tcg_gen_not_tl(t0, t0);
466 if (dc->dst & 4)
467 t_gen_swapw(t0, t0);
468 if (dc->dst & 2)
469 t_gen_swapb(t0, t0);
470 if (dc->dst & 1)
471 t_gen_swapr(t0, t0);
472 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
473 tcg_temp_free(t0);
474 }
475
476 static void dec10_reg_scc(DisasContext *dc)
477 {
478 int cond = dc->dst;
479
480 LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
481
482 if (cond != CC_A)
483 {
484 int l1;
485
486 gen_tst_cc (dc, cpu_R[dc->src], cond);
487 l1 = gen_new_label();
488 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->src], 0, l1);
489 tcg_gen_movi_tl(cpu_R[dc->src], 1);
490 gen_set_label(l1);
491 } else {
492 tcg_gen_movi_tl(cpu_R[dc->src], 1);
493 }
494
495 cris_cc_mask(dc, 0);
496 }
497
498 static unsigned int dec10_reg(DisasContext *dc)
499 {
500 TCGv t;
501 unsigned int insn_len = 2;
502 unsigned int size = dec10_size(dc->size);
503 unsigned int tmp;
504
505 if (dc->size != 3) {
506 switch (dc->opcode) {
507 case CRISV10_REG_MOVE_R:
508 LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
509 cris_cc_mask(dc, CC_MASK_NZVC);
510 dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
511 if (dc->dst == 15) {
512 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
513 cris_prepare_jmp(dc, JMP_INDIRECT);
514 dc->delayed_branch = 1;
515 }
516 break;
517 case CRISV10_REG_MOVX:
518 cris_cc_mask(dc, CC_MASK_NZVC);
519 dec10_reg_movs(dc);
520 break;
521 case CRISV10_REG_ADDX:
522 cris_cc_mask(dc, CC_MASK_NZVC);
523 dec10_reg_alux(dc, CC_OP_ADD);
524 break;
525 case CRISV10_REG_SUBX:
526 cris_cc_mask(dc, CC_MASK_NZVC);
527 dec10_reg_alux(dc, CC_OP_SUB);
528 break;
529 case CRISV10_REG_ADD:
530 LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
531 cris_cc_mask(dc, CC_MASK_NZVC);
532 dec10_reg_alu(dc, CC_OP_ADD, size, 0);
533 break;
534 case CRISV10_REG_SUB:
535 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
536 cris_cc_mask(dc, CC_MASK_NZVC);
537 dec10_reg_alu(dc, CC_OP_SUB, size, 0);
538 break;
539 case CRISV10_REG_CMP:
540 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
541 cris_cc_mask(dc, CC_MASK_NZVC);
542 dec10_reg_alu(dc, CC_OP_CMP, size, 0);
543 break;
544 case CRISV10_REG_BOUND:
545 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
546 cris_cc_mask(dc, CC_MASK_NZVC);
547 dec10_reg_bound(dc, size);
548 break;
549 case CRISV10_REG_AND:
550 LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
551 cris_cc_mask(dc, CC_MASK_NZVC);
552 dec10_reg_alu(dc, CC_OP_AND, size, 0);
553 break;
554 case CRISV10_REG_ADDI:
555 if (dc->src == 15) {
556 /* nop. */
557 return 2;
558 }
559 t = tcg_temp_new();
560 LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
561 tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
562 tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
563 tcg_temp_free(t);
564 break;
565 case CRISV10_REG_LSL:
566 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
567 cris_cc_mask(dc, CC_MASK_NZVC);
568 dec10_reg_alu(dc, CC_OP_LSL, size, 0);
569 break;
570 case CRISV10_REG_LSR:
571 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
572 cris_cc_mask(dc, CC_MASK_NZVC);
573 dec10_reg_alu(dc, CC_OP_LSR, size, 0);
574 break;
575 case CRISV10_REG_ASR:
576 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
577 cris_cc_mask(dc, CC_MASK_NZVC);
578 dec10_reg_alu(dc, CC_OP_ASR, size, 1);
579 break;
580 case CRISV10_REG_OR:
581 LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
582 cris_cc_mask(dc, CC_MASK_NZVC);
583 dec10_reg_alu(dc, CC_OP_OR, size, 0);
584 break;
585 case CRISV10_REG_NEG:
586 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
587 cris_cc_mask(dc, CC_MASK_NZVC);
588 dec10_reg_alu(dc, CC_OP_NEG, size, 0);
589 break;
590 case CRISV10_REG_BIAP:
591 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
592 dc->opcode, dc->src, dc->dst, size);
593 switch (size) {
594 case 4: tmp = 2; break;
595 case 2: tmp = 1; break;
596 case 1: tmp = 0; break;
597 default: assert(0); break;
598 }
599
600 t = tcg_temp_new();
601 tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
602 if (dc->src == 15) {
603 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
604 } else {
605 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
606 }
607 tcg_temp_free(t);
608 cris_set_prefix(dc);
609 break;
610
611 default:
612 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
613 dc->opcode, dc->src, dc->dst);
614 assert(0);
615 break;
616 }
617 } else {
618 switch (dc->opcode) {
619 case CRISV10_REG_MOVX:
620 cris_cc_mask(dc, CC_MASK_NZVC);
621 dec10_reg_movs(dc);
622 break;
623 case CRISV10_REG_ADDX:
624 cris_cc_mask(dc, CC_MASK_NZVC);
625 dec10_reg_alux(dc, CC_OP_ADD);
626 break;
627 case CRISV10_REG_SUBX:
628 cris_cc_mask(dc, CC_MASK_NZVC);
629 dec10_reg_alux(dc, CC_OP_SUB);
630 break;
631 case CRISV10_REG_MOVE_SPR_R:
632 cris_evaluate_flags(dc);
633 cris_cc_mask(dc, 0);
634 dec10_reg_mov_pr(dc);
635 break;
636 case CRISV10_REG_MOVE_R_SPR:
637 LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
638 cris_evaluate_flags(dc);
639 if (dc->src != 11) /* fast for srp. */
640 dc->cpustate_changed = 1;
641 t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
642 break;
643 case CRISV10_REG_SETF:
644 case CRISV10_REG_CLEARF:
645 dec10_setclrf(dc);
646 break;
647 case CRISV10_REG_SWAP:
648 dec10_reg_swap(dc);
649 break;
650 case CRISV10_REG_ABS:
651 cris_cc_mask(dc, CC_MASK_NZVC);
652 dec10_reg_abs(dc);
653 break;
654 case CRISV10_REG_LZ:
655 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
656 cris_cc_mask(dc, CC_MASK_NZVC);
657 dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
658 break;
659 case CRISV10_REG_XOR:
660 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
661 cris_cc_mask(dc, CC_MASK_NZVC);
662 dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
663 break;
664 case CRISV10_REG_BTST:
665 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
666 cris_cc_mask(dc, CC_MASK_NZVC);
667 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
668 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
669 cpu_R[dc->src], cpu_PR[PR_CCS]);
670 break;
671 case CRISV10_REG_DSTEP:
672 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
673 cris_cc_mask(dc, CC_MASK_NZVC);
674 cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
675 cpu_R[dc->dst], cpu_R[dc->src], 4);
676 break;
677 case CRISV10_REG_MSTEP:
678 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
679 cris_evaluate_flags(dc);
680 cris_cc_mask(dc, CC_MASK_NZVC);
681 cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
682 cpu_R[dc->dst], cpu_R[dc->src], 4);
683 break;
684 case CRISV10_REG_SCC:
685 dec10_reg_scc(dc);
686 break;
687 default:
688 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
689 dc->opcode, dc->src, dc->dst);
690 assert(0);
691 break;
692 }
693 }
694 return insn_len;
695 }
696
697 static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size)
698 {
699 unsigned int insn_len = 2;
700 TCGv t;
701
702 LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
703 size, dc->src, dc->dst);
704
705 cris_cc_mask(dc, CC_MASK_NZVC);
706 t = tcg_temp_new();
707 insn_len += dec10_prep_move_m(dc, 0, size, t);
708 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
709 if (dc->dst == 15) {
710 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
711 cris_prepare_jmp(dc, JMP_INDIRECT);
712 dc->delayed_branch = 1;
713 return insn_len;
714 }
715
716 tcg_temp_free(t);
717 return insn_len;
718 }
719
720 static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
721 {
722 unsigned int insn_len = 2;
723 TCGv addr;
724
725 LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
726 addr = tcg_temp_new();
727 crisv10_prepare_memaddr(dc, addr, size);
728 gen_store(dc, addr, cpu_R[dc->dst], size);
729 insn_len += crisv10_post_memaddr(dc, size);
730
731 return insn_len;
732 }
733
734 static unsigned int dec10_ind_move_m_pr(DisasContext *dc)
735 {
736 unsigned int insn_len = 2, rd = dc->dst;
737 TCGv t, addr;
738
739 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
740 cris_lock_irq(dc);
741
742 addr = tcg_temp_new();
743 t = tcg_temp_new();
744 insn_len += dec10_prep_move_m(dc, 0, 4, t);
745 if (rd == 15) {
746 tcg_gen_mov_tl(env_btarget, t);
747 cris_prepare_jmp(dc, JMP_INDIRECT);
748 dc->delayed_branch = 1;
749 return insn_len;
750 }
751
752 tcg_gen_mov_tl(cpu_PR[rd], t);
753 dc->cpustate_changed = 1;
754 tcg_temp_free(addr);
755 tcg_temp_free(t);
756 return insn_len;
757 }
758
759 static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
760 {
761 unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
762 TCGv addr, t0;
763
764 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
765
766 addr = tcg_temp_new();
767 crisv10_prepare_memaddr(dc, addr, size);
768 if (dc->dst == PR_CCS) {
769 t0 = tcg_temp_new();
770 cris_evaluate_flags(dc);
771 tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
772 gen_store(dc, addr, t0, size);
773 tcg_temp_free(t0);
774 } else {
775 gen_store(dc, addr, cpu_PR[dc->dst], size);
776 }
777 t0 = tcg_temp_new();
778 insn_len += crisv10_post_memaddr(dc, size);
779 cris_lock_irq(dc);
780
781 return insn_len;
782 }
783
784 static void dec10_movem_r_m(DisasContext *dc)
785 {
786 int i, pfix = dc->tb_flags & PFIX_FLAG;
787 TCGv addr, t0;
788
789 LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
790 dc->dst, dc->src, dc->postinc, dc->ir);
791
792 addr = tcg_temp_new();
793 t0 = tcg_temp_new();
794 crisv10_prepare_memaddr(dc, addr, 4);
795 tcg_gen_mov_tl(t0, addr);
796 for (i = dc->dst; i >= 0; i--) {
797 if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
798 gen_store(dc, addr, t0, 4);
799 } else {
800 gen_store(dc, addr, cpu_R[i], 4);
801 }
802 tcg_gen_addi_tl(addr, addr, 4);
803 }
804
805 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
806 tcg_gen_mov_tl(cpu_R[dc->src], t0);
807 }
808
809 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
810 tcg_gen_mov_tl(cpu_R[dc->src], addr);
811 }
812 tcg_temp_free(addr);
813 tcg_temp_free(t0);
814 }
815
816 static void dec10_movem_m_r(DisasContext *dc)
817 {
818 int i, pfix = dc->tb_flags & PFIX_FLAG;
819 TCGv addr, t0;
820
821 LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
822 dc->src, dc->dst, dc->postinc, dc->ir);
823
824 addr = tcg_temp_new();
825 t0 = tcg_temp_new();
826 crisv10_prepare_memaddr(dc, addr, 4);
827 tcg_gen_mov_tl(t0, addr);
828 for (i = dc->dst; i >= 0; i--) {
829 gen_load(dc, cpu_R[i], addr, 4, 0);
830 tcg_gen_addi_tl(addr, addr, 4);
831 }
832
833 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
834 tcg_gen_mov_tl(cpu_R[dc->src], t0);
835 }
836
837 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
838 tcg_gen_mov_tl(cpu_R[dc->src], addr);
839 }
840 tcg_temp_free(addr);
841 tcg_temp_free(t0);
842 }
843
844 static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size)
845 {
846 int insn_len = 0;
847 int rd = dc->dst;
848 TCGv t[2];
849
850 cris_alu_m_alloc_temps(t);
851 insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
852 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
853 if (dc->dst == 15) {
854 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
855 cris_prepare_jmp(dc, JMP_INDIRECT);
856 dc->delayed_branch = 1;
857 return insn_len;
858 }
859
860 cris_alu_m_free_temps(t);
861
862 return insn_len;
863 }
864
865 static int dec10_ind_bound(DisasContext *dc, unsigned int size)
866 {
867 int insn_len = 0;
868 int rd = dc->dst;
869 TCGv t;
870
871 t = tcg_temp_local_new();
872 insn_len += dec10_prep_move_m(dc, 0, size, t);
873 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
874 if (dc->dst == 15) {
875 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
876 cris_prepare_jmp(dc, JMP_INDIRECT);
877 dc->delayed_branch = 1;
878 return insn_len;
879 }
880
881 tcg_temp_free(t);
882 return insn_len;
883 }
884
885 static int dec10_alux_m(DisasContext *dc, int op)
886 {
887 unsigned int size = (dc->size & 1) ? 2 : 1;
888 unsigned int sx = !!(dc->size & 2);
889 int insn_len = 2;
890 int rd = dc->dst;
891 TCGv t;
892
893 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
894
895 t = tcg_temp_new();
896
897 cris_cc_mask(dc, CC_MASK_NZVC);
898 insn_len += dec10_prep_move_m(dc, sx, size, t);
899 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
900 if (dc->dst == 15) {
901 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
902 cris_prepare_jmp(dc, JMP_INDIRECT);
903 dc->delayed_branch = 1;
904 return insn_len;
905 }
906
907 tcg_temp_free(t);
908 return insn_len;
909 }
910
911 static int dec10_dip(DisasContext *dc)
912 {
913 int insn_len = 2;
914 uint32_t imm;
915
916 LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
917 dc->pc, dc->opcode, dc->src, dc->dst);
918 if (dc->src == 15) {
919 imm = ldl_code(dc->pc + 2);
920 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
921 if (dc->postinc)
922 insn_len += 4;
923 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
924 } else {
925 gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
926 if (dc->postinc)
927 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
928 }
929
930 cris_set_prefix(dc);
931 return insn_len;
932 }
933
934 static int dec10_bdap_m(DisasContext *dc, int size)
935 {
936 int insn_len = 2;
937 int rd = dc->dst;
938
939 LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
940 dc->pc, dc->opcode, dc->src, dc->dst, size);
941
942 assert(dc->dst != 15);
943 #if 0
944 /* 8bit embedded offset? */
945 if (!dc->postinc && (dc->ir & (1 << 11))) {
946 int simm = dc->ir & 0xff;
947
948 // assert(0);
949 /* sign extended. */
950 simm = (int8_t)simm;
951
952 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
953
954 cris_set_prefix(dc);
955 return insn_len;
956 }
957 #endif
958 /* Now the rest of the modes are truely indirect. */
959 insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]);
960 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
961 cris_set_prefix(dc);
962 return insn_len;
963 }
964
965 static unsigned int dec10_ind(DisasContext *dc)
966 {
967 unsigned int insn_len = 2;
968 unsigned int size = dec10_size(dc->size);
969 uint32_t imm;
970 int32_t simm;
971 TCGv t[2];
972
973 if (dc->size != 3) {
974 switch (dc->opcode) {
975 case CRISV10_IND_MOVE_M_R:
976 return dec10_ind_move_m_r(dc, size);
977 break;
978 case CRISV10_IND_MOVE_R_M:
979 return dec10_ind_move_r_m(dc, size);
980 break;
981 case CRISV10_IND_CMP:
982 LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
983 cris_cc_mask(dc, CC_MASK_NZVC);
984 insn_len += dec10_ind_alu(dc, CC_OP_CMP, size);
985 break;
986 case CRISV10_IND_TEST:
987 LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
988
989 cris_evaluate_flags(dc);
990 cris_cc_mask(dc, CC_MASK_NZVC);
991 cris_alu_m_alloc_temps(t);
992 insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
993 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
994 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
995 t[0], tcg_const_tl(0), size);
996 cris_alu_m_free_temps(t);
997 break;
998 case CRISV10_IND_ADD:
999 LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
1000 cris_cc_mask(dc, CC_MASK_NZVC);
1001 insn_len += dec10_ind_alu(dc, CC_OP_ADD, size);
1002 break;
1003 case CRISV10_IND_SUB:
1004 LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
1005 cris_cc_mask(dc, CC_MASK_NZVC);
1006 insn_len += dec10_ind_alu(dc, CC_OP_SUB, size);
1007 break;
1008 case CRISV10_IND_BOUND:
1009 LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
1010 cris_cc_mask(dc, CC_MASK_NZVC);
1011 insn_len += dec10_ind_bound(dc, size);
1012 break;
1013 case CRISV10_IND_AND:
1014 LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
1015 cris_cc_mask(dc, CC_MASK_NZVC);
1016 insn_len += dec10_ind_alu(dc, CC_OP_AND, size);
1017 break;
1018 case CRISV10_IND_OR:
1019 LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
1020 cris_cc_mask(dc, CC_MASK_NZVC);
1021 insn_len += dec10_ind_alu(dc, CC_OP_OR, size);
1022 break;
1023 case CRISV10_IND_MOVX:
1024 insn_len = dec10_alux_m(dc, CC_OP_MOVE);
1025 break;
1026 case CRISV10_IND_ADDX:
1027 insn_len = dec10_alux_m(dc, CC_OP_ADD);
1028 break;
1029 case CRISV10_IND_SUBX:
1030 insn_len = dec10_alux_m(dc, CC_OP_SUB);
1031 break;
1032 case CRISV10_IND_CMPX:
1033 insn_len = dec10_alux_m(dc, CC_OP_CMP);
1034 break;
1035 case CRISV10_IND_MUL:
1036 /* This is a reg insn coded in the mem indir space. */
1037 LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
1038 cris_cc_mask(dc, CC_MASK_NZVC);
1039 dec10_reg_mul(dc, size, dc->ir & (1 << 10));
1040 break;
1041 case CRISV10_IND_BDAP_M:
1042 insn_len = dec10_bdap_m(dc, size);
1043 break;
1044 default:
1045 LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
1046 dc->pc, size, dc->opcode, dc->src, dc->dst);
1047 assert(0);
1048 break;
1049 }
1050 return insn_len;
1051 }
1052
1053 switch (dc->opcode) {
1054 case CRISV10_IND_MOVE_M_SPR:
1055 insn_len = dec10_ind_move_m_pr(dc);
1056 break;
1057 case CRISV10_IND_MOVE_SPR_M:
1058 insn_len = dec10_ind_move_pr_m(dc);
1059 break;
1060 case CRISV10_IND_JUMP_M:
1061 if (dc->src == 15) {
1062 LOG_DIS("jump.%d %d r%d r%d\n", size,
1063 dc->opcode, dc->src, dc->dst);
1064 imm = ldl_code(dc->pc + 2);
1065 if (dc->mode == CRISV10_MODE_AUTOINC)
1066 insn_len += size;
1067
1068 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1069 tcg_gen_movi_tl(env_btarget, imm);
1070 cris_prepare_jmp(dc, JMP_INDIRECT);
1071 dc->delayed_branch--; /* v10 has no dslot here. */
1072 } else {
1073 if (dc->dst == 14) {
1074 LOG_DIS("break %d\n", dc->src);
1075 cris_evaluate_flags(dc);
1076 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1077 t_gen_raise_exception(EXCP_BREAK);
1078 dc->is_jmp = DISAS_UPDATE;
1079 return insn_len;
1080 }
1081 LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
1082 dc->opcode, dc->src, dc->dst);
1083 t[0] = tcg_temp_new();
1084 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1085 crisv10_prepare_memaddr(dc, t[0], size);
1086 gen_load(dc, env_btarget, t[0], 4, 0);
1087 insn_len += crisv10_post_memaddr(dc, size);
1088 cris_prepare_jmp(dc, JMP_INDIRECT);
1089 dc->delayed_branch--; /* v10 has no dslot here. */
1090 tcg_temp_free(t[0]);
1091 }
1092 break;
1093
1094 case CRISV10_IND_MOVEM_R_M:
1095 LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
1096 dc->pc, dc->opcode, dc->dst, dc->src);
1097 dec10_movem_r_m(dc);
1098 break;
1099 case CRISV10_IND_MOVEM_M_R:
1100 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
1101 dec10_movem_m_r(dc);
1102 break;
1103 case CRISV10_IND_JUMP_R:
1104 LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
1105 dc->pc, dc->opcode, dc->dst, dc->src);
1106 tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
1107 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1108 cris_prepare_jmp(dc, JMP_INDIRECT);
1109 dc->delayed_branch--; /* v10 has no dslot here. */
1110 break;
1111 case CRISV10_IND_MOVX:
1112 insn_len = dec10_alux_m(dc, CC_OP_MOVE);
1113 break;
1114 case CRISV10_IND_ADDX:
1115 insn_len = dec10_alux_m(dc, CC_OP_ADD);
1116 break;
1117 case CRISV10_IND_SUBX:
1118 insn_len = dec10_alux_m(dc, CC_OP_SUB);
1119 break;
1120 case CRISV10_IND_CMPX:
1121 insn_len = dec10_alux_m(dc, CC_OP_CMP);
1122 break;
1123 case CRISV10_IND_DIP:
1124 insn_len = dec10_dip(dc);
1125 break;
1126 case CRISV10_IND_BCC_M:
1127
1128 cris_cc_mask(dc, 0);
1129 imm = ldsw_code(dc->pc + 2);
1130 simm = (int16_t)imm;
1131 simm += 4;
1132
1133 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
1134 cris_prepare_cc_branch(dc, simm, dc->cond);
1135 insn_len = 4;
1136 break;
1137 default:
1138 LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
1139 assert(0);
1140 break;
1141 }
1142
1143 return insn_len;
1144 }
1145
1146 static unsigned int crisv10_decoder(DisasContext *dc)
1147 {
1148 unsigned int insn_len = 2;
1149
1150 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1151 tcg_gen_debug_insn_start(dc->pc);
1152
1153 /* Load a halfword onto the instruction register. */
1154 dc->ir = lduw_code(dc->pc);
1155
1156 /* Now decode it. */
1157 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
1158 dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
1159 dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
1160 dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
1161 dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
1162 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
1163
1164 dc->clear_prefix = 1;
1165
1166 /* FIXME: What if this insn insn't 2 in length?? */
1167 if (dc->src == 15 || dc->dst == 15)
1168 tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
1169
1170 switch (dc->mode) {
1171 case CRISV10_MODE_QIMMEDIATE:
1172 insn_len = dec10_quick_imm(dc);
1173 break;
1174 case CRISV10_MODE_REG:
1175 insn_len = dec10_reg(dc);
1176 break;
1177 case CRISV10_MODE_AUTOINC:
1178 case CRISV10_MODE_INDIRECT:
1179 insn_len = dec10_ind(dc);
1180 break;
1181 }
1182
1183 if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
1184 dc->tb_flags &= ~PFIX_FLAG;
1185 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
1186 dc->cpustate_changed = 1;
1187 }
1188
1189 /* CRISv10 locks out interrupts on dslots. */
1190 if (dc->delayed_branch == 2) {
1191 cris_lock_irq(dc);
1192 }
1193 return insn_len;
1194 }
1195
1196 static CPUCRISState *cpu_crisv10_init (CPUState *env)
1197 {
1198 int i;
1199
1200 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1201 cc_x = tcg_global_mem_new(TCG_AREG0,
1202 offsetof(CPUState, cc_x), "cc_x");
1203 cc_src = tcg_global_mem_new(TCG_AREG0,
1204 offsetof(CPUState, cc_src), "cc_src");
1205 cc_dest = tcg_global_mem_new(TCG_AREG0,
1206 offsetof(CPUState, cc_dest),
1207 "cc_dest");
1208 cc_result = tcg_global_mem_new(TCG_AREG0,
1209 offsetof(CPUState, cc_result),
1210 "cc_result");
1211 cc_op = tcg_global_mem_new(TCG_AREG0,
1212 offsetof(CPUState, cc_op), "cc_op");
1213 cc_size = tcg_global_mem_new(TCG_AREG0,
1214 offsetof(CPUState, cc_size),
1215 "cc_size");
1216 cc_mask = tcg_global_mem_new(TCG_AREG0,
1217 offsetof(CPUState, cc_mask),
1218 "cc_mask");
1219
1220 env_pc = tcg_global_mem_new(TCG_AREG0,
1221 offsetof(CPUState, pc),
1222 "pc");
1223 env_btarget = tcg_global_mem_new(TCG_AREG0,
1224 offsetof(CPUState, btarget),
1225 "btarget");
1226 env_btaken = tcg_global_mem_new(TCG_AREG0,
1227 offsetof(CPUState, btaken),
1228 "btaken");
1229 for (i = 0; i < 16; i++) {
1230 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1231 offsetof(CPUState, regs[i]),
1232 regnames_v10[i]);
1233 }
1234 for (i = 0; i < 16; i++) {
1235 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
1236 offsetof(CPUState, pregs[i]),
1237 pregnames_v10[i]);
1238 }
1239
1240 return env;
1241 }
1242
Qemu copy for testing