3 - rework eflags optimization (will be a consequence of TCG port)
4 - SVM: rework the implementation: simplify code, move most intercept
5 tests as dynamic, correct segment access, verify exception safety,
6 cpu save/restore, SMM save/restore.
7 - arpl eflags computation is invalid
8 - x86_64: fxsave/fxrestore intel/amd differences
9 - x86_64: lcall/ljmp intel/amd differences ?
10 - x86_64: cmpxchgl intel/amd differences ?
11 - x86_64: cmovl intel/amd differences ?
12 - cmpxchg16b + cmpxchg8b cpuid test
13 - x86: monitor invalid
14 - better code fetch (different exception handling + CS.limit support)
15 - user/kernel PUSHL/POPL in helper.c
16 - add missing cpuid tests
17 - return UD exception if LOCK prefix incorrectly used
18 - test ldt limit < 7 ?
19 - fix some 16 bit sp push/pop overflow (pusha/popa, lcall lret)
20 - full support of segment limit/rights
21 - full x87 exception support
22 - improve x87 bit exactness (use bochs code ?)
23 - DRx register support
25 - SSE alignment checks
26 - fix SSE min/max with nans
28 Optimizations/Features:
31 - add SVM nested paging support
35 - evaluate x87 stack pointer statically
36 - find a way to avoid translating several time the same TB if CR0.TS
38 - move kqemu support outside target-i386.