target-i386/arch_memory_mapping.c

   1 /*
   2  * i386 memory mapping
   3  *
   4  * Copyright Fujitsu, Corp. 2011, 2012
   5  *
   6  * Authors:
   7  *     Wen Congyang <wency@cn.fujitsu.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "cpu.h"
  15 #include "exec/cpu-all.h"
  16 #include "sysemu/memory_mapping.h"
  17
  18 /* PAE Paging or IA-32e Paging */
  19 static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
  20                      int32_t a20_mask, target_ulong start_line_addr)
  21 {
  22     hwaddr pte_addr, start_paddr;
  23     uint64_t pte;
  24     target_ulong start_vaddr;
  25     int i;
  26
  27     for (i = 0; i < 512; i++) {
  28         pte_addr = (pte_start_addr + i * 8) & a20_mask;
  29         pte = ldq_phys(pte_addr);
  30         if (!(pte & PG_PRESENT_MASK)) {
  31             /* not present */
  32             continue;
  33         }
  34
  35         start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
  36         if (cpu_physical_memory_is_io(start_paddr)) {
  37             /* I/O region */
  38             continue;
  39         }
  40
  41         start_vaddr = start_line_addr | ((i & 0x1ff) << 12);
  42         memory_mapping_list_add_merge_sorted(list, start_paddr,
  43                                              start_vaddr, 1 << 12);
  44     }
  45 }
  46
  47 /* 32-bit Paging */
  48 static void walk_pte2(MemoryMappingList *list,
  49                       hwaddr pte_start_addr, int32_t a20_mask,
  50                       target_ulong start_line_addr)
  51 {
  52     hwaddr pte_addr, start_paddr;
  53     uint32_t pte;
  54     target_ulong start_vaddr;
  55     int i;
  56
  57     for (i = 0; i < 1024; i++) {
  58         pte_addr = (pte_start_addr + i * 4) & a20_mask;
  59         pte = ldl_phys(pte_addr);
  60         if (!(pte & PG_PRESENT_MASK)) {
  61             /* not present */
  62             continue;
  63         }
  64
  65         start_paddr = pte & ~0xfff;
  66         if (cpu_physical_memory_is_io(start_paddr)) {
  67             /* I/O region */
  68             continue;
  69         }
  70
  71         start_vaddr = start_line_addr | ((i & 0x3ff) << 12);
  72         memory_mapping_list_add_merge_sorted(list, start_paddr,
  73                                              start_vaddr, 1 << 12);
  74     }
  75 }
  76
  77 /* PAE Paging or IA-32e Paging */
  78 #define PLM4_ADDR_MASK 0xffffffffff000 /* selects bits 51:12 */
  79
  80 static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
  81                      int32_t a20_mask, target_ulong start_line_addr)
  82 {
  83     hwaddr pde_addr, pte_start_addr, start_paddr;
  84     uint64_t pde;
  85     target_ulong line_addr, start_vaddr;
  86     int i;
  87
  88     for (i = 0; i < 512; i++) {
  89         pde_addr = (pde_start_addr + i * 8) & a20_mask;
  90         pde = ldq_phys(pde_addr);
  91         if (!(pde & PG_PRESENT_MASK)) {
  92             /* not present */
  93             continue;
  94         }
  95
  96         line_addr = start_line_addr | ((i & 0x1ff) << 21);
  97         if (pde & PG_PSE_MASK) {
  98             /* 2 MB page */
  99             start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
 100             if (cpu_physical_memory_is_io(start_paddr)) {
 101                 /* I/O region */
 102                 continue;
 103             }
 104             start_vaddr = line_addr;
 105             memory_mapping_list_add_merge_sorted(list, start_paddr,
 106                                                  start_vaddr, 1 << 21);
 107             continue;
 108         }
 109
 110         pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
 111         walk_pte(list, pte_start_addr, a20_mask, line_addr);
 112     }
 113 }
 114
 115 /* 32-bit Paging */
 116 static void walk_pde2(MemoryMappingList *list,
 117                       hwaddr pde_start_addr, int32_t a20_mask,
 118                       bool pse)
 119 {
 120     hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr;
 121     uint32_t pde;
 122     target_ulong line_addr, start_vaddr;
 123     int i;
 124
 125     for (i = 0; i < 1024; i++) {
 126         pde_addr = (pde_start_addr + i * 4) & a20_mask;
 127         pde = ldl_phys(pde_addr);
 128         if (!(pde & PG_PRESENT_MASK)) {
 129             /* not present */
 130             continue;
 131         }
 132
 133         line_addr = (((unsigned int)i & 0x3ff) << 22);
 134         if ((pde & PG_PSE_MASK) && pse) {
 135             /*
 136              * 4 MB page:
 137              * bits 39:32 are bits 20:13 of the PDE
 138              * bit3 31:22 are bits 31:22 of the PDE
 139              */
 140             high_paddr = ((hwaddr)(pde & 0x1fe000) << 19);
 141             start_paddr = (pde & ~0x3fffff) | high_paddr;
 142             if (cpu_physical_memory_is_io(start_paddr)) {
 143                 /* I/O region */
 144                 continue;
 145             }
 146             start_vaddr = line_addr;
 147             memory_mapping_list_add_merge_sorted(list, start_paddr,
 148                                                  start_vaddr, 1 << 22);
 149             continue;
 150         }
 151
 152         pte_start_addr = (pde & ~0xfff) & a20_mask;
 153         walk_pte2(list, pte_start_addr, a20_mask, line_addr);
 154     }
 155 }
 156
 157 /* PAE Paging */
 158 static void walk_pdpe2(MemoryMappingList *list,
 159                        hwaddr pdpe_start_addr, int32_t a20_mask)
 160 {
 161     hwaddr pdpe_addr, pde_start_addr;
 162     uint64_t pdpe;
 163     target_ulong line_addr;
 164     int i;
 165
 166     for (i = 0; i < 4; i++) {
 167         pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
 168         pdpe = ldq_phys(pdpe_addr);
 169         if (!(pdpe & PG_PRESENT_MASK)) {
 170             /* not present */
 171             continue;
 172         }
 173
 174         line_addr = (((unsigned int)i & 0x3) << 30);
 175         pde_start_addr = (pdpe & ~0xfff) & a20_mask;
 176         walk_pde(list, pde_start_addr, a20_mask, line_addr);
 177     }
 178 }
 179
 180 #ifdef TARGET_X86_64
 181 /* IA-32e Paging */
 182 static void walk_pdpe(MemoryMappingList *list,
 183                       hwaddr pdpe_start_addr, int32_t a20_mask,
 184                       target_ulong start_line_addr)
 185 {
 186     hwaddr pdpe_addr, pde_start_addr, start_paddr;
 187     uint64_t pdpe;
 188     target_ulong line_addr, start_vaddr;
 189     int i;
 190
 191     for (i = 0; i < 512; i++) {
 192         pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
 193         pdpe = ldq_phys(pdpe_addr);
 194         if (!(pdpe & PG_PRESENT_MASK)) {
 195             /* not present */
 196             continue;
 197         }
 198
 199         line_addr = start_line_addr | ((i & 0x1ffULL) << 30);
 200         if (pdpe & PG_PSE_MASK) {
 201             /* 1 GB page */
 202             start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
 203             if (cpu_physical_memory_is_io(start_paddr)) {
 204                 /* I/O region */
 205                 continue;
 206             }
 207             start_vaddr = line_addr;
 208             memory_mapping_list_add_merge_sorted(list, start_paddr,
 209                                                  start_vaddr, 1 << 30);
 210             continue;
 211         }
 212
 213         pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
 214         walk_pde(list, pde_start_addr, a20_mask, line_addr);
 215     }
 216 }
 217
 218 /* IA-32e Paging */
 219 static void walk_pml4e(MemoryMappingList *list,
 220                        hwaddr pml4e_start_addr, int32_t a20_mask)
 221 {
 222     hwaddr pml4e_addr, pdpe_start_addr;
 223     uint64_t pml4e;
 224     target_ulong line_addr;
 225     int i;
 226
 227     for (i = 0; i < 512; i++) {
 228         pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
 229         pml4e = ldq_phys(pml4e_addr);
 230         if (!(pml4e & PG_PRESENT_MASK)) {
 231             /* not present */
 232             continue;
 233         }
 234
 235         line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
 236         pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
 237         walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
 238     }
 239 }
 240 #endif
 241
 242 int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env)
 243 {
 244     if (!cpu_paging_enabled(env)) {
 245         /* paging is disabled */
 246         return 0;
 247     }
 248
 249     if (env->cr[4] & CR4_PAE_MASK) {
 250 #ifdef TARGET_X86_64
 251         if (env->hflags & HF_LMA_MASK) {
 252             hwaddr pml4e_addr;
 253
 254             pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
 255             walk_pml4e(list, pml4e_addr, env->a20_mask);
 256         } else
 257 #endif
 258         {
 259             hwaddr pdpe_addr;
 260
 261             pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
 262             walk_pdpe2(list, pdpe_addr, env->a20_mask);
 263         }
 264     } else {
 265         hwaddr pde_addr;
 266         bool pse;
 267
 268         pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
 269         pse = !!(env->cr[4] & CR4_PSE_MASK);
 270         walk_pde2(list, pde_addr, env->a20_mask, pse);
 271     }
 272
 273     return 0;
 274 }
 275
 276 bool cpu_paging_enabled(CPUArchState *env)
 277 {
 278     return env->cr[0] & CR0_PG_MASK;
 279 }