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target-i386: Replace uint32_t vendor fields by vendor string in x86_def_t
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52 {
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60 }
61
62 /* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66 static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75 };
76 static const char *ext_feature_name[] = {
77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
78 "ds_cpl", "vmx", "smx", "est",
79 "tm2", "ssse3", "cid", NULL,
80 "fma", "cx16", "xtpr", "pdcm",
81 NULL, "pcid", "dca", "sse4.1|sse4_1",
82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
83 "tsc-deadline", "aes", "xsave", "osxsave",
84 "avx", "f16c", "rdrand", "hypervisor",
85 };
86 /* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
91 static const char *ext2_feature_name[] = {
92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
99 NULL, "lm|i64", "3dnowext", "3dnow",
100 };
101 static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
104 "3dnowprefetch", "osvw", "ibs", "xop",
105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 };
111
112 static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 };
122
123 static const char *kvm_feature_name[] = {
124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 };
133
134 static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 };
144
145 static const char *cpuid_7_0_ebx_feature_name[] = {
146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150 };
151
152 typedef struct FeatureWordInfo {
153 const char **feat_names;
154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
156 } FeatureWordInfo;
157
158 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
191 };
192
193 const char *get_register_name_32(unsigned int reg)
194 {
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210 }
211
212 /* collects per-function cpuid data
213 */
214 typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
217 FeatureWord feat_word;
218 } model_features_t;
219
220 int check_cpuid = 0;
221 int enforce_cpuid = 0;
222
223 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
228 (1 << KVM_FEATURE_PV_EOI) |
229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
230
231 void disable_kvm_pv_eoi(void)
232 {
233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
234 }
235
236 void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
238 {
239 #if defined(CONFIG_KVM)
240 uint32_t vec[4];
241
242 #ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247 #else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257 #endif
258
259 if (eax)
260 *eax = vec[0];
261 if (ebx)
262 *ebx = vec[1];
263 if (ecx)
264 *ecx = vec[2];
265 if (edx)
266 *edx = vec[3];
267 #endif
268 }
269
270 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277 static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279 {
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291 }
292
293 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298 static int altcmp(const char *s, const char *e, const char *altstr)
299 {
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312 }
313
314 /* search featureset for flag *[s..e), if found set corresponding bit in
315 * *pval and return true, otherwise return false
316 */
317 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
319 {
320 uint32_t mask;
321 const char **ppc;
322 bool found = false;
323
324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
327 found = true;
328 }
329 }
330 return found;
331 }
332
333 static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
335 {
336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
347 }
348
349 typedef struct x86_def_t {
350 const char *name;
351 uint32_t level;
352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
354 int family;
355 int model;
356 int stepping;
357 int tsc_khz;
358 uint32_t features, ext_features, ext2_features, ext3_features;
359 uint32_t kvm_features, svm_features;
360 uint32_t xlevel;
361 char model_id[48];
362 int vendor_override;
363 /* Store the results of Centaur's CPUID instructions */
364 uint32_t ext4_features;
365 uint32_t xlevel2;
366 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
367 uint32_t cpuid_7_0_ebx_features;
368 } x86_def_t;
369
370 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
371 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
372 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
373 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
374 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
375 CPUID_PSE36 | CPUID_FXSR)
376 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
377 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
378 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
379 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
380 CPUID_PAE | CPUID_SEP | CPUID_APIC)
381
382 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
383 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
384 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
385 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
386 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
387 /* partly implemented:
388 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
389 CPUID_PSE36 (needed for Solaris) */
390 /* missing:
391 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
392 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
393 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
394 CPUID_EXT_HYPERVISOR)
395 /* missing:
396 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
397 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
398 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
399 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
400 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
401 /* missing:
402 CPUID_EXT2_PDPE1GB */
403 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
404 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
405 #define TCG_SVM_FEATURES 0
406 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
407
408 /* built-in CPU model definitions
409 */
410 static x86_def_t builtin_x86_defs[] = {
411 {
412 .name = "qemu64",
413 .level = 4,
414 .vendor = CPUID_VENDOR_AMD,
415 .family = 6,
416 .model = 2,
417 .stepping = 3,
418 .features = PPRO_FEATURES |
419 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
420 CPUID_PSE36,
421 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
422 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
423 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
424 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
425 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
426 .xlevel = 0x8000000A,
427 },
428 {
429 .name = "phenom",
430 .level = 5,
431 .vendor = CPUID_VENDOR_AMD,
432 .family = 16,
433 .model = 2,
434 .stepping = 3,
435 .features = PPRO_FEATURES |
436 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
437 CPUID_PSE36 | CPUID_VME | CPUID_HT,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
439 CPUID_EXT_POPCNT,
440 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
441 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
442 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
443 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
444 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
445 CPUID_EXT3_CR8LEG,
446 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
447 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
448 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
449 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
450 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
451 .xlevel = 0x8000001A,
452 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
453 },
454 {
455 .name = "core2duo",
456 .level = 10,
457 .vendor = CPUID_VENDOR_INTEL,
458 .family = 6,
459 .model = 15,
460 .stepping = 11,
461 .features = PPRO_FEATURES |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
463 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
464 CPUID_HT | CPUID_TM | CPUID_PBE,
465 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
466 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
467 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
468 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
469 .ext3_features = CPUID_EXT3_LAHF_LM,
470 .xlevel = 0x80000008,
471 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
472 },
473 {
474 .name = "kvm64",
475 .level = 5,
476 .vendor = CPUID_VENDOR_INTEL,
477 .family = 15,
478 .model = 6,
479 .stepping = 1,
480 /* Missing: CPUID_VME, CPUID_HT */
481 .features = PPRO_FEATURES |
482 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
483 CPUID_PSE36,
484 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
485 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
486 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
487 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
488 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
489 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
490 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
491 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
492 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
493 .ext3_features = 0,
494 .xlevel = 0x80000008,
495 .model_id = "Common KVM processor"
496 },
497 {
498 .name = "qemu32",
499 .level = 4,
500 .vendor = CPUID_VENDOR_INTEL,
501 .family = 6,
502 .model = 3,
503 .stepping = 3,
504 .features = PPRO_FEATURES,
505 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
506 .xlevel = 0x80000004,
507 },
508 {
509 .name = "kvm32",
510 .level = 5,
511 .vendor = CPUID_VENDOR_INTEL,
512 .family = 15,
513 .model = 6,
514 .stepping = 1,
515 .features = PPRO_FEATURES |
516 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
517 .ext_features = CPUID_EXT_SSE3,
518 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
519 .ext3_features = 0,
520 .xlevel = 0x80000008,
521 .model_id = "Common 32-bit KVM processor"
522 },
523 {
524 .name = "coreduo",
525 .level = 10,
526 .vendor = CPUID_VENDOR_INTEL,
527 .family = 6,
528 .model = 14,
529 .stepping = 8,
530 .features = PPRO_FEATURES | CPUID_VME |
531 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
532 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
533 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
534 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
535 .ext2_features = CPUID_EXT2_NX,
536 .xlevel = 0x80000008,
537 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
538 },
539 {
540 .name = "486",
541 .level = 1,
542 .vendor = CPUID_VENDOR_INTEL,
543 .family = 4,
544 .model = 0,
545 .stepping = 0,
546 .features = I486_FEATURES,
547 .xlevel = 0,
548 },
549 {
550 .name = "pentium",
551 .level = 1,
552 .vendor = CPUID_VENDOR_INTEL,
553 .family = 5,
554 .model = 4,
555 .stepping = 3,
556 .features = PENTIUM_FEATURES,
557 .xlevel = 0,
558 },
559 {
560 .name = "pentium2",
561 .level = 2,
562 .vendor = CPUID_VENDOR_INTEL,
563 .family = 6,
564 .model = 5,
565 .stepping = 2,
566 .features = PENTIUM2_FEATURES,
567 .xlevel = 0,
568 },
569 {
570 .name = "pentium3",
571 .level = 2,
572 .vendor = CPUID_VENDOR_INTEL,
573 .family = 6,
574 .model = 7,
575 .stepping = 3,
576 .features = PENTIUM3_FEATURES,
577 .xlevel = 0,
578 },
579 {
580 .name = "athlon",
581 .level = 2,
582 .vendor = CPUID_VENDOR_AMD,
583 .family = 6,
584 .model = 2,
585 .stepping = 3,
586 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
587 CPUID_MCA,
588 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
589 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
590 .xlevel = 0x80000008,
591 },
592 {
593 .name = "n270",
594 /* original is on level 10 */
595 .level = 5,
596 .vendor = CPUID_VENDOR_INTEL,
597 .family = 6,
598 .model = 28,
599 .stepping = 2,
600 .features = PPRO_FEATURES |
601 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
602 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
603 /* Some CPUs got no CPUID_SEP */
604 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
605 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
606 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
607 CPUID_EXT2_NX,
608 .ext3_features = CPUID_EXT3_LAHF_LM,
609 .xlevel = 0x8000000A,
610 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
611 },
612 {
613 .name = "Conroe",
614 .level = 2,
615 .vendor = CPUID_VENDOR_INTEL,
616 .family = 6,
617 .model = 2,
618 .stepping = 3,
619 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
620 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
621 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
622 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
623 CPUID_DE | CPUID_FP87,
624 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
625 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
626 .ext3_features = CPUID_EXT3_LAHF_LM,
627 .xlevel = 0x8000000A,
628 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
629 },
630 {
631 .name = "Penryn",
632 .level = 2,
633 .vendor = CPUID_VENDOR_INTEL,
634 .family = 6,
635 .model = 2,
636 .stepping = 3,
637 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
638 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
639 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
640 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
641 CPUID_DE | CPUID_FP87,
642 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
643 CPUID_EXT_SSE3,
644 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
648 },
649 {
650 .name = "Nehalem",
651 .level = 2,
652 .vendor = CPUID_VENDOR_INTEL,
653 .family = 6,
654 .model = 2,
655 .stepping = 3,
656 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
657 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
658 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
659 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
660 CPUID_DE | CPUID_FP87,
661 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
662 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
663 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
664 .ext3_features = CPUID_EXT3_LAHF_LM,
665 .xlevel = 0x8000000A,
666 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
667 },
668 {
669 .name = "Westmere",
670 .level = 11,
671 .vendor = CPUID_VENDOR_INTEL,
672 .family = 6,
673 .model = 44,
674 .stepping = 1,
675 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
676 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
677 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
678 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
679 CPUID_DE | CPUID_FP87,
680 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
681 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
682 CPUID_EXT_SSE3,
683 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
684 .ext3_features = CPUID_EXT3_LAHF_LM,
685 .xlevel = 0x8000000A,
686 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
687 },
688 {
689 .name = "SandyBridge",
690 .level = 0xd,
691 .vendor = CPUID_VENDOR_INTEL,
692 .family = 6,
693 .model = 42,
694 .stepping = 1,
695 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
696 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
697 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
698 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
699 CPUID_DE | CPUID_FP87,
700 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
701 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
702 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
703 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
704 CPUID_EXT_SSE3,
705 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
706 CPUID_EXT2_SYSCALL,
707 .ext3_features = CPUID_EXT3_LAHF_LM,
708 .xlevel = 0x8000000A,
709 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
710 },
711 {
712 .name = "Haswell",
713 .level = 0xd,
714 .vendor = CPUID_VENDOR_INTEL,
715 .family = 6,
716 .model = 60,
717 .stepping = 1,
718 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
722 CPUID_DE | CPUID_FP87,
723 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
724 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
725 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
726 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
727 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
728 CPUID_EXT_PCID,
729 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
730 CPUID_EXT2_SYSCALL,
731 .ext3_features = CPUID_EXT3_LAHF_LM,
732 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
733 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
734 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
735 CPUID_7_0_EBX_RTM,
736 .xlevel = 0x8000000A,
737 .model_id = "Intel Core Processor (Haswell)",
738 },
739 {
740 .name = "Opteron_G1",
741 .level = 5,
742 .vendor = CPUID_VENDOR_AMD,
743 .family = 15,
744 .model = 6,
745 .stepping = 1,
746 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
750 CPUID_DE | CPUID_FP87,
751 .ext_features = CPUID_EXT_SSE3,
752 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
753 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
754 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
755 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
756 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
757 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
758 .xlevel = 0x80000008,
759 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
760 },
761 {
762 .name = "Opteron_G2",
763 .level = 5,
764 .vendor = CPUID_VENDOR_AMD,
765 .family = 15,
766 .model = 6,
767 .stepping = 1,
768 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
769 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
770 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
771 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
772 CPUID_DE | CPUID_FP87,
773 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
774 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
775 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
776 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
777 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
778 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
779 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
780 CPUID_EXT2_DE | CPUID_EXT2_FPU,
781 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
782 .xlevel = 0x80000008,
783 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
784 },
785 {
786 .name = "Opteron_G3",
787 .level = 5,
788 .vendor = CPUID_VENDOR_AMD,
789 .family = 15,
790 .model = 6,
791 .stepping = 1,
792 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
793 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
794 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
795 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
796 CPUID_DE | CPUID_FP87,
797 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
798 CPUID_EXT_SSE3,
799 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
800 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
801 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
802 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
803 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
804 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
805 CPUID_EXT2_DE | CPUID_EXT2_FPU,
806 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
807 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
808 .xlevel = 0x80000008,
809 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
810 },
811 {
812 .name = "Opteron_G4",
813 .level = 0xd,
814 .vendor = CPUID_VENDOR_AMD,
815 .family = 21,
816 .model = 1,
817 .stepping = 2,
818 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
819 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
820 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
821 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
822 CPUID_DE | CPUID_FP87,
823 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
824 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
825 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
826 CPUID_EXT_SSE3,
827 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
828 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
829 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
830 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
831 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
832 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
833 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
834 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
835 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
836 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
837 CPUID_EXT3_LAHF_LM,
838 .xlevel = 0x8000001A,
839 .model_id = "AMD Opteron 62xx class CPU",
840 },
841 {
842 .name = "Opteron_G5",
843 .level = 0xd,
844 .vendor = CPUID_VENDOR_AMD,
845 .family = 21,
846 .model = 2,
847 .stepping = 0,
848 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
849 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
850 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
851 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
852 CPUID_DE | CPUID_FP87,
853 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
854 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
855 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
856 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
857 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
858 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
859 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
860 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
861 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
862 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
863 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
864 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
865 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
866 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
867 CPUID_EXT3_LAHF_LM,
868 .xlevel = 0x8000001A,
869 .model_id = "AMD Opteron 63xx class CPU",
870 },
871 };
872
873 #ifdef CONFIG_KVM
874 static int cpu_x86_fill_model_id(char *str)
875 {
876 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
877 int i;
878
879 for (i = 0; i < 3; i++) {
880 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
881 memcpy(str + i * 16 + 0, &eax, 4);
882 memcpy(str + i * 16 + 4, &ebx, 4);
883 memcpy(str + i * 16 + 8, &ecx, 4);
884 memcpy(str + i * 16 + 12, &edx, 4);
885 }
886 return 0;
887 }
888 #endif
889
890 /* Fill a x86_def_t struct with information about the host CPU, and
891 * the CPU features supported by the host hardware + host kernel
892 *
893 * This function may be called only if KVM is enabled.
894 */
895 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
896 {
897 #ifdef CONFIG_KVM
898 KVMState *s = kvm_state;
899 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
900
901 assert(kvm_enabled());
902
903 x86_cpu_def->name = "host";
904 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
905 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
906
907 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
908 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
909 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
910 x86_cpu_def->stepping = eax & 0x0F;
911
912 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
913 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
914 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
915
916 if (x86_cpu_def->level >= 7) {
917 x86_cpu_def->cpuid_7_0_ebx_features =
918 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
919 } else {
920 x86_cpu_def->cpuid_7_0_ebx_features = 0;
921 }
922
923 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
924 x86_cpu_def->ext2_features =
925 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
926 x86_cpu_def->ext3_features =
927 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
928
929 cpu_x86_fill_model_id(x86_cpu_def->model_id);
930 x86_cpu_def->vendor_override = 0;
931
932 /* Call Centaur's CPUID instruction. */
933 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
934 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
935 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
936 if (eax >= 0xC0000001) {
937 /* Support VIA max extended level */
938 x86_cpu_def->xlevel2 = eax;
939 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
940 x86_cpu_def->ext4_features =
941 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
942 }
943 }
944
945 /* Other KVM-specific feature fields: */
946 x86_cpu_def->svm_features =
947 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
948 x86_cpu_def->kvm_features =
949 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
950
951 #endif /* CONFIG_KVM */
952 }
953
954 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
955 {
956 int i;
957
958 for (i = 0; i < 32; ++i)
959 if (1 << i & mask) {
960 const char *reg = get_register_name_32(f->cpuid_reg);
961 assert(reg);
962 fprintf(stderr, "warning: host doesn't support requested feature: "
963 "CPUID.%02XH:%s%s%s [bit %d]\n",
964 f->cpuid_eax, reg,
965 f->feat_names[i] ? "." : "",
966 f->feat_names[i] ? f->feat_names[i] : "", i);
967 break;
968 }
969 return 0;
970 }
971
972 /* Check if all requested cpu flags are making their way to the guest
973 *
974 * Returns 0 if all flags are supported by the host, non-zero otherwise.
975 *
976 * This function may be called only if KVM is enabled.
977 */
978 static int kvm_check_features_against_host(X86CPU *cpu)
979 {
980 CPUX86State *env = &cpu->env;
981 x86_def_t host_def;
982 uint32_t mask;
983 int rv, i;
984 struct model_features_t ft[] = {
985 {&env->cpuid_features, &host_def.features,
986 FEAT_1_EDX },
987 {&env->cpuid_ext_features, &host_def.ext_features,
988 FEAT_1_ECX },
989 {&env->cpuid_ext2_features, &host_def.ext2_features,
990 FEAT_8000_0001_EDX },
991 {&env->cpuid_ext3_features, &host_def.ext3_features,
992 FEAT_8000_0001_ECX },
993 {&env->cpuid_ext4_features, &host_def.ext4_features,
994 FEAT_C000_0001_EDX },
995 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
996 FEAT_7_0_EBX },
997 {&env->cpuid_svm_features, &host_def.svm_features,
998 FEAT_SVM },
999 {&env->cpuid_kvm_features, &host_def.kvm_features,
1000 FEAT_KVM },
1001 };
1002
1003 assert(kvm_enabled());
1004
1005 kvm_cpu_fill_host(&host_def);
1006 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1007 FeatureWord w = ft[i].feat_word;
1008 FeatureWordInfo *wi = &feature_word_info[w];
1009 for (mask = 1; mask; mask <<= 1) {
1010 if (*ft[i].guest_feat & mask &&
1011 !(*ft[i].host_feat & mask)) {
1012 unavailable_host_feature(wi, mask);
1013 rv = 1;
1014 }
1015 }
1016 }
1017 return rv;
1018 }
1019
1020 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1021 const char *name, Error **errp)
1022 {
1023 X86CPU *cpu = X86_CPU(obj);
1024 CPUX86State *env = &cpu->env;
1025 int64_t value;
1026
1027 value = (env->cpuid_version >> 8) & 0xf;
1028 if (value == 0xf) {
1029 value += (env->cpuid_version >> 20) & 0xff;
1030 }
1031 visit_type_int(v, &value, name, errp);
1032 }
1033
1034 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1035 const char *name, Error **errp)
1036 {
1037 X86CPU *cpu = X86_CPU(obj);
1038 CPUX86State *env = &cpu->env;
1039 const int64_t min = 0;
1040 const int64_t max = 0xff + 0xf;
1041 int64_t value;
1042
1043 visit_type_int(v, &value, name, errp);
1044 if (error_is_set(errp)) {
1045 return;
1046 }
1047 if (value < min || value > max) {
1048 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1049 name ? name : "null", value, min, max);
1050 return;
1051 }
1052
1053 env->cpuid_version &= ~0xff00f00;
1054 if (value > 0x0f) {
1055 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1056 } else {
1057 env->cpuid_version |= value << 8;
1058 }
1059 }
1060
1061 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1062 const char *name, Error **errp)
1063 {
1064 X86CPU *cpu = X86_CPU(obj);
1065 CPUX86State *env = &cpu->env;
1066 int64_t value;
1067
1068 value = (env->cpuid_version >> 4) & 0xf;
1069 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1070 visit_type_int(v, &value, name, errp);
1071 }
1072
1073 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1074 const char *name, Error **errp)
1075 {
1076 X86CPU *cpu = X86_CPU(obj);
1077 CPUX86State *env = &cpu->env;
1078 const int64_t min = 0;
1079 const int64_t max = 0xff;
1080 int64_t value;
1081
1082 visit_type_int(v, &value, name, errp);
1083 if (error_is_set(errp)) {
1084 return;
1085 }
1086 if (value < min || value > max) {
1087 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1088 name ? name : "null", value, min, max);
1089 return;
1090 }
1091
1092 env->cpuid_version &= ~0xf00f0;
1093 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1094 }
1095
1096 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1097 void *opaque, const char *name,
1098 Error **errp)
1099 {
1100 X86CPU *cpu = X86_CPU(obj);
1101 CPUX86State *env = &cpu->env;
1102 int64_t value;
1103
1104 value = env->cpuid_version & 0xf;
1105 visit_type_int(v, &value, name, errp);
1106 }
1107
1108 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1109 void *opaque, const char *name,
1110 Error **errp)
1111 {
1112 X86CPU *cpu = X86_CPU(obj);
1113 CPUX86State *env = &cpu->env;
1114 const int64_t min = 0;
1115 const int64_t max = 0xf;
1116 int64_t value;
1117
1118 visit_type_int(v, &value, name, errp);
1119 if (error_is_set(errp)) {
1120 return;
1121 }
1122 if (value < min || value > max) {
1123 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1124 name ? name : "null", value, min, max);
1125 return;
1126 }
1127
1128 env->cpuid_version &= ~0xf;
1129 env->cpuid_version |= value & 0xf;
1130 }
1131
1132 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1133 const char *name, Error **errp)
1134 {
1135 X86CPU *cpu = X86_CPU(obj);
1136
1137 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1138 }
1139
1140 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1141 const char *name, Error **errp)
1142 {
1143 X86CPU *cpu = X86_CPU(obj);
1144
1145 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1146 }
1147
1148 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1149 const char *name, Error **errp)
1150 {
1151 X86CPU *cpu = X86_CPU(obj);
1152
1153 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1154 }
1155
1156 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1157 const char *name, Error **errp)
1158 {
1159 X86CPU *cpu = X86_CPU(obj);
1160
1161 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1162 }
1163
1164 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1165 {
1166 X86CPU *cpu = X86_CPU(obj);
1167 CPUX86State *env = &cpu->env;
1168 char *value;
1169
1170 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1171 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1172 env->cpuid_vendor3);
1173 return value;
1174 }
1175
1176 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1177 Error **errp)
1178 {
1179 X86CPU *cpu = X86_CPU(obj);
1180 CPUX86State *env = &cpu->env;
1181 int i;
1182
1183 if (strlen(value) != CPUID_VENDOR_SZ) {
1184 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1185 "vendor", value);
1186 return;
1187 }
1188
1189 env->cpuid_vendor1 = 0;
1190 env->cpuid_vendor2 = 0;
1191 env->cpuid_vendor3 = 0;
1192 for (i = 0; i < 4; i++) {
1193 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1194 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1195 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1196 }
1197 env->cpuid_vendor_override = 1;
1198 }
1199
1200 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1201 {
1202 X86CPU *cpu = X86_CPU(obj);
1203 CPUX86State *env = &cpu->env;
1204 char *value;
1205 int i;
1206
1207 value = g_malloc(48 + 1);
1208 for (i = 0; i < 48; i++) {
1209 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1210 }
1211 value[48] = '\0';
1212 return value;
1213 }
1214
1215 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1216 Error **errp)
1217 {
1218 X86CPU *cpu = X86_CPU(obj);
1219 CPUX86State *env = &cpu->env;
1220 int c, len, i;
1221
1222 if (model_id == NULL) {
1223 model_id = "";
1224 }
1225 len = strlen(model_id);
1226 memset(env->cpuid_model, 0, 48);
1227 for (i = 0; i < 48; i++) {
1228 if (i >= len) {
1229 c = '\0';
1230 } else {
1231 c = (uint8_t)model_id[i];
1232 }
1233 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1234 }
1235 }
1236
1237 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1238 const char *name, Error **errp)
1239 {
1240 X86CPU *cpu = X86_CPU(obj);
1241 int64_t value;
1242
1243 value = cpu->env.tsc_khz * 1000;
1244 visit_type_int(v, &value, name, errp);
1245 }
1246
1247 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1248 const char *name, Error **errp)
1249 {
1250 X86CPU *cpu = X86_CPU(obj);
1251 const int64_t min = 0;
1252 const int64_t max = INT64_MAX;
1253 int64_t value;
1254
1255 visit_type_int(v, &value, name, errp);
1256 if (error_is_set(errp)) {
1257 return;
1258 }
1259 if (value < min || value > max) {
1260 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1261 name ? name : "null", value, min, max);
1262 return;
1263 }
1264
1265 cpu->env.tsc_khz = value / 1000;
1266 }
1267
1268 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1269 {
1270 x86_def_t *def;
1271 int i;
1272
1273 if (name == NULL) {
1274 return -1;
1275 }
1276 if (kvm_enabled() && strcmp(name, "host") == 0) {
1277 kvm_cpu_fill_host(x86_cpu_def);
1278 return 0;
1279 }
1280
1281 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1282 def = &builtin_x86_defs[i];
1283 if (strcmp(name, def->name) == 0) {
1284 memcpy(x86_cpu_def, def, sizeof(*def));
1285 return 0;
1286 }
1287 }
1288
1289 return -1;
1290 }
1291
1292 /* Parse "+feature,-feature,feature=foo" CPU feature string
1293 */
1294 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1295 {
1296 char *featurestr; /* Single 'key=value" string being parsed */
1297 /* Features to be added */
1298 FeatureWordArray plus_features = { 0 };
1299 /* Features to be removed */
1300 FeatureWordArray minus_features = { 0 };
1301 uint32_t numvalue;
1302
1303 featurestr = features ? strtok(features, ",") : NULL;
1304
1305 while (featurestr) {
1306 char *val;
1307 if (featurestr[0] == '+') {
1308 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1309 } else if (featurestr[0] == '-') {
1310 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1311 } else if ((val = strchr(featurestr, '='))) {
1312 *val = 0; val++;
1313 if (!strcmp(featurestr, "family")) {
1314 char *err;
1315 numvalue = strtoul(val, &err, 0);
1316 if (!*val || *err || numvalue > 0xff + 0xf) {
1317 fprintf(stderr, "bad numerical value %s\n", val);
1318 goto error;
1319 }
1320 x86_cpu_def->family = numvalue;
1321 } else if (!strcmp(featurestr, "model")) {
1322 char *err;
1323 numvalue = strtoul(val, &err, 0);
1324 if (!*val || *err || numvalue > 0xff) {
1325 fprintf(stderr, "bad numerical value %s\n", val);
1326 goto error;
1327 }
1328 x86_cpu_def->model = numvalue;
1329 } else if (!strcmp(featurestr, "stepping")) {
1330 char *err;
1331 numvalue = strtoul(val, &err, 0);
1332 if (!*val || *err || numvalue > 0xf) {
1333 fprintf(stderr, "bad numerical value %s\n", val);
1334 goto error;
1335 }
1336 x86_cpu_def->stepping = numvalue ;
1337 } else if (!strcmp(featurestr, "level")) {
1338 char *err;
1339 numvalue = strtoul(val, &err, 0);
1340 if (!*val || *err) {
1341 fprintf(stderr, "bad numerical value %s\n", val);
1342 goto error;
1343 }
1344 x86_cpu_def->level = numvalue;
1345 } else if (!strcmp(featurestr, "xlevel")) {
1346 char *err;
1347 numvalue = strtoul(val, &err, 0);
1348 if (!*val || *err) {
1349 fprintf(stderr, "bad numerical value %s\n", val);
1350 goto error;
1351 }
1352 if (numvalue < 0x80000000) {
1353 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1354 ", fixup will be removed in future versions\n");
1355 numvalue += 0x80000000;
1356 }
1357 x86_cpu_def->xlevel = numvalue;
1358 } else if (!strcmp(featurestr, "vendor")) {
1359 pstrcpy(x86_cpu_def->vendor, sizeof(x86_cpu_def->vendor), val);
1360 x86_cpu_def->vendor_override = 1;
1361 } else if (!strcmp(featurestr, "model_id")) {
1362 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1363 val);
1364 } else if (!strcmp(featurestr, "tsc_freq")) {
1365 int64_t tsc_freq;
1366 char *err;
1367
1368 tsc_freq = strtosz_suffix_unit(val, &err,
1369 STRTOSZ_DEFSUFFIX_B, 1000);
1370 if (tsc_freq < 0 || *err) {
1371 fprintf(stderr, "bad numerical value %s\n", val);
1372 goto error;
1373 }
1374 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1375 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1376 char *err;
1377 numvalue = strtoul(val, &err, 0);
1378 if (!*val || *err) {
1379 fprintf(stderr, "bad numerical value %s\n", val);
1380 goto error;
1381 }
1382 hyperv_set_spinlock_retries(numvalue);
1383 } else {
1384 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1385 goto error;
1386 }
1387 } else if (!strcmp(featurestr, "check")) {
1388 check_cpuid = 1;
1389 } else if (!strcmp(featurestr, "enforce")) {
1390 check_cpuid = enforce_cpuid = 1;
1391 } else if (!strcmp(featurestr, "hv_relaxed")) {
1392 hyperv_enable_relaxed_timing(true);
1393 } else if (!strcmp(featurestr, "hv_vapic")) {
1394 hyperv_enable_vapic_recommended(true);
1395 } else {
1396 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1397 goto error;
1398 }
1399 featurestr = strtok(NULL, ",");
1400 }
1401 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1402 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1403 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1404 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1405 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
1406 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1407 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1408 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1409 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1410 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1411 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1412 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1413 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1414 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1415 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1416 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1417 return 0;
1418
1419 error:
1420 return -1;
1421 }
1422
1423 /* generate a composite string into buf of all cpuid names in featureset
1424 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1425 * if flags, suppress names undefined in featureset.
1426 */
1427 static void listflags(char *buf, int bufsize, uint32_t fbits,
1428 const char **featureset, uint32_t flags)
1429 {
1430 const char **p = &featureset[31];
1431 char *q, *b, bit;
1432 int nc;
1433
1434 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1435 *buf = '\0';
1436 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1437 if (fbits & 1 << bit && (*p || !flags)) {
1438 if (*p)
1439 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1440 else
1441 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1442 if (bufsize <= nc) {
1443 if (b) {
1444 memcpy(b, "...", sizeof("..."));
1445 }
1446 return;
1447 }
1448 q += nc;
1449 bufsize -= nc;
1450 }
1451 }
1452
1453 /* generate CPU information. */
1454 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1455 {
1456 x86_def_t *def;
1457 char buf[256];
1458 int i;
1459
1460 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1461 def = &builtin_x86_defs[i];
1462 snprintf(buf, sizeof(buf), "%s", def->name);
1463 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1464 }
1465 if (kvm_enabled()) {
1466 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1467 }
1468 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1469 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1470 (*cpu_fprintf)(f, " %s\n", buf);
1471 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1472 (*cpu_fprintf)(f, " %s\n", buf);
1473 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1474 (*cpu_fprintf)(f, " %s\n", buf);
1475 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1476 (*cpu_fprintf)(f, " %s\n", buf);
1477 }
1478
1479 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1480 {
1481 CpuDefinitionInfoList *cpu_list = NULL;
1482 x86_def_t *def;
1483 int i;
1484
1485 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1486 CpuDefinitionInfoList *entry;
1487 CpuDefinitionInfo *info;
1488
1489 def = &builtin_x86_defs[i];
1490 info = g_malloc0(sizeof(*info));
1491 info->name = g_strdup(def->name);
1492
1493 entry = g_malloc0(sizeof(*entry));
1494 entry->value = info;
1495 entry->next = cpu_list;
1496 cpu_list = entry;
1497 }
1498
1499 return cpu_list;
1500 }
1501
1502 #ifdef CONFIG_KVM
1503 static void filter_features_for_kvm(X86CPU *cpu)
1504 {
1505 CPUX86State *env = &cpu->env;
1506 KVMState *s = kvm_state;
1507
1508 env->cpuid_features &=
1509 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1510 env->cpuid_ext_features &=
1511 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1512 env->cpuid_ext2_features &=
1513 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1514 env->cpuid_ext3_features &=
1515 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1516 env->cpuid_svm_features &=
1517 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1518 env->cpuid_7_0_ebx_features &=
1519 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1520 env->cpuid_kvm_features &=
1521 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1522 env->cpuid_ext4_features &=
1523 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1524
1525 }
1526 #endif
1527
1528 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1529 {
1530 CPUX86State *env = &cpu->env;
1531 x86_def_t def1, *def = &def1;
1532 Error *error = NULL;
1533 char *name, *features;
1534 gchar **model_pieces;
1535
1536 memset(def, 0, sizeof(*def));
1537
1538 model_pieces = g_strsplit(cpu_model, ",", 2);
1539 if (!model_pieces[0]) {
1540 error_setg(&error, "Invalid/empty CPU model name");
1541 goto out;
1542 }
1543 name = model_pieces[0];
1544 features = model_pieces[1];
1545
1546 if (cpu_x86_find_by_name(def, name) < 0) {
1547 error_setg(&error, "Unable to find CPU definition: %s", name);
1548 goto out;
1549 }
1550
1551 if (kvm_enabled()) {
1552 def->kvm_features |= kvm_default_features;
1553 }
1554 def->ext_features |= CPUID_EXT_HYPERVISOR;
1555
1556 if (cpu_x86_parse_featurestr(def, features) < 0) {
1557 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1558 goto out;
1559 }
1560 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", &error);
1561 env->cpuid_vendor_override = def->vendor_override;
1562 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1563 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1564 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1565 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1566 env->cpuid_features = def->features;
1567 env->cpuid_ext_features = def->ext_features;
1568 env->cpuid_ext2_features = def->ext2_features;
1569 env->cpuid_ext3_features = def->ext3_features;
1570 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1571 env->cpuid_kvm_features = def->kvm_features;
1572 env->cpuid_svm_features = def->svm_features;
1573 env->cpuid_ext4_features = def->ext4_features;
1574 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1575 env->cpuid_xlevel2 = def->xlevel2;
1576 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1577 "tsc-frequency", &error);
1578
1579 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1580
1581 out:
1582 g_strfreev(model_pieces);
1583 if (error) {
1584 fprintf(stderr, "%s\n", error_get_pretty(error));
1585 error_free(error);
1586 return -1;
1587 }
1588 return 0;
1589 }
1590
1591 #if !defined(CONFIG_USER_ONLY)
1592
1593 void cpu_clear_apic_feature(CPUX86State *env)
1594 {
1595 env->cpuid_features &= ~CPUID_APIC;
1596 }
1597
1598 #endif /* !CONFIG_USER_ONLY */
1599
1600 /* Initialize list of CPU models, filling some non-static fields if necessary
1601 */
1602 void x86_cpudef_setup(void)
1603 {
1604 int i, j;
1605 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1606
1607 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1608 x86_def_t *def = &builtin_x86_defs[i];
1609
1610 /* Look for specific "cpudef" models that */
1611 /* have the QEMU version in .model_id */
1612 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1613 if (strcmp(model_with_versions[j], def->name) == 0) {
1614 pstrcpy(def->model_id, sizeof(def->model_id),
1615 "QEMU Virtual CPU version ");
1616 pstrcat(def->model_id, sizeof(def->model_id),
1617 qemu_get_version());
1618 break;
1619 }
1620 }
1621 }
1622 }
1623
1624 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1625 uint32_t *ecx, uint32_t *edx)
1626 {
1627 *ebx = env->cpuid_vendor1;
1628 *edx = env->cpuid_vendor2;
1629 *ecx = env->cpuid_vendor3;
1630
1631 /* sysenter isn't supported on compatibility mode on AMD, syscall
1632 * isn't supported in compatibility mode on Intel.
1633 * Normally we advertise the actual cpu vendor, but you can override
1634 * this if you want to use KVM's sysenter/syscall emulation
1635 * in compatibility mode and when doing cross vendor migration
1636 */
1637 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1638 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1639 }
1640 }
1641
1642 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1643 uint32_t *eax, uint32_t *ebx,
1644 uint32_t *ecx, uint32_t *edx)
1645 {
1646 X86CPU *cpu = x86_env_get_cpu(env);
1647 CPUState *cs = CPU(cpu);
1648
1649 /* test if maximum index reached */
1650 if (index & 0x80000000) {
1651 if (index > env->cpuid_xlevel) {
1652 if (env->cpuid_xlevel2 > 0) {
1653 /* Handle the Centaur's CPUID instruction. */
1654 if (index > env->cpuid_xlevel2) {
1655 index = env->cpuid_xlevel2;
1656 } else if (index < 0xC0000000) {
1657 index = env->cpuid_xlevel;
1658 }
1659 } else {
1660 /* Intel documentation states that invalid EAX input will
1661 * return the same information as EAX=cpuid_level
1662 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1663 */
1664 index = env->cpuid_level;
1665 }
1666 }
1667 } else {
1668 if (index > env->cpuid_level)
1669 index = env->cpuid_level;
1670 }
1671
1672 switch(index) {
1673 case 0:
1674 *eax = env->cpuid_level;
1675 get_cpuid_vendor(env, ebx, ecx, edx);
1676 break;
1677 case 1:
1678 *eax = env->cpuid_version;
1679 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1680 *ecx = env->cpuid_ext_features;
1681 *edx = env->cpuid_features;
1682 if (cs->nr_cores * cs->nr_threads > 1) {
1683 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1684 *edx |= 1 << 28; /* HTT bit */
1685 }
1686 break;
1687 case 2:
1688 /* cache info: needed for Pentium Pro compatibility */
1689 *eax = 1;
1690 *ebx = 0;
1691 *ecx = 0;
1692 *edx = 0x2c307d;
1693 break;
1694 case 4:
1695 /* cache info: needed for Core compatibility */
1696 if (cs->nr_cores > 1) {
1697 *eax = (cs->nr_cores - 1) << 26;
1698 } else {
1699 *eax = 0;
1700 }
1701 switch (count) {
1702 case 0: /* L1 dcache info */
1703 *eax |= 0x0000121;
1704 *ebx = 0x1c0003f;
1705 *ecx = 0x000003f;
1706 *edx = 0x0000001;
1707 break;
1708 case 1: /* L1 icache info */
1709 *eax |= 0x0000122;
1710 *ebx = 0x1c0003f;
1711 *ecx = 0x000003f;
1712 *edx = 0x0000001;
1713 break;
1714 case 2: /* L2 cache info */
1715 *eax |= 0x0000143;
1716 if (cs->nr_threads > 1) {
1717 *eax |= (cs->nr_threads - 1) << 14;
1718 }
1719 *ebx = 0x3c0003f;
1720 *ecx = 0x0000fff;
1721 *edx = 0x0000001;
1722 break;
1723 default: /* end of info */
1724 *eax = 0;
1725 *ebx = 0;
1726 *ecx = 0;
1727 *edx = 0;
1728 break;
1729 }
1730 break;
1731 case 5:
1732 /* mwait info: needed for Core compatibility */
1733 *eax = 0; /* Smallest monitor-line size in bytes */
1734 *ebx = 0; /* Largest monitor-line size in bytes */
1735 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1736 *edx = 0;
1737 break;
1738 case 6:
1739 /* Thermal and Power Leaf */
1740 *eax = 0;
1741 *ebx = 0;
1742 *ecx = 0;
1743 *edx = 0;
1744 break;
1745 case 7:
1746 /* Structured Extended Feature Flags Enumeration Leaf */
1747 if (count == 0) {
1748 *eax = 0; /* Maximum ECX value for sub-leaves */
1749 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1750 *ecx = 0; /* Reserved */
1751 *edx = 0; /* Reserved */
1752 } else {
1753 *eax = 0;
1754 *ebx = 0;
1755 *ecx = 0;
1756 *edx = 0;
1757 }
1758 break;
1759 case 9:
1760 /* Direct Cache Access Information Leaf */
1761 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1762 *ebx = 0;
1763 *ecx = 0;
1764 *edx = 0;
1765 break;
1766 case 0xA:
1767 /* Architectural Performance Monitoring Leaf */
1768 if (kvm_enabled()) {
1769 KVMState *s = cs->kvm_state;
1770
1771 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1772 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1773 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1774 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1775 } else {
1776 *eax = 0;
1777 *ebx = 0;
1778 *ecx = 0;
1779 *edx = 0;
1780 }
1781 break;
1782 case 0xD:
1783 /* Processor Extended State */
1784 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1785 *eax = 0;
1786 *ebx = 0;
1787 *ecx = 0;
1788 *edx = 0;
1789 break;
1790 }
1791 if (kvm_enabled()) {
1792 KVMState *s = cs->kvm_state;
1793
1794 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1795 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1796 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1797 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1798 } else {
1799 *eax = 0;
1800 *ebx = 0;
1801 *ecx = 0;
1802 *edx = 0;
1803 }
1804 break;
1805 case 0x80000000:
1806 *eax = env->cpuid_xlevel;
1807 *ebx = env->cpuid_vendor1;
1808 *edx = env->cpuid_vendor2;
1809 *ecx = env->cpuid_vendor3;
1810 break;
1811 case 0x80000001:
1812 *eax = env->cpuid_version;
1813 *ebx = 0;
1814 *ecx = env->cpuid_ext3_features;
1815 *edx = env->cpuid_ext2_features;
1816
1817 /* The Linux kernel checks for the CMPLegacy bit and
1818 * discards multiple thread information if it is set.
1819 * So dont set it here for Intel to make Linux guests happy.
1820 */
1821 if (cs->nr_cores * cs->nr_threads > 1) {
1822 uint32_t tebx, tecx, tedx;
1823 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1824 if (tebx != CPUID_VENDOR_INTEL_1 ||
1825 tedx != CPUID_VENDOR_INTEL_2 ||
1826 tecx != CPUID_VENDOR_INTEL_3) {
1827 *ecx |= 1 << 1; /* CmpLegacy bit */
1828 }
1829 }
1830 break;
1831 case 0x80000002:
1832 case 0x80000003:
1833 case 0x80000004:
1834 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1835 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1836 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1837 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1838 break;
1839 case 0x80000005:
1840 /* cache info (L1 cache) */
1841 *eax = 0x01ff01ff;
1842 *ebx = 0x01ff01ff;
1843 *ecx = 0x40020140;
1844 *edx = 0x40020140;
1845 break;
1846 case 0x80000006:
1847 /* cache info (L2 cache) */
1848 *eax = 0;
1849 *ebx = 0x42004200;
1850 *ecx = 0x02008140;
1851 *edx = 0;
1852 break;
1853 case 0x80000008:
1854 /* virtual & phys address size in low 2 bytes. */
1855 /* XXX: This value must match the one used in the MMU code. */
1856 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1857 /* 64 bit processor */
1858 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1859 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1860 } else {
1861 if (env->cpuid_features & CPUID_PSE36)
1862 *eax = 0x00000024; /* 36 bits physical */
1863 else
1864 *eax = 0x00000020; /* 32 bits physical */
1865 }
1866 *ebx = 0;
1867 *ecx = 0;
1868 *edx = 0;
1869 if (cs->nr_cores * cs->nr_threads > 1) {
1870 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1871 }
1872 break;
1873 case 0x8000000A:
1874 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1875 *eax = 0x00000001; /* SVM Revision */
1876 *ebx = 0x00000010; /* nr of ASIDs */
1877 *ecx = 0;
1878 *edx = env->cpuid_svm_features; /* optional features */
1879 } else {
1880 *eax = 0;
1881 *ebx = 0;
1882 *ecx = 0;
1883 *edx = 0;
1884 }
1885 break;
1886 case 0xC0000000:
1887 *eax = env->cpuid_xlevel2;
1888 *ebx = 0;
1889 *ecx = 0;
1890 *edx = 0;
1891 break;
1892 case 0xC0000001:
1893 /* Support for VIA CPU's CPUID instruction */
1894 *eax = env->cpuid_version;
1895 *ebx = 0;
1896 *ecx = 0;
1897 *edx = env->cpuid_ext4_features;
1898 break;
1899 case 0xC0000002:
1900 case 0xC0000003:
1901 case 0xC0000004:
1902 /* Reserved for the future, and now filled with zero */
1903 *eax = 0;
1904 *ebx = 0;
1905 *ecx = 0;
1906 *edx = 0;
1907 break;
1908 default:
1909 /* reserved values: zero */
1910 *eax = 0;
1911 *ebx = 0;
1912 *ecx = 0;
1913 *edx = 0;
1914 break;
1915 }
1916 }
1917
1918 /* CPUClass::reset() */
1919 static void x86_cpu_reset(CPUState *s)
1920 {
1921 X86CPU *cpu = X86_CPU(s);
1922 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1923 CPUX86State *env = &cpu->env;
1924 int i;
1925
1926 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1927 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1928 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1929 }
1930
1931 xcc->parent_reset(s);
1932
1933
1934 memset(env, 0, offsetof(CPUX86State, breakpoints));
1935
1936 tlb_flush(env, 1);
1937
1938 env->old_exception = -1;
1939
1940 /* init to reset state */
1941
1942 #ifdef CONFIG_SOFTMMU
1943 env->hflags |= HF_SOFTMMU_MASK;
1944 #endif
1945 env->hflags2 |= HF2_GIF_MASK;
1946
1947 cpu_x86_update_cr0(env, 0x60000010);
1948 env->a20_mask = ~0x0;
1949 env->smbase = 0x30000;
1950
1951 env->idt.limit = 0xffff;
1952 env->gdt.limit = 0xffff;
1953 env->ldt.limit = 0xffff;
1954 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1955 env->tr.limit = 0xffff;
1956 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1957
1958 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1959 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1960 DESC_R_MASK | DESC_A_MASK);
1961 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1962 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1963 DESC_A_MASK);
1964 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1965 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1966 DESC_A_MASK);
1967 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1968 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1969 DESC_A_MASK);
1970 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1971 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1972 DESC_A_MASK);
1973 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1974 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1975 DESC_A_MASK);
1976
1977 env->eip = 0xfff0;
1978 env->regs[R_EDX] = env->cpuid_version;
1979
1980 env->eflags = 0x2;
1981
1982 /* FPU init */
1983 for (i = 0; i < 8; i++) {
1984 env->fptags[i] = 1;
1985 }
1986 env->fpuc = 0x37f;
1987
1988 env->mxcsr = 0x1f80;
1989
1990 env->pat = 0x0007040600070406ULL;
1991 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1992
1993 memset(env->dr, 0, sizeof(env->dr));
1994 env->dr[6] = DR6_FIXED_1;
1995 env->dr[7] = DR7_FIXED_1;
1996 cpu_breakpoint_remove_all(env, BP_CPU);
1997 cpu_watchpoint_remove_all(env, BP_CPU);
1998
1999 #if !defined(CONFIG_USER_ONLY)
2000 /* We hard-wire the BSP to the first CPU. */
2001 if (s->cpu_index == 0) {
2002 apic_designate_bsp(env->apic_state);
2003 }
2004
2005 env->halted = !cpu_is_bsp(cpu);
2006 #endif
2007 }
2008
2009 #ifndef CONFIG_USER_ONLY
2010 bool cpu_is_bsp(X86CPU *cpu)
2011 {
2012 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2013 }
2014
2015 /* TODO: remove me, when reset over QOM tree is implemented */
2016 static void x86_cpu_machine_reset_cb(void *opaque)
2017 {
2018 X86CPU *cpu = opaque;
2019 cpu_reset(CPU(cpu));
2020 }
2021 #endif
2022
2023 static void mce_init(X86CPU *cpu)
2024 {
2025 CPUX86State *cenv = &cpu->env;
2026 unsigned int bank;
2027
2028 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2029 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2030 (CPUID_MCE | CPUID_MCA)) {
2031 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2032 cenv->mcg_ctl = ~(uint64_t)0;
2033 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2034 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2035 }
2036 }
2037 }
2038
2039 #define MSI_ADDR_BASE 0xfee00000
2040
2041 #ifndef CONFIG_USER_ONLY
2042 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2043 {
2044 static int apic_mapped;
2045 CPUX86State *env = &cpu->env;
2046 APICCommonState *apic;
2047 const char *apic_type = "apic";
2048
2049 if (kvm_irqchip_in_kernel()) {
2050 apic_type = "kvm-apic";
2051 } else if (xen_enabled()) {
2052 apic_type = "xen-apic";
2053 }
2054
2055 env->apic_state = qdev_try_create(NULL, apic_type);
2056 if (env->apic_state == NULL) {
2057 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2058 return;
2059 }
2060
2061 object_property_add_child(OBJECT(cpu), "apic",
2062 OBJECT(env->apic_state), NULL);
2063 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2064 /* TODO: convert to link<> */
2065 apic = APIC_COMMON(env->apic_state);
2066 apic->cpu = cpu;
2067
2068 if (qdev_init(env->apic_state)) {
2069 error_setg(errp, "APIC device '%s' could not be initialized",
2070 object_get_typename(OBJECT(env->apic_state)));
2071 return;
2072 }
2073
2074 /* XXX: mapping more APICs at the same memory location */
2075 if (apic_mapped == 0) {
2076 /* NOTE: the APIC is directly connected to the CPU - it is not
2077 on the global memory bus. */
2078 /* XXX: what if the base changes? */
2079 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2080 apic_mapped = 1;
2081 }
2082 }
2083 #endif
2084
2085 void x86_cpu_realize(Object *obj, Error **errp)
2086 {
2087 X86CPU *cpu = X86_CPU(obj);
2088 CPUX86State *env = &cpu->env;
2089
2090 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2091 env->cpuid_level = 7;
2092 }
2093
2094 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2095 * CPUID[1].EDX.
2096 */
2097 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2098 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2099 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2100 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2101 env->cpuid_ext2_features |= (env->cpuid_features
2102 & CPUID_EXT2_AMD_ALIASES);
2103 }
2104
2105 if (!kvm_enabled()) {
2106 env->cpuid_features &= TCG_FEATURES;
2107 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2108 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2109 #ifdef TARGET_X86_64
2110 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2111 #endif
2112 );
2113 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2114 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2115 } else {
2116 #ifdef CONFIG_KVM
2117 filter_features_for_kvm(cpu);
2118 #endif
2119 if (check_cpuid && kvm_check_features_against_host(cpu)
2120 && enforce_cpuid) {
2121 error_setg(errp, "Host's CPU doesn't support requested features");
2122 return;
2123 }
2124 }
2125
2126 #ifndef CONFIG_USER_ONLY
2127 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2128
2129 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2130 x86_cpu_apic_init(cpu, errp);
2131 if (error_is_set(errp)) {
2132 return;
2133 }
2134 }
2135 #endif
2136
2137 mce_init(cpu);
2138 qemu_init_vcpu(&cpu->env);
2139 cpu_reset(CPU(cpu));
2140 }
2141
2142 /* Enables contiguous-apic-ID mode, for compatibility */
2143 static bool compat_apic_id_mode;
2144
2145 void enable_compat_apic_id_mode(void)
2146 {
2147 compat_apic_id_mode = true;
2148 }
2149
2150 /* Calculates initial APIC ID for a specific CPU index
2151 *
2152 * Currently we need to be able to calculate the APIC ID from the CPU index
2153 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2154 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2155 * all CPUs up to max_cpus.
2156 */
2157 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2158 {
2159 uint32_t correct_id;
2160 static bool warned;
2161
2162 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2163 if (compat_apic_id_mode) {
2164 if (cpu_index != correct_id && !warned) {
2165 error_report("APIC IDs set in compatibility mode, "
2166 "CPU topology won't match the configuration");
2167 warned = true;
2168 }
2169 return cpu_index;
2170 } else {
2171 return correct_id;
2172 }
2173 }
2174
2175 static void x86_cpu_initfn(Object *obj)
2176 {
2177 CPUState *cs = CPU(obj);
2178 X86CPU *cpu = X86_CPU(obj);
2179 CPUX86State *env = &cpu->env;
2180 static int inited;
2181
2182 cpu_exec_init(env);
2183
2184 object_property_add(obj, "family", "int",
2185 x86_cpuid_version_get_family,
2186 x86_cpuid_version_set_family, NULL, NULL, NULL);
2187 object_property_add(obj, "model", "int",
2188 x86_cpuid_version_get_model,
2189 x86_cpuid_version_set_model, NULL, NULL, NULL);
2190 object_property_add(obj, "stepping", "int",
2191 x86_cpuid_version_get_stepping,
2192 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2193 object_property_add(obj, "level", "int",
2194 x86_cpuid_get_level,
2195 x86_cpuid_set_level, NULL, NULL, NULL);
2196 object_property_add(obj, "xlevel", "int",
2197 x86_cpuid_get_xlevel,
2198 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2199 object_property_add_str(obj, "vendor",
2200 x86_cpuid_get_vendor,
2201 x86_cpuid_set_vendor, NULL);
2202 object_property_add_str(obj, "model-id",
2203 x86_cpuid_get_model_id,
2204 x86_cpuid_set_model_id, NULL);
2205 object_property_add(obj, "tsc-frequency", "int",
2206 x86_cpuid_get_tsc_freq,
2207 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2208
2209 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2210
2211 /* init various static tables used in TCG mode */
2212 if (tcg_enabled() && !inited) {
2213 inited = 1;
2214 optimize_flags_init();
2215 #ifndef CONFIG_USER_ONLY
2216 cpu_set_debug_excp_handler(breakpoint_handler);
2217 #endif
2218 }
2219 }
2220
2221 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2222 {
2223 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2224 CPUClass *cc = CPU_CLASS(oc);
2225
2226 xcc->parent_reset = cc->reset;
2227 cc->reset = x86_cpu_reset;
2228 }
2229
2230 static const TypeInfo x86_cpu_type_info = {
2231 .name = TYPE_X86_CPU,
2232 .parent = TYPE_CPU,
2233 .instance_size = sizeof(X86CPU),
2234 .instance_init = x86_cpu_initfn,
2235 .abstract = false,
2236 .class_size = sizeof(X86CPUClass),
2237 .class_init = x86_cpu_common_class_init,
2238 };
2239
2240 static void x86_cpu_register_types(void)
2241 {
2242 type_register_static(&x86_cpu_type_info);
2243 }
2244
2245 type_init(x86_cpu_register_types)
Qemu copy for testing