2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
52 static const char *feature_name
[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL
, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
62 static const char *ext_feature_name
[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL
,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL
, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
77 static const char *ext2_feature_name
[] = {
78 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
79 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
80 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
81 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
82 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
83 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
84 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL
, "lm|i64", "3dnowext", "3dnow",
87 static const char *ext3_feature_name
[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL
, "lwp",
92 "fma4", "tce", NULL
, "nodeid_msr",
93 NULL
, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL
, NULL
, NULL
,
95 NULL
, NULL
, NULL
, NULL
,
98 static const char *kvm_feature_name
[] = {
99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL
,
101 NULL
, NULL
, NULL
, NULL
,
102 NULL
, NULL
, NULL
, NULL
,
103 NULL
, NULL
, NULL
, NULL
,
104 NULL
, NULL
, NULL
, NULL
,
105 NULL
, NULL
, NULL
, NULL
,
106 NULL
, NULL
, NULL
, NULL
,
109 static const char *svm_feature_name
[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL
, NULL
, "pause_filter", NULL
,
113 "pfthreshold", NULL
, NULL
, NULL
,
114 NULL
, NULL
, NULL
, NULL
,
115 NULL
, NULL
, NULL
, NULL
,
116 NULL
, NULL
, NULL
, NULL
,
117 NULL
, NULL
, NULL
, NULL
,
120 static const char *cpuid_7_0_ebx_feature_name
[] = {
121 "fsgsbase", NULL
, NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, NULL
, NULL
,
123 NULL
, NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
124 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
127 typedef struct FeatureWordInfo
{
128 const char **feat_names
;
129 uint32_t cpuid_eax
; /* Input EAX for CPUID */
130 int cpuid_reg
; /* R_* register constant */
133 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
135 .feat_names
= feature_name
,
136 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
139 .feat_names
= ext_feature_name
,
140 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
142 [FEAT_8000_0001_EDX
] = {
143 .feat_names
= ext2_feature_name
,
144 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
146 [FEAT_8000_0001_ECX
] = {
147 .feat_names
= ext3_feature_name
,
148 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
151 .feat_names
= kvm_feature_name
,
152 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
155 .feat_names
= svm_feature_name
,
156 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
159 .feat_names
= cpuid_7_0_ebx_feature_name
,
160 .cpuid_eax
= 7, .cpuid_reg
= R_EBX
,
164 const char *get_register_name_32(unsigned int reg
)
166 static const char *reg_names
[CPU_NB_REGS32
] = {
177 if (reg
> CPU_NB_REGS32
) {
180 return reg_names
[reg
];
183 /* collects per-function cpuid data
185 typedef struct model_features_t
{
186 uint32_t *guest_feat
;
188 FeatureWord feat_word
;
192 int enforce_cpuid
= 0;
194 #if defined(CONFIG_KVM)
195 static uint32_t kvm_default_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
196 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
197 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
198 (1 << KVM_FEATURE_ASYNC_PF
) |
199 (1 << KVM_FEATURE_STEAL_TIME
) |
200 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
201 static const uint32_t kvm_pv_eoi_features
= (0x1 << KVM_FEATURE_PV_EOI
);
203 static uint32_t kvm_default_features
= 0;
204 static const uint32_t kvm_pv_eoi_features
= 0;
207 void enable_kvm_pv_eoi(void)
209 kvm_default_features
|= kvm_pv_eoi_features
;
212 void host_cpuid(uint32_t function
, uint32_t count
,
213 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
215 #if defined(CONFIG_KVM)
220 : "=a"(vec
[0]), "=b"(vec
[1]),
221 "=c"(vec
[2]), "=d"(vec
[3])
222 : "0"(function
), "c"(count
) : "cc");
224 asm volatile("pusha \n\t"
226 "mov %%eax, 0(%2) \n\t"
227 "mov %%ebx, 4(%2) \n\t"
228 "mov %%ecx, 8(%2) \n\t"
229 "mov %%edx, 12(%2) \n\t"
231 : : "a"(function
), "c"(count
), "S"(vec
)
246 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
248 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
249 * a substring. ex if !NULL points to the first char after a substring,
250 * otherwise the string is assumed to sized by a terminating nul.
251 * Return lexical ordering of *s1:*s2.
253 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
257 if (!*s1
|| !*s2
|| *s1
!= *s2
)
260 if (s1
== e1
&& s2
== e2
)
269 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
270 * '|' delimited (possibly empty) strings in which case search for a match
271 * within the alternatives proceeds left to right. Return 0 for success,
272 * non-zero otherwise.
274 static int altcmp(const char *s
, const char *e
, const char *altstr
)
278 for (q
= p
= altstr
; ; ) {
279 while (*p
&& *p
!= '|')
281 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
290 /* search featureset for flag *[s..e), if found set corresponding bit in
291 * *pval and return true, otherwise return false
293 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
294 const char **featureset
)
300 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
301 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
309 static void add_flagname_to_bitmaps(const char *flagname
,
310 FeatureWordArray words
)
313 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
314 FeatureWordInfo
*wi
= &feature_word_info
[w
];
315 if (wi
->feat_names
&&
316 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
320 if (w
== FEATURE_WORDS
) {
321 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
325 typedef struct x86_def_t
{
326 struct x86_def_t
*next
;
329 uint32_t vendor1
, vendor2
, vendor3
;
334 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
335 uint32_t kvm_features
, svm_features
;
339 /* Store the results of Centaur's CPUID instructions */
340 uint32_t ext4_features
;
342 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
343 uint32_t cpuid_7_0_ebx_features
;
346 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
347 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
348 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
349 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
350 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
351 CPUID_PSE36 | CPUID_FXSR)
352 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
353 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
354 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
355 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
356 CPUID_PAE | CPUID_SEP | CPUID_APIC)
358 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
359 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
360 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
361 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
362 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
363 /* partly implemented:
364 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
365 CPUID_PSE36 (needed for Solaris) */
367 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
368 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
369 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
370 CPUID_EXT_HYPERVISOR)
372 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
373 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
374 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
375 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
376 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
378 CPUID_EXT2_PDPE1GB */
379 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
380 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
381 #define TCG_SVM_FEATURES 0
382 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
384 /* maintains list of cpu model definitions
386 static x86_def_t
*x86_defs
= {NULL
};
388 /* built-in cpu model definitions (deprecated)
390 static x86_def_t builtin_x86_defs
[] = {
394 .vendor1
= CPUID_VENDOR_AMD_1
,
395 .vendor2
= CPUID_VENDOR_AMD_2
,
396 .vendor3
= CPUID_VENDOR_AMD_3
,
400 .features
= PPRO_FEATURES
|
401 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
403 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
404 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
405 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
406 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
407 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
408 .xlevel
= 0x8000000A,
413 .vendor1
= CPUID_VENDOR_AMD_1
,
414 .vendor2
= CPUID_VENDOR_AMD_2
,
415 .vendor3
= CPUID_VENDOR_AMD_3
,
419 .features
= PPRO_FEATURES
|
420 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
421 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
422 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
424 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
425 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
426 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
427 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
428 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
430 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
431 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
432 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
433 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
434 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
435 .xlevel
= 0x8000001A,
436 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
441 .vendor1
= CPUID_VENDOR_INTEL_1
,
442 .vendor2
= CPUID_VENDOR_INTEL_2
,
443 .vendor3
= CPUID_VENDOR_INTEL_3
,
447 .features
= PPRO_FEATURES
|
448 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
449 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
450 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
451 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
452 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
453 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
454 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
455 .ext3_features
= CPUID_EXT3_LAHF_LM
,
456 .xlevel
= 0x80000008,
457 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
462 .vendor1
= CPUID_VENDOR_INTEL_1
,
463 .vendor2
= CPUID_VENDOR_INTEL_2
,
464 .vendor3
= CPUID_VENDOR_INTEL_3
,
468 /* Missing: CPUID_VME, CPUID_HT */
469 .features
= PPRO_FEATURES
|
470 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
472 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
473 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
474 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
475 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
476 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
477 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
478 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
479 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
480 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
482 .xlevel
= 0x80000008,
483 .model_id
= "Common KVM processor"
488 .vendor1
= CPUID_VENDOR_INTEL_1
,
489 .vendor2
= CPUID_VENDOR_INTEL_2
,
490 .vendor3
= CPUID_VENDOR_INTEL_3
,
494 .features
= PPRO_FEATURES
,
495 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
496 .xlevel
= 0x80000004,
501 .vendor1
= CPUID_VENDOR_INTEL_1
,
502 .vendor2
= CPUID_VENDOR_INTEL_2
,
503 .vendor3
= CPUID_VENDOR_INTEL_3
,
507 .features
= PPRO_FEATURES
|
508 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
509 .ext_features
= CPUID_EXT_SSE3
,
510 .ext2_features
= PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
512 .xlevel
= 0x80000008,
513 .model_id
= "Common 32-bit KVM processor"
518 .vendor1
= CPUID_VENDOR_INTEL_1
,
519 .vendor2
= CPUID_VENDOR_INTEL_2
,
520 .vendor3
= CPUID_VENDOR_INTEL_3
,
524 .features
= PPRO_FEATURES
| CPUID_VME
|
525 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
526 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
527 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
528 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
529 .ext2_features
= CPUID_EXT2_NX
,
530 .xlevel
= 0x80000008,
531 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
536 .vendor1
= CPUID_VENDOR_INTEL_1
,
537 .vendor2
= CPUID_VENDOR_INTEL_2
,
538 .vendor3
= CPUID_VENDOR_INTEL_3
,
542 .features
= I486_FEATURES
,
548 .vendor1
= CPUID_VENDOR_INTEL_1
,
549 .vendor2
= CPUID_VENDOR_INTEL_2
,
550 .vendor3
= CPUID_VENDOR_INTEL_3
,
554 .features
= PENTIUM_FEATURES
,
560 .vendor1
= CPUID_VENDOR_INTEL_1
,
561 .vendor2
= CPUID_VENDOR_INTEL_2
,
562 .vendor3
= CPUID_VENDOR_INTEL_3
,
566 .features
= PENTIUM2_FEATURES
,
572 .vendor1
= CPUID_VENDOR_INTEL_1
,
573 .vendor2
= CPUID_VENDOR_INTEL_2
,
574 .vendor3
= CPUID_VENDOR_INTEL_3
,
578 .features
= PENTIUM3_FEATURES
,
584 .vendor1
= CPUID_VENDOR_AMD_1
,
585 .vendor2
= CPUID_VENDOR_AMD_2
,
586 .vendor3
= CPUID_VENDOR_AMD_3
,
590 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
592 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
593 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
594 .xlevel
= 0x80000008,
598 /* original is on level 10 */
600 .vendor1
= CPUID_VENDOR_INTEL_1
,
601 .vendor2
= CPUID_VENDOR_INTEL_2
,
602 .vendor3
= CPUID_VENDOR_INTEL_3
,
606 .features
= PPRO_FEATURES
|
607 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
608 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
609 /* Some CPUs got no CPUID_SEP */
610 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
611 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
612 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
614 .ext3_features
= CPUID_EXT3_LAHF_LM
,
615 .xlevel
= 0x8000000A,
616 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
621 .vendor1
= CPUID_VENDOR_INTEL_1
,
622 .vendor2
= CPUID_VENDOR_INTEL_2
,
623 .vendor3
= CPUID_VENDOR_INTEL_3
,
627 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
628 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
629 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
630 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
631 CPUID_DE
| CPUID_FP87
,
632 .ext_features
= CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
633 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
634 .ext3_features
= CPUID_EXT3_LAHF_LM
,
635 .xlevel
= 0x8000000A,
636 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
641 .vendor1
= CPUID_VENDOR_INTEL_1
,
642 .vendor2
= CPUID_VENDOR_INTEL_2
,
643 .vendor3
= CPUID_VENDOR_INTEL_3
,
647 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
648 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
649 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
650 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
651 CPUID_DE
| CPUID_FP87
,
652 .ext_features
= CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
654 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
655 .ext3_features
= CPUID_EXT3_LAHF_LM
,
656 .xlevel
= 0x8000000A,
657 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
662 .vendor1
= CPUID_VENDOR_INTEL_1
,
663 .vendor2
= CPUID_VENDOR_INTEL_2
,
664 .vendor3
= CPUID_VENDOR_INTEL_3
,
668 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
669 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
670 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
671 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
672 CPUID_DE
| CPUID_FP87
,
673 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
674 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
675 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
676 .ext3_features
= CPUID_EXT3_LAHF_LM
,
677 .xlevel
= 0x8000000A,
678 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
683 .vendor1
= CPUID_VENDOR_INTEL_1
,
684 .vendor2
= CPUID_VENDOR_INTEL_2
,
685 .vendor3
= CPUID_VENDOR_INTEL_3
,
689 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
690 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
691 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
692 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
693 CPUID_DE
| CPUID_FP87
,
694 .ext_features
= CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
695 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
697 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
698 .ext3_features
= CPUID_EXT3_LAHF_LM
,
699 .xlevel
= 0x8000000A,
700 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
703 .name
= "SandyBridge",
705 .vendor1
= CPUID_VENDOR_INTEL_1
,
706 .vendor2
= CPUID_VENDOR_INTEL_2
,
707 .vendor3
= CPUID_VENDOR_INTEL_3
,
711 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
712 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
713 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
714 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
715 CPUID_DE
| CPUID_FP87
,
716 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
717 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
718 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
719 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
721 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
723 .ext3_features
= CPUID_EXT3_LAHF_LM
,
724 .xlevel
= 0x8000000A,
725 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
730 .vendor1
= CPUID_VENDOR_INTEL_1
,
731 .vendor2
= CPUID_VENDOR_INTEL_2
,
732 .vendor3
= CPUID_VENDOR_INTEL_3
,
736 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
737 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
738 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
739 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
740 CPUID_DE
| CPUID_FP87
,
741 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
742 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
743 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
744 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
745 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
747 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
749 .ext3_features
= CPUID_EXT3_LAHF_LM
,
750 .cpuid_7_0_ebx_features
= CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
751 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
752 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
754 .xlevel
= 0x8000000A,
755 .model_id
= "Intel Core Processor (Haswell)",
758 .name
= "Opteron_G1",
760 .vendor1
= CPUID_VENDOR_AMD_1
,
761 .vendor2
= CPUID_VENDOR_AMD_2
,
762 .vendor3
= CPUID_VENDOR_AMD_3
,
766 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
767 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
768 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
769 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
770 CPUID_DE
| CPUID_FP87
,
771 .ext_features
= CPUID_EXT_SSE3
,
772 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
773 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
774 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
775 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
776 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
777 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
778 .xlevel
= 0x80000008,
779 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
782 .name
= "Opteron_G2",
784 .vendor1
= CPUID_VENDOR_AMD_1
,
785 .vendor2
= CPUID_VENDOR_AMD_2
,
786 .vendor3
= CPUID_VENDOR_AMD_3
,
790 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
791 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
792 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
793 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
794 CPUID_DE
| CPUID_FP87
,
795 .ext_features
= CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
796 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
797 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
798 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
799 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
800 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
801 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
802 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
803 .ext3_features
= CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
804 .xlevel
= 0x80000008,
805 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
808 .name
= "Opteron_G3",
810 .vendor1
= CPUID_VENDOR_AMD_1
,
811 .vendor2
= CPUID_VENDOR_AMD_2
,
812 .vendor3
= CPUID_VENDOR_AMD_3
,
816 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
817 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
818 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
819 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
820 CPUID_DE
| CPUID_FP87
,
821 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
823 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
824 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
825 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
826 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
827 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
828 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
829 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
830 .ext3_features
= CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
831 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
832 .xlevel
= 0x80000008,
833 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
836 .name
= "Opteron_G4",
838 .vendor1
= CPUID_VENDOR_AMD_1
,
839 .vendor2
= CPUID_VENDOR_AMD_2
,
840 .vendor3
= CPUID_VENDOR_AMD_3
,
844 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
845 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
846 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
847 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
848 CPUID_DE
| CPUID_FP87
,
849 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
850 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
851 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
853 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
854 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
855 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
856 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
857 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
858 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
859 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
860 .ext3_features
= CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
861 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
862 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
864 .xlevel
= 0x8000001A,
865 .model_id
= "AMD Opteron 62xx class CPU",
868 .name
= "Opteron_G5",
870 .vendor1
= CPUID_VENDOR_AMD_1
,
871 .vendor2
= CPUID_VENDOR_AMD_2
,
872 .vendor3
= CPUID_VENDOR_AMD_3
,
876 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
877 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
878 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
879 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
880 CPUID_DE
| CPUID_FP87
,
881 .ext_features
= CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
882 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
883 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
884 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
885 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
886 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
887 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
888 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
889 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
890 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
891 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
892 .ext3_features
= CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
893 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
894 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
896 .xlevel
= 0x8000001A,
897 .model_id
= "AMD Opteron 63xx class CPU",
902 static int cpu_x86_fill_model_id(char *str
)
904 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
907 for (i
= 0; i
< 3; i
++) {
908 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
909 memcpy(str
+ i
* 16 + 0, &eax
, 4);
910 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
911 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
912 memcpy(str
+ i
* 16 + 12, &edx
, 4);
918 /* Fill a x86_def_t struct with information about the host CPU, and
919 * the CPU features supported by the host hardware + host kernel
921 * This function may be called only if KVM is enabled.
923 static void kvm_cpu_fill_host(x86_def_t
*x86_cpu_def
)
926 KVMState
*s
= kvm_state
;
927 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
929 assert(kvm_enabled());
931 x86_cpu_def
->name
= "host";
932 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
933 x86_cpu_def
->vendor1
= ebx
;
934 x86_cpu_def
->vendor2
= edx
;
935 x86_cpu_def
->vendor3
= ecx
;
937 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
938 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
939 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
940 x86_cpu_def
->stepping
= eax
& 0x0F;
942 x86_cpu_def
->level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
943 x86_cpu_def
->features
= kvm_arch_get_supported_cpuid(s
, 0x1, 0, R_EDX
);
944 x86_cpu_def
->ext_features
= kvm_arch_get_supported_cpuid(s
, 0x1, 0, R_ECX
);
946 if (x86_cpu_def
->level
>= 7) {
947 x86_cpu_def
->cpuid_7_0_ebx_features
=
948 kvm_arch_get_supported_cpuid(s
, 0x7, 0, R_EBX
);
950 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
953 x86_cpu_def
->xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
954 x86_cpu_def
->ext2_features
=
955 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
);
956 x86_cpu_def
->ext3_features
=
957 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_ECX
);
959 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
960 x86_cpu_def
->vendor_override
= 0;
962 /* Call Centaur's CPUID instruction. */
963 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
964 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
965 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
966 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
967 eax
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
968 if (eax
>= 0xC0000001) {
969 /* Support VIA max extended level */
970 x86_cpu_def
->xlevel2
= eax
;
971 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
972 x86_cpu_def
->ext4_features
=
973 kvm_arch_get_supported_cpuid(s
, 0xC0000001, 0, R_EDX
);
977 /* Other KVM-specific feature fields: */
978 x86_cpu_def
->svm_features
=
979 kvm_arch_get_supported_cpuid(s
, 0x8000000A, 0, R_EDX
);
980 x86_cpu_def
->kvm_features
=
981 kvm_arch_get_supported_cpuid(s
, KVM_CPUID_FEATURES
, 0, R_EAX
);
983 #endif /* CONFIG_KVM */
986 static int unavailable_host_feature(FeatureWordInfo
*f
, uint32_t mask
)
990 for (i
= 0; i
< 32; ++i
)
992 const char *reg
= get_register_name_32(f
->cpuid_reg
);
994 fprintf(stderr
, "warning: host doesn't support requested feature: "
995 "CPUID.%02XH:%s%s%s [bit %d]\n",
997 f
->feat_names
[i
] ? "." : "",
998 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1004 /* best effort attempt to inform user requested cpu flags aren't making
1005 * their way to the guest.
1007 * This function may be called only if KVM is enabled.
1009 static int kvm_check_features_against_host(x86_def_t
*guest_def
)
1014 struct model_features_t ft
[] = {
1015 {&guest_def
->features
, &host_def
.features
,
1017 {&guest_def
->ext_features
, &host_def
.ext_features
,
1019 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
1020 FEAT_8000_0001_EDX
},
1021 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
1022 FEAT_8000_0001_ECX
},
1025 assert(kvm_enabled());
1027 kvm_cpu_fill_host(&host_def
);
1028 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
) {
1029 FeatureWord w
= ft
[i
].feat_word
;
1030 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1031 for (mask
= 1; mask
; mask
<<= 1) {
1032 if (*ft
[i
].guest_feat
& mask
&&
1033 !(*ft
[i
].host_feat
& mask
)) {
1034 unavailable_host_feature(wi
, mask
);
1042 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1043 const char *name
, Error
**errp
)
1045 X86CPU
*cpu
= X86_CPU(obj
);
1046 CPUX86State
*env
= &cpu
->env
;
1049 value
= (env
->cpuid_version
>> 8) & 0xf;
1051 value
+= (env
->cpuid_version
>> 20) & 0xff;
1053 visit_type_int(v
, &value
, name
, errp
);
1056 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1057 const char *name
, Error
**errp
)
1059 X86CPU
*cpu
= X86_CPU(obj
);
1060 CPUX86State
*env
= &cpu
->env
;
1061 const int64_t min
= 0;
1062 const int64_t max
= 0xff + 0xf;
1065 visit_type_int(v
, &value
, name
, errp
);
1066 if (error_is_set(errp
)) {
1069 if (value
< min
|| value
> max
) {
1070 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1071 name
? name
: "null", value
, min
, max
);
1075 env
->cpuid_version
&= ~0xff00f00;
1077 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1079 env
->cpuid_version
|= value
<< 8;
1083 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1084 const char *name
, Error
**errp
)
1086 X86CPU
*cpu
= X86_CPU(obj
);
1087 CPUX86State
*env
= &cpu
->env
;
1090 value
= (env
->cpuid_version
>> 4) & 0xf;
1091 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1092 visit_type_int(v
, &value
, name
, errp
);
1095 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1096 const char *name
, Error
**errp
)
1098 X86CPU
*cpu
= X86_CPU(obj
);
1099 CPUX86State
*env
= &cpu
->env
;
1100 const int64_t min
= 0;
1101 const int64_t max
= 0xff;
1104 visit_type_int(v
, &value
, name
, errp
);
1105 if (error_is_set(errp
)) {
1108 if (value
< min
|| value
> max
) {
1109 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1110 name
? name
: "null", value
, min
, max
);
1114 env
->cpuid_version
&= ~0xf00f0;
1115 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1118 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1119 void *opaque
, const char *name
,
1122 X86CPU
*cpu
= X86_CPU(obj
);
1123 CPUX86State
*env
= &cpu
->env
;
1126 value
= env
->cpuid_version
& 0xf;
1127 visit_type_int(v
, &value
, name
, errp
);
1130 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1131 void *opaque
, const char *name
,
1134 X86CPU
*cpu
= X86_CPU(obj
);
1135 CPUX86State
*env
= &cpu
->env
;
1136 const int64_t min
= 0;
1137 const int64_t max
= 0xf;
1140 visit_type_int(v
, &value
, name
, errp
);
1141 if (error_is_set(errp
)) {
1144 if (value
< min
|| value
> max
) {
1145 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1146 name
? name
: "null", value
, min
, max
);
1150 env
->cpuid_version
&= ~0xf;
1151 env
->cpuid_version
|= value
& 0xf;
1154 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1155 const char *name
, Error
**errp
)
1157 X86CPU
*cpu
= X86_CPU(obj
);
1159 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1162 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1163 const char *name
, Error
**errp
)
1165 X86CPU
*cpu
= X86_CPU(obj
);
1167 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1170 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1171 const char *name
, Error
**errp
)
1173 X86CPU
*cpu
= X86_CPU(obj
);
1175 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1178 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1179 const char *name
, Error
**errp
)
1181 X86CPU
*cpu
= X86_CPU(obj
);
1183 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1186 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1188 X86CPU
*cpu
= X86_CPU(obj
);
1189 CPUX86State
*env
= &cpu
->env
;
1193 value
= (char *)g_malloc(CPUID_VENDOR_SZ
+ 1);
1194 for (i
= 0; i
< 4; i
++) {
1195 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
1196 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
1197 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
1199 value
[CPUID_VENDOR_SZ
] = '\0';
1203 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1206 X86CPU
*cpu
= X86_CPU(obj
);
1207 CPUX86State
*env
= &cpu
->env
;
1210 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1211 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1216 env
->cpuid_vendor1
= 0;
1217 env
->cpuid_vendor2
= 0;
1218 env
->cpuid_vendor3
= 0;
1219 for (i
= 0; i
< 4; i
++) {
1220 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1221 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1222 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1224 env
->cpuid_vendor_override
= 1;
1227 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1229 X86CPU
*cpu
= X86_CPU(obj
);
1230 CPUX86State
*env
= &cpu
->env
;
1234 value
= g_malloc(48 + 1);
1235 for (i
= 0; i
< 48; i
++) {
1236 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1242 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1245 X86CPU
*cpu
= X86_CPU(obj
);
1246 CPUX86State
*env
= &cpu
->env
;
1249 if (model_id
== NULL
) {
1252 len
= strlen(model_id
);
1253 memset(env
->cpuid_model
, 0, 48);
1254 for (i
= 0; i
< 48; i
++) {
1258 c
= (uint8_t)model_id
[i
];
1260 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1264 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1265 const char *name
, Error
**errp
)
1267 X86CPU
*cpu
= X86_CPU(obj
);
1270 value
= cpu
->env
.tsc_khz
* 1000;
1271 visit_type_int(v
, &value
, name
, errp
);
1274 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1275 const char *name
, Error
**errp
)
1277 X86CPU
*cpu
= X86_CPU(obj
);
1278 const int64_t min
= 0;
1279 const int64_t max
= INT64_MAX
;
1282 visit_type_int(v
, &value
, name
, errp
);
1283 if (error_is_set(errp
)) {
1286 if (value
< min
|| value
> max
) {
1287 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1288 name
? name
: "null", value
, min
, max
);
1292 cpu
->env
.tsc_khz
= value
/ 1000;
1295 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *name
)
1299 for (def
= x86_defs
; def
; def
= def
->next
) {
1300 if (name
&& !strcmp(name
, def
->name
)) {
1304 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
1305 kvm_cpu_fill_host(x86_cpu_def
);
1309 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1315 /* Parse "+feature,-feature,feature=foo" CPU feature string
1317 static int cpu_x86_parse_featurestr(x86_def_t
*x86_cpu_def
, char *features
)
1320 char *featurestr
; /* Single 'key=value" string being parsed */
1321 /* Features to be added */
1322 FeatureWordArray plus_features
= {
1323 [FEAT_KVM
] = kvm_default_features
,
1325 /* Features to be removed */
1326 FeatureWordArray minus_features
= { 0 };
1329 add_flagname_to_bitmaps("hypervisor", plus_features
);
1331 featurestr
= features
? strtok(features
, ",") : NULL
;
1333 while (featurestr
) {
1335 if (featurestr
[0] == '+') {
1336 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
);
1337 } else if (featurestr
[0] == '-') {
1338 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
);
1339 } else if ((val
= strchr(featurestr
, '='))) {
1341 if (!strcmp(featurestr
, "family")) {
1343 numvalue
= strtoul(val
, &err
, 0);
1344 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
1345 fprintf(stderr
, "bad numerical value %s\n", val
);
1348 x86_cpu_def
->family
= numvalue
;
1349 } else if (!strcmp(featurestr
, "model")) {
1351 numvalue
= strtoul(val
, &err
, 0);
1352 if (!*val
|| *err
|| numvalue
> 0xff) {
1353 fprintf(stderr
, "bad numerical value %s\n", val
);
1356 x86_cpu_def
->model
= numvalue
;
1357 } else if (!strcmp(featurestr
, "stepping")) {
1359 numvalue
= strtoul(val
, &err
, 0);
1360 if (!*val
|| *err
|| numvalue
> 0xf) {
1361 fprintf(stderr
, "bad numerical value %s\n", val
);
1364 x86_cpu_def
->stepping
= numvalue
;
1365 } else if (!strcmp(featurestr
, "level")) {
1367 numvalue
= strtoul(val
, &err
, 0);
1368 if (!*val
|| *err
) {
1369 fprintf(stderr
, "bad numerical value %s\n", val
);
1372 x86_cpu_def
->level
= numvalue
;
1373 } else if (!strcmp(featurestr
, "xlevel")) {
1375 numvalue
= strtoul(val
, &err
, 0);
1376 if (!*val
|| *err
) {
1377 fprintf(stderr
, "bad numerical value %s\n", val
);
1380 if (numvalue
< 0x80000000) {
1381 numvalue
+= 0x80000000;
1383 x86_cpu_def
->xlevel
= numvalue
;
1384 } else if (!strcmp(featurestr
, "vendor")) {
1385 if (strlen(val
) != 12) {
1386 fprintf(stderr
, "vendor string must be 12 chars long\n");
1389 x86_cpu_def
->vendor1
= 0;
1390 x86_cpu_def
->vendor2
= 0;
1391 x86_cpu_def
->vendor3
= 0;
1392 for(i
= 0; i
< 4; i
++) {
1393 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
1394 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
1395 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
1397 x86_cpu_def
->vendor_override
= 1;
1398 } else if (!strcmp(featurestr
, "model_id")) {
1399 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
1401 } else if (!strcmp(featurestr
, "tsc_freq")) {
1405 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1406 STRTOSZ_DEFSUFFIX_B
, 1000);
1407 if (tsc_freq
< 0 || *err
) {
1408 fprintf(stderr
, "bad numerical value %s\n", val
);
1411 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
1412 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
1414 numvalue
= strtoul(val
, &err
, 0);
1415 if (!*val
|| *err
) {
1416 fprintf(stderr
, "bad numerical value %s\n", val
);
1419 hyperv_set_spinlock_retries(numvalue
);
1421 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1424 } else if (!strcmp(featurestr
, "check")) {
1426 } else if (!strcmp(featurestr
, "enforce")) {
1427 check_cpuid
= enforce_cpuid
= 1;
1428 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1429 hyperv_enable_relaxed_timing(true);
1430 } else if (!strcmp(featurestr
, "hv_vapic")) {
1431 hyperv_enable_vapic_recommended(true);
1433 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1436 featurestr
= strtok(NULL
, ",");
1438 x86_cpu_def
->features
|= plus_features
[FEAT_1_EDX
];
1439 x86_cpu_def
->ext_features
|= plus_features
[FEAT_1_ECX
];
1440 x86_cpu_def
->ext2_features
|= plus_features
[FEAT_8000_0001_EDX
];
1441 x86_cpu_def
->ext3_features
|= plus_features
[FEAT_8000_0001_ECX
];
1442 x86_cpu_def
->kvm_features
|= plus_features
[FEAT_KVM
];
1443 x86_cpu_def
->svm_features
|= plus_features
[FEAT_SVM
];
1444 x86_cpu_def
->cpuid_7_0_ebx_features
|= plus_features
[FEAT_7_0_EBX
];
1445 x86_cpu_def
->features
&= ~minus_features
[FEAT_1_EDX
];
1446 x86_cpu_def
->ext_features
&= ~minus_features
[FEAT_1_ECX
];
1447 x86_cpu_def
->ext2_features
&= ~minus_features
[FEAT_8000_0001_EDX
];
1448 x86_cpu_def
->ext3_features
&= ~minus_features
[FEAT_8000_0001_ECX
];
1449 x86_cpu_def
->kvm_features
&= ~minus_features
[FEAT_KVM
];
1450 x86_cpu_def
->svm_features
&= ~minus_features
[FEAT_SVM
];
1451 x86_cpu_def
->cpuid_7_0_ebx_features
&= ~minus_features
[FEAT_7_0_EBX
];
1452 if (check_cpuid
&& kvm_enabled()) {
1453 if (kvm_check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1462 /* generate a composite string into buf of all cpuid names in featureset
1463 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1464 * if flags, suppress names undefined in featureset.
1466 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1467 const char **featureset
, uint32_t flags
)
1469 const char **p
= &featureset
[31];
1473 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1475 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1476 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1478 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1480 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1481 if (bufsize
<= nc
) {
1483 memcpy(b
, "...", sizeof("..."));
1492 /* generate CPU information. */
1493 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1498 for (def
= x86_defs
; def
; def
= def
->next
) {
1499 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1500 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1502 if (kvm_enabled()) {
1503 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1505 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1506 listflags(buf
, sizeof(buf
), (uint32_t)~0, feature_name
, 1);
1507 (*cpu_fprintf
)(f
, " %s\n", buf
);
1508 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext_feature_name
, 1);
1509 (*cpu_fprintf
)(f
, " %s\n", buf
);
1510 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext2_feature_name
, 1);
1511 (*cpu_fprintf
)(f
, " %s\n", buf
);
1512 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext3_feature_name
, 1);
1513 (*cpu_fprintf
)(f
, " %s\n", buf
);
1516 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1518 CpuDefinitionInfoList
*cpu_list
= NULL
;
1521 for (def
= x86_defs
; def
; def
= def
->next
) {
1522 CpuDefinitionInfoList
*entry
;
1523 CpuDefinitionInfo
*info
;
1525 info
= g_malloc0(sizeof(*info
));
1526 info
->name
= g_strdup(def
->name
);
1528 entry
= g_malloc0(sizeof(*entry
));
1529 entry
->value
= info
;
1530 entry
->next
= cpu_list
;
1538 static void filter_features_for_kvm(X86CPU
*cpu
)
1540 CPUX86State
*env
= &cpu
->env
;
1541 KVMState
*s
= kvm_state
;
1543 env
->cpuid_features
&=
1544 kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
1545 env
->cpuid_ext_features
&=
1546 kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
);
1547 env
->cpuid_ext2_features
&=
1548 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
);
1549 env
->cpuid_ext3_features
&=
1550 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_ECX
);
1551 env
->cpuid_svm_features
&=
1552 kvm_arch_get_supported_cpuid(s
, 0x8000000A, 0, R_EDX
);
1553 env
->cpuid_7_0_ebx_features
&=
1554 kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
);
1555 env
->cpuid_kvm_features
&=
1556 kvm_arch_get_supported_cpuid(s
, KVM_CPUID_FEATURES
, 0, R_EAX
);
1557 env
->cpuid_ext4_features
&=
1558 kvm_arch_get_supported_cpuid(s
, 0xC0000001, 0, R_EDX
);
1563 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1565 CPUX86State
*env
= &cpu
->env
;
1566 x86_def_t def1
, *def
= &def1
;
1567 Error
*error
= NULL
;
1568 char *name
, *features
;
1569 gchar
**model_pieces
;
1571 memset(def
, 0, sizeof(*def
));
1573 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1574 if (!model_pieces
[0]) {
1577 name
= model_pieces
[0];
1578 features
= model_pieces
[1];
1580 if (cpu_x86_find_by_name(def
, name
) < 0) {
1584 if (cpu_x86_parse_featurestr(def
, features
) < 0) {
1587 assert(def
->vendor1
);
1588 env
->cpuid_vendor1
= def
->vendor1
;
1589 env
->cpuid_vendor2
= def
->vendor2
;
1590 env
->cpuid_vendor3
= def
->vendor3
;
1591 env
->cpuid_vendor_override
= def
->vendor_override
;
1592 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1593 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1594 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1595 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1596 env
->cpuid_features
= def
->features
;
1597 env
->cpuid_ext_features
= def
->ext_features
;
1598 env
->cpuid_ext2_features
= def
->ext2_features
;
1599 env
->cpuid_ext3_features
= def
->ext3_features
;
1600 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1601 env
->cpuid_kvm_features
= def
->kvm_features
;
1602 env
->cpuid_svm_features
= def
->svm_features
;
1603 env
->cpuid_ext4_features
= def
->ext4_features
;
1604 env
->cpuid_7_0_ebx_features
= def
->cpuid_7_0_ebx_features
;
1605 env
->cpuid_xlevel2
= def
->xlevel2
;
1606 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1607 "tsc-frequency", &error
);
1609 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1611 fprintf(stderr
, "%s\n", error_get_pretty(error
));
1616 g_strfreev(model_pieces
);
1619 g_strfreev(model_pieces
);
1623 #if !defined(CONFIG_USER_ONLY)
1625 void cpu_clear_apic_feature(CPUX86State
*env
)
1627 env
->cpuid_features
&= ~CPUID_APIC
;
1630 #endif /* !CONFIG_USER_ONLY */
1632 /* Initialize list of CPU models, filling some non-static fields if necessary
1634 void x86_cpudef_setup(void)
1637 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1639 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1640 x86_def_t
*def
= &builtin_x86_defs
[i
];
1641 def
->next
= x86_defs
;
1643 /* Look for specific "cpudef" models that */
1644 /* have the QEMU version in .model_id */
1645 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1646 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1647 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1648 "QEMU Virtual CPU version ");
1649 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1650 qemu_get_version());
1659 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1660 uint32_t *ecx
, uint32_t *edx
)
1662 *ebx
= env
->cpuid_vendor1
;
1663 *edx
= env
->cpuid_vendor2
;
1664 *ecx
= env
->cpuid_vendor3
;
1666 /* sysenter isn't supported on compatibility mode on AMD, syscall
1667 * isn't supported in compatibility mode on Intel.
1668 * Normally we advertise the actual cpu vendor, but you can override
1669 * this if you want to use KVM's sysenter/syscall emulation
1670 * in compatibility mode and when doing cross vendor migration
1672 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1673 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1677 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1678 uint32_t *eax
, uint32_t *ebx
,
1679 uint32_t *ecx
, uint32_t *edx
)
1681 X86CPU
*cpu
= x86_env_get_cpu(env
);
1682 CPUState
*cs
= CPU(cpu
);
1684 /* test if maximum index reached */
1685 if (index
& 0x80000000) {
1686 if (index
> env
->cpuid_xlevel
) {
1687 if (env
->cpuid_xlevel2
> 0) {
1688 /* Handle the Centaur's CPUID instruction. */
1689 if (index
> env
->cpuid_xlevel2
) {
1690 index
= env
->cpuid_xlevel2
;
1691 } else if (index
< 0xC0000000) {
1692 index
= env
->cpuid_xlevel
;
1695 /* Intel documentation states that invalid EAX input will
1696 * return the same information as EAX=cpuid_level
1697 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1699 index
= env
->cpuid_level
;
1703 if (index
> env
->cpuid_level
)
1704 index
= env
->cpuid_level
;
1709 *eax
= env
->cpuid_level
;
1710 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1713 *eax
= env
->cpuid_version
;
1714 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1715 *ecx
= env
->cpuid_ext_features
;
1716 *edx
= env
->cpuid_features
;
1717 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
1718 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
1719 *edx
|= 1 << 28; /* HTT bit */
1723 /* cache info: needed for Pentium Pro compatibility */
1730 /* cache info: needed for Core compatibility */
1731 if (cs
->nr_cores
> 1) {
1732 *eax
= (cs
->nr_cores
- 1) << 26;
1737 case 0: /* L1 dcache info */
1743 case 1: /* L1 icache info */
1749 case 2: /* L2 cache info */
1751 if (cs
->nr_threads
> 1) {
1752 *eax
|= (cs
->nr_threads
- 1) << 14;
1758 default: /* end of info */
1767 /* mwait info: needed for Core compatibility */
1768 *eax
= 0; /* Smallest monitor-line size in bytes */
1769 *ebx
= 0; /* Largest monitor-line size in bytes */
1770 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1774 /* Thermal and Power Leaf */
1781 /* Structured Extended Feature Flags Enumeration Leaf */
1783 *eax
= 0; /* Maximum ECX value for sub-leaves */
1784 *ebx
= env
->cpuid_7_0_ebx_features
; /* Feature flags */
1785 *ecx
= 0; /* Reserved */
1786 *edx
= 0; /* Reserved */
1795 /* Direct Cache Access Information Leaf */
1796 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1802 /* Architectural Performance Monitoring Leaf */
1803 if (kvm_enabled()) {
1804 KVMState
*s
= cs
->kvm_state
;
1806 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1807 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1808 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1809 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1818 /* Processor Extended State */
1819 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1826 if (kvm_enabled()) {
1827 KVMState
*s
= cs
->kvm_state
;
1829 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1830 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1831 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1832 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1841 *eax
= env
->cpuid_xlevel
;
1842 *ebx
= env
->cpuid_vendor1
;
1843 *edx
= env
->cpuid_vendor2
;
1844 *ecx
= env
->cpuid_vendor3
;
1847 *eax
= env
->cpuid_version
;
1849 *ecx
= env
->cpuid_ext3_features
;
1850 *edx
= env
->cpuid_ext2_features
;
1852 /* The Linux kernel checks for the CMPLegacy bit and
1853 * discards multiple thread information if it is set.
1854 * So dont set it here for Intel to make Linux guests happy.
1856 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
1857 uint32_t tebx
, tecx
, tedx
;
1858 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1859 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1860 tedx
!= CPUID_VENDOR_INTEL_2
||
1861 tecx
!= CPUID_VENDOR_INTEL_3
) {
1862 *ecx
|= 1 << 1; /* CmpLegacy bit */
1869 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1870 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1871 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1872 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1875 /* cache info (L1 cache) */
1882 /* cache info (L2 cache) */
1889 /* virtual & phys address size in low 2 bytes. */
1890 /* XXX: This value must match the one used in the MMU code. */
1891 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1892 /* 64 bit processor */
1893 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1894 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1896 if (env
->cpuid_features
& CPUID_PSE36
)
1897 *eax
= 0x00000024; /* 36 bits physical */
1899 *eax
= 0x00000020; /* 32 bits physical */
1904 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
1905 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
1909 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1910 *eax
= 0x00000001; /* SVM Revision */
1911 *ebx
= 0x00000010; /* nr of ASIDs */
1913 *edx
= env
->cpuid_svm_features
; /* optional features */
1922 *eax
= env
->cpuid_xlevel2
;
1928 /* Support for VIA CPU's CPUID instruction */
1929 *eax
= env
->cpuid_version
;
1932 *edx
= env
->cpuid_ext4_features
;
1937 /* Reserved for the future, and now filled with zero */
1944 /* reserved values: zero */
1953 /* CPUClass::reset() */
1954 static void x86_cpu_reset(CPUState
*s
)
1956 X86CPU
*cpu
= X86_CPU(s
);
1957 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1958 CPUX86State
*env
= &cpu
->env
;
1961 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1962 qemu_log("CPU Reset (CPU %d)\n", s
->cpu_index
);
1963 log_cpu_state(env
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1966 xcc
->parent_reset(s
);
1969 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1973 env
->old_exception
= -1;
1975 /* init to reset state */
1977 #ifdef CONFIG_SOFTMMU
1978 env
->hflags
|= HF_SOFTMMU_MASK
;
1980 env
->hflags2
|= HF2_GIF_MASK
;
1982 cpu_x86_update_cr0(env
, 0x60000010);
1983 env
->a20_mask
= ~0x0;
1984 env
->smbase
= 0x30000;
1986 env
->idt
.limit
= 0xffff;
1987 env
->gdt
.limit
= 0xffff;
1988 env
->ldt
.limit
= 0xffff;
1989 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1990 env
->tr
.limit
= 0xffff;
1991 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1993 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1994 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1995 DESC_R_MASK
| DESC_A_MASK
);
1996 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1997 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1999 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2000 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2002 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2003 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2005 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2006 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2008 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2009 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2013 env
->regs
[R_EDX
] = env
->cpuid_version
;
2018 for (i
= 0; i
< 8; i
++) {
2023 env
->mxcsr
= 0x1f80;
2025 env
->pat
= 0x0007040600070406ULL
;
2026 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2028 memset(env
->dr
, 0, sizeof(env
->dr
));
2029 env
->dr
[6] = DR6_FIXED_1
;
2030 env
->dr
[7] = DR7_FIXED_1
;
2031 cpu_breakpoint_remove_all(env
, BP_CPU
);
2032 cpu_watchpoint_remove_all(env
, BP_CPU
);
2034 #if !defined(CONFIG_USER_ONLY)
2035 /* We hard-wire the BSP to the first CPU. */
2036 if (s
->cpu_index
== 0) {
2037 apic_designate_bsp(env
->apic_state
);
2040 env
->halted
= !cpu_is_bsp(cpu
);
2044 #ifndef CONFIG_USER_ONLY
2045 bool cpu_is_bsp(X86CPU
*cpu
)
2047 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
2050 /* TODO: remove me, when reset over QOM tree is implemented */
2051 static void x86_cpu_machine_reset_cb(void *opaque
)
2053 X86CPU
*cpu
= opaque
;
2054 cpu_reset(CPU(cpu
));
2058 static void mce_init(X86CPU
*cpu
)
2060 CPUX86State
*cenv
= &cpu
->env
;
2063 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2064 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
2065 (CPUID_MCE
| CPUID_MCA
)) {
2066 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2067 cenv
->mcg_ctl
= ~(uint64_t)0;
2068 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2069 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2074 #define MSI_ADDR_BASE 0xfee00000
2076 #ifndef CONFIG_USER_ONLY
2077 static void x86_cpu_apic_init(X86CPU
*cpu
, Error
**errp
)
2079 static int apic_mapped
;
2080 CPUX86State
*env
= &cpu
->env
;
2081 APICCommonState
*apic
;
2082 const char *apic_type
= "apic";
2084 if (kvm_irqchip_in_kernel()) {
2085 apic_type
= "kvm-apic";
2086 } else if (xen_enabled()) {
2087 apic_type
= "xen-apic";
2090 env
->apic_state
= qdev_try_create(NULL
, apic_type
);
2091 if (env
->apic_state
== NULL
) {
2092 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2096 object_property_add_child(OBJECT(cpu
), "apic",
2097 OBJECT(env
->apic_state
), NULL
);
2098 qdev_prop_set_uint8(env
->apic_state
, "id", env
->cpuid_apic_id
);
2099 /* TODO: convert to link<> */
2100 apic
= APIC_COMMON(env
->apic_state
);
2103 if (qdev_init(env
->apic_state
)) {
2104 error_setg(errp
, "APIC device '%s' could not be initialized",
2105 object_get_typename(OBJECT(env
->apic_state
)));
2109 /* XXX: mapping more APICs at the same memory location */
2110 if (apic_mapped
== 0) {
2111 /* NOTE: the APIC is directly connected to the CPU - it is not
2112 on the global memory bus. */
2113 /* XXX: what if the base changes? */
2114 sysbus_mmio_map(sysbus_from_qdev(env
->apic_state
), 0, MSI_ADDR_BASE
);
2120 void x86_cpu_realize(Object
*obj
, Error
**errp
)
2122 X86CPU
*cpu
= X86_CPU(obj
);
2123 CPUX86State
*env
= &cpu
->env
;
2125 if (env
->cpuid_7_0_ebx_features
&& env
->cpuid_level
< 7) {
2126 env
->cpuid_level
= 7;
2129 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2132 if (env
->cpuid_vendor1
== CPUID_VENDOR_AMD_1
&&
2133 env
->cpuid_vendor2
== CPUID_VENDOR_AMD_2
&&
2134 env
->cpuid_vendor3
== CPUID_VENDOR_AMD_3
) {
2135 env
->cpuid_ext2_features
&= ~CPUID_EXT2_AMD_ALIASES
;
2136 env
->cpuid_ext2_features
|= (env
->cpuid_features
2137 & CPUID_EXT2_AMD_ALIASES
);
2140 if (!kvm_enabled()) {
2141 env
->cpuid_features
&= TCG_FEATURES
;
2142 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
2143 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
2144 #ifdef TARGET_X86_64
2145 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
2148 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
2149 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
2152 filter_features_for_kvm(cpu
);
2156 #ifndef CONFIG_USER_ONLY
2157 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2159 if (cpu
->env
.cpuid_features
& CPUID_APIC
|| smp_cpus
> 1) {
2160 x86_cpu_apic_init(cpu
, errp
);
2161 if (error_is_set(errp
)) {
2168 qemu_init_vcpu(&cpu
->env
);
2169 cpu_reset(CPU(cpu
));
2172 static void x86_cpu_initfn(Object
*obj
)
2174 CPUState
*cs
= CPU(obj
);
2175 X86CPU
*cpu
= X86_CPU(obj
);
2176 CPUX86State
*env
= &cpu
->env
;
2181 object_property_add(obj
, "family", "int",
2182 x86_cpuid_version_get_family
,
2183 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2184 object_property_add(obj
, "model", "int",
2185 x86_cpuid_version_get_model
,
2186 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2187 object_property_add(obj
, "stepping", "int",
2188 x86_cpuid_version_get_stepping
,
2189 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2190 object_property_add(obj
, "level", "int",
2191 x86_cpuid_get_level
,
2192 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2193 object_property_add(obj
, "xlevel", "int",
2194 x86_cpuid_get_xlevel
,
2195 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2196 object_property_add_str(obj
, "vendor",
2197 x86_cpuid_get_vendor
,
2198 x86_cpuid_set_vendor
, NULL
);
2199 object_property_add_str(obj
, "model-id",
2200 x86_cpuid_get_model_id
,
2201 x86_cpuid_set_model_id
, NULL
);
2202 object_property_add(obj
, "tsc-frequency", "int",
2203 x86_cpuid_get_tsc_freq
,
2204 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2206 env
->cpuid_apic_id
= cs
->cpu_index
;
2208 /* init various static tables used in TCG mode */
2209 if (tcg_enabled() && !inited
) {
2211 optimize_flags_init();
2212 #ifndef CONFIG_USER_ONLY
2213 cpu_set_debug_excp_handler(breakpoint_handler
);
2218 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2220 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2221 CPUClass
*cc
= CPU_CLASS(oc
);
2223 xcc
->parent_reset
= cc
->reset
;
2224 cc
->reset
= x86_cpu_reset
;
2227 static const TypeInfo x86_cpu_type_info
= {
2228 .name
= TYPE_X86_CPU
,
2230 .instance_size
= sizeof(X86CPU
),
2231 .instance_init
= x86_cpu_initfn
,
2233 .class_size
= sizeof(X86CPUClass
),
2234 .class_init
= x86_cpu_common_class_init
,
2237 static void x86_cpu_register_types(void)
2239 type_register_static(&x86_cpu_type_info
);
2242 type_init(x86_cpu_register_types
)