2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
51 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
52 uint32_t vendor2
, uint32_t vendor3
)
55 for (i
= 0; i
< 4; i
++) {
56 dst
[i
] = vendor1
>> (8 * i
);
57 dst
[i
+ 4] = vendor2
>> (8 * i
);
58 dst
[i
+ 8] = vendor3
>> (8 * i
);
60 dst
[CPUID_VENDOR_SZ
] = '\0';
63 /* feature flags taken from "Intel Processor Identification and the CPUID
64 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
65 * between feature naming conventions, aliases may be added.
67 static const char *feature_name
[] = {
68 "fpu", "vme", "de", "pse",
69 "tsc", "msr", "pae", "mce",
70 "cx8", "apic", NULL
, "sep",
71 "mtrr", "pge", "mca", "cmov",
72 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
73 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
74 "fxsr", "sse", "sse2", "ss",
75 "ht" /* Intel htt */, "tm", "ia64", "pbe",
77 static const char *ext_feature_name
[] = {
78 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
79 "ds_cpl", "vmx", "smx", "est",
80 "tm2", "ssse3", "cid", NULL
,
81 "fma", "cx16", "xtpr", "pdcm",
82 NULL
, "pcid", "dca", "sse4.1|sse4_1",
83 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
84 "tsc-deadline", "aes", "xsave", "osxsave",
85 "avx", "f16c", "rdrand", "hypervisor",
87 /* Feature names that are already defined on feature_name[] but are set on
88 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
89 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
90 * if and only if CPU vendor is AMD.
92 static const char *ext2_feature_name
[] = {
93 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
94 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
95 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
96 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
97 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
98 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
99 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
100 NULL
, "lm|i64", "3dnowext", "3dnow",
102 static const char *ext3_feature_name
[] = {
103 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
104 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
105 "3dnowprefetch", "osvw", "ibs", "xop",
106 "skinit", "wdt", NULL
, "lwp",
107 "fma4", "tce", NULL
, "nodeid_msr",
108 NULL
, "tbm", "topoext", "perfctr_core",
109 "perfctr_nb", NULL
, NULL
, NULL
,
110 NULL
, NULL
, NULL
, NULL
,
113 static const char *ext4_feature_name
[] = {
114 NULL
, NULL
, "xstore", "xstore-en",
115 NULL
, NULL
, "xcrypt", "xcrypt-en",
116 "ace2", "ace2-en", "phe", "phe-en",
117 "pmm", "pmm-en", NULL
, NULL
,
118 NULL
, NULL
, NULL
, NULL
,
119 NULL
, NULL
, NULL
, NULL
,
120 NULL
, NULL
, NULL
, NULL
,
121 NULL
, NULL
, NULL
, NULL
,
124 static const char *kvm_feature_name
[] = {
125 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
126 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL
,
127 NULL
, NULL
, NULL
, NULL
,
128 NULL
, NULL
, NULL
, NULL
,
129 NULL
, NULL
, NULL
, NULL
,
130 NULL
, NULL
, NULL
, NULL
,
131 NULL
, NULL
, NULL
, NULL
,
132 NULL
, NULL
, NULL
, NULL
,
135 static const char *svm_feature_name
[] = {
136 "npt", "lbrv", "svm_lock", "nrip_save",
137 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
138 NULL
, NULL
, "pause_filter", NULL
,
139 "pfthreshold", NULL
, NULL
, NULL
,
140 NULL
, NULL
, NULL
, NULL
,
141 NULL
, NULL
, NULL
, NULL
,
142 NULL
, NULL
, NULL
, NULL
,
143 NULL
, NULL
, NULL
, NULL
,
146 static const char *cpuid_7_0_ebx_feature_name
[] = {
147 "fsgsbase", NULL
, NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
148 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, NULL
, NULL
,
149 NULL
, NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
150 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
153 typedef struct FeatureWordInfo
{
154 const char **feat_names
;
155 uint32_t cpuid_eax
; /* Input EAX for CPUID */
156 int cpuid_reg
; /* R_* register constant */
159 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
161 .feat_names
= feature_name
,
162 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
165 .feat_names
= ext_feature_name
,
166 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
168 [FEAT_8000_0001_EDX
] = {
169 .feat_names
= ext2_feature_name
,
170 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
172 [FEAT_8000_0001_ECX
] = {
173 .feat_names
= ext3_feature_name
,
174 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
176 [FEAT_C000_0001_EDX
] = {
177 .feat_names
= ext4_feature_name
,
178 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
181 .feat_names
= kvm_feature_name
,
182 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
185 .feat_names
= svm_feature_name
,
186 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
189 .feat_names
= cpuid_7_0_ebx_feature_name
,
190 .cpuid_eax
= 7, .cpuid_reg
= R_EBX
,
194 const char *get_register_name_32(unsigned int reg
)
196 static const char *reg_names
[CPU_NB_REGS32
] = {
207 if (reg
> CPU_NB_REGS32
) {
210 return reg_names
[reg
];
213 /* collects per-function cpuid data
215 typedef struct model_features_t
{
216 uint32_t *guest_feat
;
218 FeatureWord feat_word
;
222 int enforce_cpuid
= 0;
224 static uint32_t kvm_default_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
225 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
226 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
227 (1 << KVM_FEATURE_ASYNC_PF
) |
228 (1 << KVM_FEATURE_STEAL_TIME
) |
229 (1 << KVM_FEATURE_PV_EOI
) |
230 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
232 void disable_kvm_pv_eoi(void)
234 kvm_default_features
&= ~(1UL << KVM_FEATURE_PV_EOI
);
237 void host_cpuid(uint32_t function
, uint32_t count
,
238 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
240 #if defined(CONFIG_KVM)
245 : "=a"(vec
[0]), "=b"(vec
[1]),
246 "=c"(vec
[2]), "=d"(vec
[3])
247 : "0"(function
), "c"(count
) : "cc");
249 asm volatile("pusha \n\t"
251 "mov %%eax, 0(%2) \n\t"
252 "mov %%ebx, 4(%2) \n\t"
253 "mov %%ecx, 8(%2) \n\t"
254 "mov %%edx, 12(%2) \n\t"
256 : : "a"(function
), "c"(count
), "S"(vec
)
271 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
273 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
274 * a substring. ex if !NULL points to the first char after a substring,
275 * otherwise the string is assumed to sized by a terminating nul.
276 * Return lexical ordering of *s1:*s2.
278 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
282 if (!*s1
|| !*s2
|| *s1
!= *s2
)
285 if (s1
== e1
&& s2
== e2
)
294 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
295 * '|' delimited (possibly empty) strings in which case search for a match
296 * within the alternatives proceeds left to right. Return 0 for success,
297 * non-zero otherwise.
299 static int altcmp(const char *s
, const char *e
, const char *altstr
)
303 for (q
= p
= altstr
; ; ) {
304 while (*p
&& *p
!= '|')
306 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
315 /* search featureset for flag *[s..e), if found set corresponding bit in
316 * *pval and return true, otherwise return false
318 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
319 const char **featureset
)
325 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
326 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
334 static void add_flagname_to_bitmaps(const char *flagname
,
335 FeatureWordArray words
)
338 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
339 FeatureWordInfo
*wi
= &feature_word_info
[w
];
340 if (wi
->feat_names
&&
341 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
345 if (w
== FEATURE_WORDS
) {
346 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
350 typedef struct x86_def_t
{
355 /* vendor is zero-terminated, 12 character ASCII string */
356 char vendor
[CPUID_VENDOR_SZ
+ 1];
360 FeatureWordArray features
;
364 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
365 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
366 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
367 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
368 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
369 CPUID_PSE36 | CPUID_FXSR)
370 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
371 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
372 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
373 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
374 CPUID_PAE | CPUID_SEP | CPUID_APIC)
376 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
377 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
378 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
379 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
380 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
381 /* partly implemented:
382 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
383 CPUID_PSE36 (needed for Solaris) */
385 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
386 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
387 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
388 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
389 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
391 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
392 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
393 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
394 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
395 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
397 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
398 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
399 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
401 CPUID_EXT2_PDPE1GB */
402 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
403 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
404 #define TCG_SVM_FEATURES 0
405 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
406 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
408 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
409 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
410 CPUID_7_0_EBX_RDSEED */
412 /* built-in CPU model definitions
414 static x86_def_t builtin_x86_defs
[] = {
418 .vendor
= CPUID_VENDOR_AMD
,
422 .features
[FEAT_1_EDX
] =
424 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
426 .features
[FEAT_1_ECX
] =
427 CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
428 .features
[FEAT_8000_0001_EDX
] =
429 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
430 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
431 .features
[FEAT_8000_0001_ECX
] =
432 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
433 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
434 .xlevel
= 0x8000000A,
439 .vendor
= CPUID_VENDOR_AMD
,
443 .features
[FEAT_1_EDX
] =
445 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
446 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
447 .features
[FEAT_1_ECX
] =
448 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
450 .features
[FEAT_8000_0001_EDX
] =
451 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
452 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
453 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
454 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
455 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
457 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
458 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
459 .features
[FEAT_8000_0001_ECX
] =
460 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
461 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
462 .features
[FEAT_SVM
] =
463 CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
464 .xlevel
= 0x8000001A,
465 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
470 .vendor
= CPUID_VENDOR_INTEL
,
474 .features
[FEAT_1_EDX
] =
476 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
477 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
478 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
479 .features
[FEAT_1_ECX
] =
480 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
481 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
482 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
483 .features
[FEAT_8000_0001_EDX
] =
484 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
485 .features
[FEAT_8000_0001_ECX
] =
487 .xlevel
= 0x80000008,
488 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
493 .vendor
= CPUID_VENDOR_INTEL
,
497 /* Missing: CPUID_VME, CPUID_HT */
498 .features
[FEAT_1_EDX
] =
500 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
502 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
503 .features
[FEAT_1_ECX
] =
504 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
505 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
506 .features
[FEAT_8000_0001_EDX
] =
507 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
508 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
509 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
510 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
511 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
512 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
513 .features
[FEAT_8000_0001_ECX
] =
515 .xlevel
= 0x80000008,
516 .model_id
= "Common KVM processor"
521 .vendor
= CPUID_VENDOR_INTEL
,
525 .features
[FEAT_1_EDX
] =
527 .features
[FEAT_1_ECX
] =
528 CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
529 .xlevel
= 0x80000004,
534 .vendor
= CPUID_VENDOR_INTEL
,
538 .features
[FEAT_1_EDX
] =
540 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
541 .features
[FEAT_1_ECX
] =
543 .features
[FEAT_8000_0001_EDX
] =
544 PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
545 .features
[FEAT_8000_0001_ECX
] =
547 .xlevel
= 0x80000008,
548 .model_id
= "Common 32-bit KVM processor"
553 .vendor
= CPUID_VENDOR_INTEL
,
557 .features
[FEAT_1_EDX
] =
558 PPRO_FEATURES
| CPUID_VME
|
559 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
560 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
561 .features
[FEAT_1_ECX
] =
562 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
563 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
564 .features
[FEAT_8000_0001_EDX
] =
566 .xlevel
= 0x80000008,
567 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
572 .vendor
= CPUID_VENDOR_INTEL
,
576 .features
[FEAT_1_EDX
] =
583 .vendor
= CPUID_VENDOR_INTEL
,
587 .features
[FEAT_1_EDX
] =
594 .vendor
= CPUID_VENDOR_INTEL
,
598 .features
[FEAT_1_EDX
] =
605 .vendor
= CPUID_VENDOR_INTEL
,
609 .features
[FEAT_1_EDX
] =
616 .vendor
= CPUID_VENDOR_AMD
,
620 .features
[FEAT_1_EDX
] =
621 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
623 .features
[FEAT_8000_0001_EDX
] =
624 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
625 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
626 .xlevel
= 0x80000008,
630 /* original is on level 10 */
632 .vendor
= CPUID_VENDOR_INTEL
,
636 .features
[FEAT_1_EDX
] =
638 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
639 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
640 /* Some CPUs got no CPUID_SEP */
641 .features
[FEAT_1_ECX
] =
642 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
643 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
644 .features
[FEAT_8000_0001_EDX
] =
645 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
647 .features
[FEAT_8000_0001_ECX
] =
649 .xlevel
= 0x8000000A,
650 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
655 .vendor
= CPUID_VENDOR_INTEL
,
659 .features
[FEAT_1_EDX
] =
660 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
661 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
662 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
663 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
664 CPUID_DE
| CPUID_FP87
,
665 .features
[FEAT_1_ECX
] =
666 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
667 .features
[FEAT_8000_0001_EDX
] =
668 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
669 .features
[FEAT_8000_0001_ECX
] =
671 .xlevel
= 0x8000000A,
672 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
677 .vendor
= CPUID_VENDOR_INTEL
,
681 .features
[FEAT_1_EDX
] =
682 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
683 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
684 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
685 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
686 CPUID_DE
| CPUID_FP87
,
687 .features
[FEAT_1_ECX
] =
688 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
690 .features
[FEAT_8000_0001_EDX
] =
691 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
692 .features
[FEAT_8000_0001_ECX
] =
694 .xlevel
= 0x8000000A,
695 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
700 .vendor
= CPUID_VENDOR_INTEL
,
704 .features
[FEAT_1_EDX
] =
705 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
706 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
707 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
708 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
709 CPUID_DE
| CPUID_FP87
,
710 .features
[FEAT_1_ECX
] =
711 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
712 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
713 .features
[FEAT_8000_0001_EDX
] =
714 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
715 .features
[FEAT_8000_0001_ECX
] =
717 .xlevel
= 0x8000000A,
718 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
723 .vendor
= CPUID_VENDOR_INTEL
,
727 .features
[FEAT_1_EDX
] =
728 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
729 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
730 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
731 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
732 CPUID_DE
| CPUID_FP87
,
733 .features
[FEAT_1_ECX
] =
734 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
735 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
736 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
737 .features
[FEAT_8000_0001_EDX
] =
738 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
739 .features
[FEAT_8000_0001_ECX
] =
741 .xlevel
= 0x8000000A,
742 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
745 .name
= "SandyBridge",
747 .vendor
= CPUID_VENDOR_INTEL
,
751 .features
[FEAT_1_EDX
] =
752 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
753 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
754 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
755 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
756 CPUID_DE
| CPUID_FP87
,
757 .features
[FEAT_1_ECX
] =
758 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
759 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
760 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
761 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
763 .features
[FEAT_8000_0001_EDX
] =
764 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
766 .features
[FEAT_8000_0001_ECX
] =
768 .xlevel
= 0x8000000A,
769 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
774 .vendor
= CPUID_VENDOR_INTEL
,
778 .features
[FEAT_1_EDX
] =
779 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
780 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
781 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
782 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
783 CPUID_DE
| CPUID_FP87
,
784 .features
[FEAT_1_ECX
] =
785 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
786 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
787 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
788 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
789 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
791 .features
[FEAT_8000_0001_EDX
] =
792 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
794 .features
[FEAT_8000_0001_ECX
] =
796 .features
[FEAT_7_0_EBX
] =
797 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
798 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
799 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
801 .xlevel
= 0x8000000A,
802 .model_id
= "Intel Core Processor (Haswell)",
805 .name
= "Opteron_G1",
807 .vendor
= CPUID_VENDOR_AMD
,
811 .features
[FEAT_1_EDX
] =
812 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
813 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
814 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
815 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
816 CPUID_DE
| CPUID_FP87
,
817 .features
[FEAT_1_ECX
] =
819 .features
[FEAT_8000_0001_EDX
] =
820 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
821 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
822 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
823 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
824 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
825 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
826 .xlevel
= 0x80000008,
827 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
830 .name
= "Opteron_G2",
832 .vendor
= CPUID_VENDOR_AMD
,
836 .features
[FEAT_1_EDX
] =
837 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
838 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
839 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
840 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
841 CPUID_DE
| CPUID_FP87
,
842 .features
[FEAT_1_ECX
] =
843 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
844 .features
[FEAT_8000_0001_EDX
] =
845 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
846 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
847 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
848 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
849 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
850 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
851 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
852 .features
[FEAT_8000_0001_ECX
] =
853 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
854 .xlevel
= 0x80000008,
855 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
858 .name
= "Opteron_G3",
860 .vendor
= CPUID_VENDOR_AMD
,
864 .features
[FEAT_1_EDX
] =
865 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
866 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
867 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
868 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
869 CPUID_DE
| CPUID_FP87
,
870 .features
[FEAT_1_ECX
] =
871 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
873 .features
[FEAT_8000_0001_EDX
] =
874 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
875 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
876 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
877 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
878 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
879 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
880 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
881 .features
[FEAT_8000_0001_ECX
] =
882 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
883 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
884 .xlevel
= 0x80000008,
885 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
888 .name
= "Opteron_G4",
890 .vendor
= CPUID_VENDOR_AMD
,
894 .features
[FEAT_1_EDX
] =
895 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
896 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
897 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
898 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
899 CPUID_DE
| CPUID_FP87
,
900 .features
[FEAT_1_ECX
] =
901 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
902 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
903 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
905 .features
[FEAT_8000_0001_EDX
] =
906 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
907 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
908 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
909 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
910 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
911 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
912 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
913 .features
[FEAT_8000_0001_ECX
] =
914 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
915 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
916 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
918 .xlevel
= 0x8000001A,
919 .model_id
= "AMD Opteron 62xx class CPU",
922 .name
= "Opteron_G5",
924 .vendor
= CPUID_VENDOR_AMD
,
928 .features
[FEAT_1_EDX
] =
929 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
930 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
931 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
932 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
933 CPUID_DE
| CPUID_FP87
,
934 .features
[FEAT_1_ECX
] =
935 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
936 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
937 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
938 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
939 .features
[FEAT_8000_0001_EDX
] =
940 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
941 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
942 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
943 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
944 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
945 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
946 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
947 .features
[FEAT_8000_0001_ECX
] =
948 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
949 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
950 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
952 .xlevel
= 0x8000001A,
953 .model_id
= "AMD Opteron 63xx class CPU",
958 static int cpu_x86_fill_model_id(char *str
)
960 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
963 for (i
= 0; i
< 3; i
++) {
964 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
965 memcpy(str
+ i
* 16 + 0, &eax
, 4);
966 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
967 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
968 memcpy(str
+ i
* 16 + 12, &edx
, 4);
974 /* Fill a x86_def_t struct with information about the host CPU, and
975 * the CPU features supported by the host hardware + host kernel
977 * This function may be called only if KVM is enabled.
979 static void kvm_cpu_fill_host(x86_def_t
*x86_cpu_def
)
982 KVMState
*s
= kvm_state
;
983 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
985 assert(kvm_enabled());
987 x86_cpu_def
->name
= "host";
988 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
989 x86_cpu_vendor_words2str(x86_cpu_def
->vendor
, ebx
, edx
, ecx
);
991 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
992 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
993 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
994 x86_cpu_def
->stepping
= eax
& 0x0F;
996 x86_cpu_def
->level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
997 x86_cpu_def
->features
[FEAT_1_EDX
] =
998 kvm_arch_get_supported_cpuid(s
, 0x1, 0, R_EDX
);
999 x86_cpu_def
->features
[FEAT_1_ECX
] =
1000 kvm_arch_get_supported_cpuid(s
, 0x1, 0, R_ECX
);
1002 if (x86_cpu_def
->level
>= 7) {
1003 x86_cpu_def
->features
[FEAT_7_0_EBX
] =
1004 kvm_arch_get_supported_cpuid(s
, 0x7, 0, R_EBX
);
1006 x86_cpu_def
->features
[FEAT_7_0_EBX
] = 0;
1009 x86_cpu_def
->xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1010 x86_cpu_def
->features
[FEAT_8000_0001_EDX
] =
1011 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
);
1012 x86_cpu_def
->features
[FEAT_8000_0001_ECX
] =
1013 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_ECX
);
1015 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
1017 /* Call Centaur's CPUID instruction. */
1018 if (!strcmp(x86_cpu_def
->vendor
, CPUID_VENDOR_VIA
)) {
1019 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
1020 eax
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1021 if (eax
>= 0xC0000001) {
1022 /* Support VIA max extended level */
1023 x86_cpu_def
->xlevel2
= eax
;
1024 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
1025 x86_cpu_def
->features
[FEAT_C000_0001_EDX
] =
1026 kvm_arch_get_supported_cpuid(s
, 0xC0000001, 0, R_EDX
);
1030 /* Other KVM-specific feature fields: */
1031 x86_cpu_def
->features
[FEAT_SVM
] =
1032 kvm_arch_get_supported_cpuid(s
, 0x8000000A, 0, R_EDX
);
1033 x86_cpu_def
->features
[FEAT_KVM
] =
1034 kvm_arch_get_supported_cpuid(s
, KVM_CPUID_FEATURES
, 0, R_EAX
);
1036 #endif /* CONFIG_KVM */
1039 static int unavailable_host_feature(FeatureWordInfo
*f
, uint32_t mask
)
1043 for (i
= 0; i
< 32; ++i
)
1044 if (1 << i
& mask
) {
1045 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1047 fprintf(stderr
, "warning: host doesn't support requested feature: "
1048 "CPUID.%02XH:%s%s%s [bit %d]\n",
1050 f
->feat_names
[i
] ? "." : "",
1051 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1057 /* Check if all requested cpu flags are making their way to the guest
1059 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1061 * This function may be called only if KVM is enabled.
1063 static int kvm_check_features_against_host(X86CPU
*cpu
)
1065 CPUX86State
*env
= &cpu
->env
;
1069 struct model_features_t ft
[] = {
1070 {&env
->features
[FEAT_1_EDX
],
1071 &host_def
.features
[FEAT_1_EDX
],
1073 {&env
->features
[FEAT_1_ECX
],
1074 &host_def
.features
[FEAT_1_ECX
],
1076 {&env
->features
[FEAT_8000_0001_EDX
],
1077 &host_def
.features
[FEAT_8000_0001_EDX
],
1078 FEAT_8000_0001_EDX
},
1079 {&env
->features
[FEAT_8000_0001_ECX
],
1080 &host_def
.features
[FEAT_8000_0001_ECX
],
1081 FEAT_8000_0001_ECX
},
1082 {&env
->features
[FEAT_C000_0001_EDX
],
1083 &host_def
.features
[FEAT_C000_0001_EDX
],
1084 FEAT_C000_0001_EDX
},
1085 {&env
->features
[FEAT_7_0_EBX
],
1086 &host_def
.features
[FEAT_7_0_EBX
],
1088 {&env
->features
[FEAT_SVM
],
1089 &host_def
.features
[FEAT_SVM
],
1091 {&env
->features
[FEAT_KVM
],
1092 &host_def
.features
[FEAT_KVM
],
1096 assert(kvm_enabled());
1098 kvm_cpu_fill_host(&host_def
);
1099 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
) {
1100 FeatureWord w
= ft
[i
].feat_word
;
1101 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1102 for (mask
= 1; mask
; mask
<<= 1) {
1103 if (*ft
[i
].guest_feat
& mask
&&
1104 !(*ft
[i
].host_feat
& mask
)) {
1105 unavailable_host_feature(wi
, mask
);
1113 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1114 const char *name
, Error
**errp
)
1116 X86CPU
*cpu
= X86_CPU(obj
);
1117 CPUX86State
*env
= &cpu
->env
;
1120 value
= (env
->cpuid_version
>> 8) & 0xf;
1122 value
+= (env
->cpuid_version
>> 20) & 0xff;
1124 visit_type_int(v
, &value
, name
, errp
);
1127 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1128 const char *name
, Error
**errp
)
1130 X86CPU
*cpu
= X86_CPU(obj
);
1131 CPUX86State
*env
= &cpu
->env
;
1132 const int64_t min
= 0;
1133 const int64_t max
= 0xff + 0xf;
1136 visit_type_int(v
, &value
, name
, errp
);
1137 if (error_is_set(errp
)) {
1140 if (value
< min
|| value
> max
) {
1141 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1142 name
? name
: "null", value
, min
, max
);
1146 env
->cpuid_version
&= ~0xff00f00;
1148 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1150 env
->cpuid_version
|= value
<< 8;
1154 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1155 const char *name
, Error
**errp
)
1157 X86CPU
*cpu
= X86_CPU(obj
);
1158 CPUX86State
*env
= &cpu
->env
;
1161 value
= (env
->cpuid_version
>> 4) & 0xf;
1162 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1163 visit_type_int(v
, &value
, name
, errp
);
1166 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1167 const char *name
, Error
**errp
)
1169 X86CPU
*cpu
= X86_CPU(obj
);
1170 CPUX86State
*env
= &cpu
->env
;
1171 const int64_t min
= 0;
1172 const int64_t max
= 0xff;
1175 visit_type_int(v
, &value
, name
, errp
);
1176 if (error_is_set(errp
)) {
1179 if (value
< min
|| value
> max
) {
1180 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1181 name
? name
: "null", value
, min
, max
);
1185 env
->cpuid_version
&= ~0xf00f0;
1186 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1189 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1190 void *opaque
, const char *name
,
1193 X86CPU
*cpu
= X86_CPU(obj
);
1194 CPUX86State
*env
= &cpu
->env
;
1197 value
= env
->cpuid_version
& 0xf;
1198 visit_type_int(v
, &value
, name
, errp
);
1201 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1202 void *opaque
, const char *name
,
1205 X86CPU
*cpu
= X86_CPU(obj
);
1206 CPUX86State
*env
= &cpu
->env
;
1207 const int64_t min
= 0;
1208 const int64_t max
= 0xf;
1211 visit_type_int(v
, &value
, name
, errp
);
1212 if (error_is_set(errp
)) {
1215 if (value
< min
|| value
> max
) {
1216 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1217 name
? name
: "null", value
, min
, max
);
1221 env
->cpuid_version
&= ~0xf;
1222 env
->cpuid_version
|= value
& 0xf;
1225 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1226 const char *name
, Error
**errp
)
1228 X86CPU
*cpu
= X86_CPU(obj
);
1230 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1233 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1234 const char *name
, Error
**errp
)
1236 X86CPU
*cpu
= X86_CPU(obj
);
1238 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1241 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1242 const char *name
, Error
**errp
)
1244 X86CPU
*cpu
= X86_CPU(obj
);
1246 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1249 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1250 const char *name
, Error
**errp
)
1252 X86CPU
*cpu
= X86_CPU(obj
);
1254 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1257 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1259 X86CPU
*cpu
= X86_CPU(obj
);
1260 CPUX86State
*env
= &cpu
->env
;
1263 value
= (char *)g_malloc(CPUID_VENDOR_SZ
+ 1);
1264 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1265 env
->cpuid_vendor3
);
1269 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1272 X86CPU
*cpu
= X86_CPU(obj
);
1273 CPUX86State
*env
= &cpu
->env
;
1276 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1277 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1282 env
->cpuid_vendor1
= 0;
1283 env
->cpuid_vendor2
= 0;
1284 env
->cpuid_vendor3
= 0;
1285 for (i
= 0; i
< 4; i
++) {
1286 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1287 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1288 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1292 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1294 X86CPU
*cpu
= X86_CPU(obj
);
1295 CPUX86State
*env
= &cpu
->env
;
1299 value
= g_malloc(48 + 1);
1300 for (i
= 0; i
< 48; i
++) {
1301 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1307 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1310 X86CPU
*cpu
= X86_CPU(obj
);
1311 CPUX86State
*env
= &cpu
->env
;
1314 if (model_id
== NULL
) {
1317 len
= strlen(model_id
);
1318 memset(env
->cpuid_model
, 0, 48);
1319 for (i
= 0; i
< 48; i
++) {
1323 c
= (uint8_t)model_id
[i
];
1325 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1329 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1330 const char *name
, Error
**errp
)
1332 X86CPU
*cpu
= X86_CPU(obj
);
1335 value
= cpu
->env
.tsc_khz
* 1000;
1336 visit_type_int(v
, &value
, name
, errp
);
1339 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1340 const char *name
, Error
**errp
)
1342 X86CPU
*cpu
= X86_CPU(obj
);
1343 const int64_t min
= 0;
1344 const int64_t max
= INT64_MAX
;
1347 visit_type_int(v
, &value
, name
, errp
);
1348 if (error_is_set(errp
)) {
1351 if (value
< min
|| value
> max
) {
1352 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1353 name
? name
: "null", value
, min
, max
);
1357 cpu
->env
.tsc_khz
= value
/ 1000;
1360 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1361 const char *name
, Error
**errp
)
1363 X86CPU
*cpu
= X86_CPU(obj
);
1364 int64_t value
= cpu
->env
.cpuid_apic_id
;
1366 visit_type_int(v
, &value
, name
, errp
);
1369 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1370 const char *name
, Error
**errp
)
1372 X86CPU
*cpu
= X86_CPU(obj
);
1373 DeviceState
*dev
= DEVICE(obj
);
1374 const int64_t min
= 0;
1375 const int64_t max
= UINT32_MAX
;
1376 Error
*error
= NULL
;
1379 if (dev
->realized
) {
1380 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1381 "it was realized", name
, object_get_typename(obj
));
1385 visit_type_int(v
, &value
, name
, &error
);
1387 error_propagate(errp
, error
);
1390 if (value
< min
|| value
> max
) {
1391 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1392 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1393 object_get_typename(obj
), name
, value
, min
, max
);
1397 if ((value
!= cpu
->env
.cpuid_apic_id
) && cpu_exists(value
)) {
1398 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1401 cpu
->env
.cpuid_apic_id
= value
;
1404 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *name
)
1412 if (kvm_enabled() && strcmp(name
, "host") == 0) {
1413 kvm_cpu_fill_host(x86_cpu_def
);
1417 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1418 def
= &builtin_x86_defs
[i
];
1419 if (strcmp(name
, def
->name
) == 0) {
1420 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1421 /* sysenter isn't supported in compatibility mode on AMD,
1422 * syscall isn't supported in compatibility mode on Intel.
1423 * Normally we advertise the actual CPU vendor, but you can
1424 * override this using the 'vendor' property if you want to use
1425 * KVM's sysenter/syscall emulation in compatibility mode and
1426 * when doing cross vendor migration
1428 if (kvm_enabled()) {
1429 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
1430 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
1431 x86_cpu_vendor_words2str(x86_cpu_def
->vendor
, ebx
, edx
, ecx
);
1440 /* Convert all '_' in a feature string option name to '-', to make feature
1441 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1443 static inline void feat2prop(char *s
)
1445 while ((s
= strchr(s
, '_'))) {
1450 /* Parse "+feature,-feature,feature=foo" CPU feature string
1452 static void cpu_x86_parse_featurestr(X86CPU
*cpu
, char *features
, Error
**errp
)
1454 char *featurestr
; /* Single 'key=value" string being parsed */
1455 /* Features to be added */
1456 FeatureWordArray plus_features
= { 0 };
1457 /* Features to be removed */
1458 FeatureWordArray minus_features
= { 0 };
1460 CPUX86State
*env
= &cpu
->env
;
1462 featurestr
= features
? strtok(features
, ",") : NULL
;
1464 while (featurestr
) {
1466 if (featurestr
[0] == '+') {
1467 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
);
1468 } else if (featurestr
[0] == '-') {
1469 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
);
1470 } else if ((val
= strchr(featurestr
, '='))) {
1472 feat2prop(featurestr
);
1473 if (!strcmp(featurestr
, "family")) {
1474 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1475 } else if (!strcmp(featurestr
, "model")) {
1476 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1477 } else if (!strcmp(featurestr
, "stepping")) {
1478 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1479 } else if (!strcmp(featurestr
, "level")) {
1480 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1481 } else if (!strcmp(featurestr
, "xlevel")) {
1485 numvalue
= strtoul(val
, &err
, 0);
1486 if (!*val
|| *err
) {
1487 error_setg(errp
, "bad numerical value %s", val
);
1490 if (numvalue
< 0x80000000) {
1491 fprintf(stderr
, "xlevel value shall always be >= 0x80000000"
1492 ", fixup will be removed in future versions\n");
1493 numvalue
+= 0x80000000;
1495 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1496 object_property_parse(OBJECT(cpu
), num
, featurestr
, errp
);
1497 } else if (!strcmp(featurestr
, "vendor")) {
1498 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1499 } else if (!strcmp(featurestr
, "model-id")) {
1500 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1501 } else if (!strcmp(featurestr
, "tsc-freq")) {
1506 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1507 STRTOSZ_DEFSUFFIX_B
, 1000);
1508 if (tsc_freq
< 0 || *err
) {
1509 error_setg(errp
, "bad numerical value %s", val
);
1512 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1513 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency", errp
);
1514 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1516 numvalue
= strtoul(val
, &err
, 0);
1517 if (!*val
|| *err
) {
1518 error_setg(errp
, "bad numerical value %s", val
);
1521 hyperv_set_spinlock_retries(numvalue
);
1523 error_setg(errp
, "unrecognized feature %s", featurestr
);
1526 } else if (!strcmp(featurestr
, "check")) {
1528 } else if (!strcmp(featurestr
, "enforce")) {
1529 check_cpuid
= enforce_cpuid
= 1;
1530 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1531 hyperv_enable_relaxed_timing(true);
1532 } else if (!strcmp(featurestr
, "hv_vapic")) {
1533 hyperv_enable_vapic_recommended(true);
1535 error_setg(errp
, "feature string `%s' not in format (+feature|"
1536 "-feature|feature=xyz)", featurestr
);
1539 if (error_is_set(errp
)) {
1542 featurestr
= strtok(NULL
, ",");
1544 env
->features
[FEAT_1_EDX
] |= plus_features
[FEAT_1_EDX
];
1545 env
->features
[FEAT_1_ECX
] |= plus_features
[FEAT_1_ECX
];
1546 env
->features
[FEAT_8000_0001_EDX
] |= plus_features
[FEAT_8000_0001_EDX
];
1547 env
->features
[FEAT_8000_0001_ECX
] |= plus_features
[FEAT_8000_0001_ECX
];
1548 env
->features
[FEAT_C000_0001_EDX
] |= plus_features
[FEAT_C000_0001_EDX
];
1549 env
->features
[FEAT_KVM
] |= plus_features
[FEAT_KVM
];
1550 env
->features
[FEAT_SVM
] |= plus_features
[FEAT_SVM
];
1551 env
->features
[FEAT_7_0_EBX
] |= plus_features
[FEAT_7_0_EBX
];
1552 env
->features
[FEAT_1_EDX
] &= ~minus_features
[FEAT_1_EDX
];
1553 env
->features
[FEAT_1_ECX
] &= ~minus_features
[FEAT_1_ECX
];
1554 env
->features
[FEAT_8000_0001_EDX
] &= ~minus_features
[FEAT_8000_0001_EDX
];
1555 env
->features
[FEAT_8000_0001_ECX
] &= ~minus_features
[FEAT_8000_0001_ECX
];
1556 env
->features
[FEAT_C000_0001_EDX
] &= ~minus_features
[FEAT_C000_0001_EDX
];
1557 env
->features
[FEAT_KVM
] &= ~minus_features
[FEAT_KVM
];
1558 env
->features
[FEAT_SVM
] &= ~minus_features
[FEAT_SVM
];
1559 env
->features
[FEAT_7_0_EBX
] &= ~minus_features
[FEAT_7_0_EBX
];
1565 /* generate a composite string into buf of all cpuid names in featureset
1566 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1567 * if flags, suppress names undefined in featureset.
1569 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1570 const char **featureset
, uint32_t flags
)
1572 const char **p
= &featureset
[31];
1576 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1578 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1579 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1581 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1583 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1584 if (bufsize
<= nc
) {
1586 memcpy(b
, "...", sizeof("..."));
1595 /* generate CPU information. */
1596 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1602 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1603 def
= &builtin_x86_defs
[i
];
1604 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1605 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1608 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
1609 "KVM processor with all supported host features "
1610 "(only available in KVM mode)");
1613 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1614 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
1615 FeatureWordInfo
*fw
= &feature_word_info
[i
];
1617 listflags(buf
, sizeof(buf
), (uint32_t)~0, fw
->feat_names
, 1);
1618 (*cpu_fprintf
)(f
, " %s\n", buf
);
1622 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1624 CpuDefinitionInfoList
*cpu_list
= NULL
;
1628 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1629 CpuDefinitionInfoList
*entry
;
1630 CpuDefinitionInfo
*info
;
1632 def
= &builtin_x86_defs
[i
];
1633 info
= g_malloc0(sizeof(*info
));
1634 info
->name
= g_strdup(def
->name
);
1636 entry
= g_malloc0(sizeof(*entry
));
1637 entry
->value
= info
;
1638 entry
->next
= cpu_list
;
1646 static void filter_features_for_kvm(X86CPU
*cpu
)
1648 CPUX86State
*env
= &cpu
->env
;
1649 KVMState
*s
= kvm_state
;
1651 env
->features
[FEAT_1_EDX
] &=
1652 kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
1653 env
->features
[FEAT_1_ECX
] &=
1654 kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
);
1655 env
->features
[FEAT_8000_0001_EDX
] &=
1656 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
);
1657 env
->features
[FEAT_8000_0001_ECX
] &=
1658 kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_ECX
);
1659 env
->features
[FEAT_SVM
] &=
1660 kvm_arch_get_supported_cpuid(s
, 0x8000000A, 0, R_EDX
);
1661 env
->features
[FEAT_7_0_EBX
] &=
1662 kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
);
1663 env
->features
[FEAT_KVM
] &=
1664 kvm_arch_get_supported_cpuid(s
, KVM_CPUID_FEATURES
, 0, R_EAX
);
1665 env
->features
[FEAT_C000_0001_EDX
] &=
1666 kvm_arch_get_supported_cpuid(s
, 0xC0000001, 0, R_EDX
);
1671 static void cpu_x86_register(X86CPU
*cpu
, const char *name
, Error
**errp
)
1673 CPUX86State
*env
= &cpu
->env
;
1674 x86_def_t def1
, *def
= &def1
;
1676 memset(def
, 0, sizeof(*def
));
1678 if (cpu_x86_find_by_name(def
, name
) < 0) {
1679 error_setg(errp
, "Unable to find CPU definition: %s", name
);
1683 if (kvm_enabled()) {
1684 def
->features
[FEAT_KVM
] |= kvm_default_features
;
1686 def
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
1688 object_property_set_str(OBJECT(cpu
), def
->vendor
, "vendor", errp
);
1689 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
1690 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
1691 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
1692 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
1693 env
->features
[FEAT_1_EDX
] = def
->features
[FEAT_1_EDX
];
1694 env
->features
[FEAT_1_ECX
] = def
->features
[FEAT_1_ECX
];
1695 env
->features
[FEAT_8000_0001_EDX
] = def
->features
[FEAT_8000_0001_EDX
];
1696 env
->features
[FEAT_8000_0001_ECX
] = def
->features
[FEAT_8000_0001_ECX
];
1697 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
1698 env
->features
[FEAT_KVM
] = def
->features
[FEAT_KVM
];
1699 env
->features
[FEAT_SVM
] = def
->features
[FEAT_SVM
];
1700 env
->features
[FEAT_C000_0001_EDX
] = def
->features
[FEAT_C000_0001_EDX
];
1701 env
->features
[FEAT_7_0_EBX
] = def
->features
[FEAT_7_0_EBX
];
1702 env
->cpuid_xlevel2
= def
->xlevel2
;
1704 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
1707 X86CPU
*cpu_x86_create(const char *cpu_model
, DeviceState
*icc_bridge
,
1712 gchar
**model_pieces
;
1713 char *name
, *features
;
1714 Error
*error
= NULL
;
1716 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1717 if (!model_pieces
[0]) {
1718 error_setg(&error
, "Invalid/empty CPU model name");
1721 name
= model_pieces
[0];
1722 features
= model_pieces
[1];
1724 cpu
= X86_CPU(object_new(TYPE_X86_CPU
));
1725 #ifndef CONFIG_USER_ONLY
1726 if (icc_bridge
== NULL
) {
1727 error_setg(&error
, "Invalid icc-bridge value");
1730 qdev_set_parent_bus(DEVICE(cpu
), qdev_get_child_bus(icc_bridge
, "icc"));
1731 object_unref(OBJECT(cpu
));
1734 env
->cpu_model_str
= cpu_model
;
1736 cpu_x86_register(cpu
, name
, &error
);
1741 cpu_x86_parse_featurestr(cpu
, features
, &error
);
1747 error_propagate(errp
, error
);
1748 g_strfreev(model_pieces
);
1752 X86CPU
*cpu_x86_init(const char *cpu_model
)
1754 Error
*error
= NULL
;
1757 cpu
= cpu_x86_create(cpu_model
, NULL
, &error
);
1762 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
1766 fprintf(stderr
, "%s\n", error_get_pretty(error
));
1769 object_unref(OBJECT(cpu
));
1776 #if !defined(CONFIG_USER_ONLY)
1778 void cpu_clear_apic_feature(CPUX86State
*env
)
1780 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
1783 #endif /* !CONFIG_USER_ONLY */
1785 /* Initialize list of CPU models, filling some non-static fields if necessary
1787 void x86_cpudef_setup(void)
1790 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1792 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1793 x86_def_t
*def
= &builtin_x86_defs
[i
];
1795 /* Look for specific "cpudef" models that */
1796 /* have the QEMU version in .model_id */
1797 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1798 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1799 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1800 "QEMU Virtual CPU version ");
1801 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1802 qemu_get_version());
1809 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1810 uint32_t *ecx
, uint32_t *edx
)
1812 *ebx
= env
->cpuid_vendor1
;
1813 *edx
= env
->cpuid_vendor2
;
1814 *ecx
= env
->cpuid_vendor3
;
1817 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1818 uint32_t *eax
, uint32_t *ebx
,
1819 uint32_t *ecx
, uint32_t *edx
)
1821 X86CPU
*cpu
= x86_env_get_cpu(env
);
1822 CPUState
*cs
= CPU(cpu
);
1824 /* test if maximum index reached */
1825 if (index
& 0x80000000) {
1826 if (index
> env
->cpuid_xlevel
) {
1827 if (env
->cpuid_xlevel2
> 0) {
1828 /* Handle the Centaur's CPUID instruction. */
1829 if (index
> env
->cpuid_xlevel2
) {
1830 index
= env
->cpuid_xlevel2
;
1831 } else if (index
< 0xC0000000) {
1832 index
= env
->cpuid_xlevel
;
1835 /* Intel documentation states that invalid EAX input will
1836 * return the same information as EAX=cpuid_level
1837 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1839 index
= env
->cpuid_level
;
1843 if (index
> env
->cpuid_level
)
1844 index
= env
->cpuid_level
;
1849 *eax
= env
->cpuid_level
;
1850 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1853 *eax
= env
->cpuid_version
;
1854 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1855 *ecx
= env
->features
[FEAT_1_ECX
];
1856 *edx
= env
->features
[FEAT_1_EDX
];
1857 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
1858 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
1859 *edx
|= 1 << 28; /* HTT bit */
1863 /* cache info: needed for Pentium Pro compatibility */
1870 /* cache info: needed for Core compatibility */
1871 if (cs
->nr_cores
> 1) {
1872 *eax
= (cs
->nr_cores
- 1) << 26;
1877 case 0: /* L1 dcache info */
1883 case 1: /* L1 icache info */
1889 case 2: /* L2 cache info */
1891 if (cs
->nr_threads
> 1) {
1892 *eax
|= (cs
->nr_threads
- 1) << 14;
1898 default: /* end of info */
1907 /* mwait info: needed for Core compatibility */
1908 *eax
= 0; /* Smallest monitor-line size in bytes */
1909 *ebx
= 0; /* Largest monitor-line size in bytes */
1910 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1914 /* Thermal and Power Leaf */
1921 /* Structured Extended Feature Flags Enumeration Leaf */
1923 *eax
= 0; /* Maximum ECX value for sub-leaves */
1924 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
1925 *ecx
= 0; /* Reserved */
1926 *edx
= 0; /* Reserved */
1935 /* Direct Cache Access Information Leaf */
1936 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1942 /* Architectural Performance Monitoring Leaf */
1943 if (kvm_enabled()) {
1944 KVMState
*s
= cs
->kvm_state
;
1946 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1947 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1948 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1949 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1958 /* Processor Extended State */
1959 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
1966 if (kvm_enabled()) {
1967 KVMState
*s
= cs
->kvm_state
;
1969 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1970 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1971 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1972 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1981 *eax
= env
->cpuid_xlevel
;
1982 *ebx
= env
->cpuid_vendor1
;
1983 *edx
= env
->cpuid_vendor2
;
1984 *ecx
= env
->cpuid_vendor3
;
1987 *eax
= env
->cpuid_version
;
1989 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
1990 *edx
= env
->features
[FEAT_8000_0001_EDX
];
1992 /* The Linux kernel checks for the CMPLegacy bit and
1993 * discards multiple thread information if it is set.
1994 * So dont set it here for Intel to make Linux guests happy.
1996 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
1997 uint32_t tebx
, tecx
, tedx
;
1998 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1999 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2000 tedx
!= CPUID_VENDOR_INTEL_2
||
2001 tecx
!= CPUID_VENDOR_INTEL_3
) {
2002 *ecx
|= 1 << 1; /* CmpLegacy bit */
2009 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2010 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2011 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2012 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2015 /* cache info (L1 cache) */
2022 /* cache info (L2 cache) */
2029 /* virtual & phys address size in low 2 bytes. */
2030 /* XXX: This value must match the one used in the MMU code. */
2031 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2032 /* 64 bit processor */
2033 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2034 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2036 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2037 *eax
= 0x00000024; /* 36 bits physical */
2039 *eax
= 0x00000020; /* 32 bits physical */
2045 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2046 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2050 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2051 *eax
= 0x00000001; /* SVM Revision */
2052 *ebx
= 0x00000010; /* nr of ASIDs */
2054 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2063 *eax
= env
->cpuid_xlevel2
;
2069 /* Support for VIA CPU's CPUID instruction */
2070 *eax
= env
->cpuid_version
;
2073 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2078 /* Reserved for the future, and now filled with zero */
2085 /* reserved values: zero */
2094 /* CPUClass::reset() */
2095 static void x86_cpu_reset(CPUState
*s
)
2097 X86CPU
*cpu
= X86_CPU(s
);
2098 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2099 CPUX86State
*env
= &cpu
->env
;
2102 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
2103 qemu_log("CPU Reset (CPU %d)\n", s
->cpu_index
);
2104 log_cpu_state(env
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
2107 xcc
->parent_reset(s
);
2110 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
2114 env
->old_exception
= -1;
2116 /* init to reset state */
2118 #ifdef CONFIG_SOFTMMU
2119 env
->hflags
|= HF_SOFTMMU_MASK
;
2121 env
->hflags2
|= HF2_GIF_MASK
;
2123 cpu_x86_update_cr0(env
, 0x60000010);
2124 env
->a20_mask
= ~0x0;
2125 env
->smbase
= 0x30000;
2127 env
->idt
.limit
= 0xffff;
2128 env
->gdt
.limit
= 0xffff;
2129 env
->ldt
.limit
= 0xffff;
2130 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2131 env
->tr
.limit
= 0xffff;
2132 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2134 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2135 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2136 DESC_R_MASK
| DESC_A_MASK
);
2137 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2138 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2140 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2141 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2143 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2144 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2146 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2147 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2149 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2150 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2154 env
->regs
[R_EDX
] = env
->cpuid_version
;
2159 for (i
= 0; i
< 8; i
++) {
2164 env
->mxcsr
= 0x1f80;
2166 env
->pat
= 0x0007040600070406ULL
;
2167 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2169 memset(env
->dr
, 0, sizeof(env
->dr
));
2170 env
->dr
[6] = DR6_FIXED_1
;
2171 env
->dr
[7] = DR7_FIXED_1
;
2172 cpu_breakpoint_remove_all(env
, BP_CPU
);
2173 cpu_watchpoint_remove_all(env
, BP_CPU
);
2175 #if !defined(CONFIG_USER_ONLY)
2176 /* We hard-wire the BSP to the first CPU. */
2177 if (s
->cpu_index
== 0) {
2178 apic_designate_bsp(env
->apic_state
);
2181 s
->halted
= !cpu_is_bsp(cpu
);
2185 #ifndef CONFIG_USER_ONLY
2186 bool cpu_is_bsp(X86CPU
*cpu
)
2188 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
2191 /* TODO: remove me, when reset over QOM tree is implemented */
2192 static void x86_cpu_machine_reset_cb(void *opaque
)
2194 X86CPU
*cpu
= opaque
;
2195 cpu_reset(CPU(cpu
));
2199 static void mce_init(X86CPU
*cpu
)
2201 CPUX86State
*cenv
= &cpu
->env
;
2204 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2205 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2206 (CPUID_MCE
| CPUID_MCA
)) {
2207 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2208 cenv
->mcg_ctl
= ~(uint64_t)0;
2209 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2210 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2215 #ifndef CONFIG_USER_ONLY
2216 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2218 CPUX86State
*env
= &cpu
->env
;
2219 DeviceState
*dev
= DEVICE(cpu
);
2220 APICCommonState
*apic
;
2221 const char *apic_type
= "apic";
2223 if (kvm_irqchip_in_kernel()) {
2224 apic_type
= "kvm-apic";
2225 } else if (xen_enabled()) {
2226 apic_type
= "xen-apic";
2229 env
->apic_state
= qdev_try_create(qdev_get_parent_bus(dev
), apic_type
);
2230 if (env
->apic_state
== NULL
) {
2231 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2235 object_property_add_child(OBJECT(cpu
), "apic",
2236 OBJECT(env
->apic_state
), NULL
);
2237 qdev_prop_set_uint8(env
->apic_state
, "id", env
->cpuid_apic_id
);
2238 /* TODO: convert to link<> */
2239 apic
= APIC_COMMON(env
->apic_state
);
2243 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2245 CPUX86State
*env
= &cpu
->env
;
2247 if (env
->apic_state
== NULL
) {
2251 if (qdev_init(env
->apic_state
)) {
2252 error_setg(errp
, "APIC device '%s' could not be initialized",
2253 object_get_typename(OBJECT(env
->apic_state
)));
2258 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2263 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2265 X86CPU
*cpu
= X86_CPU(dev
);
2266 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2267 CPUX86State
*env
= &cpu
->env
;
2268 Error
*local_err
= NULL
;
2270 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2271 env
->cpuid_level
= 7;
2274 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2277 if (env
->cpuid_vendor1
== CPUID_VENDOR_AMD_1
&&
2278 env
->cpuid_vendor2
== CPUID_VENDOR_AMD_2
&&
2279 env
->cpuid_vendor3
== CPUID_VENDOR_AMD_3
) {
2280 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2281 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2282 & CPUID_EXT2_AMD_ALIASES
);
2285 if (!kvm_enabled()) {
2286 env
->features
[FEAT_1_EDX
] &= TCG_FEATURES
;
2287 env
->features
[FEAT_1_ECX
] &= TCG_EXT_FEATURES
;
2288 env
->features
[FEAT_8000_0001_EDX
] &= (TCG_EXT2_FEATURES
2289 #ifdef TARGET_X86_64
2290 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
2293 env
->features
[FEAT_8000_0001_ECX
] &= TCG_EXT3_FEATURES
;
2294 env
->features
[FEAT_SVM
] &= TCG_SVM_FEATURES
;
2296 if (check_cpuid
&& kvm_check_features_against_host(cpu
)
2298 error_setg(&local_err
,
2299 "Host's CPU doesn't support requested features");
2303 filter_features_for_kvm(cpu
);
2307 #ifndef CONFIG_USER_ONLY
2308 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2310 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2311 x86_cpu_apic_create(cpu
, &local_err
);
2312 if (local_err
!= NULL
) {
2319 qemu_init_vcpu(&cpu
->env
);
2321 x86_cpu_apic_realize(cpu
, &local_err
);
2322 if (local_err
!= NULL
) {
2325 cpu_reset(CPU(cpu
));
2327 xcc
->parent_realize(dev
, &local_err
);
2329 if (local_err
!= NULL
) {
2330 error_propagate(errp
, local_err
);
2335 /* Enables contiguous-apic-ID mode, for compatibility */
2336 static bool compat_apic_id_mode
;
2338 void enable_compat_apic_id_mode(void)
2340 compat_apic_id_mode
= true;
2343 /* Calculates initial APIC ID for a specific CPU index
2345 * Currently we need to be able to calculate the APIC ID from the CPU index
2346 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2347 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2348 * all CPUs up to max_cpus.
2350 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
2352 uint32_t correct_id
;
2355 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
2356 if (compat_apic_id_mode
) {
2357 if (cpu_index
!= correct_id
&& !warned
) {
2358 error_report("APIC IDs set in compatibility mode, "
2359 "CPU topology won't match the configuration");
2368 static void x86_cpu_initfn(Object
*obj
)
2370 CPUState
*cs
= CPU(obj
);
2371 X86CPU
*cpu
= X86_CPU(obj
);
2372 CPUX86State
*env
= &cpu
->env
;
2378 object_property_add(obj
, "family", "int",
2379 x86_cpuid_version_get_family
,
2380 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2381 object_property_add(obj
, "model", "int",
2382 x86_cpuid_version_get_model
,
2383 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2384 object_property_add(obj
, "stepping", "int",
2385 x86_cpuid_version_get_stepping
,
2386 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2387 object_property_add(obj
, "level", "int",
2388 x86_cpuid_get_level
,
2389 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2390 object_property_add(obj
, "xlevel", "int",
2391 x86_cpuid_get_xlevel
,
2392 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2393 object_property_add_str(obj
, "vendor",
2394 x86_cpuid_get_vendor
,
2395 x86_cpuid_set_vendor
, NULL
);
2396 object_property_add_str(obj
, "model-id",
2397 x86_cpuid_get_model_id
,
2398 x86_cpuid_set_model_id
, NULL
);
2399 object_property_add(obj
, "tsc-frequency", "int",
2400 x86_cpuid_get_tsc_freq
,
2401 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2402 object_property_add(obj
, "apic-id", "int",
2403 x86_cpuid_get_apic_id
,
2404 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
2406 env
->cpuid_apic_id
= x86_cpu_apic_id_from_index(cs
->cpu_index
);
2408 /* init various static tables used in TCG mode */
2409 if (tcg_enabled() && !inited
) {
2411 optimize_flags_init();
2412 #ifndef CONFIG_USER_ONLY
2413 cpu_set_debug_excp_handler(breakpoint_handler
);
2418 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
2420 X86CPU
*cpu
= X86_CPU(cs
);
2421 CPUX86State
*env
= &cpu
->env
;
2423 return env
->cpuid_apic_id
;
2426 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2428 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2429 CPUClass
*cc
= CPU_CLASS(oc
);
2430 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2432 xcc
->parent_realize
= dc
->realize
;
2433 dc
->realize
= x86_cpu_realizefn
;
2434 dc
->bus_type
= TYPE_ICC_BUS
;
2436 xcc
->parent_reset
= cc
->reset
;
2437 cc
->reset
= x86_cpu_reset
;
2439 cc
->do_interrupt
= x86_cpu_do_interrupt
;
2440 #ifndef CONFIG_USER_ONLY
2441 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
2442 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
2443 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
2444 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
2446 cpu_class_set_vmsd(cc
, &vmstate_x86_cpu
);
2448 cc
->get_arch_id
= x86_cpu_get_arch_id
;
2451 static const TypeInfo x86_cpu_type_info
= {
2452 .name
= TYPE_X86_CPU
,
2454 .instance_size
= sizeof(X86CPU
),
2455 .instance_init
= x86_cpu_initfn
,
2457 .class_size
= sizeof(X86CPUClass
),
2458 .class_init
= x86_cpu_common_class_init
,
2461 static void x86_cpu_register_types(void)
2463 type_register_static(&x86_cpu_type_info
);
2466 type_init(x86_cpu_register_types
)