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pc: Generate APIC IDs according to CPU topology
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 /* feature flags taken from "Intel Processor Identification and the CPUID
51 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
52 * between feature naming conventions, aliases may be added.
53 */
54 static const char *feature_name[] = {
55 "fpu", "vme", "de", "pse",
56 "tsc", "msr", "pae", "mce",
57 "cx8", "apic", NULL, "sep",
58 "mtrr", "pge", "mca", "cmov",
59 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
60 NULL, "ds" /* Intel dts */, "acpi", "mmx",
61 "fxsr", "sse", "sse2", "ss",
62 "ht" /* Intel htt */, "tm", "ia64", "pbe",
63 };
64 static const char *ext_feature_name[] = {
65 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
66 "ds_cpl", "vmx", "smx", "est",
67 "tm2", "ssse3", "cid", NULL,
68 "fma", "cx16", "xtpr", "pdcm",
69 NULL, "pcid", "dca", "sse4.1|sse4_1",
70 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
71 "tsc-deadline", "aes", "xsave", "osxsave",
72 "avx", "f16c", "rdrand", "hypervisor",
73 };
74 /* Feature names that are already defined on feature_name[] but are set on
75 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
76 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
77 * if and only if CPU vendor is AMD.
78 */
79 static const char *ext2_feature_name[] = {
80 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
81 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
82 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
83 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
84 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
85 "nx|xd", NULL, "mmxext", NULL /* mmx */,
86 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
87 NULL, "lm|i64", "3dnowext", "3dnow",
88 };
89 static const char *ext3_feature_name[] = {
90 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
91 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
92 "3dnowprefetch", "osvw", "ibs", "xop",
93 "skinit", "wdt", NULL, "lwp",
94 "fma4", "tce", NULL, "nodeid_msr",
95 NULL, "tbm", "topoext", "perfctr_core",
96 "perfctr_nb", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 };
99
100 static const char *ext4_feature_name[] = {
101 NULL, NULL, "xstore", "xstore-en",
102 NULL, NULL, "xcrypt", "xcrypt-en",
103 "ace2", "ace2-en", "phe", "phe-en",
104 "pmm", "pmm-en", NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 NULL, NULL, NULL, NULL,
108 NULL, NULL, NULL, NULL,
109 };
110
111 static const char *kvm_feature_name[] = {
112 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
113 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 };
121
122 static const char *svm_feature_name[] = {
123 "npt", "lbrv", "svm_lock", "nrip_save",
124 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
125 NULL, NULL, "pause_filter", NULL,
126 "pfthreshold", NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 };
132
133 static const char *cpuid_7_0_ebx_feature_name[] = {
134 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
135 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
136 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
137 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
138 };
139
140 typedef struct FeatureWordInfo {
141 const char **feat_names;
142 uint32_t cpuid_eax; /* Input EAX for CPUID */
143 int cpuid_reg; /* R_* register constant */
144 } FeatureWordInfo;
145
146 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
147 [FEAT_1_EDX] = {
148 .feat_names = feature_name,
149 .cpuid_eax = 1, .cpuid_reg = R_EDX,
150 },
151 [FEAT_1_ECX] = {
152 .feat_names = ext_feature_name,
153 .cpuid_eax = 1, .cpuid_reg = R_ECX,
154 },
155 [FEAT_8000_0001_EDX] = {
156 .feat_names = ext2_feature_name,
157 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
158 },
159 [FEAT_8000_0001_ECX] = {
160 .feat_names = ext3_feature_name,
161 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
162 },
163 [FEAT_C000_0001_EDX] = {
164 .feat_names = ext4_feature_name,
165 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
166 },
167 [FEAT_KVM] = {
168 .feat_names = kvm_feature_name,
169 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
170 },
171 [FEAT_SVM] = {
172 .feat_names = svm_feature_name,
173 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
174 },
175 [FEAT_7_0_EBX] = {
176 .feat_names = cpuid_7_0_ebx_feature_name,
177 .cpuid_eax = 7, .cpuid_reg = R_EBX,
178 },
179 };
180
181 const char *get_register_name_32(unsigned int reg)
182 {
183 static const char *reg_names[CPU_NB_REGS32] = {
184 [R_EAX] = "EAX",
185 [R_ECX] = "ECX",
186 [R_EDX] = "EDX",
187 [R_EBX] = "EBX",
188 [R_ESP] = "ESP",
189 [R_EBP] = "EBP",
190 [R_ESI] = "ESI",
191 [R_EDI] = "EDI",
192 };
193
194 if (reg > CPU_NB_REGS32) {
195 return NULL;
196 }
197 return reg_names[reg];
198 }
199
200 /* collects per-function cpuid data
201 */
202 typedef struct model_features_t {
203 uint32_t *guest_feat;
204 uint32_t *host_feat;
205 FeatureWord feat_word;
206 } model_features_t;
207
208 int check_cpuid = 0;
209 int enforce_cpuid = 0;
210
211 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
212 (1 << KVM_FEATURE_NOP_IO_DELAY) |
213 (1 << KVM_FEATURE_CLOCKSOURCE2) |
214 (1 << KVM_FEATURE_ASYNC_PF) |
215 (1 << KVM_FEATURE_STEAL_TIME) |
216 (1 << KVM_FEATURE_PV_EOI) |
217 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
218
219 void disable_kvm_pv_eoi(void)
220 {
221 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
222 }
223
224 void host_cpuid(uint32_t function, uint32_t count,
225 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
226 {
227 #if defined(CONFIG_KVM)
228 uint32_t vec[4];
229
230 #ifdef __x86_64__
231 asm volatile("cpuid"
232 : "=a"(vec[0]), "=b"(vec[1]),
233 "=c"(vec[2]), "=d"(vec[3])
234 : "0"(function), "c"(count) : "cc");
235 #else
236 asm volatile("pusha \n\t"
237 "cpuid \n\t"
238 "mov %%eax, 0(%2) \n\t"
239 "mov %%ebx, 4(%2) \n\t"
240 "mov %%ecx, 8(%2) \n\t"
241 "mov %%edx, 12(%2) \n\t"
242 "popa"
243 : : "a"(function), "c"(count), "S"(vec)
244 : "memory", "cc");
245 #endif
246
247 if (eax)
248 *eax = vec[0];
249 if (ebx)
250 *ebx = vec[1];
251 if (ecx)
252 *ecx = vec[2];
253 if (edx)
254 *edx = vec[3];
255 #endif
256 }
257
258 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
259
260 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
261 * a substring. ex if !NULL points to the first char after a substring,
262 * otherwise the string is assumed to sized by a terminating nul.
263 * Return lexical ordering of *s1:*s2.
264 */
265 static int sstrcmp(const char *s1, const char *e1, const char *s2,
266 const char *e2)
267 {
268 for (;;) {
269 if (!*s1 || !*s2 || *s1 != *s2)
270 return (*s1 - *s2);
271 ++s1, ++s2;
272 if (s1 == e1 && s2 == e2)
273 return (0);
274 else if (s1 == e1)
275 return (*s2);
276 else if (s2 == e2)
277 return (*s1);
278 }
279 }
280
281 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
282 * '|' delimited (possibly empty) strings in which case search for a match
283 * within the alternatives proceeds left to right. Return 0 for success,
284 * non-zero otherwise.
285 */
286 static int altcmp(const char *s, const char *e, const char *altstr)
287 {
288 const char *p, *q;
289
290 for (q = p = altstr; ; ) {
291 while (*p && *p != '|')
292 ++p;
293 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
294 return (0);
295 if (!*p)
296 return (1);
297 else
298 q = ++p;
299 }
300 }
301
302 /* search featureset for flag *[s..e), if found set corresponding bit in
303 * *pval and return true, otherwise return false
304 */
305 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
306 const char **featureset)
307 {
308 uint32_t mask;
309 const char **ppc;
310 bool found = false;
311
312 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
313 if (*ppc && !altcmp(s, e, *ppc)) {
314 *pval |= mask;
315 found = true;
316 }
317 }
318 return found;
319 }
320
321 static void add_flagname_to_bitmaps(const char *flagname,
322 FeatureWordArray words)
323 {
324 FeatureWord w;
325 for (w = 0; w < FEATURE_WORDS; w++) {
326 FeatureWordInfo *wi = &feature_word_info[w];
327 if (wi->feat_names &&
328 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
329 break;
330 }
331 }
332 if (w == FEATURE_WORDS) {
333 fprintf(stderr, "CPU feature %s not found\n", flagname);
334 }
335 }
336
337 typedef struct x86_def_t {
338 struct x86_def_t *next;
339 const char *name;
340 uint32_t level;
341 uint32_t vendor1, vendor2, vendor3;
342 int family;
343 int model;
344 int stepping;
345 int tsc_khz;
346 uint32_t features, ext_features, ext2_features, ext3_features;
347 uint32_t kvm_features, svm_features;
348 uint32_t xlevel;
349 char model_id[48];
350 int vendor_override;
351 /* Store the results of Centaur's CPUID instructions */
352 uint32_t ext4_features;
353 uint32_t xlevel2;
354 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
355 uint32_t cpuid_7_0_ebx_features;
356 } x86_def_t;
357
358 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
359 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
360 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
361 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
362 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
363 CPUID_PSE36 | CPUID_FXSR)
364 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
365 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
366 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
367 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
368 CPUID_PAE | CPUID_SEP | CPUID_APIC)
369
370 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
371 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
373 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
374 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
375 /* partly implemented:
376 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
377 CPUID_PSE36 (needed for Solaris) */
378 /* missing:
379 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
380 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
381 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
382 CPUID_EXT_HYPERVISOR)
383 /* missing:
384 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
385 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
386 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
387 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
388 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
389 /* missing:
390 CPUID_EXT2_PDPE1GB */
391 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
392 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
393 #define TCG_SVM_FEATURES 0
394 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
395
396 /* maintains list of cpu model definitions
397 */
398 static x86_def_t *x86_defs = {NULL};
399
400 /* built-in cpu model definitions (deprecated)
401 */
402 static x86_def_t builtin_x86_defs[] = {
403 {
404 .name = "qemu64",
405 .level = 4,
406 .vendor1 = CPUID_VENDOR_AMD_1,
407 .vendor2 = CPUID_VENDOR_AMD_2,
408 .vendor3 = CPUID_VENDOR_AMD_3,
409 .family = 6,
410 .model = 2,
411 .stepping = 3,
412 .features = PPRO_FEATURES |
413 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
414 CPUID_PSE36,
415 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
416 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
417 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
418 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
419 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
420 .xlevel = 0x8000000A,
421 },
422 {
423 .name = "phenom",
424 .level = 5,
425 .vendor1 = CPUID_VENDOR_AMD_1,
426 .vendor2 = CPUID_VENDOR_AMD_2,
427 .vendor3 = CPUID_VENDOR_AMD_3,
428 .family = 16,
429 .model = 2,
430 .stepping = 3,
431 .features = PPRO_FEATURES |
432 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
433 CPUID_PSE36 | CPUID_VME | CPUID_HT,
434 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
435 CPUID_EXT_POPCNT,
436 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
437 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
438 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
439 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
440 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
441 CPUID_EXT3_CR8LEG,
442 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
443 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
444 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
445 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
446 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
447 .xlevel = 0x8000001A,
448 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
449 },
450 {
451 .name = "core2duo",
452 .level = 10,
453 .vendor1 = CPUID_VENDOR_INTEL_1,
454 .vendor2 = CPUID_VENDOR_INTEL_2,
455 .vendor3 = CPUID_VENDOR_INTEL_3,
456 .family = 6,
457 .model = 15,
458 .stepping = 11,
459 .features = PPRO_FEATURES |
460 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
461 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
462 CPUID_HT | CPUID_TM | CPUID_PBE,
463 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
464 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
465 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
467 .ext3_features = CPUID_EXT3_LAHF_LM,
468 .xlevel = 0x80000008,
469 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
470 },
471 {
472 .name = "kvm64",
473 .level = 5,
474 .vendor1 = CPUID_VENDOR_INTEL_1,
475 .vendor2 = CPUID_VENDOR_INTEL_2,
476 .vendor3 = CPUID_VENDOR_INTEL_3,
477 .family = 15,
478 .model = 6,
479 .stepping = 1,
480 /* Missing: CPUID_VME, CPUID_HT */
481 .features = PPRO_FEATURES |
482 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
483 CPUID_PSE36,
484 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
485 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
486 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
487 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
488 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
489 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
490 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
491 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
492 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
493 .ext3_features = 0,
494 .xlevel = 0x80000008,
495 .model_id = "Common KVM processor"
496 },
497 {
498 .name = "qemu32",
499 .level = 4,
500 .vendor1 = CPUID_VENDOR_INTEL_1,
501 .vendor2 = CPUID_VENDOR_INTEL_2,
502 .vendor3 = CPUID_VENDOR_INTEL_3,
503 .family = 6,
504 .model = 3,
505 .stepping = 3,
506 .features = PPRO_FEATURES,
507 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
508 .xlevel = 0x80000004,
509 },
510 {
511 .name = "kvm32",
512 .level = 5,
513 .vendor1 = CPUID_VENDOR_INTEL_1,
514 .vendor2 = CPUID_VENDOR_INTEL_2,
515 .vendor3 = CPUID_VENDOR_INTEL_3,
516 .family = 15,
517 .model = 6,
518 .stepping = 1,
519 .features = PPRO_FEATURES |
520 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
521 .ext_features = CPUID_EXT_SSE3,
522 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
523 .ext3_features = 0,
524 .xlevel = 0x80000008,
525 .model_id = "Common 32-bit KVM processor"
526 },
527 {
528 .name = "coreduo",
529 .level = 10,
530 .vendor1 = CPUID_VENDOR_INTEL_1,
531 .vendor2 = CPUID_VENDOR_INTEL_2,
532 .vendor3 = CPUID_VENDOR_INTEL_3,
533 .family = 6,
534 .model = 14,
535 .stepping = 8,
536 .features = PPRO_FEATURES | CPUID_VME |
537 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
538 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
539 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
540 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
541 .ext2_features = CPUID_EXT2_NX,
542 .xlevel = 0x80000008,
543 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
544 },
545 {
546 .name = "486",
547 .level = 1,
548 .vendor1 = CPUID_VENDOR_INTEL_1,
549 .vendor2 = CPUID_VENDOR_INTEL_2,
550 .vendor3 = CPUID_VENDOR_INTEL_3,
551 .family = 4,
552 .model = 0,
553 .stepping = 0,
554 .features = I486_FEATURES,
555 .xlevel = 0,
556 },
557 {
558 .name = "pentium",
559 .level = 1,
560 .vendor1 = CPUID_VENDOR_INTEL_1,
561 .vendor2 = CPUID_VENDOR_INTEL_2,
562 .vendor3 = CPUID_VENDOR_INTEL_3,
563 .family = 5,
564 .model = 4,
565 .stepping = 3,
566 .features = PENTIUM_FEATURES,
567 .xlevel = 0,
568 },
569 {
570 .name = "pentium2",
571 .level = 2,
572 .vendor1 = CPUID_VENDOR_INTEL_1,
573 .vendor2 = CPUID_VENDOR_INTEL_2,
574 .vendor3 = CPUID_VENDOR_INTEL_3,
575 .family = 6,
576 .model = 5,
577 .stepping = 2,
578 .features = PENTIUM2_FEATURES,
579 .xlevel = 0,
580 },
581 {
582 .name = "pentium3",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 7,
589 .stepping = 3,
590 .features = PENTIUM3_FEATURES,
591 .xlevel = 0,
592 },
593 {
594 .name = "athlon",
595 .level = 2,
596 .vendor1 = CPUID_VENDOR_AMD_1,
597 .vendor2 = CPUID_VENDOR_AMD_2,
598 .vendor3 = CPUID_VENDOR_AMD_3,
599 .family = 6,
600 .model = 2,
601 .stepping = 3,
602 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
603 CPUID_MCA,
604 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
605 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
606 .xlevel = 0x80000008,
607 },
608 {
609 .name = "n270",
610 /* original is on level 10 */
611 .level = 5,
612 .vendor1 = CPUID_VENDOR_INTEL_1,
613 .vendor2 = CPUID_VENDOR_INTEL_2,
614 .vendor3 = CPUID_VENDOR_INTEL_3,
615 .family = 6,
616 .model = 28,
617 .stepping = 2,
618 .features = PPRO_FEATURES |
619 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
620 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
621 /* Some CPUs got no CPUID_SEP */
622 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
623 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
624 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
625 CPUID_EXT2_NX,
626 .ext3_features = CPUID_EXT3_LAHF_LM,
627 .xlevel = 0x8000000A,
628 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
629 },
630 {
631 .name = "Conroe",
632 .level = 2,
633 .vendor1 = CPUID_VENDOR_INTEL_1,
634 .vendor2 = CPUID_VENDOR_INTEL_2,
635 .vendor3 = CPUID_VENDOR_INTEL_3,
636 .family = 6,
637 .model = 2,
638 .stepping = 3,
639 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
640 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
641 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
642 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
643 CPUID_DE | CPUID_FP87,
644 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
645 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
646 .ext3_features = CPUID_EXT3_LAHF_LM,
647 .xlevel = 0x8000000A,
648 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
649 },
650 {
651 .name = "Penryn",
652 .level = 2,
653 .vendor1 = CPUID_VENDOR_INTEL_1,
654 .vendor2 = CPUID_VENDOR_INTEL_2,
655 .vendor3 = CPUID_VENDOR_INTEL_3,
656 .family = 6,
657 .model = 2,
658 .stepping = 3,
659 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
660 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
661 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
662 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
663 CPUID_DE | CPUID_FP87,
664 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
665 CPUID_EXT_SSE3,
666 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
667 .ext3_features = CPUID_EXT3_LAHF_LM,
668 .xlevel = 0x8000000A,
669 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
670 },
671 {
672 .name = "Nehalem",
673 .level = 2,
674 .vendor1 = CPUID_VENDOR_INTEL_1,
675 .vendor2 = CPUID_VENDOR_INTEL_2,
676 .vendor3 = CPUID_VENDOR_INTEL_3,
677 .family = 6,
678 .model = 2,
679 .stepping = 3,
680 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
681 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
682 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
683 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
684 CPUID_DE | CPUID_FP87,
685 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
686 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
687 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
688 .ext3_features = CPUID_EXT3_LAHF_LM,
689 .xlevel = 0x8000000A,
690 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
691 },
692 {
693 .name = "Westmere",
694 .level = 11,
695 .vendor1 = CPUID_VENDOR_INTEL_1,
696 .vendor2 = CPUID_VENDOR_INTEL_2,
697 .vendor3 = CPUID_VENDOR_INTEL_3,
698 .family = 6,
699 .model = 44,
700 .stepping = 1,
701 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
702 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
703 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
704 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
705 CPUID_DE | CPUID_FP87,
706 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
707 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
708 CPUID_EXT_SSE3,
709 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
710 .ext3_features = CPUID_EXT3_LAHF_LM,
711 .xlevel = 0x8000000A,
712 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
713 },
714 {
715 .name = "SandyBridge",
716 .level = 0xd,
717 .vendor1 = CPUID_VENDOR_INTEL_1,
718 .vendor2 = CPUID_VENDOR_INTEL_2,
719 .vendor3 = CPUID_VENDOR_INTEL_3,
720 .family = 6,
721 .model = 42,
722 .stepping = 1,
723 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
724 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
725 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
726 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
727 CPUID_DE | CPUID_FP87,
728 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
729 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
730 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
731 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
732 CPUID_EXT_SSE3,
733 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
734 CPUID_EXT2_SYSCALL,
735 .ext3_features = CPUID_EXT3_LAHF_LM,
736 .xlevel = 0x8000000A,
737 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
738 },
739 {
740 .name = "Haswell",
741 .level = 0xd,
742 .vendor1 = CPUID_VENDOR_INTEL_1,
743 .vendor2 = CPUID_VENDOR_INTEL_2,
744 .vendor3 = CPUID_VENDOR_INTEL_3,
745 .family = 6,
746 .model = 60,
747 .stepping = 1,
748 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
749 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
750 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
751 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
752 CPUID_DE | CPUID_FP87,
753 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
754 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
755 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
756 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
757 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
758 CPUID_EXT_PCID,
759 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
760 CPUID_EXT2_SYSCALL,
761 .ext3_features = CPUID_EXT3_LAHF_LM,
762 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
763 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
764 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
765 CPUID_7_0_EBX_RTM,
766 .xlevel = 0x8000000A,
767 .model_id = "Intel Core Processor (Haswell)",
768 },
769 {
770 .name = "Opteron_G1",
771 .level = 5,
772 .vendor1 = CPUID_VENDOR_AMD_1,
773 .vendor2 = CPUID_VENDOR_AMD_2,
774 .vendor3 = CPUID_VENDOR_AMD_3,
775 .family = 15,
776 .model = 6,
777 .stepping = 1,
778 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
779 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
780 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
781 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
782 CPUID_DE | CPUID_FP87,
783 .ext_features = CPUID_EXT_SSE3,
784 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
785 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
786 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
787 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
788 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
789 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
790 .xlevel = 0x80000008,
791 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
792 },
793 {
794 .name = "Opteron_G2",
795 .level = 5,
796 .vendor1 = CPUID_VENDOR_AMD_1,
797 .vendor2 = CPUID_VENDOR_AMD_2,
798 .vendor3 = CPUID_VENDOR_AMD_3,
799 .family = 15,
800 .model = 6,
801 .stepping = 1,
802 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
803 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
804 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
805 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
806 CPUID_DE | CPUID_FP87,
807 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
808 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
809 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
810 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
811 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
812 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
813 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
814 CPUID_EXT2_DE | CPUID_EXT2_FPU,
815 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
816 .xlevel = 0x80000008,
817 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
818 },
819 {
820 .name = "Opteron_G3",
821 .level = 5,
822 .vendor1 = CPUID_VENDOR_AMD_1,
823 .vendor2 = CPUID_VENDOR_AMD_2,
824 .vendor3 = CPUID_VENDOR_AMD_3,
825 .family = 15,
826 .model = 6,
827 .stepping = 1,
828 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
829 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
830 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
831 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
832 CPUID_DE | CPUID_FP87,
833 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
834 CPUID_EXT_SSE3,
835 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
836 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
837 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
838 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
839 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
840 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
841 CPUID_EXT2_DE | CPUID_EXT2_FPU,
842 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
843 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
844 .xlevel = 0x80000008,
845 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
846 },
847 {
848 .name = "Opteron_G4",
849 .level = 0xd,
850 .vendor1 = CPUID_VENDOR_AMD_1,
851 .vendor2 = CPUID_VENDOR_AMD_2,
852 .vendor3 = CPUID_VENDOR_AMD_3,
853 .family = 21,
854 .model = 1,
855 .stepping = 2,
856 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
860 CPUID_DE | CPUID_FP87,
861 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
862 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
863 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
864 CPUID_EXT_SSE3,
865 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
866 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
867 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
868 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
869 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
870 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
871 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
872 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
873 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
874 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
875 CPUID_EXT3_LAHF_LM,
876 .xlevel = 0x8000001A,
877 .model_id = "AMD Opteron 62xx class CPU",
878 },
879 {
880 .name = "Opteron_G5",
881 .level = 0xd,
882 .vendor1 = CPUID_VENDOR_AMD_1,
883 .vendor2 = CPUID_VENDOR_AMD_2,
884 .vendor3 = CPUID_VENDOR_AMD_3,
885 .family = 21,
886 .model = 2,
887 .stepping = 0,
888 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
889 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
890 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
891 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
892 CPUID_DE | CPUID_FP87,
893 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
894 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
895 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
896 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
897 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
898 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
899 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
900 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
901 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
902 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
903 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
904 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
905 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
906 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
907 CPUID_EXT3_LAHF_LM,
908 .xlevel = 0x8000001A,
909 .model_id = "AMD Opteron 63xx class CPU",
910 },
911 };
912
913 #ifdef CONFIG_KVM
914 static int cpu_x86_fill_model_id(char *str)
915 {
916 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
917 int i;
918
919 for (i = 0; i < 3; i++) {
920 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
921 memcpy(str + i * 16 + 0, &eax, 4);
922 memcpy(str + i * 16 + 4, &ebx, 4);
923 memcpy(str + i * 16 + 8, &ecx, 4);
924 memcpy(str + i * 16 + 12, &edx, 4);
925 }
926 return 0;
927 }
928 #endif
929
930 /* Fill a x86_def_t struct with information about the host CPU, and
931 * the CPU features supported by the host hardware + host kernel
932 *
933 * This function may be called only if KVM is enabled.
934 */
935 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
936 {
937 #ifdef CONFIG_KVM
938 KVMState *s = kvm_state;
939 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
940
941 assert(kvm_enabled());
942
943 x86_cpu_def->name = "host";
944 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
945 x86_cpu_def->vendor1 = ebx;
946 x86_cpu_def->vendor2 = edx;
947 x86_cpu_def->vendor3 = ecx;
948
949 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
950 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
951 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
952 x86_cpu_def->stepping = eax & 0x0F;
953
954 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
955 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
956 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
957
958 if (x86_cpu_def->level >= 7) {
959 x86_cpu_def->cpuid_7_0_ebx_features =
960 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
961 } else {
962 x86_cpu_def->cpuid_7_0_ebx_features = 0;
963 }
964
965 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
966 x86_cpu_def->ext2_features =
967 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
968 x86_cpu_def->ext3_features =
969 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
970
971 cpu_x86_fill_model_id(x86_cpu_def->model_id);
972 x86_cpu_def->vendor_override = 0;
973
974 /* Call Centaur's CPUID instruction. */
975 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
976 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
977 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
978 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
979 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
980 if (eax >= 0xC0000001) {
981 /* Support VIA max extended level */
982 x86_cpu_def->xlevel2 = eax;
983 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
984 x86_cpu_def->ext4_features =
985 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
986 }
987 }
988
989 /* Other KVM-specific feature fields: */
990 x86_cpu_def->svm_features =
991 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
992 x86_cpu_def->kvm_features =
993 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
994
995 #endif /* CONFIG_KVM */
996 }
997
998 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
999 {
1000 int i;
1001
1002 for (i = 0; i < 32; ++i)
1003 if (1 << i & mask) {
1004 const char *reg = get_register_name_32(f->cpuid_reg);
1005 assert(reg);
1006 fprintf(stderr, "warning: host doesn't support requested feature: "
1007 "CPUID.%02XH:%s%s%s [bit %d]\n",
1008 f->cpuid_eax, reg,
1009 f->feat_names[i] ? "." : "",
1010 f->feat_names[i] ? f->feat_names[i] : "", i);
1011 break;
1012 }
1013 return 0;
1014 }
1015
1016 /* Check if all requested cpu flags are making their way to the guest
1017 *
1018 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1019 *
1020 * This function may be called only if KVM is enabled.
1021 */
1022 static int kvm_check_features_against_host(X86CPU *cpu)
1023 {
1024 CPUX86State *env = &cpu->env;
1025 x86_def_t host_def;
1026 uint32_t mask;
1027 int rv, i;
1028 struct model_features_t ft[] = {
1029 {&env->cpuid_features, &host_def.features,
1030 FEAT_1_EDX },
1031 {&env->cpuid_ext_features, &host_def.ext_features,
1032 FEAT_1_ECX },
1033 {&env->cpuid_ext2_features, &host_def.ext2_features,
1034 FEAT_8000_0001_EDX },
1035 {&env->cpuid_ext3_features, &host_def.ext3_features,
1036 FEAT_8000_0001_ECX },
1037 {&env->cpuid_ext4_features, &host_def.ext4_features,
1038 FEAT_C000_0001_EDX },
1039 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1040 FEAT_7_0_EBX },
1041 {&env->cpuid_svm_features, &host_def.svm_features,
1042 FEAT_SVM },
1043 {&env->cpuid_kvm_features, &host_def.kvm_features,
1044 FEAT_KVM },
1045 };
1046
1047 assert(kvm_enabled());
1048
1049 kvm_cpu_fill_host(&host_def);
1050 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1051 FeatureWord w = ft[i].feat_word;
1052 FeatureWordInfo *wi = &feature_word_info[w];
1053 for (mask = 1; mask; mask <<= 1) {
1054 if (*ft[i].guest_feat & mask &&
1055 !(*ft[i].host_feat & mask)) {
1056 unavailable_host_feature(wi, mask);
1057 rv = 1;
1058 }
1059 }
1060 }
1061 return rv;
1062 }
1063
1064 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1065 const char *name, Error **errp)
1066 {
1067 X86CPU *cpu = X86_CPU(obj);
1068 CPUX86State *env = &cpu->env;
1069 int64_t value;
1070
1071 value = (env->cpuid_version >> 8) & 0xf;
1072 if (value == 0xf) {
1073 value += (env->cpuid_version >> 20) & 0xff;
1074 }
1075 visit_type_int(v, &value, name, errp);
1076 }
1077
1078 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1079 const char *name, Error **errp)
1080 {
1081 X86CPU *cpu = X86_CPU(obj);
1082 CPUX86State *env = &cpu->env;
1083 const int64_t min = 0;
1084 const int64_t max = 0xff + 0xf;
1085 int64_t value;
1086
1087 visit_type_int(v, &value, name, errp);
1088 if (error_is_set(errp)) {
1089 return;
1090 }
1091 if (value < min || value > max) {
1092 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1093 name ? name : "null", value, min, max);
1094 return;
1095 }
1096
1097 env->cpuid_version &= ~0xff00f00;
1098 if (value > 0x0f) {
1099 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1100 } else {
1101 env->cpuid_version |= value << 8;
1102 }
1103 }
1104
1105 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1106 const char *name, Error **errp)
1107 {
1108 X86CPU *cpu = X86_CPU(obj);
1109 CPUX86State *env = &cpu->env;
1110 int64_t value;
1111
1112 value = (env->cpuid_version >> 4) & 0xf;
1113 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1114 visit_type_int(v, &value, name, errp);
1115 }
1116
1117 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1118 const char *name, Error **errp)
1119 {
1120 X86CPU *cpu = X86_CPU(obj);
1121 CPUX86State *env = &cpu->env;
1122 const int64_t min = 0;
1123 const int64_t max = 0xff;
1124 int64_t value;
1125
1126 visit_type_int(v, &value, name, errp);
1127 if (error_is_set(errp)) {
1128 return;
1129 }
1130 if (value < min || value > max) {
1131 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1132 name ? name : "null", value, min, max);
1133 return;
1134 }
1135
1136 env->cpuid_version &= ~0xf00f0;
1137 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1138 }
1139
1140 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1141 void *opaque, const char *name,
1142 Error **errp)
1143 {
1144 X86CPU *cpu = X86_CPU(obj);
1145 CPUX86State *env = &cpu->env;
1146 int64_t value;
1147
1148 value = env->cpuid_version & 0xf;
1149 visit_type_int(v, &value, name, errp);
1150 }
1151
1152 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1153 void *opaque, const char *name,
1154 Error **errp)
1155 {
1156 X86CPU *cpu = X86_CPU(obj);
1157 CPUX86State *env = &cpu->env;
1158 const int64_t min = 0;
1159 const int64_t max = 0xf;
1160 int64_t value;
1161
1162 visit_type_int(v, &value, name, errp);
1163 if (error_is_set(errp)) {
1164 return;
1165 }
1166 if (value < min || value > max) {
1167 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1168 name ? name : "null", value, min, max);
1169 return;
1170 }
1171
1172 env->cpuid_version &= ~0xf;
1173 env->cpuid_version |= value & 0xf;
1174 }
1175
1176 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1177 const char *name, Error **errp)
1178 {
1179 X86CPU *cpu = X86_CPU(obj);
1180
1181 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1182 }
1183
1184 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1185 const char *name, Error **errp)
1186 {
1187 X86CPU *cpu = X86_CPU(obj);
1188
1189 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1190 }
1191
1192 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1193 const char *name, Error **errp)
1194 {
1195 X86CPU *cpu = X86_CPU(obj);
1196
1197 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1198 }
1199
1200 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1201 const char *name, Error **errp)
1202 {
1203 X86CPU *cpu = X86_CPU(obj);
1204
1205 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1206 }
1207
1208 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1209 {
1210 X86CPU *cpu = X86_CPU(obj);
1211 CPUX86State *env = &cpu->env;
1212 char *value;
1213 int i;
1214
1215 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1216 for (i = 0; i < 4; i++) {
1217 value[i ] = env->cpuid_vendor1 >> (8 * i);
1218 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1219 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1220 }
1221 value[CPUID_VENDOR_SZ] = '\0';
1222 return value;
1223 }
1224
1225 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1226 Error **errp)
1227 {
1228 X86CPU *cpu = X86_CPU(obj);
1229 CPUX86State *env = &cpu->env;
1230 int i;
1231
1232 if (strlen(value) != CPUID_VENDOR_SZ) {
1233 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1234 "vendor", value);
1235 return;
1236 }
1237
1238 env->cpuid_vendor1 = 0;
1239 env->cpuid_vendor2 = 0;
1240 env->cpuid_vendor3 = 0;
1241 for (i = 0; i < 4; i++) {
1242 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1243 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1244 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1245 }
1246 env->cpuid_vendor_override = 1;
1247 }
1248
1249 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1250 {
1251 X86CPU *cpu = X86_CPU(obj);
1252 CPUX86State *env = &cpu->env;
1253 char *value;
1254 int i;
1255
1256 value = g_malloc(48 + 1);
1257 for (i = 0; i < 48; i++) {
1258 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1259 }
1260 value[48] = '\0';
1261 return value;
1262 }
1263
1264 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1265 Error **errp)
1266 {
1267 X86CPU *cpu = X86_CPU(obj);
1268 CPUX86State *env = &cpu->env;
1269 int c, len, i;
1270
1271 if (model_id == NULL) {
1272 model_id = "";
1273 }
1274 len = strlen(model_id);
1275 memset(env->cpuid_model, 0, 48);
1276 for (i = 0; i < 48; i++) {
1277 if (i >= len) {
1278 c = '\0';
1279 } else {
1280 c = (uint8_t)model_id[i];
1281 }
1282 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1283 }
1284 }
1285
1286 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1287 const char *name, Error **errp)
1288 {
1289 X86CPU *cpu = X86_CPU(obj);
1290 int64_t value;
1291
1292 value = cpu->env.tsc_khz * 1000;
1293 visit_type_int(v, &value, name, errp);
1294 }
1295
1296 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1297 const char *name, Error **errp)
1298 {
1299 X86CPU *cpu = X86_CPU(obj);
1300 const int64_t min = 0;
1301 const int64_t max = INT64_MAX;
1302 int64_t value;
1303
1304 visit_type_int(v, &value, name, errp);
1305 if (error_is_set(errp)) {
1306 return;
1307 }
1308 if (value < min || value > max) {
1309 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1310 name ? name : "null", value, min, max);
1311 return;
1312 }
1313
1314 cpu->env.tsc_khz = value / 1000;
1315 }
1316
1317 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1318 {
1319 x86_def_t *def;
1320
1321 for (def = x86_defs; def; def = def->next) {
1322 if (name && !strcmp(name, def->name)) {
1323 break;
1324 }
1325 }
1326 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1327 kvm_cpu_fill_host(x86_cpu_def);
1328 } else if (!def) {
1329 return -1;
1330 } else {
1331 memcpy(x86_cpu_def, def, sizeof(*def));
1332 }
1333
1334 return 0;
1335 }
1336
1337 /* Parse "+feature,-feature,feature=foo" CPU feature string
1338 */
1339 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1340 {
1341 unsigned int i;
1342 char *featurestr; /* Single 'key=value" string being parsed */
1343 /* Features to be added */
1344 FeatureWordArray plus_features = { 0 };
1345 /* Features to be removed */
1346 FeatureWordArray minus_features = { 0 };
1347 uint32_t numvalue;
1348
1349 featurestr = features ? strtok(features, ",") : NULL;
1350
1351 while (featurestr) {
1352 char *val;
1353 if (featurestr[0] == '+') {
1354 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1355 } else if (featurestr[0] == '-') {
1356 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1357 } else if ((val = strchr(featurestr, '='))) {
1358 *val = 0; val++;
1359 if (!strcmp(featurestr, "family")) {
1360 char *err;
1361 numvalue = strtoul(val, &err, 0);
1362 if (!*val || *err || numvalue > 0xff + 0xf) {
1363 fprintf(stderr, "bad numerical value %s\n", val);
1364 goto error;
1365 }
1366 x86_cpu_def->family = numvalue;
1367 } else if (!strcmp(featurestr, "model")) {
1368 char *err;
1369 numvalue = strtoul(val, &err, 0);
1370 if (!*val || *err || numvalue > 0xff) {
1371 fprintf(stderr, "bad numerical value %s\n", val);
1372 goto error;
1373 }
1374 x86_cpu_def->model = numvalue;
1375 } else if (!strcmp(featurestr, "stepping")) {
1376 char *err;
1377 numvalue = strtoul(val, &err, 0);
1378 if (!*val || *err || numvalue > 0xf) {
1379 fprintf(stderr, "bad numerical value %s\n", val);
1380 goto error;
1381 }
1382 x86_cpu_def->stepping = numvalue ;
1383 } else if (!strcmp(featurestr, "level")) {
1384 char *err;
1385 numvalue = strtoul(val, &err, 0);
1386 if (!*val || *err) {
1387 fprintf(stderr, "bad numerical value %s\n", val);
1388 goto error;
1389 }
1390 x86_cpu_def->level = numvalue;
1391 } else if (!strcmp(featurestr, "xlevel")) {
1392 char *err;
1393 numvalue = strtoul(val, &err, 0);
1394 if (!*val || *err) {
1395 fprintf(stderr, "bad numerical value %s\n", val);
1396 goto error;
1397 }
1398 if (numvalue < 0x80000000) {
1399 numvalue += 0x80000000;
1400 }
1401 x86_cpu_def->xlevel = numvalue;
1402 } else if (!strcmp(featurestr, "vendor")) {
1403 if (strlen(val) != 12) {
1404 fprintf(stderr, "vendor string must be 12 chars long\n");
1405 goto error;
1406 }
1407 x86_cpu_def->vendor1 = 0;
1408 x86_cpu_def->vendor2 = 0;
1409 x86_cpu_def->vendor3 = 0;
1410 for(i = 0; i < 4; i++) {
1411 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1412 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1413 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1414 }
1415 x86_cpu_def->vendor_override = 1;
1416 } else if (!strcmp(featurestr, "model_id")) {
1417 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1418 val);
1419 } else if (!strcmp(featurestr, "tsc_freq")) {
1420 int64_t tsc_freq;
1421 char *err;
1422
1423 tsc_freq = strtosz_suffix_unit(val, &err,
1424 STRTOSZ_DEFSUFFIX_B, 1000);
1425 if (tsc_freq < 0 || *err) {
1426 fprintf(stderr, "bad numerical value %s\n", val);
1427 goto error;
1428 }
1429 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1430 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1431 char *err;
1432 numvalue = strtoul(val, &err, 0);
1433 if (!*val || *err) {
1434 fprintf(stderr, "bad numerical value %s\n", val);
1435 goto error;
1436 }
1437 hyperv_set_spinlock_retries(numvalue);
1438 } else {
1439 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1440 goto error;
1441 }
1442 } else if (!strcmp(featurestr, "check")) {
1443 check_cpuid = 1;
1444 } else if (!strcmp(featurestr, "enforce")) {
1445 check_cpuid = enforce_cpuid = 1;
1446 } else if (!strcmp(featurestr, "hv_relaxed")) {
1447 hyperv_enable_relaxed_timing(true);
1448 } else if (!strcmp(featurestr, "hv_vapic")) {
1449 hyperv_enable_vapic_recommended(true);
1450 } else {
1451 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1452 goto error;
1453 }
1454 featurestr = strtok(NULL, ",");
1455 }
1456 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1457 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1458 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1459 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1460 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
1461 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1462 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1463 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1464 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1465 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1466 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1467 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1468 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1469 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1470 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1471 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1472 return 0;
1473
1474 error:
1475 return -1;
1476 }
1477
1478 /* generate a composite string into buf of all cpuid names in featureset
1479 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1480 * if flags, suppress names undefined in featureset.
1481 */
1482 static void listflags(char *buf, int bufsize, uint32_t fbits,
1483 const char **featureset, uint32_t flags)
1484 {
1485 const char **p = &featureset[31];
1486 char *q, *b, bit;
1487 int nc;
1488
1489 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1490 *buf = '\0';
1491 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1492 if (fbits & 1 << bit && (*p || !flags)) {
1493 if (*p)
1494 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1495 else
1496 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1497 if (bufsize <= nc) {
1498 if (b) {
1499 memcpy(b, "...", sizeof("..."));
1500 }
1501 return;
1502 }
1503 q += nc;
1504 bufsize -= nc;
1505 }
1506 }
1507
1508 /* generate CPU information. */
1509 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1510 {
1511 x86_def_t *def;
1512 char buf[256];
1513
1514 for (def = x86_defs; def; def = def->next) {
1515 snprintf(buf, sizeof(buf), "%s", def->name);
1516 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1517 }
1518 if (kvm_enabled()) {
1519 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1520 }
1521 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1522 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1523 (*cpu_fprintf)(f, " %s\n", buf);
1524 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1525 (*cpu_fprintf)(f, " %s\n", buf);
1526 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1527 (*cpu_fprintf)(f, " %s\n", buf);
1528 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1529 (*cpu_fprintf)(f, " %s\n", buf);
1530 }
1531
1532 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1533 {
1534 CpuDefinitionInfoList *cpu_list = NULL;
1535 x86_def_t *def;
1536
1537 for (def = x86_defs; def; def = def->next) {
1538 CpuDefinitionInfoList *entry;
1539 CpuDefinitionInfo *info;
1540
1541 info = g_malloc0(sizeof(*info));
1542 info->name = g_strdup(def->name);
1543
1544 entry = g_malloc0(sizeof(*entry));
1545 entry->value = info;
1546 entry->next = cpu_list;
1547 cpu_list = entry;
1548 }
1549
1550 return cpu_list;
1551 }
1552
1553 #ifdef CONFIG_KVM
1554 static void filter_features_for_kvm(X86CPU *cpu)
1555 {
1556 CPUX86State *env = &cpu->env;
1557 KVMState *s = kvm_state;
1558
1559 env->cpuid_features &=
1560 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1561 env->cpuid_ext_features &=
1562 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1563 env->cpuid_ext2_features &=
1564 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1565 env->cpuid_ext3_features &=
1566 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1567 env->cpuid_svm_features &=
1568 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1569 env->cpuid_7_0_ebx_features &=
1570 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1571 env->cpuid_kvm_features &=
1572 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1573 env->cpuid_ext4_features &=
1574 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1575
1576 }
1577 #endif
1578
1579 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1580 {
1581 CPUX86State *env = &cpu->env;
1582 x86_def_t def1, *def = &def1;
1583 Error *error = NULL;
1584 char *name, *features;
1585 gchar **model_pieces;
1586
1587 memset(def, 0, sizeof(*def));
1588
1589 model_pieces = g_strsplit(cpu_model, ",", 2);
1590 if (!model_pieces[0]) {
1591 error_setg(&error, "Invalid/empty CPU model name");
1592 goto out;
1593 }
1594 name = model_pieces[0];
1595 features = model_pieces[1];
1596
1597 if (cpu_x86_find_by_name(def, name) < 0) {
1598 error_setg(&error, "Unable to find CPU definition: %s", name);
1599 goto out;
1600 }
1601
1602 if (kvm_enabled()) {
1603 def->kvm_features |= kvm_default_features;
1604 }
1605 def->ext_features |= CPUID_EXT_HYPERVISOR;
1606
1607 if (cpu_x86_parse_featurestr(def, features) < 0) {
1608 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1609 goto out;
1610 }
1611 assert(def->vendor1);
1612 env->cpuid_vendor1 = def->vendor1;
1613 env->cpuid_vendor2 = def->vendor2;
1614 env->cpuid_vendor3 = def->vendor3;
1615 env->cpuid_vendor_override = def->vendor_override;
1616 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1617 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1618 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1619 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1620 env->cpuid_features = def->features;
1621 env->cpuid_ext_features = def->ext_features;
1622 env->cpuid_ext2_features = def->ext2_features;
1623 env->cpuid_ext3_features = def->ext3_features;
1624 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1625 env->cpuid_kvm_features = def->kvm_features;
1626 env->cpuid_svm_features = def->svm_features;
1627 env->cpuid_ext4_features = def->ext4_features;
1628 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1629 env->cpuid_xlevel2 = def->xlevel2;
1630 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1631 "tsc-frequency", &error);
1632
1633 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1634
1635 out:
1636 g_strfreev(model_pieces);
1637 if (error) {
1638 fprintf(stderr, "%s\n", error_get_pretty(error));
1639 error_free(error);
1640 return -1;
1641 }
1642 return 0;
1643 }
1644
1645 #if !defined(CONFIG_USER_ONLY)
1646
1647 void cpu_clear_apic_feature(CPUX86State *env)
1648 {
1649 env->cpuid_features &= ~CPUID_APIC;
1650 }
1651
1652 #endif /* !CONFIG_USER_ONLY */
1653
1654 /* Initialize list of CPU models, filling some non-static fields if necessary
1655 */
1656 void x86_cpudef_setup(void)
1657 {
1658 int i, j;
1659 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1660
1661 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1662 x86_def_t *def = &builtin_x86_defs[i];
1663 def->next = x86_defs;
1664
1665 /* Look for specific "cpudef" models that */
1666 /* have the QEMU version in .model_id */
1667 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1668 if (strcmp(model_with_versions[j], def->name) == 0) {
1669 pstrcpy(def->model_id, sizeof(def->model_id),
1670 "QEMU Virtual CPU version ");
1671 pstrcat(def->model_id, sizeof(def->model_id),
1672 qemu_get_version());
1673 break;
1674 }
1675 }
1676
1677 x86_defs = def;
1678 }
1679 }
1680
1681 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1682 uint32_t *ecx, uint32_t *edx)
1683 {
1684 *ebx = env->cpuid_vendor1;
1685 *edx = env->cpuid_vendor2;
1686 *ecx = env->cpuid_vendor3;
1687
1688 /* sysenter isn't supported on compatibility mode on AMD, syscall
1689 * isn't supported in compatibility mode on Intel.
1690 * Normally we advertise the actual cpu vendor, but you can override
1691 * this if you want to use KVM's sysenter/syscall emulation
1692 * in compatibility mode and when doing cross vendor migration
1693 */
1694 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1695 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1696 }
1697 }
1698
1699 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1700 uint32_t *eax, uint32_t *ebx,
1701 uint32_t *ecx, uint32_t *edx)
1702 {
1703 X86CPU *cpu = x86_env_get_cpu(env);
1704 CPUState *cs = CPU(cpu);
1705
1706 /* test if maximum index reached */
1707 if (index & 0x80000000) {
1708 if (index > env->cpuid_xlevel) {
1709 if (env->cpuid_xlevel2 > 0) {
1710 /* Handle the Centaur's CPUID instruction. */
1711 if (index > env->cpuid_xlevel2) {
1712 index = env->cpuid_xlevel2;
1713 } else if (index < 0xC0000000) {
1714 index = env->cpuid_xlevel;
1715 }
1716 } else {
1717 /* Intel documentation states that invalid EAX input will
1718 * return the same information as EAX=cpuid_level
1719 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1720 */
1721 index = env->cpuid_level;
1722 }
1723 }
1724 } else {
1725 if (index > env->cpuid_level)
1726 index = env->cpuid_level;
1727 }
1728
1729 switch(index) {
1730 case 0:
1731 *eax = env->cpuid_level;
1732 get_cpuid_vendor(env, ebx, ecx, edx);
1733 break;
1734 case 1:
1735 *eax = env->cpuid_version;
1736 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1737 *ecx = env->cpuid_ext_features;
1738 *edx = env->cpuid_features;
1739 if (cs->nr_cores * cs->nr_threads > 1) {
1740 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1741 *edx |= 1 << 28; /* HTT bit */
1742 }
1743 break;
1744 case 2:
1745 /* cache info: needed for Pentium Pro compatibility */
1746 *eax = 1;
1747 *ebx = 0;
1748 *ecx = 0;
1749 *edx = 0x2c307d;
1750 break;
1751 case 4:
1752 /* cache info: needed for Core compatibility */
1753 if (cs->nr_cores > 1) {
1754 *eax = (cs->nr_cores - 1) << 26;
1755 } else {
1756 *eax = 0;
1757 }
1758 switch (count) {
1759 case 0: /* L1 dcache info */
1760 *eax |= 0x0000121;
1761 *ebx = 0x1c0003f;
1762 *ecx = 0x000003f;
1763 *edx = 0x0000001;
1764 break;
1765 case 1: /* L1 icache info */
1766 *eax |= 0x0000122;
1767 *ebx = 0x1c0003f;
1768 *ecx = 0x000003f;
1769 *edx = 0x0000001;
1770 break;
1771 case 2: /* L2 cache info */
1772 *eax |= 0x0000143;
1773 if (cs->nr_threads > 1) {
1774 *eax |= (cs->nr_threads - 1) << 14;
1775 }
1776 *ebx = 0x3c0003f;
1777 *ecx = 0x0000fff;
1778 *edx = 0x0000001;
1779 break;
1780 default: /* end of info */
1781 *eax = 0;
1782 *ebx = 0;
1783 *ecx = 0;
1784 *edx = 0;
1785 break;
1786 }
1787 break;
1788 case 5:
1789 /* mwait info: needed for Core compatibility */
1790 *eax = 0; /* Smallest monitor-line size in bytes */
1791 *ebx = 0; /* Largest monitor-line size in bytes */
1792 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1793 *edx = 0;
1794 break;
1795 case 6:
1796 /* Thermal and Power Leaf */
1797 *eax = 0;
1798 *ebx = 0;
1799 *ecx = 0;
1800 *edx = 0;
1801 break;
1802 case 7:
1803 /* Structured Extended Feature Flags Enumeration Leaf */
1804 if (count == 0) {
1805 *eax = 0; /* Maximum ECX value for sub-leaves */
1806 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1807 *ecx = 0; /* Reserved */
1808 *edx = 0; /* Reserved */
1809 } else {
1810 *eax = 0;
1811 *ebx = 0;
1812 *ecx = 0;
1813 *edx = 0;
1814 }
1815 break;
1816 case 9:
1817 /* Direct Cache Access Information Leaf */
1818 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1819 *ebx = 0;
1820 *ecx = 0;
1821 *edx = 0;
1822 break;
1823 case 0xA:
1824 /* Architectural Performance Monitoring Leaf */
1825 if (kvm_enabled()) {
1826 KVMState *s = cs->kvm_state;
1827
1828 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1829 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1830 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1831 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1832 } else {
1833 *eax = 0;
1834 *ebx = 0;
1835 *ecx = 0;
1836 *edx = 0;
1837 }
1838 break;
1839 case 0xD:
1840 /* Processor Extended State */
1841 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1842 *eax = 0;
1843 *ebx = 0;
1844 *ecx = 0;
1845 *edx = 0;
1846 break;
1847 }
1848 if (kvm_enabled()) {
1849 KVMState *s = cs->kvm_state;
1850
1851 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1852 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1853 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1854 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1855 } else {
1856 *eax = 0;
1857 *ebx = 0;
1858 *ecx = 0;
1859 *edx = 0;
1860 }
1861 break;
1862 case 0x80000000:
1863 *eax = env->cpuid_xlevel;
1864 *ebx = env->cpuid_vendor1;
1865 *edx = env->cpuid_vendor2;
1866 *ecx = env->cpuid_vendor3;
1867 break;
1868 case 0x80000001:
1869 *eax = env->cpuid_version;
1870 *ebx = 0;
1871 *ecx = env->cpuid_ext3_features;
1872 *edx = env->cpuid_ext2_features;
1873
1874 /* The Linux kernel checks for the CMPLegacy bit and
1875 * discards multiple thread information if it is set.
1876 * So dont set it here for Intel to make Linux guests happy.
1877 */
1878 if (cs->nr_cores * cs->nr_threads > 1) {
1879 uint32_t tebx, tecx, tedx;
1880 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1881 if (tebx != CPUID_VENDOR_INTEL_1 ||
1882 tedx != CPUID_VENDOR_INTEL_2 ||
1883 tecx != CPUID_VENDOR_INTEL_3) {
1884 *ecx |= 1 << 1; /* CmpLegacy bit */
1885 }
1886 }
1887 break;
1888 case 0x80000002:
1889 case 0x80000003:
1890 case 0x80000004:
1891 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1892 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1893 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1894 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1895 break;
1896 case 0x80000005:
1897 /* cache info (L1 cache) */
1898 *eax = 0x01ff01ff;
1899 *ebx = 0x01ff01ff;
1900 *ecx = 0x40020140;
1901 *edx = 0x40020140;
1902 break;
1903 case 0x80000006:
1904 /* cache info (L2 cache) */
1905 *eax = 0;
1906 *ebx = 0x42004200;
1907 *ecx = 0x02008140;
1908 *edx = 0;
1909 break;
1910 case 0x80000008:
1911 /* virtual & phys address size in low 2 bytes. */
1912 /* XXX: This value must match the one used in the MMU code. */
1913 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1914 /* 64 bit processor */
1915 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1916 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1917 } else {
1918 if (env->cpuid_features & CPUID_PSE36)
1919 *eax = 0x00000024; /* 36 bits physical */
1920 else
1921 *eax = 0x00000020; /* 32 bits physical */
1922 }
1923 *ebx = 0;
1924 *ecx = 0;
1925 *edx = 0;
1926 if (cs->nr_cores * cs->nr_threads > 1) {
1927 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1928 }
1929 break;
1930 case 0x8000000A:
1931 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1932 *eax = 0x00000001; /* SVM Revision */
1933 *ebx = 0x00000010; /* nr of ASIDs */
1934 *ecx = 0;
1935 *edx = env->cpuid_svm_features; /* optional features */
1936 } else {
1937 *eax = 0;
1938 *ebx = 0;
1939 *ecx = 0;
1940 *edx = 0;
1941 }
1942 break;
1943 case 0xC0000000:
1944 *eax = env->cpuid_xlevel2;
1945 *ebx = 0;
1946 *ecx = 0;
1947 *edx = 0;
1948 break;
1949 case 0xC0000001:
1950 /* Support for VIA CPU's CPUID instruction */
1951 *eax = env->cpuid_version;
1952 *ebx = 0;
1953 *ecx = 0;
1954 *edx = env->cpuid_ext4_features;
1955 break;
1956 case 0xC0000002:
1957 case 0xC0000003:
1958 case 0xC0000004:
1959 /* Reserved for the future, and now filled with zero */
1960 *eax = 0;
1961 *ebx = 0;
1962 *ecx = 0;
1963 *edx = 0;
1964 break;
1965 default:
1966 /* reserved values: zero */
1967 *eax = 0;
1968 *ebx = 0;
1969 *ecx = 0;
1970 *edx = 0;
1971 break;
1972 }
1973 }
1974
1975 /* CPUClass::reset() */
1976 static void x86_cpu_reset(CPUState *s)
1977 {
1978 X86CPU *cpu = X86_CPU(s);
1979 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1980 CPUX86State *env = &cpu->env;
1981 int i;
1982
1983 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1984 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1985 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1986 }
1987
1988 xcc->parent_reset(s);
1989
1990
1991 memset(env, 0, offsetof(CPUX86State, breakpoints));
1992
1993 tlb_flush(env, 1);
1994
1995 env->old_exception = -1;
1996
1997 /* init to reset state */
1998
1999 #ifdef CONFIG_SOFTMMU
2000 env->hflags |= HF_SOFTMMU_MASK;
2001 #endif
2002 env->hflags2 |= HF2_GIF_MASK;
2003
2004 cpu_x86_update_cr0(env, 0x60000010);
2005 env->a20_mask = ~0x0;
2006 env->smbase = 0x30000;
2007
2008 env->idt.limit = 0xffff;
2009 env->gdt.limit = 0xffff;
2010 env->ldt.limit = 0xffff;
2011 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2012 env->tr.limit = 0xffff;
2013 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2014
2015 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2016 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2017 DESC_R_MASK | DESC_A_MASK);
2018 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2019 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2020 DESC_A_MASK);
2021 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2022 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2023 DESC_A_MASK);
2024 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2025 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2026 DESC_A_MASK);
2027 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2028 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2029 DESC_A_MASK);
2030 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2031 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2032 DESC_A_MASK);
2033
2034 env->eip = 0xfff0;
2035 env->regs[R_EDX] = env->cpuid_version;
2036
2037 env->eflags = 0x2;
2038
2039 /* FPU init */
2040 for (i = 0; i < 8; i++) {
2041 env->fptags[i] = 1;
2042 }
2043 env->fpuc = 0x37f;
2044
2045 env->mxcsr = 0x1f80;
2046
2047 env->pat = 0x0007040600070406ULL;
2048 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2049
2050 memset(env->dr, 0, sizeof(env->dr));
2051 env->dr[6] = DR6_FIXED_1;
2052 env->dr[7] = DR7_FIXED_1;
2053 cpu_breakpoint_remove_all(env, BP_CPU);
2054 cpu_watchpoint_remove_all(env, BP_CPU);
2055
2056 #if !defined(CONFIG_USER_ONLY)
2057 /* We hard-wire the BSP to the first CPU. */
2058 if (s->cpu_index == 0) {
2059 apic_designate_bsp(env->apic_state);
2060 }
2061
2062 env->halted = !cpu_is_bsp(cpu);
2063 #endif
2064 }
2065
2066 #ifndef CONFIG_USER_ONLY
2067 bool cpu_is_bsp(X86CPU *cpu)
2068 {
2069 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2070 }
2071
2072 /* TODO: remove me, when reset over QOM tree is implemented */
2073 static void x86_cpu_machine_reset_cb(void *opaque)
2074 {
2075 X86CPU *cpu = opaque;
2076 cpu_reset(CPU(cpu));
2077 }
2078 #endif
2079
2080 static void mce_init(X86CPU *cpu)
2081 {
2082 CPUX86State *cenv = &cpu->env;
2083 unsigned int bank;
2084
2085 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2086 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2087 (CPUID_MCE | CPUID_MCA)) {
2088 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2089 cenv->mcg_ctl = ~(uint64_t)0;
2090 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2091 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2092 }
2093 }
2094 }
2095
2096 #define MSI_ADDR_BASE 0xfee00000
2097
2098 #ifndef CONFIG_USER_ONLY
2099 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2100 {
2101 static int apic_mapped;
2102 CPUX86State *env = &cpu->env;
2103 APICCommonState *apic;
2104 const char *apic_type = "apic";
2105
2106 if (kvm_irqchip_in_kernel()) {
2107 apic_type = "kvm-apic";
2108 } else if (xen_enabled()) {
2109 apic_type = "xen-apic";
2110 }
2111
2112 env->apic_state = qdev_try_create(NULL, apic_type);
2113 if (env->apic_state == NULL) {
2114 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2115 return;
2116 }
2117
2118 object_property_add_child(OBJECT(cpu), "apic",
2119 OBJECT(env->apic_state), NULL);
2120 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2121 /* TODO: convert to link<> */
2122 apic = APIC_COMMON(env->apic_state);
2123 apic->cpu = cpu;
2124
2125 if (qdev_init(env->apic_state)) {
2126 error_setg(errp, "APIC device '%s' could not be initialized",
2127 object_get_typename(OBJECT(env->apic_state)));
2128 return;
2129 }
2130
2131 /* XXX: mapping more APICs at the same memory location */
2132 if (apic_mapped == 0) {
2133 /* NOTE: the APIC is directly connected to the CPU - it is not
2134 on the global memory bus. */
2135 /* XXX: what if the base changes? */
2136 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2137 apic_mapped = 1;
2138 }
2139 }
2140 #endif
2141
2142 void x86_cpu_realize(Object *obj, Error **errp)
2143 {
2144 X86CPU *cpu = X86_CPU(obj);
2145 CPUX86State *env = &cpu->env;
2146
2147 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2148 env->cpuid_level = 7;
2149 }
2150
2151 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2152 * CPUID[1].EDX.
2153 */
2154 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2155 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2156 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2157 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2158 env->cpuid_ext2_features |= (env->cpuid_features
2159 & CPUID_EXT2_AMD_ALIASES);
2160 }
2161
2162 if (!kvm_enabled()) {
2163 env->cpuid_features &= TCG_FEATURES;
2164 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2165 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2166 #ifdef TARGET_X86_64
2167 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2168 #endif
2169 );
2170 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2171 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2172 } else {
2173 #ifdef CONFIG_KVM
2174 filter_features_for_kvm(cpu);
2175 #endif
2176 if (check_cpuid && kvm_check_features_against_host(cpu)
2177 && enforce_cpuid) {
2178 error_setg(errp, "Host's CPU doesn't support requested features");
2179 return;
2180 }
2181 }
2182
2183 #ifndef CONFIG_USER_ONLY
2184 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2185
2186 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2187 x86_cpu_apic_init(cpu, errp);
2188 if (error_is_set(errp)) {
2189 return;
2190 }
2191 }
2192 #endif
2193
2194 mce_init(cpu);
2195 qemu_init_vcpu(&cpu->env);
2196 cpu_reset(CPU(cpu));
2197 }
2198
2199 /* Enables contiguous-apic-ID mode, for compatibility */
2200 static bool compat_apic_id_mode;
2201
2202 void enable_compat_apic_id_mode(void)
2203 {
2204 compat_apic_id_mode = true;
2205 }
2206
2207 /* Calculates initial APIC ID for a specific CPU index
2208 *
2209 * Currently we need to be able to calculate the APIC ID from the CPU index
2210 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2211 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2212 * all CPUs up to max_cpus.
2213 */
2214 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2215 {
2216 uint32_t correct_id;
2217 static bool warned;
2218
2219 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2220 if (compat_apic_id_mode) {
2221 if (cpu_index != correct_id && !warned) {
2222 error_report("APIC IDs set in compatibility mode, "
2223 "CPU topology won't match the configuration");
2224 warned = true;
2225 }
2226 return cpu_index;
2227 } else {
2228 return correct_id;
2229 }
2230 }
2231
2232 static void x86_cpu_initfn(Object *obj)
2233 {
2234 CPUState *cs = CPU(obj);
2235 X86CPU *cpu = X86_CPU(obj);
2236 CPUX86State *env = &cpu->env;
2237 static int inited;
2238
2239 cpu_exec_init(env);
2240
2241 object_property_add(obj, "family", "int",
2242 x86_cpuid_version_get_family,
2243 x86_cpuid_version_set_family, NULL, NULL, NULL);
2244 object_property_add(obj, "model", "int",
2245 x86_cpuid_version_get_model,
2246 x86_cpuid_version_set_model, NULL, NULL, NULL);
2247 object_property_add(obj, "stepping", "int",
2248 x86_cpuid_version_get_stepping,
2249 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2250 object_property_add(obj, "level", "int",
2251 x86_cpuid_get_level,
2252 x86_cpuid_set_level, NULL, NULL, NULL);
2253 object_property_add(obj, "xlevel", "int",
2254 x86_cpuid_get_xlevel,
2255 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2256 object_property_add_str(obj, "vendor",
2257 x86_cpuid_get_vendor,
2258 x86_cpuid_set_vendor, NULL);
2259 object_property_add_str(obj, "model-id",
2260 x86_cpuid_get_model_id,
2261 x86_cpuid_set_model_id, NULL);
2262 object_property_add(obj, "tsc-frequency", "int",
2263 x86_cpuid_get_tsc_freq,
2264 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2265
2266 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2267
2268 /* init various static tables used in TCG mode */
2269 if (tcg_enabled() && !inited) {
2270 inited = 1;
2271 optimize_flags_init();
2272 #ifndef CONFIG_USER_ONLY
2273 cpu_set_debug_excp_handler(breakpoint_handler);
2274 #endif
2275 }
2276 }
2277
2278 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2279 {
2280 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2281 CPUClass *cc = CPU_CLASS(oc);
2282
2283 xcc->parent_reset = cc->reset;
2284 cc->reset = x86_cpu_reset;
2285 }
2286
2287 static const TypeInfo x86_cpu_type_info = {
2288 .name = TYPE_X86_CPU,
2289 .parent = TYPE_CPU,
2290 .instance_size = sizeof(X86CPU),
2291 .instance_init = x86_cpu_initfn,
2292 .abstract = false,
2293 .class_size = sizeof(X86CPUClass),
2294 .class_init = x86_cpu_common_class_init,
2295 };
2296
2297 static void x86_cpu_register_types(void)
2298 {
2299 type_register_static(&x86_cpu_type_info);
2300 }
2301
2302 type_init(x86_cpu_register_types)
Qemu copy for testing