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Drop cpu_list_id macro
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
43 */
44 static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
53 };
54 static const char *ext_feature_name[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL, NULL, "hypervisor",
63 };
64 static const char *ext2_feature_name[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL, NULL /* Linux mp */,
70 "nx|xd", NULL, "mmxext", "mmx",
71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
72 NULL, "lm|i64", "3dnowext", "3dnow",
73 };
74 static const char *ext3_feature_name[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
77 "3dnowprefetch", "osvw", "ibs", "xop",
78 "skinit", "wdt", NULL, NULL,
79 "fma4", NULL, "cvt16", "nodeid_msr",
80 NULL, NULL, NULL, NULL,
81 NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL,
83 };
84
85 static const char *kvm_feature_name[] = {
86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
89 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
90 };
91
92 static const char *svm_feature_name[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL, NULL, "pause_filter", NULL,
96 "pfthreshold", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 NULL, NULL, NULL, NULL,
99 NULL, NULL, NULL, NULL,
100 NULL, NULL, NULL, NULL,
101 };
102
103 /* collects per-function cpuid data
104 */
105 typedef struct model_features_t {
106 uint32_t *guest_feat;
107 uint32_t *host_feat;
108 uint32_t check_feat;
109 const char **flag_names;
110 uint32_t cpuid;
111 } model_features_t;
112
113 int check_cpuid = 0;
114 int enforce_cpuid = 0;
115
116 void host_cpuid(uint32_t function, uint32_t count,
117 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
118 {
119 #if defined(CONFIG_KVM)
120 uint32_t vec[4];
121
122 #ifdef __x86_64__
123 asm volatile("cpuid"
124 : "=a"(vec[0]), "=b"(vec[1]),
125 "=c"(vec[2]), "=d"(vec[3])
126 : "0"(function), "c"(count) : "cc");
127 #else
128 asm volatile("pusha \n\t"
129 "cpuid \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
134 "popa"
135 : : "a"(function), "c"(count), "S"(vec)
136 : "memory", "cc");
137 #endif
138
139 if (eax)
140 *eax = vec[0];
141 if (ebx)
142 *ebx = vec[1];
143 if (ecx)
144 *ecx = vec[2];
145 if (edx)
146 *edx = vec[3];
147 #endif
148 }
149
150 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
151
152 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
156 */
157 static int sstrcmp(const char *s1, const char *e1, const char *s2,
158 const char *e2)
159 {
160 for (;;) {
161 if (!*s1 || !*s2 || *s1 != *s2)
162 return (*s1 - *s2);
163 ++s1, ++s2;
164 if (s1 == e1 && s2 == e2)
165 return (0);
166 else if (s1 == e1)
167 return (*s2);
168 else if (s2 == e2)
169 return (*s1);
170 }
171 }
172
173 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
177 */
178 static int altcmp(const char *s, const char *e, const char *altstr)
179 {
180 const char *p, *q;
181
182 for (q = p = altstr; ; ) {
183 while (*p && *p != '|')
184 ++p;
185 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
186 return (0);
187 if (!*p)
188 return (1);
189 else
190 q = ++p;
191 }
192 }
193
194 /* search featureset for flag *[s..e), if found set corresponding bit in
195 * *pval and return true, otherwise return false
196 */
197 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
198 const char **featureset)
199 {
200 uint32_t mask;
201 const char **ppc;
202 bool found = false;
203
204 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
205 if (*ppc && !altcmp(s, e, *ppc)) {
206 *pval |= mask;
207 found = true;
208 }
209 }
210 return found;
211 }
212
213 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
214 uint32_t *ext_features,
215 uint32_t *ext2_features,
216 uint32_t *ext3_features,
217 uint32_t *kvm_features,
218 uint32_t *svm_features)
219 {
220 if (!lookup_feature(features, flagname, NULL, feature_name) &&
221 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
222 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
223 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
224 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
225 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
226 fprintf(stderr, "CPU feature %s not found\n", flagname);
227 }
228
229 typedef struct x86_def_t {
230 struct x86_def_t *next;
231 const char *name;
232 uint32_t level;
233 uint32_t vendor1, vendor2, vendor3;
234 int family;
235 int model;
236 int stepping;
237 int tsc_khz;
238 uint32_t features, ext_features, ext2_features, ext3_features;
239 uint32_t kvm_features, svm_features;
240 uint32_t xlevel;
241 char model_id[48];
242 int vendor_override;
243 uint32_t flags;
244 /* Store the results of Centaur's CPUID instructions */
245 uint32_t ext4_features;
246 uint32_t xlevel2;
247 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
248 uint32_t cpuid_7_0_ebx_features;
249 } x86_def_t;
250
251 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
252 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
253 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
254 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
255 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
256 CPUID_PSE36 | CPUID_FXSR)
257 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
258 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
259 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
260 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
261 CPUID_PAE | CPUID_SEP | CPUID_APIC)
262 #define EXT2_FEATURE_MASK 0x0183F3FF
263
264 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
265 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
266 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
267 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
268 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
269 /* partly implemented:
270 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
271 CPUID_PSE36 (needed for Solaris) */
272 /* missing:
273 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
274 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
275 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
276 CPUID_EXT_HYPERVISOR)
277 /* missing:
278 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
279 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
280 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
281 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
282 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
283 /* missing:
284 CPUID_EXT2_PDPE1GB */
285 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
286 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
287 #define TCG_SVM_FEATURES 0
288
289 /* maintains list of cpu model definitions
290 */
291 static x86_def_t *x86_defs = {NULL};
292
293 /* built-in cpu model definitions (deprecated)
294 */
295 static x86_def_t builtin_x86_defs[] = {
296 {
297 .name = "qemu64",
298 .level = 4,
299 .vendor1 = CPUID_VENDOR_AMD_1,
300 .vendor2 = CPUID_VENDOR_AMD_2,
301 .vendor3 = CPUID_VENDOR_AMD_3,
302 .family = 6,
303 .model = 2,
304 .stepping = 3,
305 .features = PPRO_FEATURES |
306 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
307 CPUID_PSE36,
308 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
309 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
310 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
311 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
312 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
313 .xlevel = 0x8000000A,
314 },
315 {
316 .name = "phenom",
317 .level = 5,
318 .vendor1 = CPUID_VENDOR_AMD_1,
319 .vendor2 = CPUID_VENDOR_AMD_2,
320 .vendor3 = CPUID_VENDOR_AMD_3,
321 .family = 16,
322 .model = 2,
323 .stepping = 3,
324 .features = PPRO_FEATURES |
325 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
326 CPUID_PSE36 | CPUID_VME | CPUID_HT,
327 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
328 CPUID_EXT_POPCNT,
329 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
330 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
331 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
332 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
333 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
334 CPUID_EXT3_CR8LEG,
335 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
336 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
337 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
338 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
339 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
340 .xlevel = 0x8000001A,
341 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
342 },
343 {
344 .name = "core2duo",
345 .level = 10,
346 .family = 6,
347 .model = 15,
348 .stepping = 11,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
352 CPUID_HT | CPUID_TM | CPUID_PBE,
353 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
354 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
355 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
356 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
357 .ext3_features = CPUID_EXT3_LAHF_LM,
358 .xlevel = 0x80000008,
359 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
360 },
361 {
362 .name = "kvm64",
363 .level = 5,
364 .vendor1 = CPUID_VENDOR_INTEL_1,
365 .vendor2 = CPUID_VENDOR_INTEL_2,
366 .vendor3 = CPUID_VENDOR_INTEL_3,
367 .family = 15,
368 .model = 6,
369 .stepping = 1,
370 /* Missing: CPUID_VME, CPUID_HT */
371 .features = PPRO_FEATURES |
372 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
373 CPUID_PSE36,
374 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
375 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
376 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
377 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
378 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
379 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
380 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
381 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
382 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
383 .ext3_features = 0,
384 .xlevel = 0x80000008,
385 .model_id = "Common KVM processor"
386 },
387 {
388 .name = "qemu32",
389 .level = 4,
390 .family = 6,
391 .model = 3,
392 .stepping = 3,
393 .features = PPRO_FEATURES,
394 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
395 .xlevel = 0x80000004,
396 },
397 {
398 .name = "kvm32",
399 .level = 5,
400 .family = 15,
401 .model = 6,
402 .stepping = 1,
403 .features = PPRO_FEATURES |
404 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
405 .ext_features = CPUID_EXT_SSE3,
406 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
407 .ext3_features = 0,
408 .xlevel = 0x80000008,
409 .model_id = "Common 32-bit KVM processor"
410 },
411 {
412 .name = "coreduo",
413 .level = 10,
414 .family = 6,
415 .model = 14,
416 .stepping = 8,
417 .features = PPRO_FEATURES | CPUID_VME |
418 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
419 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
420 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
421 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
422 .ext2_features = CPUID_EXT2_NX,
423 .xlevel = 0x80000008,
424 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
425 },
426 {
427 .name = "486",
428 .level = 1,
429 .family = 4,
430 .model = 0,
431 .stepping = 0,
432 .features = I486_FEATURES,
433 .xlevel = 0,
434 },
435 {
436 .name = "pentium",
437 .level = 1,
438 .family = 5,
439 .model = 4,
440 .stepping = 3,
441 .features = PENTIUM_FEATURES,
442 .xlevel = 0,
443 },
444 {
445 .name = "pentium2",
446 .level = 2,
447 .family = 6,
448 .model = 5,
449 .stepping = 2,
450 .features = PENTIUM2_FEATURES,
451 .xlevel = 0,
452 },
453 {
454 .name = "pentium3",
455 .level = 2,
456 .family = 6,
457 .model = 7,
458 .stepping = 3,
459 .features = PENTIUM3_FEATURES,
460 .xlevel = 0,
461 },
462 {
463 .name = "athlon",
464 .level = 2,
465 .vendor1 = CPUID_VENDOR_AMD_1,
466 .vendor2 = CPUID_VENDOR_AMD_2,
467 .vendor3 = CPUID_VENDOR_AMD_3,
468 .family = 6,
469 .model = 2,
470 .stepping = 3,
471 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
472 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
473 .xlevel = 0x80000008,
474 },
475 {
476 .name = "n270",
477 /* original is on level 10 */
478 .level = 5,
479 .family = 6,
480 .model = 28,
481 .stepping = 2,
482 .features = PPRO_FEATURES |
483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
484 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
485 /* Some CPUs got no CPUID_SEP */
486 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
487 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
488 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
489 .ext3_features = CPUID_EXT3_LAHF_LM,
490 .xlevel = 0x8000000A,
491 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
492 },
493 };
494
495 static int cpu_x86_fill_model_id(char *str)
496 {
497 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
498 int i;
499
500 for (i = 0; i < 3; i++) {
501 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
502 memcpy(str + i * 16 + 0, &eax, 4);
503 memcpy(str + i * 16 + 4, &ebx, 4);
504 memcpy(str + i * 16 + 8, &ecx, 4);
505 memcpy(str + i * 16 + 12, &edx, 4);
506 }
507 return 0;
508 }
509
510 static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
511 {
512 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
513
514 x86_cpu_def->name = "host";
515 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
516 x86_cpu_def->level = eax;
517 x86_cpu_def->vendor1 = ebx;
518 x86_cpu_def->vendor2 = edx;
519 x86_cpu_def->vendor3 = ecx;
520
521 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
522 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
523 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
524 x86_cpu_def->stepping = eax & 0x0F;
525 x86_cpu_def->ext_features = ecx;
526 x86_cpu_def->features = edx;
527
528 if (kvm_enabled() && x86_cpu_def->level >= 7) {
529 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
530 } else {
531 x86_cpu_def->cpuid_7_0_ebx_features = 0;
532 }
533
534 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
535 x86_cpu_def->xlevel = eax;
536
537 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
538 x86_cpu_def->ext2_features = edx;
539 x86_cpu_def->ext3_features = ecx;
540 cpu_x86_fill_model_id(x86_cpu_def->model_id);
541 x86_cpu_def->vendor_override = 0;
542
543 /* Call Centaur's CPUID instruction. */
544 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
545 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
546 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
547 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
548 if (eax >= 0xC0000001) {
549 /* Support VIA max extended level */
550 x86_cpu_def->xlevel2 = eax;
551 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
552 x86_cpu_def->ext4_features = edx;
553 }
554 }
555
556 /*
557 * Every SVM feature requires emulation support in KVM - so we can't just
558 * read the host features here. KVM might even support SVM features not
559 * available on the host hardware. Just set all bits and mask out the
560 * unsupported ones later.
561 */
562 x86_cpu_def->svm_features = -1;
563
564 return 0;
565 }
566
567 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
568 {
569 int i;
570
571 for (i = 0; i < 32; ++i)
572 if (1 << i & mask) {
573 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
574 " flag '%s' [0x%08x]\n",
575 f->cpuid >> 16, f->cpuid & 0xffff,
576 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
577 break;
578 }
579 return 0;
580 }
581
582 /* best effort attempt to inform user requested cpu flags aren't making
583 * their way to the guest. Note: ft[].check_feat ideally should be
584 * specified via a guest_def field to suppress report of extraneous flags.
585 */
586 static int check_features_against_host(x86_def_t *guest_def)
587 {
588 x86_def_t host_def;
589 uint32_t mask;
590 int rv, i;
591 struct model_features_t ft[] = {
592 {&guest_def->features, &host_def.features,
593 ~0, feature_name, 0x00000000},
594 {&guest_def->ext_features, &host_def.ext_features,
595 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
596 {&guest_def->ext2_features, &host_def.ext2_features,
597 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
598 {&guest_def->ext3_features, &host_def.ext3_features,
599 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
600
601 cpu_x86_fill_host(&host_def);
602 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
603 for (mask = 1; mask; mask <<= 1)
604 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
605 !(*ft[i].host_feat & mask)) {
606 unavailable_host_feature(&ft[i], mask);
607 rv = 1;
608 }
609 return rv;
610 }
611
612 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
613 const char *name, Error **errp)
614 {
615 X86CPU *cpu = X86_CPU(obj);
616 CPUX86State *env = &cpu->env;
617 int64_t value;
618
619 value = (env->cpuid_version >> 8) & 0xf;
620 if (value == 0xf) {
621 value += (env->cpuid_version >> 20) & 0xff;
622 }
623 visit_type_int(v, &value, name, errp);
624 }
625
626 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
627 const char *name, Error **errp)
628 {
629 X86CPU *cpu = X86_CPU(obj);
630 CPUX86State *env = &cpu->env;
631 const int64_t min = 0;
632 const int64_t max = 0xff + 0xf;
633 int64_t value;
634
635 visit_type_int(v, &value, name, errp);
636 if (error_is_set(errp)) {
637 return;
638 }
639 if (value < min || value > max) {
640 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
641 name ? name : "null", value, min, max);
642 return;
643 }
644
645 env->cpuid_version &= ~0xff00f00;
646 if (value > 0x0f) {
647 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
648 } else {
649 env->cpuid_version |= value << 8;
650 }
651 }
652
653 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
654 const char *name, Error **errp)
655 {
656 X86CPU *cpu = X86_CPU(obj);
657 CPUX86State *env = &cpu->env;
658 int64_t value;
659
660 value = (env->cpuid_version >> 4) & 0xf;
661 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
662 visit_type_int(v, &value, name, errp);
663 }
664
665 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
666 const char *name, Error **errp)
667 {
668 X86CPU *cpu = X86_CPU(obj);
669 CPUX86State *env = &cpu->env;
670 const int64_t min = 0;
671 const int64_t max = 0xff;
672 int64_t value;
673
674 visit_type_int(v, &value, name, errp);
675 if (error_is_set(errp)) {
676 return;
677 }
678 if (value < min || value > max) {
679 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
680 name ? name : "null", value, min, max);
681 return;
682 }
683
684 env->cpuid_version &= ~0xf00f0;
685 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
686 }
687
688 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
689 void *opaque, const char *name,
690 Error **errp)
691 {
692 X86CPU *cpu = X86_CPU(obj);
693 CPUX86State *env = &cpu->env;
694 int64_t value;
695
696 value = env->cpuid_version & 0xf;
697 visit_type_int(v, &value, name, errp);
698 }
699
700 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
701 void *opaque, const char *name,
702 Error **errp)
703 {
704 X86CPU *cpu = X86_CPU(obj);
705 CPUX86State *env = &cpu->env;
706 const int64_t min = 0;
707 const int64_t max = 0xf;
708 int64_t value;
709
710 visit_type_int(v, &value, name, errp);
711 if (error_is_set(errp)) {
712 return;
713 }
714 if (value < min || value > max) {
715 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
716 name ? name : "null", value, min, max);
717 return;
718 }
719
720 env->cpuid_version &= ~0xf;
721 env->cpuid_version |= value & 0xf;
722 }
723
724 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
725 const char *name, Error **errp)
726 {
727 X86CPU *cpu = X86_CPU(obj);
728
729 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
730 }
731
732 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
733 const char *name, Error **errp)
734 {
735 X86CPU *cpu = X86_CPU(obj);
736
737 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
738 }
739
740 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
741 const char *name, Error **errp)
742 {
743 X86CPU *cpu = X86_CPU(obj);
744
745 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
746 }
747
748 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
749 const char *name, Error **errp)
750 {
751 X86CPU *cpu = X86_CPU(obj);
752
753 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
754 }
755
756 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
757 {
758 X86CPU *cpu = X86_CPU(obj);
759 CPUX86State *env = &cpu->env;
760 char *value;
761 int i;
762
763 value = (char *)g_malloc(12 + 1);
764 for (i = 0; i < 4; i++) {
765 value[i ] = env->cpuid_vendor1 >> (8 * i);
766 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
767 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
768 }
769 value[12] = '\0';
770 return value;
771 }
772
773 static void x86_cpuid_set_vendor(Object *obj, const char *value,
774 Error **errp)
775 {
776 X86CPU *cpu = X86_CPU(obj);
777 CPUX86State *env = &cpu->env;
778 int i;
779
780 if (strlen(value) != 12) {
781 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
782 "vendor", value);
783 return;
784 }
785
786 env->cpuid_vendor1 = 0;
787 env->cpuid_vendor2 = 0;
788 env->cpuid_vendor3 = 0;
789 for (i = 0; i < 4; i++) {
790 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
791 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
792 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
793 }
794 env->cpuid_vendor_override = 1;
795 }
796
797 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
798 {
799 X86CPU *cpu = X86_CPU(obj);
800 CPUX86State *env = &cpu->env;
801 char *value;
802 int i;
803
804 value = g_malloc(48 + 1);
805 for (i = 0; i < 48; i++) {
806 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
807 }
808 value[48] = '\0';
809 return value;
810 }
811
812 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
813 Error **errp)
814 {
815 X86CPU *cpu = X86_CPU(obj);
816 CPUX86State *env = &cpu->env;
817 int c, len, i;
818
819 if (model_id == NULL) {
820 model_id = "";
821 }
822 len = strlen(model_id);
823 memset(env->cpuid_model, 0, 48);
824 for (i = 0; i < 48; i++) {
825 if (i >= len) {
826 c = '\0';
827 } else {
828 c = (uint8_t)model_id[i];
829 }
830 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
831 }
832 }
833
834 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
835 const char *name, Error **errp)
836 {
837 X86CPU *cpu = X86_CPU(obj);
838 int64_t value;
839
840 value = cpu->env.tsc_khz * 1000;
841 visit_type_int(v, &value, name, errp);
842 }
843
844 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
845 const char *name, Error **errp)
846 {
847 X86CPU *cpu = X86_CPU(obj);
848 const int64_t min = 0;
849 const int64_t max = INT_MAX;
850 int64_t value;
851
852 visit_type_int(v, &value, name, errp);
853 if (error_is_set(errp)) {
854 return;
855 }
856 if (value < min || value > max) {
857 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
858 name ? name : "null", value, min, max);
859 return;
860 }
861
862 cpu->env.tsc_khz = value / 1000;
863 }
864
865 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
866 {
867 unsigned int i;
868 x86_def_t *def;
869
870 char *s = g_strdup(cpu_model);
871 char *featurestr, *name = strtok(s, ",");
872 /* Features to be added*/
873 uint32_t plus_features = 0, plus_ext_features = 0;
874 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
875 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
876 /* Features to be removed */
877 uint32_t minus_features = 0, minus_ext_features = 0;
878 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
879 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
880 uint32_t numvalue;
881
882 for (def = x86_defs; def; def = def->next)
883 if (name && !strcmp(name, def->name))
884 break;
885 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
886 cpu_x86_fill_host(x86_cpu_def);
887 } else if (!def) {
888 goto error;
889 } else {
890 memcpy(x86_cpu_def, def, sizeof(*def));
891 }
892
893 #if defined(CONFIG_KVM)
894 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
895 (1 << KVM_FEATURE_NOP_IO_DELAY) |
896 (1 << KVM_FEATURE_MMU_OP) |
897 (1 << KVM_FEATURE_CLOCKSOURCE2) |
898 (1 << KVM_FEATURE_ASYNC_PF) |
899 (1 << KVM_FEATURE_STEAL_TIME) |
900 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
901 #else
902 plus_kvm_features = 0;
903 #endif
904
905 add_flagname_to_bitmaps("hypervisor", &plus_features,
906 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
907 &plus_kvm_features, &plus_svm_features);
908
909 featurestr = strtok(NULL, ",");
910
911 while (featurestr) {
912 char *val;
913 if (featurestr[0] == '+') {
914 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
915 &plus_ext_features, &plus_ext2_features,
916 &plus_ext3_features, &plus_kvm_features,
917 &plus_svm_features);
918 } else if (featurestr[0] == '-') {
919 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
920 &minus_ext_features, &minus_ext2_features,
921 &minus_ext3_features, &minus_kvm_features,
922 &minus_svm_features);
923 } else if ((val = strchr(featurestr, '='))) {
924 *val = 0; val++;
925 if (!strcmp(featurestr, "family")) {
926 char *err;
927 numvalue = strtoul(val, &err, 0);
928 if (!*val || *err || numvalue > 0xff + 0xf) {
929 fprintf(stderr, "bad numerical value %s\n", val);
930 goto error;
931 }
932 x86_cpu_def->family = numvalue;
933 } else if (!strcmp(featurestr, "model")) {
934 char *err;
935 numvalue = strtoul(val, &err, 0);
936 if (!*val || *err || numvalue > 0xff) {
937 fprintf(stderr, "bad numerical value %s\n", val);
938 goto error;
939 }
940 x86_cpu_def->model = numvalue;
941 } else if (!strcmp(featurestr, "stepping")) {
942 char *err;
943 numvalue = strtoul(val, &err, 0);
944 if (!*val || *err || numvalue > 0xf) {
945 fprintf(stderr, "bad numerical value %s\n", val);
946 goto error;
947 }
948 x86_cpu_def->stepping = numvalue ;
949 } else if (!strcmp(featurestr, "level")) {
950 char *err;
951 numvalue = strtoul(val, &err, 0);
952 if (!*val || *err) {
953 fprintf(stderr, "bad numerical value %s\n", val);
954 goto error;
955 }
956 x86_cpu_def->level = numvalue;
957 } else if (!strcmp(featurestr, "xlevel")) {
958 char *err;
959 numvalue = strtoul(val, &err, 0);
960 if (!*val || *err) {
961 fprintf(stderr, "bad numerical value %s\n", val);
962 goto error;
963 }
964 if (numvalue < 0x80000000) {
965 numvalue += 0x80000000;
966 }
967 x86_cpu_def->xlevel = numvalue;
968 } else if (!strcmp(featurestr, "vendor")) {
969 if (strlen(val) != 12) {
970 fprintf(stderr, "vendor string must be 12 chars long\n");
971 goto error;
972 }
973 x86_cpu_def->vendor1 = 0;
974 x86_cpu_def->vendor2 = 0;
975 x86_cpu_def->vendor3 = 0;
976 for(i = 0; i < 4; i++) {
977 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
978 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
979 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
980 }
981 x86_cpu_def->vendor_override = 1;
982 } else if (!strcmp(featurestr, "model_id")) {
983 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
984 val);
985 } else if (!strcmp(featurestr, "tsc_freq")) {
986 int64_t tsc_freq;
987 char *err;
988
989 tsc_freq = strtosz_suffix_unit(val, &err,
990 STRTOSZ_DEFSUFFIX_B, 1000);
991 if (tsc_freq < 0 || *err) {
992 fprintf(stderr, "bad numerical value %s\n", val);
993 goto error;
994 }
995 x86_cpu_def->tsc_khz = tsc_freq / 1000;
996 } else if (!strcmp(featurestr, "hv_spinlocks")) {
997 char *err;
998 numvalue = strtoul(val, &err, 0);
999 if (!*val || *err) {
1000 fprintf(stderr, "bad numerical value %s\n", val);
1001 goto error;
1002 }
1003 hyperv_set_spinlock_retries(numvalue);
1004 } else {
1005 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1006 goto error;
1007 }
1008 } else if (!strcmp(featurestr, "check")) {
1009 check_cpuid = 1;
1010 } else if (!strcmp(featurestr, "enforce")) {
1011 check_cpuid = enforce_cpuid = 1;
1012 } else if (!strcmp(featurestr, "hv_relaxed")) {
1013 hyperv_enable_relaxed_timing(true);
1014 } else if (!strcmp(featurestr, "hv_vapic")) {
1015 hyperv_enable_vapic_recommended(true);
1016 } else {
1017 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1018 goto error;
1019 }
1020 featurestr = strtok(NULL, ",");
1021 }
1022 x86_cpu_def->features |= plus_features;
1023 x86_cpu_def->ext_features |= plus_ext_features;
1024 x86_cpu_def->ext2_features |= plus_ext2_features;
1025 x86_cpu_def->ext3_features |= plus_ext3_features;
1026 x86_cpu_def->kvm_features |= plus_kvm_features;
1027 x86_cpu_def->svm_features |= plus_svm_features;
1028 x86_cpu_def->features &= ~minus_features;
1029 x86_cpu_def->ext_features &= ~minus_ext_features;
1030 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1031 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1032 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1033 x86_cpu_def->svm_features &= ~minus_svm_features;
1034 if (check_cpuid) {
1035 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1036 goto error;
1037 }
1038 g_free(s);
1039 return 0;
1040
1041 error:
1042 g_free(s);
1043 return -1;
1044 }
1045
1046 /* generate a composite string into buf of all cpuid names in featureset
1047 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1048 * if flags, suppress names undefined in featureset.
1049 */
1050 static void listflags(char *buf, int bufsize, uint32_t fbits,
1051 const char **featureset, uint32_t flags)
1052 {
1053 const char **p = &featureset[31];
1054 char *q, *b, bit;
1055 int nc;
1056
1057 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1058 *buf = '\0';
1059 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1060 if (fbits & 1 << bit && (*p || !flags)) {
1061 if (*p)
1062 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1063 else
1064 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1065 if (bufsize <= nc) {
1066 if (b) {
1067 memcpy(b, "...", sizeof("..."));
1068 }
1069 return;
1070 }
1071 q += nc;
1072 bufsize -= nc;
1073 }
1074 }
1075
1076 /* generate CPU information. */
1077 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1078 {
1079 x86_def_t *def;
1080 char buf[256];
1081
1082 for (def = x86_defs; def; def = def->next) {
1083 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
1084 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1085 }
1086 if (kvm_enabled()) {
1087 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1088 }
1089 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1090 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1091 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1092 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1093 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1094 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1095 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1096 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1097 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1098 }
1099
1100 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1101 {
1102 CpuDefinitionInfoList *cpu_list = NULL;
1103 x86_def_t *def;
1104
1105 for (def = x86_defs; def; def = def->next) {
1106 CpuDefinitionInfoList *entry;
1107 CpuDefinitionInfo *info;
1108
1109 info = g_malloc0(sizeof(*info));
1110 info->name = g_strdup(def->name);
1111
1112 entry = g_malloc0(sizeof(*entry));
1113 entry->value = info;
1114 entry->next = cpu_list;
1115 cpu_list = entry;
1116 }
1117
1118 return cpu_list;
1119 }
1120
1121 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1122 {
1123 CPUX86State *env = &cpu->env;
1124 x86_def_t def1, *def = &def1;
1125 Error *error = NULL;
1126
1127 memset(def, 0, sizeof(*def));
1128
1129 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1130 return -1;
1131 if (def->vendor1) {
1132 env->cpuid_vendor1 = def->vendor1;
1133 env->cpuid_vendor2 = def->vendor2;
1134 env->cpuid_vendor3 = def->vendor3;
1135 } else {
1136 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1137 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1138 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1139 }
1140 env->cpuid_vendor_override = def->vendor_override;
1141 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1142 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1143 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1144 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1145 env->cpuid_features = def->features;
1146 env->cpuid_ext_features = def->ext_features;
1147 env->cpuid_ext2_features = def->ext2_features;
1148 env->cpuid_ext3_features = def->ext3_features;
1149 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1150 env->cpuid_kvm_features = def->kvm_features;
1151 env->cpuid_svm_features = def->svm_features;
1152 env->cpuid_ext4_features = def->ext4_features;
1153 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
1154 env->cpuid_xlevel2 = def->xlevel2;
1155 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1156 "tsc-frequency", &error);
1157 if (!kvm_enabled()) {
1158 env->cpuid_features &= TCG_FEATURES;
1159 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1160 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1161 #ifdef TARGET_X86_64
1162 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1163 #endif
1164 );
1165 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1166 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1167 }
1168 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1169 if (error_is_set(&error)) {
1170 error_free(error);
1171 return -1;
1172 }
1173 return 0;
1174 }
1175
1176 #if !defined(CONFIG_USER_ONLY)
1177 /* copy vendor id string to 32 bit register, nul pad as needed
1178 */
1179 static void cpyid(const char *s, uint32_t *id)
1180 {
1181 char *d = (char *)id;
1182 char i;
1183
1184 for (i = sizeof (*id); i--; )
1185 *d++ = *s ? *s++ : '\0';
1186 }
1187
1188 /* interpret radix and convert from string to arbitrary scalar,
1189 * otherwise flag failure
1190 */
1191 #define setscalar(pval, str, perr) \
1192 { \
1193 char *pend; \
1194 unsigned long ul; \
1195 \
1196 ul = strtoul(str, &pend, 0); \
1197 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1198 }
1199
1200 /* map cpuid options to feature bits, otherwise return failure
1201 * (option tags in *str are delimited by whitespace)
1202 */
1203 static void setfeatures(uint32_t *pval, const char *str,
1204 const char **featureset, int *perr)
1205 {
1206 const char *p, *q;
1207
1208 for (q = p = str; *p || *q; q = p) {
1209 while (iswhite(*p))
1210 q = ++p;
1211 while (*p && !iswhite(*p))
1212 ++p;
1213 if (!*q && !*p)
1214 return;
1215 if (!lookup_feature(pval, q, p, featureset)) {
1216 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1217 (int)(p - q), q);
1218 *perr = 1;
1219 return;
1220 }
1221 }
1222 }
1223
1224 /* map config file options to x86_def_t form
1225 */
1226 static int cpudef_setfield(const char *name, const char *str, void *opaque)
1227 {
1228 x86_def_t *def = opaque;
1229 int err = 0;
1230
1231 if (!strcmp(name, "name")) {
1232 g_free((void *)def->name);
1233 def->name = g_strdup(str);
1234 } else if (!strcmp(name, "model_id")) {
1235 strncpy(def->model_id, str, sizeof (def->model_id));
1236 } else if (!strcmp(name, "level")) {
1237 setscalar(&def->level, str, &err)
1238 } else if (!strcmp(name, "vendor")) {
1239 cpyid(&str[0], &def->vendor1);
1240 cpyid(&str[4], &def->vendor2);
1241 cpyid(&str[8], &def->vendor3);
1242 } else if (!strcmp(name, "family")) {
1243 setscalar(&def->family, str, &err)
1244 } else if (!strcmp(name, "model")) {
1245 setscalar(&def->model, str, &err)
1246 } else if (!strcmp(name, "stepping")) {
1247 setscalar(&def->stepping, str, &err)
1248 } else if (!strcmp(name, "feature_edx")) {
1249 setfeatures(&def->features, str, feature_name, &err);
1250 } else if (!strcmp(name, "feature_ecx")) {
1251 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1252 } else if (!strcmp(name, "extfeature_edx")) {
1253 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1254 } else if (!strcmp(name, "extfeature_ecx")) {
1255 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1256 } else if (!strcmp(name, "xlevel")) {
1257 setscalar(&def->xlevel, str, &err)
1258 } else {
1259 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1260 return (1);
1261 }
1262 if (err) {
1263 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1264 return (1);
1265 }
1266 return (0);
1267 }
1268
1269 /* register config file entry as x86_def_t
1270 */
1271 static int cpudef_register(QemuOpts *opts, void *opaque)
1272 {
1273 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
1274
1275 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1276 def->next = x86_defs;
1277 x86_defs = def;
1278 return (0);
1279 }
1280
1281 void cpu_clear_apic_feature(CPUX86State *env)
1282 {
1283 env->cpuid_features &= ~CPUID_APIC;
1284 }
1285
1286 #endif /* !CONFIG_USER_ONLY */
1287
1288 /* register "cpudef" models defined in configuration file. Here we first
1289 * preload any built-in definitions
1290 */
1291 void x86_cpudef_setup(void)
1292 {
1293 int i, j;
1294 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1295
1296 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1297 builtin_x86_defs[i].next = x86_defs;
1298 builtin_x86_defs[i].flags = 1;
1299
1300 /* Look for specific "cpudef" models that */
1301 /* have the QEMU version in .model_id */
1302 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1303 if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
1304 pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
1305 pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
1306 break;
1307 }
1308 }
1309
1310 x86_defs = &builtin_x86_defs[i];
1311 }
1312 #if !defined(CONFIG_USER_ONLY)
1313 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
1314 #endif
1315 }
1316
1317 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1318 uint32_t *ecx, uint32_t *edx)
1319 {
1320 *ebx = env->cpuid_vendor1;
1321 *edx = env->cpuid_vendor2;
1322 *ecx = env->cpuid_vendor3;
1323
1324 /* sysenter isn't supported on compatibility mode on AMD, syscall
1325 * isn't supported in compatibility mode on Intel.
1326 * Normally we advertise the actual cpu vendor, but you can override
1327 * this if you want to use KVM's sysenter/syscall emulation
1328 * in compatibility mode and when doing cross vendor migration
1329 */
1330 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1331 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1332 }
1333 }
1334
1335 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1336 uint32_t *eax, uint32_t *ebx,
1337 uint32_t *ecx, uint32_t *edx)
1338 {
1339 /* test if maximum index reached */
1340 if (index & 0x80000000) {
1341 if (index > env->cpuid_xlevel) {
1342 if (env->cpuid_xlevel2 > 0) {
1343 /* Handle the Centaur's CPUID instruction. */
1344 if (index > env->cpuid_xlevel2) {
1345 index = env->cpuid_xlevel2;
1346 } else if (index < 0xC0000000) {
1347 index = env->cpuid_xlevel;
1348 }
1349 } else {
1350 index = env->cpuid_xlevel;
1351 }
1352 }
1353 } else {
1354 if (index > env->cpuid_level)
1355 index = env->cpuid_level;
1356 }
1357
1358 switch(index) {
1359 case 0:
1360 *eax = env->cpuid_level;
1361 get_cpuid_vendor(env, ebx, ecx, edx);
1362 break;
1363 case 1:
1364 *eax = env->cpuid_version;
1365 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1366 *ecx = env->cpuid_ext_features;
1367 *edx = env->cpuid_features;
1368 if (env->nr_cores * env->nr_threads > 1) {
1369 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1370 *edx |= 1 << 28; /* HTT bit */
1371 }
1372 break;
1373 case 2:
1374 /* cache info: needed for Pentium Pro compatibility */
1375 *eax = 1;
1376 *ebx = 0;
1377 *ecx = 0;
1378 *edx = 0x2c307d;
1379 break;
1380 case 4:
1381 /* cache info: needed for Core compatibility */
1382 if (env->nr_cores > 1) {
1383 *eax = (env->nr_cores - 1) << 26;
1384 } else {
1385 *eax = 0;
1386 }
1387 switch (count) {
1388 case 0: /* L1 dcache info */
1389 *eax |= 0x0000121;
1390 *ebx = 0x1c0003f;
1391 *ecx = 0x000003f;
1392 *edx = 0x0000001;
1393 break;
1394 case 1: /* L1 icache info */
1395 *eax |= 0x0000122;
1396 *ebx = 0x1c0003f;
1397 *ecx = 0x000003f;
1398 *edx = 0x0000001;
1399 break;
1400 case 2: /* L2 cache info */
1401 *eax |= 0x0000143;
1402 if (env->nr_threads > 1) {
1403 *eax |= (env->nr_threads - 1) << 14;
1404 }
1405 *ebx = 0x3c0003f;
1406 *ecx = 0x0000fff;
1407 *edx = 0x0000001;
1408 break;
1409 default: /* end of info */
1410 *eax = 0;
1411 *ebx = 0;
1412 *ecx = 0;
1413 *edx = 0;
1414 break;
1415 }
1416 break;
1417 case 5:
1418 /* mwait info: needed for Core compatibility */
1419 *eax = 0; /* Smallest monitor-line size in bytes */
1420 *ebx = 0; /* Largest monitor-line size in bytes */
1421 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1422 *edx = 0;
1423 break;
1424 case 6:
1425 /* Thermal and Power Leaf */
1426 *eax = 0;
1427 *ebx = 0;
1428 *ecx = 0;
1429 *edx = 0;
1430 break;
1431 case 7:
1432 /* Structured Extended Feature Flags Enumeration Leaf */
1433 if (count == 0) {
1434 *eax = 0; /* Maximum ECX value for sub-leaves */
1435 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1436 *ecx = 0; /* Reserved */
1437 *edx = 0; /* Reserved */
1438 } else {
1439 *eax = 0;
1440 *ebx = 0;
1441 *ecx = 0;
1442 *edx = 0;
1443 }
1444 break;
1445 case 9:
1446 /* Direct Cache Access Information Leaf */
1447 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1448 *ebx = 0;
1449 *ecx = 0;
1450 *edx = 0;
1451 break;
1452 case 0xA:
1453 /* Architectural Performance Monitoring Leaf */
1454 if (kvm_enabled()) {
1455 KVMState *s = env->kvm_state;
1456
1457 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1458 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1459 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1460 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1461 } else {
1462 *eax = 0;
1463 *ebx = 0;
1464 *ecx = 0;
1465 *edx = 0;
1466 }
1467 break;
1468 case 0xD:
1469 /* Processor Extended State */
1470 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1471 *eax = 0;
1472 *ebx = 0;
1473 *ecx = 0;
1474 *edx = 0;
1475 break;
1476 }
1477 if (kvm_enabled()) {
1478 KVMState *s = env->kvm_state;
1479
1480 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1481 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1482 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1483 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1484 } else {
1485 *eax = 0;
1486 *ebx = 0;
1487 *ecx = 0;
1488 *edx = 0;
1489 }
1490 break;
1491 case 0x80000000:
1492 *eax = env->cpuid_xlevel;
1493 *ebx = env->cpuid_vendor1;
1494 *edx = env->cpuid_vendor2;
1495 *ecx = env->cpuid_vendor3;
1496 break;
1497 case 0x80000001:
1498 *eax = env->cpuid_version;
1499 *ebx = 0;
1500 *ecx = env->cpuid_ext3_features;
1501 *edx = env->cpuid_ext2_features;
1502
1503 /* The Linux kernel checks for the CMPLegacy bit and
1504 * discards multiple thread information if it is set.
1505 * So dont set it here for Intel to make Linux guests happy.
1506 */
1507 if (env->nr_cores * env->nr_threads > 1) {
1508 uint32_t tebx, tecx, tedx;
1509 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1510 if (tebx != CPUID_VENDOR_INTEL_1 ||
1511 tedx != CPUID_VENDOR_INTEL_2 ||
1512 tecx != CPUID_VENDOR_INTEL_3) {
1513 *ecx |= 1 << 1; /* CmpLegacy bit */
1514 }
1515 }
1516 break;
1517 case 0x80000002:
1518 case 0x80000003:
1519 case 0x80000004:
1520 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1521 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1522 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1523 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1524 break;
1525 case 0x80000005:
1526 /* cache info (L1 cache) */
1527 *eax = 0x01ff01ff;
1528 *ebx = 0x01ff01ff;
1529 *ecx = 0x40020140;
1530 *edx = 0x40020140;
1531 break;
1532 case 0x80000006:
1533 /* cache info (L2 cache) */
1534 *eax = 0;
1535 *ebx = 0x42004200;
1536 *ecx = 0x02008140;
1537 *edx = 0;
1538 break;
1539 case 0x80000008:
1540 /* virtual & phys address size in low 2 bytes. */
1541 /* XXX: This value must match the one used in the MMU code. */
1542 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1543 /* 64 bit processor */
1544 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1545 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1546 } else {
1547 if (env->cpuid_features & CPUID_PSE36)
1548 *eax = 0x00000024; /* 36 bits physical */
1549 else
1550 *eax = 0x00000020; /* 32 bits physical */
1551 }
1552 *ebx = 0;
1553 *ecx = 0;
1554 *edx = 0;
1555 if (env->nr_cores * env->nr_threads > 1) {
1556 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1557 }
1558 break;
1559 case 0x8000000A:
1560 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1561 *eax = 0x00000001; /* SVM Revision */
1562 *ebx = 0x00000010; /* nr of ASIDs */
1563 *ecx = 0;
1564 *edx = env->cpuid_svm_features; /* optional features */
1565 } else {
1566 *eax = 0;
1567 *ebx = 0;
1568 *ecx = 0;
1569 *edx = 0;
1570 }
1571 break;
1572 case 0xC0000000:
1573 *eax = env->cpuid_xlevel2;
1574 *ebx = 0;
1575 *ecx = 0;
1576 *edx = 0;
1577 break;
1578 case 0xC0000001:
1579 /* Support for VIA CPU's CPUID instruction */
1580 *eax = env->cpuid_version;
1581 *ebx = 0;
1582 *ecx = 0;
1583 *edx = env->cpuid_ext4_features;
1584 break;
1585 case 0xC0000002:
1586 case 0xC0000003:
1587 case 0xC0000004:
1588 /* Reserved for the future, and now filled with zero */
1589 *eax = 0;
1590 *ebx = 0;
1591 *ecx = 0;
1592 *edx = 0;
1593 break;
1594 default:
1595 /* reserved values: zero */
1596 *eax = 0;
1597 *ebx = 0;
1598 *ecx = 0;
1599 *edx = 0;
1600 break;
1601 }
1602 }
1603
1604 /* CPUClass::reset() */
1605 static void x86_cpu_reset(CPUState *s)
1606 {
1607 X86CPU *cpu = X86_CPU(s);
1608 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1609 CPUX86State *env = &cpu->env;
1610 int i;
1611
1612 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1613 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1614 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1615 }
1616
1617 xcc->parent_reset(s);
1618
1619
1620 memset(env, 0, offsetof(CPUX86State, breakpoints));
1621
1622 tlb_flush(env, 1);
1623
1624 env->old_exception = -1;
1625
1626 /* init to reset state */
1627
1628 #ifdef CONFIG_SOFTMMU
1629 env->hflags |= HF_SOFTMMU_MASK;
1630 #endif
1631 env->hflags2 |= HF2_GIF_MASK;
1632
1633 cpu_x86_update_cr0(env, 0x60000010);
1634 env->a20_mask = ~0x0;
1635 env->smbase = 0x30000;
1636
1637 env->idt.limit = 0xffff;
1638 env->gdt.limit = 0xffff;
1639 env->ldt.limit = 0xffff;
1640 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1641 env->tr.limit = 0xffff;
1642 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1643
1644 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1645 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1646 DESC_R_MASK | DESC_A_MASK);
1647 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1648 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1649 DESC_A_MASK);
1650 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1651 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1652 DESC_A_MASK);
1653 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1654 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1655 DESC_A_MASK);
1656 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1657 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1658 DESC_A_MASK);
1659 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1660 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1661 DESC_A_MASK);
1662
1663 env->eip = 0xfff0;
1664 env->regs[R_EDX] = env->cpuid_version;
1665
1666 env->eflags = 0x2;
1667
1668 /* FPU init */
1669 for (i = 0; i < 8; i++) {
1670 env->fptags[i] = 1;
1671 }
1672 env->fpuc = 0x37f;
1673
1674 env->mxcsr = 0x1f80;
1675
1676 env->pat = 0x0007040600070406ULL;
1677 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1678
1679 memset(env->dr, 0, sizeof(env->dr));
1680 env->dr[6] = DR6_FIXED_1;
1681 env->dr[7] = DR7_FIXED_1;
1682 cpu_breakpoint_remove_all(env, BP_CPU);
1683 cpu_watchpoint_remove_all(env, BP_CPU);
1684
1685 #if !defined(CONFIG_USER_ONLY)
1686 /* We hard-wire the BSP to the first CPU. */
1687 if (env->cpu_index == 0) {
1688 apic_designate_bsp(env->apic_state);
1689 }
1690
1691 env->halted = !cpu_is_bsp(cpu);
1692 #endif
1693 }
1694
1695 #ifndef CONFIG_USER_ONLY
1696 bool cpu_is_bsp(X86CPU *cpu)
1697 {
1698 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1699 }
1700
1701 /* TODO: remove me, when reset over QOM tree is implemented */
1702 static void x86_cpu_machine_reset_cb(void *opaque)
1703 {
1704 X86CPU *cpu = opaque;
1705 cpu_reset(CPU(cpu));
1706 }
1707 #endif
1708
1709 static void mce_init(X86CPU *cpu)
1710 {
1711 CPUX86State *cenv = &cpu->env;
1712 unsigned int bank;
1713
1714 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1715 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1716 (CPUID_MCE | CPUID_MCA)) {
1717 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1718 cenv->mcg_ctl = ~(uint64_t)0;
1719 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1720 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1721 }
1722 }
1723 }
1724
1725 void x86_cpu_realize(Object *obj, Error **errp)
1726 {
1727 X86CPU *cpu = X86_CPU(obj);
1728
1729 #ifndef CONFIG_USER_ONLY
1730 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1731 #endif
1732
1733 mce_init(cpu);
1734 qemu_init_vcpu(&cpu->env);
1735 cpu_reset(CPU(cpu));
1736 }
1737
1738 static void x86_cpu_initfn(Object *obj)
1739 {
1740 X86CPU *cpu = X86_CPU(obj);
1741 CPUX86State *env = &cpu->env;
1742 static int inited;
1743
1744 cpu_exec_init(env);
1745
1746 object_property_add(obj, "family", "int",
1747 x86_cpuid_version_get_family,
1748 x86_cpuid_version_set_family, NULL, NULL, NULL);
1749 object_property_add(obj, "model", "int",
1750 x86_cpuid_version_get_model,
1751 x86_cpuid_version_set_model, NULL, NULL, NULL);
1752 object_property_add(obj, "stepping", "int",
1753 x86_cpuid_version_get_stepping,
1754 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
1755 object_property_add(obj, "level", "int",
1756 x86_cpuid_get_level,
1757 x86_cpuid_set_level, NULL, NULL, NULL);
1758 object_property_add(obj, "xlevel", "int",
1759 x86_cpuid_get_xlevel,
1760 x86_cpuid_set_xlevel, NULL, NULL, NULL);
1761 object_property_add_str(obj, "vendor",
1762 x86_cpuid_get_vendor,
1763 x86_cpuid_set_vendor, NULL);
1764 object_property_add_str(obj, "model-id",
1765 x86_cpuid_get_model_id,
1766 x86_cpuid_set_model_id, NULL);
1767 object_property_add(obj, "tsc-frequency", "int",
1768 x86_cpuid_get_tsc_freq,
1769 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
1770
1771 env->cpuid_apic_id = env->cpu_index;
1772
1773 /* init various static tables used in TCG mode */
1774 if (tcg_enabled() && !inited) {
1775 inited = 1;
1776 optimize_flags_init();
1777 #ifndef CONFIG_USER_ONLY
1778 cpu_set_debug_excp_handler(breakpoint_handler);
1779 #endif
1780 }
1781 }
1782
1783 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1784 {
1785 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1786 CPUClass *cc = CPU_CLASS(oc);
1787
1788 xcc->parent_reset = cc->reset;
1789 cc->reset = x86_cpu_reset;
1790 }
1791
1792 static const TypeInfo x86_cpu_type_info = {
1793 .name = TYPE_X86_CPU,
1794 .parent = TYPE_CPU,
1795 .instance_size = sizeof(X86CPU),
1796 .instance_init = x86_cpu_initfn,
1797 .abstract = false,
1798 .class_size = sizeof(X86CPUClass),
1799 .class_init = x86_cpu_common_class_init,
1800 };
1801
1802 static void x86_cpu_register_types(void)
1803 {
1804 type_register_static(&x86_cpu_type_info);
1805 }
1806
1807 type_init(x86_cpu_register_types)
Qemu copy for testing