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target-i386: Pass X86CPU object to cpu_x86_find_by_name()
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hyperv.h"
39
40 #include "hw/hw.h"
41 #if defined(CONFIG_KVM)
42 #include <linux/kvm_para.h>
43 #endif
44
45 #include "sysemu/sysemu.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/cpu/icc_bus.h"
48 #ifndef CONFIG_USER_ONLY
49 #include "hw/xen/xen.h"
50 #include "hw/i386/apic_internal.h"
51 #endif
52
53 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
54 uint32_t vendor2, uint32_t vendor3)
55 {
56 int i;
57 for (i = 0; i < 4; i++) {
58 dst[i] = vendor1 >> (8 * i);
59 dst[i + 4] = vendor2 >> (8 * i);
60 dst[i + 8] = vendor3 >> (8 * i);
61 }
62 dst[CPUID_VENDOR_SZ] = '\0';
63 }
64
65 /* feature flags taken from "Intel Processor Identification and the CPUID
66 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
67 * between feature naming conventions, aliases may be added.
68 */
69 static const char *feature_name[] = {
70 "fpu", "vme", "de", "pse",
71 "tsc", "msr", "pae", "mce",
72 "cx8", "apic", NULL, "sep",
73 "mtrr", "pge", "mca", "cmov",
74 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
75 NULL, "ds" /* Intel dts */, "acpi", "mmx",
76 "fxsr", "sse", "sse2", "ss",
77 "ht" /* Intel htt */, "tm", "ia64", "pbe",
78 };
79 static const char *ext_feature_name[] = {
80 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
81 "ds_cpl", "vmx", "smx", "est",
82 "tm2", "ssse3", "cid", NULL,
83 "fma", "cx16", "xtpr", "pdcm",
84 NULL, "pcid", "dca", "sse4.1|sse4_1",
85 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
86 "tsc-deadline", "aes", "xsave", "osxsave",
87 "avx", "f16c", "rdrand", "hypervisor",
88 };
89 /* Feature names that are already defined on feature_name[] but are set on
90 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
91 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
92 * if and only if CPU vendor is AMD.
93 */
94 static const char *ext2_feature_name[] = {
95 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
96 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
97 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
98 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
99 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
100 "nx|xd", NULL, "mmxext", NULL /* mmx */,
101 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
102 NULL, "lm|i64", "3dnowext", "3dnow",
103 };
104 static const char *ext3_feature_name[] = {
105 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
106 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
107 "3dnowprefetch", "osvw", "ibs", "xop",
108 "skinit", "wdt", NULL, "lwp",
109 "fma4", "tce", NULL, "nodeid_msr",
110 NULL, "tbm", "topoext", "perfctr_core",
111 "perfctr_nb", NULL, NULL, NULL,
112 NULL, NULL, NULL, NULL,
113 };
114
115 static const char *ext4_feature_name[] = {
116 NULL, NULL, "xstore", "xstore-en",
117 NULL, NULL, "xcrypt", "xcrypt-en",
118 "ace2", "ace2-en", "phe", "phe-en",
119 "pmm", "pmm-en", NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 NULL, NULL, NULL, NULL,
122 NULL, NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL,
124 };
125
126 static const char *kvm_feature_name[] = {
127 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
128 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 NULL, NULL, NULL, NULL,
133 NULL, NULL, NULL, NULL,
134 NULL, NULL, NULL, NULL,
135 };
136
137 static const char *svm_feature_name[] = {
138 "npt", "lbrv", "svm_lock", "nrip_save",
139 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
140 NULL, NULL, "pause_filter", NULL,
141 "pfthreshold", NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 NULL, NULL, NULL, NULL,
144 NULL, NULL, NULL, NULL,
145 NULL, NULL, NULL, NULL,
146 };
147
148 static const char *cpuid_7_0_ebx_feature_name[] = {
149 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
150 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
151 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
152 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
153 };
154
155 typedef struct FeatureWordInfo {
156 const char **feat_names;
157 uint32_t cpuid_eax; /* Input EAX for CPUID */
158 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
159 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
160 int cpuid_reg; /* output register (R_* constant) */
161 } FeatureWordInfo;
162
163 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
164 [FEAT_1_EDX] = {
165 .feat_names = feature_name,
166 .cpuid_eax = 1, .cpuid_reg = R_EDX,
167 },
168 [FEAT_1_ECX] = {
169 .feat_names = ext_feature_name,
170 .cpuid_eax = 1, .cpuid_reg = R_ECX,
171 },
172 [FEAT_8000_0001_EDX] = {
173 .feat_names = ext2_feature_name,
174 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
175 },
176 [FEAT_8000_0001_ECX] = {
177 .feat_names = ext3_feature_name,
178 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
179 },
180 [FEAT_C000_0001_EDX] = {
181 .feat_names = ext4_feature_name,
182 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
183 },
184 [FEAT_KVM] = {
185 .feat_names = kvm_feature_name,
186 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
187 },
188 [FEAT_SVM] = {
189 .feat_names = svm_feature_name,
190 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
191 },
192 [FEAT_7_0_EBX] = {
193 .feat_names = cpuid_7_0_ebx_feature_name,
194 .cpuid_eax = 7,
195 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
196 .cpuid_reg = R_EBX,
197 },
198 };
199
200 typedef struct X86RegisterInfo32 {
201 /* Name of register */
202 const char *name;
203 /* QAPI enum value register */
204 X86CPURegister32 qapi_enum;
205 } X86RegisterInfo32;
206
207 #define REGISTER(reg) \
208 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
209 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
210 REGISTER(EAX),
211 REGISTER(ECX),
212 REGISTER(EDX),
213 REGISTER(EBX),
214 REGISTER(ESP),
215 REGISTER(EBP),
216 REGISTER(ESI),
217 REGISTER(EDI),
218 };
219 #undef REGISTER
220
221
222 const char *get_register_name_32(unsigned int reg)
223 {
224 if (reg >= CPU_NB_REGS32) {
225 return NULL;
226 }
227 return x86_reg_info_32[reg].name;
228 }
229
230 /* collects per-function cpuid data
231 */
232 typedef struct model_features_t {
233 uint32_t *guest_feat;
234 uint32_t *host_feat;
235 FeatureWord feat_word;
236 } model_features_t;
237
238 int check_cpuid = 0;
239 int enforce_cpuid = 0;
240
241 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
242 (1 << KVM_FEATURE_NOP_IO_DELAY) |
243 (1 << KVM_FEATURE_CLOCKSOURCE2) |
244 (1 << KVM_FEATURE_ASYNC_PF) |
245 (1 << KVM_FEATURE_STEAL_TIME) |
246 (1 << KVM_FEATURE_PV_EOI) |
247 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
248
249 void disable_kvm_pv_eoi(void)
250 {
251 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
252 }
253
254 void host_cpuid(uint32_t function, uint32_t count,
255 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
256 {
257 #if defined(CONFIG_KVM)
258 uint32_t vec[4];
259
260 #ifdef __x86_64__
261 asm volatile("cpuid"
262 : "=a"(vec[0]), "=b"(vec[1]),
263 "=c"(vec[2]), "=d"(vec[3])
264 : "0"(function), "c"(count) : "cc");
265 #else
266 asm volatile("pusha \n\t"
267 "cpuid \n\t"
268 "mov %%eax, 0(%2) \n\t"
269 "mov %%ebx, 4(%2) \n\t"
270 "mov %%ecx, 8(%2) \n\t"
271 "mov %%edx, 12(%2) \n\t"
272 "popa"
273 : : "a"(function), "c"(count), "S"(vec)
274 : "memory", "cc");
275 #endif
276
277 if (eax)
278 *eax = vec[0];
279 if (ebx)
280 *ebx = vec[1];
281 if (ecx)
282 *ecx = vec[2];
283 if (edx)
284 *edx = vec[3];
285 #endif
286 }
287
288 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
289
290 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
291 * a substring. ex if !NULL points to the first char after a substring,
292 * otherwise the string is assumed to sized by a terminating nul.
293 * Return lexical ordering of *s1:*s2.
294 */
295 static int sstrcmp(const char *s1, const char *e1, const char *s2,
296 const char *e2)
297 {
298 for (;;) {
299 if (!*s1 || !*s2 || *s1 != *s2)
300 return (*s1 - *s2);
301 ++s1, ++s2;
302 if (s1 == e1 && s2 == e2)
303 return (0);
304 else if (s1 == e1)
305 return (*s2);
306 else if (s2 == e2)
307 return (*s1);
308 }
309 }
310
311 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
312 * '|' delimited (possibly empty) strings in which case search for a match
313 * within the alternatives proceeds left to right. Return 0 for success,
314 * non-zero otherwise.
315 */
316 static int altcmp(const char *s, const char *e, const char *altstr)
317 {
318 const char *p, *q;
319
320 for (q = p = altstr; ; ) {
321 while (*p && *p != '|')
322 ++p;
323 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
324 return (0);
325 if (!*p)
326 return (1);
327 else
328 q = ++p;
329 }
330 }
331
332 /* search featureset for flag *[s..e), if found set corresponding bit in
333 * *pval and return true, otherwise return false
334 */
335 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
336 const char **featureset)
337 {
338 uint32_t mask;
339 const char **ppc;
340 bool found = false;
341
342 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
343 if (*ppc && !altcmp(s, e, *ppc)) {
344 *pval |= mask;
345 found = true;
346 }
347 }
348 return found;
349 }
350
351 static void add_flagname_to_bitmaps(const char *flagname,
352 FeatureWordArray words)
353 {
354 FeatureWord w;
355 for (w = 0; w < FEATURE_WORDS; w++) {
356 FeatureWordInfo *wi = &feature_word_info[w];
357 if (wi->feat_names &&
358 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
359 break;
360 }
361 }
362 if (w == FEATURE_WORDS) {
363 fprintf(stderr, "CPU feature %s not found\n", flagname);
364 }
365 }
366
367 typedef struct x86_def_t {
368 const char *name;
369 uint32_t level;
370 uint32_t xlevel;
371 uint32_t xlevel2;
372 /* vendor is zero-terminated, 12 character ASCII string */
373 char vendor[CPUID_VENDOR_SZ + 1];
374 int family;
375 int model;
376 int stepping;
377 FeatureWordArray features;
378 char model_id[48];
379 } x86_def_t;
380
381 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
382 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
383 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
384 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
385 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
386 CPUID_PSE36 | CPUID_FXSR)
387 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
388 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
389 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
390 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
391 CPUID_PAE | CPUID_SEP | CPUID_APIC)
392
393 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
394 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
395 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
396 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
397 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
398 /* partly implemented:
399 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
400 CPUID_PSE36 (needed for Solaris) */
401 /* missing:
402 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
403 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
404 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
405 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
406 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
407 /* missing:
408 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
409 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
410 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
411 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
412 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
413 CPUID_EXT_RDRAND */
414 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
415 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
416 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
417 /* missing:
418 CPUID_EXT2_PDPE1GB */
419 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
420 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
421 #define TCG_SVM_FEATURES 0
422 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
423 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
424 /* missing:
425 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
426 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
427 CPUID_7_0_EBX_RDSEED */
428
429 /* built-in CPU model definitions
430 */
431 static x86_def_t builtin_x86_defs[] = {
432 {
433 .name = "qemu64",
434 .level = 4,
435 .vendor = CPUID_VENDOR_AMD,
436 .family = 6,
437 .model = 2,
438 .stepping = 3,
439 .features[FEAT_1_EDX] =
440 PPRO_FEATURES |
441 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
442 CPUID_PSE36,
443 .features[FEAT_1_ECX] =
444 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
445 .features[FEAT_8000_0001_EDX] =
446 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
447 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
448 .features[FEAT_8000_0001_ECX] =
449 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
450 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
451 .xlevel = 0x8000000A,
452 },
453 {
454 .name = "phenom",
455 .level = 5,
456 .vendor = CPUID_VENDOR_AMD,
457 .family = 16,
458 .model = 2,
459 .stepping = 3,
460 .features[FEAT_1_EDX] =
461 PPRO_FEATURES |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
463 CPUID_PSE36 | CPUID_VME | CPUID_HT,
464 .features[FEAT_1_ECX] =
465 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
466 CPUID_EXT_POPCNT,
467 .features[FEAT_8000_0001_EDX] =
468 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
469 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
470 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
471 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
472 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
473 CPUID_EXT3_CR8LEG,
474 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
475 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
476 .features[FEAT_8000_0001_ECX] =
477 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
478 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
479 .features[FEAT_SVM] =
480 CPUID_SVM_NPT | CPUID_SVM_LBRV,
481 .xlevel = 0x8000001A,
482 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
483 },
484 {
485 .name = "core2duo",
486 .level = 10,
487 .vendor = CPUID_VENDOR_INTEL,
488 .family = 6,
489 .model = 15,
490 .stepping = 11,
491 .features[FEAT_1_EDX] =
492 PPRO_FEATURES |
493 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
494 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
495 CPUID_HT | CPUID_TM | CPUID_PBE,
496 .features[FEAT_1_ECX] =
497 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
498 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
499 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
500 .features[FEAT_8000_0001_EDX] =
501 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
502 .features[FEAT_8000_0001_ECX] =
503 CPUID_EXT3_LAHF_LM,
504 .xlevel = 0x80000008,
505 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
506 },
507 {
508 .name = "kvm64",
509 .level = 5,
510 .vendor = CPUID_VENDOR_INTEL,
511 .family = 15,
512 .model = 6,
513 .stepping = 1,
514 /* Missing: CPUID_VME, CPUID_HT */
515 .features[FEAT_1_EDX] =
516 PPRO_FEATURES |
517 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
518 CPUID_PSE36,
519 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
520 .features[FEAT_1_ECX] =
521 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
522 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
523 .features[FEAT_8000_0001_EDX] =
524 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
525 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
526 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
527 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
528 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
529 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
530 .features[FEAT_8000_0001_ECX] =
531 0,
532 .xlevel = 0x80000008,
533 .model_id = "Common KVM processor"
534 },
535 {
536 .name = "qemu32",
537 .level = 4,
538 .vendor = CPUID_VENDOR_INTEL,
539 .family = 6,
540 .model = 3,
541 .stepping = 3,
542 .features[FEAT_1_EDX] =
543 PPRO_FEATURES,
544 .features[FEAT_1_ECX] =
545 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
546 .xlevel = 0x80000004,
547 },
548 {
549 .name = "kvm32",
550 .level = 5,
551 .vendor = CPUID_VENDOR_INTEL,
552 .family = 15,
553 .model = 6,
554 .stepping = 1,
555 .features[FEAT_1_EDX] =
556 PPRO_FEATURES |
557 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
558 .features[FEAT_1_ECX] =
559 CPUID_EXT_SSE3,
560 .features[FEAT_8000_0001_EDX] =
561 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
562 .features[FEAT_8000_0001_ECX] =
563 0,
564 .xlevel = 0x80000008,
565 .model_id = "Common 32-bit KVM processor"
566 },
567 {
568 .name = "coreduo",
569 .level = 10,
570 .vendor = CPUID_VENDOR_INTEL,
571 .family = 6,
572 .model = 14,
573 .stepping = 8,
574 .features[FEAT_1_EDX] =
575 PPRO_FEATURES | CPUID_VME |
576 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
577 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
578 .features[FEAT_1_ECX] =
579 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
580 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
581 .features[FEAT_8000_0001_EDX] =
582 CPUID_EXT2_NX,
583 .xlevel = 0x80000008,
584 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
585 },
586 {
587 .name = "486",
588 .level = 1,
589 .vendor = CPUID_VENDOR_INTEL,
590 .family = 4,
591 .model = 8,
592 .stepping = 0,
593 .features[FEAT_1_EDX] =
594 I486_FEATURES,
595 .xlevel = 0,
596 },
597 {
598 .name = "pentium",
599 .level = 1,
600 .vendor = CPUID_VENDOR_INTEL,
601 .family = 5,
602 .model = 4,
603 .stepping = 3,
604 .features[FEAT_1_EDX] =
605 PENTIUM_FEATURES,
606 .xlevel = 0,
607 },
608 {
609 .name = "pentium2",
610 .level = 2,
611 .vendor = CPUID_VENDOR_INTEL,
612 .family = 6,
613 .model = 5,
614 .stepping = 2,
615 .features[FEAT_1_EDX] =
616 PENTIUM2_FEATURES,
617 .xlevel = 0,
618 },
619 {
620 .name = "pentium3",
621 .level = 2,
622 .vendor = CPUID_VENDOR_INTEL,
623 .family = 6,
624 .model = 7,
625 .stepping = 3,
626 .features[FEAT_1_EDX] =
627 PENTIUM3_FEATURES,
628 .xlevel = 0,
629 },
630 {
631 .name = "athlon",
632 .level = 2,
633 .vendor = CPUID_VENDOR_AMD,
634 .family = 6,
635 .model = 2,
636 .stepping = 3,
637 .features[FEAT_1_EDX] =
638 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
639 CPUID_MCA,
640 .features[FEAT_8000_0001_EDX] =
641 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
642 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
643 .xlevel = 0x80000008,
644 },
645 {
646 .name = "n270",
647 /* original is on level 10 */
648 .level = 5,
649 .vendor = CPUID_VENDOR_INTEL,
650 .family = 6,
651 .model = 28,
652 .stepping = 2,
653 .features[FEAT_1_EDX] =
654 PPRO_FEATURES |
655 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
656 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
657 /* Some CPUs got no CPUID_SEP */
658 .features[FEAT_1_ECX] =
659 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
660 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
661 CPUID_EXT_MOVBE,
662 .features[FEAT_8000_0001_EDX] =
663 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
664 CPUID_EXT2_NX,
665 .features[FEAT_8000_0001_ECX] =
666 CPUID_EXT3_LAHF_LM,
667 .xlevel = 0x8000000A,
668 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
669 },
670 {
671 .name = "Conroe",
672 .level = 4,
673 .vendor = CPUID_VENDOR_INTEL,
674 .family = 6,
675 .model = 15,
676 .stepping = 3,
677 .features[FEAT_1_EDX] =
678 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
682 CPUID_DE | CPUID_FP87,
683 .features[FEAT_1_ECX] =
684 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
685 .features[FEAT_8000_0001_EDX] =
686 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
687 .features[FEAT_8000_0001_ECX] =
688 CPUID_EXT3_LAHF_LM,
689 .xlevel = 0x8000000A,
690 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
691 },
692 {
693 .name = "Penryn",
694 .level = 4,
695 .vendor = CPUID_VENDOR_INTEL,
696 .family = 6,
697 .model = 23,
698 .stepping = 3,
699 .features[FEAT_1_EDX] =
700 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
701 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
702 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
703 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
704 CPUID_DE | CPUID_FP87,
705 .features[FEAT_1_ECX] =
706 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
707 CPUID_EXT_SSE3,
708 .features[FEAT_8000_0001_EDX] =
709 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
710 .features[FEAT_8000_0001_ECX] =
711 CPUID_EXT3_LAHF_LM,
712 .xlevel = 0x8000000A,
713 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
714 },
715 {
716 .name = "Nehalem",
717 .level = 4,
718 .vendor = CPUID_VENDOR_INTEL,
719 .family = 6,
720 .model = 26,
721 .stepping = 3,
722 .features[FEAT_1_EDX] =
723 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
724 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
725 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
726 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
727 CPUID_DE | CPUID_FP87,
728 .features[FEAT_1_ECX] =
729 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
730 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
731 .features[FEAT_8000_0001_EDX] =
732 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
733 .features[FEAT_8000_0001_ECX] =
734 CPUID_EXT3_LAHF_LM,
735 .xlevel = 0x8000000A,
736 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
737 },
738 {
739 .name = "Westmere",
740 .level = 11,
741 .vendor = CPUID_VENDOR_INTEL,
742 .family = 6,
743 .model = 44,
744 .stepping = 1,
745 .features[FEAT_1_EDX] =
746 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
750 CPUID_DE | CPUID_FP87,
751 .features[FEAT_1_ECX] =
752 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
753 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
754 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
755 .features[FEAT_8000_0001_EDX] =
756 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
757 .features[FEAT_8000_0001_ECX] =
758 CPUID_EXT3_LAHF_LM,
759 .xlevel = 0x8000000A,
760 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
761 },
762 {
763 .name = "SandyBridge",
764 .level = 0xd,
765 .vendor = CPUID_VENDOR_INTEL,
766 .family = 6,
767 .model = 42,
768 .stepping = 1,
769 .features[FEAT_1_EDX] =
770 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
771 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
772 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
773 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
774 CPUID_DE | CPUID_FP87,
775 .features[FEAT_1_ECX] =
776 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
777 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
778 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
779 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
780 CPUID_EXT_SSE3,
781 .features[FEAT_8000_0001_EDX] =
782 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
783 CPUID_EXT2_SYSCALL,
784 .features[FEAT_8000_0001_ECX] =
785 CPUID_EXT3_LAHF_LM,
786 .xlevel = 0x8000000A,
787 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
788 },
789 {
790 .name = "Haswell",
791 .level = 0xd,
792 .vendor = CPUID_VENDOR_INTEL,
793 .family = 6,
794 .model = 60,
795 .stepping = 1,
796 .features[FEAT_1_EDX] =
797 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
801 CPUID_DE | CPUID_FP87,
802 .features[FEAT_1_ECX] =
803 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
804 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
805 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
806 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
807 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
808 CPUID_EXT_PCID,
809 .features[FEAT_8000_0001_EDX] =
810 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
811 CPUID_EXT2_SYSCALL,
812 .features[FEAT_8000_0001_ECX] =
813 CPUID_EXT3_LAHF_LM,
814 .features[FEAT_7_0_EBX] =
815 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
816 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
817 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
818 CPUID_7_0_EBX_RTM,
819 .xlevel = 0x8000000A,
820 .model_id = "Intel Core Processor (Haswell)",
821 },
822 {
823 .name = "Opteron_G1",
824 .level = 5,
825 .vendor = CPUID_VENDOR_AMD,
826 .family = 15,
827 .model = 6,
828 .stepping = 1,
829 .features[FEAT_1_EDX] =
830 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
834 CPUID_DE | CPUID_FP87,
835 .features[FEAT_1_ECX] =
836 CPUID_EXT_SSE3,
837 .features[FEAT_8000_0001_EDX] =
838 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
839 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
840 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
841 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
842 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
843 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
844 .xlevel = 0x80000008,
845 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
846 },
847 {
848 .name = "Opteron_G2",
849 .level = 5,
850 .vendor = CPUID_VENDOR_AMD,
851 .family = 15,
852 .model = 6,
853 .stepping = 1,
854 .features[FEAT_1_EDX] =
855 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
856 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
857 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
858 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
859 CPUID_DE | CPUID_FP87,
860 .features[FEAT_1_ECX] =
861 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
862 .features[FEAT_8000_0001_EDX] =
863 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
864 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
865 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
866 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
867 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
868 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
869 CPUID_EXT2_DE | CPUID_EXT2_FPU,
870 .features[FEAT_8000_0001_ECX] =
871 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
872 .xlevel = 0x80000008,
873 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
874 },
875 {
876 .name = "Opteron_G3",
877 .level = 5,
878 .vendor = CPUID_VENDOR_AMD,
879 .family = 15,
880 .model = 6,
881 .stepping = 1,
882 .features[FEAT_1_EDX] =
883 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
887 CPUID_DE | CPUID_FP87,
888 .features[FEAT_1_ECX] =
889 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
890 CPUID_EXT_SSE3,
891 .features[FEAT_8000_0001_EDX] =
892 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
893 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
894 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
895 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
896 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
897 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
898 CPUID_EXT2_DE | CPUID_EXT2_FPU,
899 .features[FEAT_8000_0001_ECX] =
900 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
901 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
902 .xlevel = 0x80000008,
903 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
904 },
905 {
906 .name = "Opteron_G4",
907 .level = 0xd,
908 .vendor = CPUID_VENDOR_AMD,
909 .family = 21,
910 .model = 1,
911 .stepping = 2,
912 .features[FEAT_1_EDX] =
913 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
914 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
915 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
916 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
917 CPUID_DE | CPUID_FP87,
918 .features[FEAT_1_ECX] =
919 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
920 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
921 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
922 CPUID_EXT_SSE3,
923 .features[FEAT_8000_0001_EDX] =
924 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
925 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
926 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
927 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
928 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
929 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
930 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
931 .features[FEAT_8000_0001_ECX] =
932 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
933 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
934 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
935 CPUID_EXT3_LAHF_LM,
936 .xlevel = 0x8000001A,
937 .model_id = "AMD Opteron 62xx class CPU",
938 },
939 {
940 .name = "Opteron_G5",
941 .level = 0xd,
942 .vendor = CPUID_VENDOR_AMD,
943 .family = 21,
944 .model = 2,
945 .stepping = 0,
946 .features[FEAT_1_EDX] =
947 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
948 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
949 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
950 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
951 CPUID_DE | CPUID_FP87,
952 .features[FEAT_1_ECX] =
953 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
954 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
955 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
956 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
957 .features[FEAT_8000_0001_EDX] =
958 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
959 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
960 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
961 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
962 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
963 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
964 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
965 .features[FEAT_8000_0001_ECX] =
966 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
967 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
968 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
969 CPUID_EXT3_LAHF_LM,
970 .xlevel = 0x8000001A,
971 .model_id = "AMD Opteron 63xx class CPU",
972 },
973 };
974
975 /**
976 * x86_cpu_compat_set_features:
977 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
978 * @w: Identifies the feature word to be changed.
979 * @feat_add: Feature bits to be added to feature word
980 * @feat_remove: Feature bits to be removed from feature word
981 *
982 * Change CPU model feature bits for compatibility.
983 *
984 * This function may be used by machine-type compatibility functions
985 * to enable or disable feature bits on specific CPU models.
986 */
987 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
988 uint32_t feat_add, uint32_t feat_remove)
989 {
990 x86_def_t *def;
991 int i;
992 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
993 def = &builtin_x86_defs[i];
994 if (!cpu_model || !strcmp(cpu_model, def->name)) {
995 def->features[w] |= feat_add;
996 def->features[w] &= ~feat_remove;
997 }
998 }
999 }
1000
1001 #ifdef CONFIG_KVM
1002 static int cpu_x86_fill_model_id(char *str)
1003 {
1004 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1005 int i;
1006
1007 for (i = 0; i < 3; i++) {
1008 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1009 memcpy(str + i * 16 + 0, &eax, 4);
1010 memcpy(str + i * 16 + 4, &ebx, 4);
1011 memcpy(str + i * 16 + 8, &ecx, 4);
1012 memcpy(str + i * 16 + 12, &edx, 4);
1013 }
1014 return 0;
1015 }
1016 #endif
1017
1018 /* Fill a x86_def_t struct with information about the host CPU, and
1019 * the CPU features supported by the host hardware + host kernel
1020 *
1021 * This function may be called only if KVM is enabled.
1022 */
1023 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
1024 {
1025 #ifdef CONFIG_KVM
1026 KVMState *s = kvm_state;
1027 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1028
1029 assert(kvm_enabled());
1030
1031 x86_cpu_def->name = "host";
1032 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1033 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1034
1035 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1036 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1037 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1038 x86_cpu_def->stepping = eax & 0x0F;
1039
1040 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1041 x86_cpu_def->features[FEAT_1_EDX] =
1042 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1043 x86_cpu_def->features[FEAT_1_ECX] =
1044 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1045
1046 if (x86_cpu_def->level >= 7) {
1047 x86_cpu_def->features[FEAT_7_0_EBX] =
1048 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1049 } else {
1050 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1051 }
1052
1053 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1054 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1055 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1056 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1057 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1058
1059 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1060
1061 /* Call Centaur's CPUID instruction. */
1062 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1063 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1064 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1065 if (eax >= 0xC0000001) {
1066 /* Support VIA max extended level */
1067 x86_cpu_def->xlevel2 = eax;
1068 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1069 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1070 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1071 }
1072 }
1073
1074 /* Other KVM-specific feature fields: */
1075 x86_cpu_def->features[FEAT_SVM] =
1076 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1077 x86_cpu_def->features[FEAT_KVM] =
1078 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1079
1080 #endif /* CONFIG_KVM */
1081 }
1082
1083 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1084 {
1085 int i;
1086
1087 for (i = 0; i < 32; ++i)
1088 if (1 << i & mask) {
1089 const char *reg = get_register_name_32(f->cpuid_reg);
1090 assert(reg);
1091 fprintf(stderr, "warning: host doesn't support requested feature: "
1092 "CPUID.%02XH:%s%s%s [bit %d]\n",
1093 f->cpuid_eax, reg,
1094 f->feat_names[i] ? "." : "",
1095 f->feat_names[i] ? f->feat_names[i] : "", i);
1096 break;
1097 }
1098 return 0;
1099 }
1100
1101 /* Check if all requested cpu flags are making their way to the guest
1102 *
1103 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1104 *
1105 * This function may be called only if KVM is enabled.
1106 */
1107 static int kvm_check_features_against_host(X86CPU *cpu)
1108 {
1109 CPUX86State *env = &cpu->env;
1110 x86_def_t host_def;
1111 uint32_t mask;
1112 int rv, i;
1113 struct model_features_t ft[] = {
1114 {&env->features[FEAT_1_EDX],
1115 &host_def.features[FEAT_1_EDX],
1116 FEAT_1_EDX },
1117 {&env->features[FEAT_1_ECX],
1118 &host_def.features[FEAT_1_ECX],
1119 FEAT_1_ECX },
1120 {&env->features[FEAT_8000_0001_EDX],
1121 &host_def.features[FEAT_8000_0001_EDX],
1122 FEAT_8000_0001_EDX },
1123 {&env->features[FEAT_8000_0001_ECX],
1124 &host_def.features[FEAT_8000_0001_ECX],
1125 FEAT_8000_0001_ECX },
1126 {&env->features[FEAT_C000_0001_EDX],
1127 &host_def.features[FEAT_C000_0001_EDX],
1128 FEAT_C000_0001_EDX },
1129 {&env->features[FEAT_7_0_EBX],
1130 &host_def.features[FEAT_7_0_EBX],
1131 FEAT_7_0_EBX },
1132 {&env->features[FEAT_SVM],
1133 &host_def.features[FEAT_SVM],
1134 FEAT_SVM },
1135 {&env->features[FEAT_KVM],
1136 &host_def.features[FEAT_KVM],
1137 FEAT_KVM },
1138 };
1139
1140 assert(kvm_enabled());
1141
1142 kvm_cpu_fill_host(&host_def);
1143 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1144 FeatureWord w = ft[i].feat_word;
1145 FeatureWordInfo *wi = &feature_word_info[w];
1146 for (mask = 1; mask; mask <<= 1) {
1147 if (*ft[i].guest_feat & mask &&
1148 !(*ft[i].host_feat & mask)) {
1149 unavailable_host_feature(wi, mask);
1150 rv = 1;
1151 }
1152 }
1153 }
1154 return rv;
1155 }
1156
1157 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1158 const char *name, Error **errp)
1159 {
1160 X86CPU *cpu = X86_CPU(obj);
1161 CPUX86State *env = &cpu->env;
1162 int64_t value;
1163
1164 value = (env->cpuid_version >> 8) & 0xf;
1165 if (value == 0xf) {
1166 value += (env->cpuid_version >> 20) & 0xff;
1167 }
1168 visit_type_int(v, &value, name, errp);
1169 }
1170
1171 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1172 const char *name, Error **errp)
1173 {
1174 X86CPU *cpu = X86_CPU(obj);
1175 CPUX86State *env = &cpu->env;
1176 const int64_t min = 0;
1177 const int64_t max = 0xff + 0xf;
1178 int64_t value;
1179
1180 visit_type_int(v, &value, name, errp);
1181 if (error_is_set(errp)) {
1182 return;
1183 }
1184 if (value < min || value > max) {
1185 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1186 name ? name : "null", value, min, max);
1187 return;
1188 }
1189
1190 env->cpuid_version &= ~0xff00f00;
1191 if (value > 0x0f) {
1192 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1193 } else {
1194 env->cpuid_version |= value << 8;
1195 }
1196 }
1197
1198 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1199 const char *name, Error **errp)
1200 {
1201 X86CPU *cpu = X86_CPU(obj);
1202 CPUX86State *env = &cpu->env;
1203 int64_t value;
1204
1205 value = (env->cpuid_version >> 4) & 0xf;
1206 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1207 visit_type_int(v, &value, name, errp);
1208 }
1209
1210 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1211 const char *name, Error **errp)
1212 {
1213 X86CPU *cpu = X86_CPU(obj);
1214 CPUX86State *env = &cpu->env;
1215 const int64_t min = 0;
1216 const int64_t max = 0xff;
1217 int64_t value;
1218
1219 visit_type_int(v, &value, name, errp);
1220 if (error_is_set(errp)) {
1221 return;
1222 }
1223 if (value < min || value > max) {
1224 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1225 name ? name : "null", value, min, max);
1226 return;
1227 }
1228
1229 env->cpuid_version &= ~0xf00f0;
1230 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1231 }
1232
1233 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1234 void *opaque, const char *name,
1235 Error **errp)
1236 {
1237 X86CPU *cpu = X86_CPU(obj);
1238 CPUX86State *env = &cpu->env;
1239 int64_t value;
1240
1241 value = env->cpuid_version & 0xf;
1242 visit_type_int(v, &value, name, errp);
1243 }
1244
1245 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1246 void *opaque, const char *name,
1247 Error **errp)
1248 {
1249 X86CPU *cpu = X86_CPU(obj);
1250 CPUX86State *env = &cpu->env;
1251 const int64_t min = 0;
1252 const int64_t max = 0xf;
1253 int64_t value;
1254
1255 visit_type_int(v, &value, name, errp);
1256 if (error_is_set(errp)) {
1257 return;
1258 }
1259 if (value < min || value > max) {
1260 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1261 name ? name : "null", value, min, max);
1262 return;
1263 }
1264
1265 env->cpuid_version &= ~0xf;
1266 env->cpuid_version |= value & 0xf;
1267 }
1268
1269 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1270 const char *name, Error **errp)
1271 {
1272 X86CPU *cpu = X86_CPU(obj);
1273
1274 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1275 }
1276
1277 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1278 const char *name, Error **errp)
1279 {
1280 X86CPU *cpu = X86_CPU(obj);
1281
1282 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1283 }
1284
1285 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1286 const char *name, Error **errp)
1287 {
1288 X86CPU *cpu = X86_CPU(obj);
1289
1290 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1291 }
1292
1293 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1294 const char *name, Error **errp)
1295 {
1296 X86CPU *cpu = X86_CPU(obj);
1297
1298 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1299 }
1300
1301 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1302 {
1303 X86CPU *cpu = X86_CPU(obj);
1304 CPUX86State *env = &cpu->env;
1305 char *value;
1306
1307 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1308 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1309 env->cpuid_vendor3);
1310 return value;
1311 }
1312
1313 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1314 Error **errp)
1315 {
1316 X86CPU *cpu = X86_CPU(obj);
1317 CPUX86State *env = &cpu->env;
1318 int i;
1319
1320 if (strlen(value) != CPUID_VENDOR_SZ) {
1321 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1322 "vendor", value);
1323 return;
1324 }
1325
1326 env->cpuid_vendor1 = 0;
1327 env->cpuid_vendor2 = 0;
1328 env->cpuid_vendor3 = 0;
1329 for (i = 0; i < 4; i++) {
1330 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1331 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1332 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1333 }
1334 }
1335
1336 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1337 {
1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 char *value;
1341 int i;
1342
1343 value = g_malloc(48 + 1);
1344 for (i = 0; i < 48; i++) {
1345 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1346 }
1347 value[48] = '\0';
1348 return value;
1349 }
1350
1351 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1352 Error **errp)
1353 {
1354 X86CPU *cpu = X86_CPU(obj);
1355 CPUX86State *env = &cpu->env;
1356 int c, len, i;
1357
1358 if (model_id == NULL) {
1359 model_id = "";
1360 }
1361 len = strlen(model_id);
1362 memset(env->cpuid_model, 0, 48);
1363 for (i = 0; i < 48; i++) {
1364 if (i >= len) {
1365 c = '\0';
1366 } else {
1367 c = (uint8_t)model_id[i];
1368 }
1369 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1370 }
1371 }
1372
1373 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1374 const char *name, Error **errp)
1375 {
1376 X86CPU *cpu = X86_CPU(obj);
1377 int64_t value;
1378
1379 value = cpu->env.tsc_khz * 1000;
1380 visit_type_int(v, &value, name, errp);
1381 }
1382
1383 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1384 const char *name, Error **errp)
1385 {
1386 X86CPU *cpu = X86_CPU(obj);
1387 const int64_t min = 0;
1388 const int64_t max = INT64_MAX;
1389 int64_t value;
1390
1391 visit_type_int(v, &value, name, errp);
1392 if (error_is_set(errp)) {
1393 return;
1394 }
1395 if (value < min || value > max) {
1396 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1397 name ? name : "null", value, min, max);
1398 return;
1399 }
1400
1401 cpu->env.tsc_khz = value / 1000;
1402 }
1403
1404 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1405 const char *name, Error **errp)
1406 {
1407 X86CPU *cpu = X86_CPU(obj);
1408 int64_t value = cpu->env.cpuid_apic_id;
1409
1410 visit_type_int(v, &value, name, errp);
1411 }
1412
1413 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1414 const char *name, Error **errp)
1415 {
1416 X86CPU *cpu = X86_CPU(obj);
1417 DeviceState *dev = DEVICE(obj);
1418 const int64_t min = 0;
1419 const int64_t max = UINT32_MAX;
1420 Error *error = NULL;
1421 int64_t value;
1422
1423 if (dev->realized) {
1424 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1425 "it was realized", name, object_get_typename(obj));
1426 return;
1427 }
1428
1429 visit_type_int(v, &value, name, &error);
1430 if (error) {
1431 error_propagate(errp, error);
1432 return;
1433 }
1434 if (value < min || value > max) {
1435 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1436 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1437 object_get_typename(obj), name, value, min, max);
1438 return;
1439 }
1440
1441 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1442 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1443 return;
1444 }
1445 cpu->env.cpuid_apic_id = value;
1446 }
1447
1448 /* Generic getter for "feature-words" and "filtered-features" properties */
1449 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1450 const char *name, Error **errp)
1451 {
1452 uint32_t *array = (uint32_t *)opaque;
1453 FeatureWord w;
1454 Error *err = NULL;
1455 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1456 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1457 X86CPUFeatureWordInfoList *list = NULL;
1458
1459 for (w = 0; w < FEATURE_WORDS; w++) {
1460 FeatureWordInfo *wi = &feature_word_info[w];
1461 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1462 qwi->cpuid_input_eax = wi->cpuid_eax;
1463 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1464 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1465 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1466 qwi->features = array[w];
1467
1468 /* List will be in reverse order, but order shouldn't matter */
1469 list_entries[w].next = list;
1470 list_entries[w].value = &word_infos[w];
1471 list = &list_entries[w];
1472 }
1473
1474 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1475 error_propagate(errp, err);
1476 }
1477
1478 static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1479 const char *name)
1480 {
1481 x86_def_t *def;
1482 int i;
1483
1484 if (name == NULL) {
1485 return -1;
1486 }
1487 if (kvm_enabled() && strcmp(name, "host") == 0) {
1488 kvm_cpu_fill_host(x86_cpu_def);
1489 return 0;
1490 }
1491
1492 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1493 def = &builtin_x86_defs[i];
1494 if (strcmp(name, def->name) == 0) {
1495 memcpy(x86_cpu_def, def, sizeof(*def));
1496 /* sysenter isn't supported in compatibility mode on AMD,
1497 * syscall isn't supported in compatibility mode on Intel.
1498 * Normally we advertise the actual CPU vendor, but you can
1499 * override this using the 'vendor' property if you want to use
1500 * KVM's sysenter/syscall emulation in compatibility mode and
1501 * when doing cross vendor migration
1502 */
1503 if (kvm_enabled()) {
1504 uint32_t ebx = 0, ecx = 0, edx = 0;
1505 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1506 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1507 }
1508 return 0;
1509 }
1510 }
1511
1512 return -1;
1513 }
1514
1515 /* Convert all '_' in a feature string option name to '-', to make feature
1516 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1517 */
1518 static inline void feat2prop(char *s)
1519 {
1520 while ((s = strchr(s, '_'))) {
1521 *s = '-';
1522 }
1523 }
1524
1525 /* Parse "+feature,-feature,feature=foo" CPU feature string
1526 */
1527 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1528 {
1529 char *featurestr; /* Single 'key=value" string being parsed */
1530 /* Features to be added */
1531 FeatureWordArray plus_features = { 0 };
1532 /* Features to be removed */
1533 FeatureWordArray minus_features = { 0 };
1534 uint32_t numvalue;
1535 CPUX86State *env = &cpu->env;
1536
1537 featurestr = features ? strtok(features, ",") : NULL;
1538
1539 while (featurestr) {
1540 char *val;
1541 if (featurestr[0] == '+') {
1542 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1543 } else if (featurestr[0] == '-') {
1544 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1545 } else if ((val = strchr(featurestr, '='))) {
1546 *val = 0; val++;
1547 feat2prop(featurestr);
1548 if (!strcmp(featurestr, "family")) {
1549 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1550 } else if (!strcmp(featurestr, "model")) {
1551 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1552 } else if (!strcmp(featurestr, "stepping")) {
1553 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1554 } else if (!strcmp(featurestr, "level")) {
1555 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1556 } else if (!strcmp(featurestr, "xlevel")) {
1557 char *err;
1558 char num[32];
1559
1560 numvalue = strtoul(val, &err, 0);
1561 if (!*val || *err) {
1562 error_setg(errp, "bad numerical value %s", val);
1563 goto out;
1564 }
1565 if (numvalue < 0x80000000) {
1566 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1567 ", fixup will be removed in future versions\n");
1568 numvalue += 0x80000000;
1569 }
1570 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1571 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1572 } else if (!strcmp(featurestr, "vendor")) {
1573 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1574 } else if (!strcmp(featurestr, "model-id")) {
1575 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1576 } else if (!strcmp(featurestr, "tsc-freq")) {
1577 int64_t tsc_freq;
1578 char *err;
1579 char num[32];
1580
1581 tsc_freq = strtosz_suffix_unit(val, &err,
1582 STRTOSZ_DEFSUFFIX_B, 1000);
1583 if (tsc_freq < 0 || *err) {
1584 error_setg(errp, "bad numerical value %s", val);
1585 goto out;
1586 }
1587 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1588 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1589 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1590 char *err;
1591 numvalue = strtoul(val, &err, 0);
1592 if (!*val || *err) {
1593 error_setg(errp, "bad numerical value %s", val);
1594 goto out;
1595 }
1596 hyperv_set_spinlock_retries(numvalue);
1597 } else {
1598 error_setg(errp, "unrecognized feature %s", featurestr);
1599 goto out;
1600 }
1601 } else if (!strcmp(featurestr, "check")) {
1602 check_cpuid = 1;
1603 } else if (!strcmp(featurestr, "enforce")) {
1604 check_cpuid = enforce_cpuid = 1;
1605 } else if (!strcmp(featurestr, "hv_relaxed")) {
1606 hyperv_enable_relaxed_timing(true);
1607 } else if (!strcmp(featurestr, "hv_vapic")) {
1608 hyperv_enable_vapic_recommended(true);
1609 } else {
1610 error_setg(errp, "feature string `%s' not in format (+feature|"
1611 "-feature|feature=xyz)", featurestr);
1612 goto out;
1613 }
1614 if (error_is_set(errp)) {
1615 goto out;
1616 }
1617 featurestr = strtok(NULL, ",");
1618 }
1619 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1620 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1621 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1622 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1623 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1624 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1625 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1626 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1627 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1628 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1629 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1630 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1631 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1632 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1633 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1634 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1635
1636 out:
1637 return;
1638 }
1639
1640 /* generate a composite string into buf of all cpuid names in featureset
1641 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1642 * if flags, suppress names undefined in featureset.
1643 */
1644 static void listflags(char *buf, int bufsize, uint32_t fbits,
1645 const char **featureset, uint32_t flags)
1646 {
1647 const char **p = &featureset[31];
1648 char *q, *b, bit;
1649 int nc;
1650
1651 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1652 *buf = '\0';
1653 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1654 if (fbits & 1 << bit && (*p || !flags)) {
1655 if (*p)
1656 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1657 else
1658 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1659 if (bufsize <= nc) {
1660 if (b) {
1661 memcpy(b, "...", sizeof("..."));
1662 }
1663 return;
1664 }
1665 q += nc;
1666 bufsize -= nc;
1667 }
1668 }
1669
1670 /* generate CPU information. */
1671 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1672 {
1673 x86_def_t *def;
1674 char buf[256];
1675 int i;
1676
1677 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1678 def = &builtin_x86_defs[i];
1679 snprintf(buf, sizeof(buf), "%s", def->name);
1680 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1681 }
1682 #ifdef CONFIG_KVM
1683 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1684 "KVM processor with all supported host features "
1685 "(only available in KVM mode)");
1686 #endif
1687
1688 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1689 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1690 FeatureWordInfo *fw = &feature_word_info[i];
1691
1692 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1693 (*cpu_fprintf)(f, " %s\n", buf);
1694 }
1695 }
1696
1697 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1698 {
1699 CpuDefinitionInfoList *cpu_list = NULL;
1700 x86_def_t *def;
1701 int i;
1702
1703 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1704 CpuDefinitionInfoList *entry;
1705 CpuDefinitionInfo *info;
1706
1707 def = &builtin_x86_defs[i];
1708 info = g_malloc0(sizeof(*info));
1709 info->name = g_strdup(def->name);
1710
1711 entry = g_malloc0(sizeof(*entry));
1712 entry->value = info;
1713 entry->next = cpu_list;
1714 cpu_list = entry;
1715 }
1716
1717 return cpu_list;
1718 }
1719
1720 #ifdef CONFIG_KVM
1721 static void filter_features_for_kvm(X86CPU *cpu)
1722 {
1723 CPUX86State *env = &cpu->env;
1724 KVMState *s = kvm_state;
1725 FeatureWord w;
1726
1727 for (w = 0; w < FEATURE_WORDS; w++) {
1728 FeatureWordInfo *wi = &feature_word_info[w];
1729 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1730 wi->cpuid_ecx,
1731 wi->cpuid_reg);
1732 uint32_t requested_features = env->features[w];
1733 env->features[w] &= host_feat;
1734 cpu->filtered_features[w] = requested_features & ~env->features[w];
1735 }
1736 }
1737 #endif
1738
1739 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1740 {
1741 CPUX86State *env = &cpu->env;
1742 x86_def_t def1, *def = &def1;
1743
1744 memset(def, 0, sizeof(*def));
1745
1746 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1747 error_setg(errp, "Unable to find CPU definition: %s", name);
1748 return;
1749 }
1750
1751 if (kvm_enabled()) {
1752 def->features[FEAT_KVM] |= kvm_default_features;
1753 }
1754 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1755
1756 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1757 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1758 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1759 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1760 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1761 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1762 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1763 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1764 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1765 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1766 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1767 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1768 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1769 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1770 env->cpuid_xlevel2 = def->xlevel2;
1771
1772 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1773 }
1774
1775 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1776 Error **errp)
1777 {
1778 X86CPU *cpu = NULL;
1779 CPUX86State *env;
1780 gchar **model_pieces;
1781 char *name, *features;
1782 char *typename;
1783 Error *error = NULL;
1784
1785 model_pieces = g_strsplit(cpu_model, ",", 2);
1786 if (!model_pieces[0]) {
1787 error_setg(&error, "Invalid/empty CPU model name");
1788 goto out;
1789 }
1790 name = model_pieces[0];
1791 features = model_pieces[1];
1792
1793 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1794 #ifndef CONFIG_USER_ONLY
1795 if (icc_bridge == NULL) {
1796 error_setg(&error, "Invalid icc-bridge value");
1797 goto out;
1798 }
1799 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1800 object_unref(OBJECT(cpu));
1801 #endif
1802 env = &cpu->env;
1803 env->cpu_model_str = cpu_model;
1804
1805 cpu_x86_register(cpu, name, &error);
1806 if (error) {
1807 goto out;
1808 }
1809
1810 /* Emulate per-model subclasses for global properties */
1811 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1812 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1813 g_free(typename);
1814 if (error) {
1815 goto out;
1816 }
1817
1818 cpu_x86_parse_featurestr(cpu, features, &error);
1819 if (error) {
1820 goto out;
1821 }
1822
1823 out:
1824 error_propagate(errp, error);
1825 g_strfreev(model_pieces);
1826 return cpu;
1827 }
1828
1829 X86CPU *cpu_x86_init(const char *cpu_model)
1830 {
1831 Error *error = NULL;
1832 X86CPU *cpu;
1833
1834 cpu = cpu_x86_create(cpu_model, NULL, &error);
1835 if (error) {
1836 goto out;
1837 }
1838
1839 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1840
1841 out:
1842 if (error) {
1843 fprintf(stderr, "%s\n", error_get_pretty(error));
1844 error_free(error);
1845 if (cpu != NULL) {
1846 object_unref(OBJECT(cpu));
1847 cpu = NULL;
1848 }
1849 }
1850 return cpu;
1851 }
1852
1853 #if !defined(CONFIG_USER_ONLY)
1854
1855 void cpu_clear_apic_feature(CPUX86State *env)
1856 {
1857 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1858 }
1859
1860 #endif /* !CONFIG_USER_ONLY */
1861
1862 /* Initialize list of CPU models, filling some non-static fields if necessary
1863 */
1864 void x86_cpudef_setup(void)
1865 {
1866 int i, j;
1867 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1868
1869 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1870 x86_def_t *def = &builtin_x86_defs[i];
1871
1872 /* Look for specific "cpudef" models that */
1873 /* have the QEMU version in .model_id */
1874 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1875 if (strcmp(model_with_versions[j], def->name) == 0) {
1876 pstrcpy(def->model_id, sizeof(def->model_id),
1877 "QEMU Virtual CPU version ");
1878 pstrcat(def->model_id, sizeof(def->model_id),
1879 qemu_get_version());
1880 break;
1881 }
1882 }
1883 }
1884 }
1885
1886 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1887 uint32_t *ecx, uint32_t *edx)
1888 {
1889 *ebx = env->cpuid_vendor1;
1890 *edx = env->cpuid_vendor2;
1891 *ecx = env->cpuid_vendor3;
1892 }
1893
1894 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1895 uint32_t *eax, uint32_t *ebx,
1896 uint32_t *ecx, uint32_t *edx)
1897 {
1898 X86CPU *cpu = x86_env_get_cpu(env);
1899 CPUState *cs = CPU(cpu);
1900
1901 /* test if maximum index reached */
1902 if (index & 0x80000000) {
1903 if (index > env->cpuid_xlevel) {
1904 if (env->cpuid_xlevel2 > 0) {
1905 /* Handle the Centaur's CPUID instruction. */
1906 if (index > env->cpuid_xlevel2) {
1907 index = env->cpuid_xlevel2;
1908 } else if (index < 0xC0000000) {
1909 index = env->cpuid_xlevel;
1910 }
1911 } else {
1912 /* Intel documentation states that invalid EAX input will
1913 * return the same information as EAX=cpuid_level
1914 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1915 */
1916 index = env->cpuid_level;
1917 }
1918 }
1919 } else {
1920 if (index > env->cpuid_level)
1921 index = env->cpuid_level;
1922 }
1923
1924 switch(index) {
1925 case 0:
1926 *eax = env->cpuid_level;
1927 get_cpuid_vendor(env, ebx, ecx, edx);
1928 break;
1929 case 1:
1930 *eax = env->cpuid_version;
1931 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1932 *ecx = env->features[FEAT_1_ECX];
1933 *edx = env->features[FEAT_1_EDX];
1934 if (cs->nr_cores * cs->nr_threads > 1) {
1935 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1936 *edx |= 1 << 28; /* HTT bit */
1937 }
1938 break;
1939 case 2:
1940 /* cache info: needed for Pentium Pro compatibility */
1941 *eax = 1;
1942 *ebx = 0;
1943 *ecx = 0;
1944 *edx = 0x2c307d;
1945 break;
1946 case 4:
1947 /* cache info: needed for Core compatibility */
1948 if (cs->nr_cores > 1) {
1949 *eax = (cs->nr_cores - 1) << 26;
1950 } else {
1951 *eax = 0;
1952 }
1953 switch (count) {
1954 case 0: /* L1 dcache info */
1955 *eax |= 0x0000121;
1956 *ebx = 0x1c0003f;
1957 *ecx = 0x000003f;
1958 *edx = 0x0000001;
1959 break;
1960 case 1: /* L1 icache info */
1961 *eax |= 0x0000122;
1962 *ebx = 0x1c0003f;
1963 *ecx = 0x000003f;
1964 *edx = 0x0000001;
1965 break;
1966 case 2: /* L2 cache info */
1967 *eax |= 0x0000143;
1968 if (cs->nr_threads > 1) {
1969 *eax |= (cs->nr_threads - 1) << 14;
1970 }
1971 *ebx = 0x3c0003f;
1972 *ecx = 0x0000fff;
1973 *edx = 0x0000001;
1974 break;
1975 default: /* end of info */
1976 *eax = 0;
1977 *ebx = 0;
1978 *ecx = 0;
1979 *edx = 0;
1980 break;
1981 }
1982 break;
1983 case 5:
1984 /* mwait info: needed for Core compatibility */
1985 *eax = 0; /* Smallest monitor-line size in bytes */
1986 *ebx = 0; /* Largest monitor-line size in bytes */
1987 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1988 *edx = 0;
1989 break;
1990 case 6:
1991 /* Thermal and Power Leaf */
1992 *eax = 0;
1993 *ebx = 0;
1994 *ecx = 0;
1995 *edx = 0;
1996 break;
1997 case 7:
1998 /* Structured Extended Feature Flags Enumeration Leaf */
1999 if (count == 0) {
2000 *eax = 0; /* Maximum ECX value for sub-leaves */
2001 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2002 *ecx = 0; /* Reserved */
2003 *edx = 0; /* Reserved */
2004 } else {
2005 *eax = 0;
2006 *ebx = 0;
2007 *ecx = 0;
2008 *edx = 0;
2009 }
2010 break;
2011 case 9:
2012 /* Direct Cache Access Information Leaf */
2013 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2014 *ebx = 0;
2015 *ecx = 0;
2016 *edx = 0;
2017 break;
2018 case 0xA:
2019 /* Architectural Performance Monitoring Leaf */
2020 if (kvm_enabled()) {
2021 KVMState *s = cs->kvm_state;
2022
2023 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2024 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2025 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2026 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2027 } else {
2028 *eax = 0;
2029 *ebx = 0;
2030 *ecx = 0;
2031 *edx = 0;
2032 }
2033 break;
2034 case 0xD:
2035 /* Processor Extended State */
2036 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2037 *eax = 0;
2038 *ebx = 0;
2039 *ecx = 0;
2040 *edx = 0;
2041 break;
2042 }
2043 if (kvm_enabled()) {
2044 KVMState *s = cs->kvm_state;
2045
2046 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
2047 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
2048 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
2049 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
2050 } else {
2051 *eax = 0;
2052 *ebx = 0;
2053 *ecx = 0;
2054 *edx = 0;
2055 }
2056 break;
2057 case 0x80000000:
2058 *eax = env->cpuid_xlevel;
2059 *ebx = env->cpuid_vendor1;
2060 *edx = env->cpuid_vendor2;
2061 *ecx = env->cpuid_vendor3;
2062 break;
2063 case 0x80000001:
2064 *eax = env->cpuid_version;
2065 *ebx = 0;
2066 *ecx = env->features[FEAT_8000_0001_ECX];
2067 *edx = env->features[FEAT_8000_0001_EDX];
2068
2069 /* The Linux kernel checks for the CMPLegacy bit and
2070 * discards multiple thread information if it is set.
2071 * So dont set it here for Intel to make Linux guests happy.
2072 */
2073 if (cs->nr_cores * cs->nr_threads > 1) {
2074 uint32_t tebx, tecx, tedx;
2075 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2076 if (tebx != CPUID_VENDOR_INTEL_1 ||
2077 tedx != CPUID_VENDOR_INTEL_2 ||
2078 tecx != CPUID_VENDOR_INTEL_3) {
2079 *ecx |= 1 << 1; /* CmpLegacy bit */
2080 }
2081 }
2082 break;
2083 case 0x80000002:
2084 case 0x80000003:
2085 case 0x80000004:
2086 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2087 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2088 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2089 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2090 break;
2091 case 0x80000005:
2092 /* cache info (L1 cache) */
2093 *eax = 0x01ff01ff;
2094 *ebx = 0x01ff01ff;
2095 *ecx = 0x40020140;
2096 *edx = 0x40020140;
2097 break;
2098 case 0x80000006:
2099 /* cache info (L2 cache) */
2100 *eax = 0;
2101 *ebx = 0x42004200;
2102 *ecx = 0x02008140;
2103 *edx = 0;
2104 break;
2105 case 0x80000008:
2106 /* virtual & phys address size in low 2 bytes. */
2107 /* XXX: This value must match the one used in the MMU code. */
2108 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2109 /* 64 bit processor */
2110 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2111 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2112 } else {
2113 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2114 *eax = 0x00000024; /* 36 bits physical */
2115 } else {
2116 *eax = 0x00000020; /* 32 bits physical */
2117 }
2118 }
2119 *ebx = 0;
2120 *ecx = 0;
2121 *edx = 0;
2122 if (cs->nr_cores * cs->nr_threads > 1) {
2123 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2124 }
2125 break;
2126 case 0x8000000A:
2127 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2128 *eax = 0x00000001; /* SVM Revision */
2129 *ebx = 0x00000010; /* nr of ASIDs */
2130 *ecx = 0;
2131 *edx = env->features[FEAT_SVM]; /* optional features */
2132 } else {
2133 *eax = 0;
2134 *ebx = 0;
2135 *ecx = 0;
2136 *edx = 0;
2137 }
2138 break;
2139 case 0xC0000000:
2140 *eax = env->cpuid_xlevel2;
2141 *ebx = 0;
2142 *ecx = 0;
2143 *edx = 0;
2144 break;
2145 case 0xC0000001:
2146 /* Support for VIA CPU's CPUID instruction */
2147 *eax = env->cpuid_version;
2148 *ebx = 0;
2149 *ecx = 0;
2150 *edx = env->features[FEAT_C000_0001_EDX];
2151 break;
2152 case 0xC0000002:
2153 case 0xC0000003:
2154 case 0xC0000004:
2155 /* Reserved for the future, and now filled with zero */
2156 *eax = 0;
2157 *ebx = 0;
2158 *ecx = 0;
2159 *edx = 0;
2160 break;
2161 default:
2162 /* reserved values: zero */
2163 *eax = 0;
2164 *ebx = 0;
2165 *ecx = 0;
2166 *edx = 0;
2167 break;
2168 }
2169 }
2170
2171 /* CPUClass::reset() */
2172 static void x86_cpu_reset(CPUState *s)
2173 {
2174 X86CPU *cpu = X86_CPU(s);
2175 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2176 CPUX86State *env = &cpu->env;
2177 int i;
2178
2179 xcc->parent_reset(s);
2180
2181
2182 memset(env, 0, offsetof(CPUX86State, breakpoints));
2183
2184 tlb_flush(env, 1);
2185
2186 env->old_exception = -1;
2187
2188 /* init to reset state */
2189
2190 #ifdef CONFIG_SOFTMMU
2191 env->hflags |= HF_SOFTMMU_MASK;
2192 #endif
2193 env->hflags2 |= HF2_GIF_MASK;
2194
2195 cpu_x86_update_cr0(env, 0x60000010);
2196 env->a20_mask = ~0x0;
2197 env->smbase = 0x30000;
2198
2199 env->idt.limit = 0xffff;
2200 env->gdt.limit = 0xffff;
2201 env->ldt.limit = 0xffff;
2202 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2203 env->tr.limit = 0xffff;
2204 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2205
2206 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2207 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2208 DESC_R_MASK | DESC_A_MASK);
2209 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2210 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2211 DESC_A_MASK);
2212 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2213 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2214 DESC_A_MASK);
2215 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2216 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2217 DESC_A_MASK);
2218 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2219 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2220 DESC_A_MASK);
2221 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2222 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2223 DESC_A_MASK);
2224
2225 env->eip = 0xfff0;
2226 env->regs[R_EDX] = env->cpuid_version;
2227
2228 env->eflags = 0x2;
2229
2230 /* FPU init */
2231 for (i = 0; i < 8; i++) {
2232 env->fptags[i] = 1;
2233 }
2234 env->fpuc = 0x37f;
2235
2236 env->mxcsr = 0x1f80;
2237
2238 env->pat = 0x0007040600070406ULL;
2239 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2240
2241 memset(env->dr, 0, sizeof(env->dr));
2242 env->dr[6] = DR6_FIXED_1;
2243 env->dr[7] = DR7_FIXED_1;
2244 cpu_breakpoint_remove_all(env, BP_CPU);
2245 cpu_watchpoint_remove_all(env, BP_CPU);
2246
2247 #if !defined(CONFIG_USER_ONLY)
2248 /* We hard-wire the BSP to the first CPU. */
2249 if (s->cpu_index == 0) {
2250 apic_designate_bsp(env->apic_state);
2251 }
2252
2253 s->halted = !cpu_is_bsp(cpu);
2254 #endif
2255 }
2256
2257 #ifndef CONFIG_USER_ONLY
2258 bool cpu_is_bsp(X86CPU *cpu)
2259 {
2260 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2261 }
2262
2263 /* TODO: remove me, when reset over QOM tree is implemented */
2264 static void x86_cpu_machine_reset_cb(void *opaque)
2265 {
2266 X86CPU *cpu = opaque;
2267 cpu_reset(CPU(cpu));
2268 }
2269 #endif
2270
2271 static void mce_init(X86CPU *cpu)
2272 {
2273 CPUX86State *cenv = &cpu->env;
2274 unsigned int bank;
2275
2276 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2277 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2278 (CPUID_MCE | CPUID_MCA)) {
2279 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2280 cenv->mcg_ctl = ~(uint64_t)0;
2281 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2282 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2283 }
2284 }
2285 }
2286
2287 #ifndef CONFIG_USER_ONLY
2288 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2289 {
2290 CPUX86State *env = &cpu->env;
2291 DeviceState *dev = DEVICE(cpu);
2292 APICCommonState *apic;
2293 const char *apic_type = "apic";
2294
2295 if (kvm_irqchip_in_kernel()) {
2296 apic_type = "kvm-apic";
2297 } else if (xen_enabled()) {
2298 apic_type = "xen-apic";
2299 }
2300
2301 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2302 if (env->apic_state == NULL) {
2303 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2304 return;
2305 }
2306
2307 object_property_add_child(OBJECT(cpu), "apic",
2308 OBJECT(env->apic_state), NULL);
2309 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2310 /* TODO: convert to link<> */
2311 apic = APIC_COMMON(env->apic_state);
2312 apic->cpu = cpu;
2313 }
2314
2315 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2316 {
2317 CPUX86State *env = &cpu->env;
2318
2319 if (env->apic_state == NULL) {
2320 return;
2321 }
2322
2323 if (qdev_init(env->apic_state)) {
2324 error_setg(errp, "APIC device '%s' could not be initialized",
2325 object_get_typename(OBJECT(env->apic_state)));
2326 return;
2327 }
2328 }
2329 #else
2330 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2331 {
2332 }
2333 #endif
2334
2335 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2336 {
2337 CPUState *cs = CPU(dev);
2338 X86CPU *cpu = X86_CPU(dev);
2339 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2340 CPUX86State *env = &cpu->env;
2341 Error *local_err = NULL;
2342
2343 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2344 env->cpuid_level = 7;
2345 }
2346
2347 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2348 * CPUID[1].EDX.
2349 */
2350 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2351 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2352 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2353 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2354 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2355 & CPUID_EXT2_AMD_ALIASES);
2356 }
2357
2358 if (!kvm_enabled()) {
2359 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2360 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2361 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2362 #ifdef TARGET_X86_64
2363 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2364 #endif
2365 );
2366 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2367 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2368 } else {
2369 if (check_cpuid && kvm_check_features_against_host(cpu)
2370 && enforce_cpuid) {
2371 error_setg(&local_err,
2372 "Host's CPU doesn't support requested features");
2373 goto out;
2374 }
2375 #ifdef CONFIG_KVM
2376 filter_features_for_kvm(cpu);
2377 #endif
2378 }
2379
2380 #ifndef CONFIG_USER_ONLY
2381 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2382
2383 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2384 x86_cpu_apic_create(cpu, &local_err);
2385 if (local_err != NULL) {
2386 goto out;
2387 }
2388 }
2389 #endif
2390
2391 mce_init(cpu);
2392 qemu_init_vcpu(cs);
2393
2394 x86_cpu_apic_realize(cpu, &local_err);
2395 if (local_err != NULL) {
2396 goto out;
2397 }
2398 cpu_reset(cs);
2399
2400 xcc->parent_realize(dev, &local_err);
2401 out:
2402 if (local_err != NULL) {
2403 error_propagate(errp, local_err);
2404 return;
2405 }
2406 }
2407
2408 /* Enables contiguous-apic-ID mode, for compatibility */
2409 static bool compat_apic_id_mode;
2410
2411 void enable_compat_apic_id_mode(void)
2412 {
2413 compat_apic_id_mode = true;
2414 }
2415
2416 /* Calculates initial APIC ID for a specific CPU index
2417 *
2418 * Currently we need to be able to calculate the APIC ID from the CPU index
2419 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2420 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2421 * all CPUs up to max_cpus.
2422 */
2423 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2424 {
2425 uint32_t correct_id;
2426 static bool warned;
2427
2428 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2429 if (compat_apic_id_mode) {
2430 if (cpu_index != correct_id && !warned) {
2431 error_report("APIC IDs set in compatibility mode, "
2432 "CPU topology won't match the configuration");
2433 warned = true;
2434 }
2435 return cpu_index;
2436 } else {
2437 return correct_id;
2438 }
2439 }
2440
2441 static void x86_cpu_initfn(Object *obj)
2442 {
2443 CPUState *cs = CPU(obj);
2444 X86CPU *cpu = X86_CPU(obj);
2445 CPUX86State *env = &cpu->env;
2446 static int inited;
2447
2448 cs->env_ptr = env;
2449 cpu_exec_init(env);
2450
2451 object_property_add(obj, "family", "int",
2452 x86_cpuid_version_get_family,
2453 x86_cpuid_version_set_family, NULL, NULL, NULL);
2454 object_property_add(obj, "model", "int",
2455 x86_cpuid_version_get_model,
2456 x86_cpuid_version_set_model, NULL, NULL, NULL);
2457 object_property_add(obj, "stepping", "int",
2458 x86_cpuid_version_get_stepping,
2459 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2460 object_property_add(obj, "level", "int",
2461 x86_cpuid_get_level,
2462 x86_cpuid_set_level, NULL, NULL, NULL);
2463 object_property_add(obj, "xlevel", "int",
2464 x86_cpuid_get_xlevel,
2465 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2466 object_property_add_str(obj, "vendor",
2467 x86_cpuid_get_vendor,
2468 x86_cpuid_set_vendor, NULL);
2469 object_property_add_str(obj, "model-id",
2470 x86_cpuid_get_model_id,
2471 x86_cpuid_set_model_id, NULL);
2472 object_property_add(obj, "tsc-frequency", "int",
2473 x86_cpuid_get_tsc_freq,
2474 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2475 object_property_add(obj, "apic-id", "int",
2476 x86_cpuid_get_apic_id,
2477 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2478 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2479 x86_cpu_get_feature_words,
2480 NULL, NULL, (void *)env->features, NULL);
2481 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2482 x86_cpu_get_feature_words,
2483 NULL, NULL, (void *)cpu->filtered_features, NULL);
2484
2485 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2486
2487 /* init various static tables used in TCG mode */
2488 if (tcg_enabled() && !inited) {
2489 inited = 1;
2490 optimize_flags_init();
2491 #ifndef CONFIG_USER_ONLY
2492 cpu_set_debug_excp_handler(breakpoint_handler);
2493 #endif
2494 }
2495 }
2496
2497 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2498 {
2499 X86CPU *cpu = X86_CPU(cs);
2500 CPUX86State *env = &cpu->env;
2501
2502 return env->cpuid_apic_id;
2503 }
2504
2505 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2506 {
2507 X86CPU *cpu = X86_CPU(cs);
2508
2509 return cpu->env.cr[0] & CR0_PG_MASK;
2510 }
2511
2512 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2513 {
2514 X86CPU *cpu = X86_CPU(cs);
2515
2516 cpu->env.eip = value;
2517 }
2518
2519 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2520 {
2521 X86CPU *cpu = X86_CPU(cs);
2522
2523 cpu->env.eip = tb->pc - tb->cs_base;
2524 }
2525
2526 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2527 {
2528 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2529 CPUClass *cc = CPU_CLASS(oc);
2530 DeviceClass *dc = DEVICE_CLASS(oc);
2531
2532 xcc->parent_realize = dc->realize;
2533 dc->realize = x86_cpu_realizefn;
2534 dc->bus_type = TYPE_ICC_BUS;
2535
2536 xcc->parent_reset = cc->reset;
2537 cc->reset = x86_cpu_reset;
2538 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2539
2540 cc->do_interrupt = x86_cpu_do_interrupt;
2541 cc->dump_state = x86_cpu_dump_state;
2542 cc->set_pc = x86_cpu_set_pc;
2543 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2544 cc->gdb_read_register = x86_cpu_gdb_read_register;
2545 cc->gdb_write_register = x86_cpu_gdb_write_register;
2546 cc->get_arch_id = x86_cpu_get_arch_id;
2547 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2548 #ifndef CONFIG_USER_ONLY
2549 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2550 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2551 cc->write_elf64_note = x86_cpu_write_elf64_note;
2552 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2553 cc->write_elf32_note = x86_cpu_write_elf32_note;
2554 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2555 cc->vmsd = &vmstate_x86_cpu;
2556 #endif
2557 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2558 }
2559
2560 static const TypeInfo x86_cpu_type_info = {
2561 .name = TYPE_X86_CPU,
2562 .parent = TYPE_CPU,
2563 .instance_size = sizeof(X86CPU),
2564 .instance_init = x86_cpu_initfn,
2565 .abstract = false,
2566 .class_size = sizeof(X86CPUClass),
2567 .class_init = x86_cpu_common_class_init,
2568 };
2569
2570 static void x86_cpu_register_types(void)
2571 {
2572 type_register_static(&x86_cpu_type_info);
2573 }
2574
2575 type_init(x86_cpu_register_types)
Qemu copy for testing