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target-i386/cpu: Name new CPUID bits
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", "f16c", "rdrand", "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, "lwp",
91 "fma4", "tce", NULL, "nodeid_msr",
92 NULL, "tbm", "topoext", "perfctr_core",
93 "perfctr_nb", NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
99 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
100 NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 };
107
108 static const char *svm_feature_name[] = {
109 "npt", "lbrv", "svm_lock", "nrip_save",
110 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
111 NULL, NULL, "pause_filter", NULL,
112 "pfthreshold", NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 };
118
119 static const char *cpuid_7_0_ebx_feature_name[] = {
120 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
121 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
122 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
124 };
125
126 /* collects per-function cpuid data
127 */
128 typedef struct model_features_t {
129 uint32_t *guest_feat;
130 uint32_t *host_feat;
131 uint32_t check_feat;
132 const char **flag_names;
133 uint32_t cpuid;
134 } model_features_t;
135
136 int check_cpuid = 0;
137 int enforce_cpuid = 0;
138
139 #if defined(CONFIG_KVM)
140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
141 (1 << KVM_FEATURE_NOP_IO_DELAY) |
142 (1 << KVM_FEATURE_MMU_OP) |
143 (1 << KVM_FEATURE_CLOCKSOURCE2) |
144 (1 << KVM_FEATURE_ASYNC_PF) |
145 (1 << KVM_FEATURE_STEAL_TIME) |
146 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
148 #else
149 static uint32_t kvm_default_features = 0;
150 static const uint32_t kvm_pv_eoi_features = 0;
151 #endif
152
153 void enable_kvm_pv_eoi(void)
154 {
155 kvm_default_features |= kvm_pv_eoi_features;
156 }
157
158 void host_cpuid(uint32_t function, uint32_t count,
159 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
160 {
161 #if defined(CONFIG_KVM)
162 uint32_t vec[4];
163
164 #ifdef __x86_64__
165 asm volatile("cpuid"
166 : "=a"(vec[0]), "=b"(vec[1]),
167 "=c"(vec[2]), "=d"(vec[3])
168 : "0"(function), "c"(count) : "cc");
169 #else
170 asm volatile("pusha \n\t"
171 "cpuid \n\t"
172 "mov %%eax, 0(%2) \n\t"
173 "mov %%ebx, 4(%2) \n\t"
174 "mov %%ecx, 8(%2) \n\t"
175 "mov %%edx, 12(%2) \n\t"
176 "popa"
177 : : "a"(function), "c"(count), "S"(vec)
178 : "memory", "cc");
179 #endif
180
181 if (eax)
182 *eax = vec[0];
183 if (ebx)
184 *ebx = vec[1];
185 if (ecx)
186 *ecx = vec[2];
187 if (edx)
188 *edx = vec[3];
189 #endif
190 }
191
192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
193
194 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
195 * a substring. ex if !NULL points to the first char after a substring,
196 * otherwise the string is assumed to sized by a terminating nul.
197 * Return lexical ordering of *s1:*s2.
198 */
199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
200 const char *e2)
201 {
202 for (;;) {
203 if (!*s1 || !*s2 || *s1 != *s2)
204 return (*s1 - *s2);
205 ++s1, ++s2;
206 if (s1 == e1 && s2 == e2)
207 return (0);
208 else if (s1 == e1)
209 return (*s2);
210 else if (s2 == e2)
211 return (*s1);
212 }
213 }
214
215 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
216 * '|' delimited (possibly empty) strings in which case search for a match
217 * within the alternatives proceeds left to right. Return 0 for success,
218 * non-zero otherwise.
219 */
220 static int altcmp(const char *s, const char *e, const char *altstr)
221 {
222 const char *p, *q;
223
224 for (q = p = altstr; ; ) {
225 while (*p && *p != '|')
226 ++p;
227 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
228 return (0);
229 if (!*p)
230 return (1);
231 else
232 q = ++p;
233 }
234 }
235
236 /* search featureset for flag *[s..e), if found set corresponding bit in
237 * *pval and return true, otherwise return false
238 */
239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
240 const char **featureset)
241 {
242 uint32_t mask;
243 const char **ppc;
244 bool found = false;
245
246 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
247 if (*ppc && !altcmp(s, e, *ppc)) {
248 *pval |= mask;
249 found = true;
250 }
251 }
252 return found;
253 }
254
255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
256 uint32_t *ext_features,
257 uint32_t *ext2_features,
258 uint32_t *ext3_features,
259 uint32_t *kvm_features,
260 uint32_t *svm_features,
261 uint32_t *cpuid_7_0_ebx_features)
262 {
263 if (!lookup_feature(features, flagname, NULL, feature_name) &&
264 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
265 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
266 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
267 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
268 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
269 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
270 cpuid_7_0_ebx_feature_name))
271 fprintf(stderr, "CPU feature %s not found\n", flagname);
272 }
273
274 typedef struct x86_def_t {
275 struct x86_def_t *next;
276 const char *name;
277 uint32_t level;
278 uint32_t vendor1, vendor2, vendor3;
279 int family;
280 int model;
281 int stepping;
282 int tsc_khz;
283 uint32_t features, ext_features, ext2_features, ext3_features;
284 uint32_t kvm_features, svm_features;
285 uint32_t xlevel;
286 char model_id[48];
287 int vendor_override;
288 /* Store the results of Centaur's CPUID instructions */
289 uint32_t ext4_features;
290 uint32_t xlevel2;
291 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
292 uint32_t cpuid_7_0_ebx_features;
293 } x86_def_t;
294
295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
299 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
300 CPUID_PSE36 | CPUID_FXSR)
301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
303 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
304 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
305 CPUID_PAE | CPUID_SEP | CPUID_APIC)
306
307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
308 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
309 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
310 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
311 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
312 /* partly implemented:
313 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
314 CPUID_PSE36 (needed for Solaris) */
315 /* missing:
316 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
318 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
319 CPUID_EXT_HYPERVISOR)
320 /* missing:
321 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
322 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
324 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
325 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
326 /* missing:
327 CPUID_EXT2_PDPE1GB */
328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
329 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
330 #define TCG_SVM_FEATURES 0
331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
332
333 /* maintains list of cpu model definitions
334 */
335 static x86_def_t *x86_defs = {NULL};
336
337 /* built-in cpu model definitions (deprecated)
338 */
339 static x86_def_t builtin_x86_defs[] = {
340 {
341 .name = "qemu64",
342 .level = 4,
343 .vendor1 = CPUID_VENDOR_AMD_1,
344 .vendor2 = CPUID_VENDOR_AMD_2,
345 .vendor3 = CPUID_VENDOR_AMD_3,
346 .family = 6,
347 .model = 2,
348 .stepping = 3,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
353 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
354 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
356 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
357 .xlevel = 0x8000000A,
358 },
359 {
360 .name = "phenom",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 16,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36 | CPUID_VME | CPUID_HT,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
372 CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
375 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
376 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
377 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
381 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
382 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
383 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
384 .xlevel = 0x8000001A,
385 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
386 },
387 {
388 .name = "core2duo",
389 .level = 10,
390 .family = 6,
391 .model = 15,
392 .stepping = 11,
393 .features = PPRO_FEATURES |
394 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
395 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
396 CPUID_HT | CPUID_TM | CPUID_PBE,
397 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
398 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
399 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
400 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
401 .ext3_features = CPUID_EXT3_LAHF_LM,
402 .xlevel = 0x80000008,
403 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
404 },
405 {
406 .name = "kvm64",
407 .level = 5,
408 .vendor1 = CPUID_VENDOR_INTEL_1,
409 .vendor2 = CPUID_VENDOR_INTEL_2,
410 .vendor3 = CPUID_VENDOR_INTEL_3,
411 .family = 15,
412 .model = 6,
413 .stepping = 1,
414 /* Missing: CPUID_VME, CPUID_HT */
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
420 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
424 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
425 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
426 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
427 .ext3_features = 0,
428 .xlevel = 0x80000008,
429 .model_id = "Common KVM processor"
430 },
431 {
432 .name = "qemu32",
433 .level = 4,
434 .family = 6,
435 .model = 3,
436 .stepping = 3,
437 .features = PPRO_FEATURES,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
439 .xlevel = 0x80000004,
440 },
441 {
442 .name = "kvm32",
443 .level = 5,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
449 .ext_features = CPUID_EXT_SSE3,
450 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
451 .ext3_features = 0,
452 .xlevel = 0x80000008,
453 .model_id = "Common 32-bit KVM processor"
454 },
455 {
456 .name = "coreduo",
457 .level = 10,
458 .family = 6,
459 .model = 14,
460 .stepping = 8,
461 .features = PPRO_FEATURES | CPUID_VME |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
463 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
465 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_NX,
467 .xlevel = 0x80000008,
468 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
469 },
470 {
471 .name = "486",
472 .level = 1,
473 .family = 4,
474 .model = 0,
475 .stepping = 0,
476 .features = I486_FEATURES,
477 .xlevel = 0,
478 },
479 {
480 .name = "pentium",
481 .level = 1,
482 .family = 5,
483 .model = 4,
484 .stepping = 3,
485 .features = PENTIUM_FEATURES,
486 .xlevel = 0,
487 },
488 {
489 .name = "pentium2",
490 .level = 2,
491 .family = 6,
492 .model = 5,
493 .stepping = 2,
494 .features = PENTIUM2_FEATURES,
495 .xlevel = 0,
496 },
497 {
498 .name = "pentium3",
499 .level = 2,
500 .family = 6,
501 .model = 7,
502 .stepping = 3,
503 .features = PENTIUM3_FEATURES,
504 .xlevel = 0,
505 },
506 {
507 .name = "athlon",
508 .level = 2,
509 .vendor1 = CPUID_VENDOR_AMD_1,
510 .vendor2 = CPUID_VENDOR_AMD_2,
511 .vendor3 = CPUID_VENDOR_AMD_3,
512 .family = 6,
513 .model = 2,
514 .stepping = 3,
515 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
516 CPUID_MCA,
517 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
518 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
519 .xlevel = 0x80000008,
520 },
521 {
522 .name = "n270",
523 /* original is on level 10 */
524 .level = 5,
525 .family = 6,
526 .model = 28,
527 .stepping = 2,
528 .features = PPRO_FEATURES |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
530 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 /* Some CPUs got no CPUID_SEP */
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
533 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
534 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
535 CPUID_EXT2_NX,
536 .ext3_features = CPUID_EXT3_LAHF_LM,
537 .xlevel = 0x8000000A,
538 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
539 },
540 {
541 .name = "Conroe",
542 .level = 2,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 6,
547 .model = 2,
548 .stepping = 3,
549 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
553 CPUID_DE | CPUID_FP87,
554 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
559 },
560 {
561 .name = "Penryn",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
575 CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
580 },
581 {
582 .name = "Nehalem",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
596 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
601 },
602 {
603 .name = "Westmere",
604 .level = 11,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 44,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
617 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
618 CPUID_EXT_SSE3,
619 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
620 .ext3_features = CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x8000000A,
622 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
623 },
624 {
625 .name = "SandyBridge",
626 .level = 0xd,
627 .vendor1 = CPUID_VENDOR_INTEL_1,
628 .vendor2 = CPUID_VENDOR_INTEL_2,
629 .vendor3 = CPUID_VENDOR_INTEL_3,
630 .family = 6,
631 .model = 42,
632 .stepping = 1,
633 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
634 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
635 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
636 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
637 CPUID_DE | CPUID_FP87,
638 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
639 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
640 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
641 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
644 CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
648 },
649 {
650 .name = "Opteron_G1",
651 .level = 5,
652 .vendor1 = CPUID_VENDOR_AMD_1,
653 .vendor2 = CPUID_VENDOR_AMD_2,
654 .vendor3 = CPUID_VENDOR_AMD_3,
655 .family = 15,
656 .model = 6,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_SSE3,
664 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
665 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
666 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
667 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
668 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
669 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
670 .xlevel = 0x80000008,
671 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
672 },
673 {
674 .name = "Opteron_G2",
675 .level = 5,
676 .vendor1 = CPUID_VENDOR_AMD_1,
677 .vendor2 = CPUID_VENDOR_AMD_2,
678 .vendor3 = CPUID_VENDOR_AMD_3,
679 .family = 15,
680 .model = 6,
681 .stepping = 1,
682 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
683 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
684 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
685 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
686 CPUID_DE | CPUID_FP87,
687 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
688 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
689 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
690 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
691 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
692 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
693 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
694 CPUID_EXT2_DE | CPUID_EXT2_FPU,
695 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
696 .xlevel = 0x80000008,
697 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
698 },
699 {
700 .name = "Opteron_G3",
701 .level = 5,
702 .vendor1 = CPUID_VENDOR_AMD_1,
703 .vendor2 = CPUID_VENDOR_AMD_2,
704 .vendor3 = CPUID_VENDOR_AMD_3,
705 .family = 15,
706 .model = 6,
707 .stepping = 1,
708 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
709 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
710 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
711 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
712 CPUID_DE | CPUID_FP87,
713 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
714 CPUID_EXT_SSE3,
715 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
716 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
717 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
718 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
719 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
720 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
721 CPUID_EXT2_DE | CPUID_EXT2_FPU,
722 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
723 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
724 .xlevel = 0x80000008,
725 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
726 },
727 {
728 .name = "Opteron_G4",
729 .level = 0xd,
730 .vendor1 = CPUID_VENDOR_AMD_1,
731 .vendor2 = CPUID_VENDOR_AMD_2,
732 .vendor3 = CPUID_VENDOR_AMD_3,
733 .family = 21,
734 .model = 1,
735 .stepping = 2,
736 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
737 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
738 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
739 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
740 CPUID_DE | CPUID_FP87,
741 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
742 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
743 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
744 CPUID_EXT_SSE3,
745 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
746 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
747 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
748 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
749 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
750 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
751 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
752 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
753 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
754 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
755 CPUID_EXT3_LAHF_LM,
756 .xlevel = 0x8000001A,
757 .model_id = "AMD Opteron 62xx class CPU",
758 },
759 };
760
761 #ifdef CONFIG_KVM
762 static int cpu_x86_fill_model_id(char *str)
763 {
764 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
765 int i;
766
767 for (i = 0; i < 3; i++) {
768 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
769 memcpy(str + i * 16 + 0, &eax, 4);
770 memcpy(str + i * 16 + 4, &ebx, 4);
771 memcpy(str + i * 16 + 8, &ecx, 4);
772 memcpy(str + i * 16 + 12, &edx, 4);
773 }
774 return 0;
775 }
776 #endif
777
778 /* Fill a x86_def_t struct with information about the host CPU, and
779 * the CPU features supported by the host hardware + host kernel
780 *
781 * This function may be called only if KVM is enabled.
782 */
783 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
784 {
785 #ifdef CONFIG_KVM
786 KVMState *s = kvm_state;
787 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
788
789 assert(kvm_enabled());
790
791 x86_cpu_def->name = "host";
792 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
793 x86_cpu_def->vendor1 = ebx;
794 x86_cpu_def->vendor2 = edx;
795 x86_cpu_def->vendor3 = ecx;
796
797 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
798 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
799 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
800 x86_cpu_def->stepping = eax & 0x0F;
801
802 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
803 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
804 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
805
806 if (x86_cpu_def->level >= 7) {
807 x86_cpu_def->cpuid_7_0_ebx_features =
808 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
809 } else {
810 x86_cpu_def->cpuid_7_0_ebx_features = 0;
811 }
812
813 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
814 x86_cpu_def->ext2_features =
815 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
816 x86_cpu_def->ext3_features =
817 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
818
819 cpu_x86_fill_model_id(x86_cpu_def->model_id);
820 x86_cpu_def->vendor_override = 0;
821
822 /* Call Centaur's CPUID instruction. */
823 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
824 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
825 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
826 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
827 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
828 if (eax >= 0xC0000001) {
829 /* Support VIA max extended level */
830 x86_cpu_def->xlevel2 = eax;
831 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
832 x86_cpu_def->ext4_features =
833 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
834 }
835 }
836
837 /*
838 * Every SVM feature requires emulation support in KVM - so we can't just
839 * read the host features here. KVM might even support SVM features not
840 * available on the host hardware. Just set all bits and mask out the
841 * unsupported ones later.
842 */
843 x86_cpu_def->svm_features = -1;
844 #endif /* CONFIG_KVM */
845 }
846
847 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
848 {
849 int i;
850
851 for (i = 0; i < 32; ++i)
852 if (1 << i & mask) {
853 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
854 " flag '%s' [0x%08x]\n",
855 f->cpuid >> 16, f->cpuid & 0xffff,
856 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
857 break;
858 }
859 return 0;
860 }
861
862 /* best effort attempt to inform user requested cpu flags aren't making
863 * their way to the guest. Note: ft[].check_feat ideally should be
864 * specified via a guest_def field to suppress report of extraneous flags.
865 *
866 * This function may be called only if KVM is enabled.
867 */
868 static int kvm_check_features_against_host(x86_def_t *guest_def)
869 {
870 x86_def_t host_def;
871 uint32_t mask;
872 int rv, i;
873 struct model_features_t ft[] = {
874 {&guest_def->features, &host_def.features,
875 ~0, feature_name, 0x00000000},
876 {&guest_def->ext_features, &host_def.ext_features,
877 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
878 {&guest_def->ext2_features, &host_def.ext2_features,
879 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
880 {&guest_def->ext3_features, &host_def.ext3_features,
881 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
882
883 assert(kvm_enabled());
884
885 kvm_cpu_fill_host(&host_def);
886 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
887 for (mask = 1; mask; mask <<= 1)
888 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
889 !(*ft[i].host_feat & mask)) {
890 unavailable_host_feature(&ft[i], mask);
891 rv = 1;
892 }
893 return rv;
894 }
895
896 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
897 const char *name, Error **errp)
898 {
899 X86CPU *cpu = X86_CPU(obj);
900 CPUX86State *env = &cpu->env;
901 int64_t value;
902
903 value = (env->cpuid_version >> 8) & 0xf;
904 if (value == 0xf) {
905 value += (env->cpuid_version >> 20) & 0xff;
906 }
907 visit_type_int(v, &value, name, errp);
908 }
909
910 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
911 const char *name, Error **errp)
912 {
913 X86CPU *cpu = X86_CPU(obj);
914 CPUX86State *env = &cpu->env;
915 const int64_t min = 0;
916 const int64_t max = 0xff + 0xf;
917 int64_t value;
918
919 visit_type_int(v, &value, name, errp);
920 if (error_is_set(errp)) {
921 return;
922 }
923 if (value < min || value > max) {
924 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
925 name ? name : "null", value, min, max);
926 return;
927 }
928
929 env->cpuid_version &= ~0xff00f00;
930 if (value > 0x0f) {
931 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
932 } else {
933 env->cpuid_version |= value << 8;
934 }
935 }
936
937 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
938 const char *name, Error **errp)
939 {
940 X86CPU *cpu = X86_CPU(obj);
941 CPUX86State *env = &cpu->env;
942 int64_t value;
943
944 value = (env->cpuid_version >> 4) & 0xf;
945 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
946 visit_type_int(v, &value, name, errp);
947 }
948
949 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
950 const char *name, Error **errp)
951 {
952 X86CPU *cpu = X86_CPU(obj);
953 CPUX86State *env = &cpu->env;
954 const int64_t min = 0;
955 const int64_t max = 0xff;
956 int64_t value;
957
958 visit_type_int(v, &value, name, errp);
959 if (error_is_set(errp)) {
960 return;
961 }
962 if (value < min || value > max) {
963 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
964 name ? name : "null", value, min, max);
965 return;
966 }
967
968 env->cpuid_version &= ~0xf00f0;
969 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
970 }
971
972 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
973 void *opaque, const char *name,
974 Error **errp)
975 {
976 X86CPU *cpu = X86_CPU(obj);
977 CPUX86State *env = &cpu->env;
978 int64_t value;
979
980 value = env->cpuid_version & 0xf;
981 visit_type_int(v, &value, name, errp);
982 }
983
984 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
985 void *opaque, const char *name,
986 Error **errp)
987 {
988 X86CPU *cpu = X86_CPU(obj);
989 CPUX86State *env = &cpu->env;
990 const int64_t min = 0;
991 const int64_t max = 0xf;
992 int64_t value;
993
994 visit_type_int(v, &value, name, errp);
995 if (error_is_set(errp)) {
996 return;
997 }
998 if (value < min || value > max) {
999 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1000 name ? name : "null", value, min, max);
1001 return;
1002 }
1003
1004 env->cpuid_version &= ~0xf;
1005 env->cpuid_version |= value & 0xf;
1006 }
1007
1008 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1009 const char *name, Error **errp)
1010 {
1011 X86CPU *cpu = X86_CPU(obj);
1012
1013 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1014 }
1015
1016 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1017 const char *name, Error **errp)
1018 {
1019 X86CPU *cpu = X86_CPU(obj);
1020
1021 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1022 }
1023
1024 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1025 const char *name, Error **errp)
1026 {
1027 X86CPU *cpu = X86_CPU(obj);
1028
1029 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1030 }
1031
1032 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1033 const char *name, Error **errp)
1034 {
1035 X86CPU *cpu = X86_CPU(obj);
1036
1037 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1038 }
1039
1040 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1041 {
1042 X86CPU *cpu = X86_CPU(obj);
1043 CPUX86State *env = &cpu->env;
1044 char *value;
1045 int i;
1046
1047 value = (char *)g_malloc(12 + 1);
1048 for (i = 0; i < 4; i++) {
1049 value[i ] = env->cpuid_vendor1 >> (8 * i);
1050 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1051 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1052 }
1053 value[12] = '\0';
1054 return value;
1055 }
1056
1057 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1058 Error **errp)
1059 {
1060 X86CPU *cpu = X86_CPU(obj);
1061 CPUX86State *env = &cpu->env;
1062 int i;
1063
1064 if (strlen(value) != 12) {
1065 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1066 "vendor", value);
1067 return;
1068 }
1069
1070 env->cpuid_vendor1 = 0;
1071 env->cpuid_vendor2 = 0;
1072 env->cpuid_vendor3 = 0;
1073 for (i = 0; i < 4; i++) {
1074 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1075 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1076 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1077 }
1078 env->cpuid_vendor_override = 1;
1079 }
1080
1081 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1082 {
1083 X86CPU *cpu = X86_CPU(obj);
1084 CPUX86State *env = &cpu->env;
1085 char *value;
1086 int i;
1087
1088 value = g_malloc(48 + 1);
1089 for (i = 0; i < 48; i++) {
1090 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1091 }
1092 value[48] = '\0';
1093 return value;
1094 }
1095
1096 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1097 Error **errp)
1098 {
1099 X86CPU *cpu = X86_CPU(obj);
1100 CPUX86State *env = &cpu->env;
1101 int c, len, i;
1102
1103 if (model_id == NULL) {
1104 model_id = "";
1105 }
1106 len = strlen(model_id);
1107 memset(env->cpuid_model, 0, 48);
1108 for (i = 0; i < 48; i++) {
1109 if (i >= len) {
1110 c = '\0';
1111 } else {
1112 c = (uint8_t)model_id[i];
1113 }
1114 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1115 }
1116 }
1117
1118 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1119 const char *name, Error **errp)
1120 {
1121 X86CPU *cpu = X86_CPU(obj);
1122 int64_t value;
1123
1124 value = cpu->env.tsc_khz * 1000;
1125 visit_type_int(v, &value, name, errp);
1126 }
1127
1128 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1129 const char *name, Error **errp)
1130 {
1131 X86CPU *cpu = X86_CPU(obj);
1132 const int64_t min = 0;
1133 const int64_t max = INT64_MAX;
1134 int64_t value;
1135
1136 visit_type_int(v, &value, name, errp);
1137 if (error_is_set(errp)) {
1138 return;
1139 }
1140 if (value < min || value > max) {
1141 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1142 name ? name : "null", value, min, max);
1143 return;
1144 }
1145
1146 cpu->env.tsc_khz = value / 1000;
1147 }
1148
1149 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1150 {
1151 unsigned int i;
1152 x86_def_t *def;
1153
1154 char *s = g_strdup(cpu_model);
1155 char *featurestr, *name = strtok(s, ",");
1156 /* Features to be added*/
1157 uint32_t plus_features = 0, plus_ext_features = 0;
1158 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1159 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1160 uint32_t plus_7_0_ebx_features = 0;
1161 /* Features to be removed */
1162 uint32_t minus_features = 0, minus_ext_features = 0;
1163 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1164 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1165 uint32_t minus_7_0_ebx_features = 0;
1166 uint32_t numvalue;
1167
1168 for (def = x86_defs; def; def = def->next)
1169 if (name && !strcmp(name, def->name))
1170 break;
1171 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1172 kvm_cpu_fill_host(x86_cpu_def);
1173 } else if (!def) {
1174 goto error;
1175 } else {
1176 memcpy(x86_cpu_def, def, sizeof(*def));
1177 }
1178
1179 add_flagname_to_bitmaps("hypervisor", &plus_features,
1180 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1181 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1182
1183 featurestr = strtok(NULL, ",");
1184
1185 while (featurestr) {
1186 char *val;
1187 if (featurestr[0] == '+') {
1188 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1189 &plus_ext_features, &plus_ext2_features,
1190 &plus_ext3_features, &plus_kvm_features,
1191 &plus_svm_features, &plus_7_0_ebx_features);
1192 } else if (featurestr[0] == '-') {
1193 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1194 &minus_ext_features, &minus_ext2_features,
1195 &minus_ext3_features, &minus_kvm_features,
1196 &minus_svm_features, &minus_7_0_ebx_features);
1197 } else if ((val = strchr(featurestr, '='))) {
1198 *val = 0; val++;
1199 if (!strcmp(featurestr, "family")) {
1200 char *err;
1201 numvalue = strtoul(val, &err, 0);
1202 if (!*val || *err || numvalue > 0xff + 0xf) {
1203 fprintf(stderr, "bad numerical value %s\n", val);
1204 goto error;
1205 }
1206 x86_cpu_def->family = numvalue;
1207 } else if (!strcmp(featurestr, "model")) {
1208 char *err;
1209 numvalue = strtoul(val, &err, 0);
1210 if (!*val || *err || numvalue > 0xff) {
1211 fprintf(stderr, "bad numerical value %s\n", val);
1212 goto error;
1213 }
1214 x86_cpu_def->model = numvalue;
1215 } else if (!strcmp(featurestr, "stepping")) {
1216 char *err;
1217 numvalue = strtoul(val, &err, 0);
1218 if (!*val || *err || numvalue > 0xf) {
1219 fprintf(stderr, "bad numerical value %s\n", val);
1220 goto error;
1221 }
1222 x86_cpu_def->stepping = numvalue ;
1223 } else if (!strcmp(featurestr, "level")) {
1224 char *err;
1225 numvalue = strtoul(val, &err, 0);
1226 if (!*val || *err) {
1227 fprintf(stderr, "bad numerical value %s\n", val);
1228 goto error;
1229 }
1230 x86_cpu_def->level = numvalue;
1231 } else if (!strcmp(featurestr, "xlevel")) {
1232 char *err;
1233 numvalue = strtoul(val, &err, 0);
1234 if (!*val || *err) {
1235 fprintf(stderr, "bad numerical value %s\n", val);
1236 goto error;
1237 }
1238 if (numvalue < 0x80000000) {
1239 numvalue += 0x80000000;
1240 }
1241 x86_cpu_def->xlevel = numvalue;
1242 } else if (!strcmp(featurestr, "vendor")) {
1243 if (strlen(val) != 12) {
1244 fprintf(stderr, "vendor string must be 12 chars long\n");
1245 goto error;
1246 }
1247 x86_cpu_def->vendor1 = 0;
1248 x86_cpu_def->vendor2 = 0;
1249 x86_cpu_def->vendor3 = 0;
1250 for(i = 0; i < 4; i++) {
1251 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1252 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1253 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1254 }
1255 x86_cpu_def->vendor_override = 1;
1256 } else if (!strcmp(featurestr, "model_id")) {
1257 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1258 val);
1259 } else if (!strcmp(featurestr, "tsc_freq")) {
1260 int64_t tsc_freq;
1261 char *err;
1262
1263 tsc_freq = strtosz_suffix_unit(val, &err,
1264 STRTOSZ_DEFSUFFIX_B, 1000);
1265 if (tsc_freq < 0 || *err) {
1266 fprintf(stderr, "bad numerical value %s\n", val);
1267 goto error;
1268 }
1269 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1270 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1271 char *err;
1272 numvalue = strtoul(val, &err, 0);
1273 if (!*val || *err) {
1274 fprintf(stderr, "bad numerical value %s\n", val);
1275 goto error;
1276 }
1277 hyperv_set_spinlock_retries(numvalue);
1278 } else {
1279 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1280 goto error;
1281 }
1282 } else if (!strcmp(featurestr, "check")) {
1283 check_cpuid = 1;
1284 } else if (!strcmp(featurestr, "enforce")) {
1285 check_cpuid = enforce_cpuid = 1;
1286 } else if (!strcmp(featurestr, "hv_relaxed")) {
1287 hyperv_enable_relaxed_timing(true);
1288 } else if (!strcmp(featurestr, "hv_vapic")) {
1289 hyperv_enable_vapic_recommended(true);
1290 } else {
1291 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1292 goto error;
1293 }
1294 featurestr = strtok(NULL, ",");
1295 }
1296 x86_cpu_def->features |= plus_features;
1297 x86_cpu_def->ext_features |= plus_ext_features;
1298 x86_cpu_def->ext2_features |= plus_ext2_features;
1299 x86_cpu_def->ext3_features |= plus_ext3_features;
1300 x86_cpu_def->kvm_features |= plus_kvm_features;
1301 x86_cpu_def->svm_features |= plus_svm_features;
1302 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1303 x86_cpu_def->features &= ~minus_features;
1304 x86_cpu_def->ext_features &= ~minus_ext_features;
1305 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1306 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1307 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1308 x86_cpu_def->svm_features &= ~minus_svm_features;
1309 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1310 if (check_cpuid && kvm_enabled()) {
1311 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1312 goto error;
1313 }
1314 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1315 x86_cpu_def->level = 7;
1316 }
1317 g_free(s);
1318 return 0;
1319
1320 error:
1321 g_free(s);
1322 return -1;
1323 }
1324
1325 /* generate a composite string into buf of all cpuid names in featureset
1326 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1327 * if flags, suppress names undefined in featureset.
1328 */
1329 static void listflags(char *buf, int bufsize, uint32_t fbits,
1330 const char **featureset, uint32_t flags)
1331 {
1332 const char **p = &featureset[31];
1333 char *q, *b, bit;
1334 int nc;
1335
1336 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1337 *buf = '\0';
1338 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1339 if (fbits & 1 << bit && (*p || !flags)) {
1340 if (*p)
1341 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1342 else
1343 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1344 if (bufsize <= nc) {
1345 if (b) {
1346 memcpy(b, "...", sizeof("..."));
1347 }
1348 return;
1349 }
1350 q += nc;
1351 bufsize -= nc;
1352 }
1353 }
1354
1355 /* generate CPU information. */
1356 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1357 {
1358 x86_def_t *def;
1359 char buf[256];
1360
1361 for (def = x86_defs; def; def = def->next) {
1362 snprintf(buf, sizeof(buf), "%s", def->name);
1363 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1364 }
1365 if (kvm_enabled()) {
1366 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1367 }
1368 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1369 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1370 (*cpu_fprintf)(f, " %s\n", buf);
1371 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1372 (*cpu_fprintf)(f, " %s\n", buf);
1373 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1374 (*cpu_fprintf)(f, " %s\n", buf);
1375 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1376 (*cpu_fprintf)(f, " %s\n", buf);
1377 }
1378
1379 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1380 {
1381 CpuDefinitionInfoList *cpu_list = NULL;
1382 x86_def_t *def;
1383
1384 for (def = x86_defs; def; def = def->next) {
1385 CpuDefinitionInfoList *entry;
1386 CpuDefinitionInfo *info;
1387
1388 info = g_malloc0(sizeof(*info));
1389 info->name = g_strdup(def->name);
1390
1391 entry = g_malloc0(sizeof(*entry));
1392 entry->value = info;
1393 entry->next = cpu_list;
1394 cpu_list = entry;
1395 }
1396
1397 return cpu_list;
1398 }
1399
1400 #ifdef CONFIG_KVM
1401 static void filter_features_for_kvm(X86CPU *cpu)
1402 {
1403 CPUX86State *env = &cpu->env;
1404 KVMState *s = kvm_state;
1405
1406 env->cpuid_features &=
1407 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1408 env->cpuid_ext_features &=
1409 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1410 env->cpuid_ext2_features &=
1411 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1412 env->cpuid_ext3_features &=
1413 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1414 env->cpuid_svm_features &=
1415 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1416 env->cpuid_7_0_ebx_features &=
1417 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1418 env->cpuid_kvm_features &=
1419 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1420 env->cpuid_ext4_features &=
1421 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1422
1423 }
1424 #endif
1425
1426 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1427 {
1428 CPUX86State *env = &cpu->env;
1429 x86_def_t def1, *def = &def1;
1430 Error *error = NULL;
1431
1432 memset(def, 0, sizeof(*def));
1433
1434 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1435 return -1;
1436 if (def->vendor1) {
1437 env->cpuid_vendor1 = def->vendor1;
1438 env->cpuid_vendor2 = def->vendor2;
1439 env->cpuid_vendor3 = def->vendor3;
1440 } else {
1441 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1442 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1443 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1444 }
1445 env->cpuid_vendor_override = def->vendor_override;
1446 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1447 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1448 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1449 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1450 env->cpuid_features = def->features;
1451 env->cpuid_ext_features = def->ext_features;
1452 env->cpuid_ext2_features = def->ext2_features;
1453 env->cpuid_ext3_features = def->ext3_features;
1454 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1455 env->cpuid_kvm_features = def->kvm_features;
1456 env->cpuid_svm_features = def->svm_features;
1457 env->cpuid_ext4_features = def->ext4_features;
1458 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1459 env->cpuid_xlevel2 = def->xlevel2;
1460 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1461 "tsc-frequency", &error);
1462
1463 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1464 * CPUID[1].EDX.
1465 */
1466 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1467 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1468 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1469 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1470 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1471 }
1472
1473 if (!kvm_enabled()) {
1474 env->cpuid_features &= TCG_FEATURES;
1475 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1476 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1477 #ifdef TARGET_X86_64
1478 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1479 #endif
1480 );
1481 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1482 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1483 } else {
1484 #ifdef CONFIG_KVM
1485 filter_features_for_kvm(cpu);
1486 #endif
1487 }
1488 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1489 if (error) {
1490 fprintf(stderr, "%s\n", error_get_pretty(error));
1491 error_free(error);
1492 return -1;
1493 }
1494 return 0;
1495 }
1496
1497 #if !defined(CONFIG_USER_ONLY)
1498
1499 void cpu_clear_apic_feature(CPUX86State *env)
1500 {
1501 env->cpuid_features &= ~CPUID_APIC;
1502 }
1503
1504 #endif /* !CONFIG_USER_ONLY */
1505
1506 /* Initialize list of CPU models, filling some non-static fields if necessary
1507 */
1508 void x86_cpudef_setup(void)
1509 {
1510 int i, j;
1511 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1512
1513 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1514 x86_def_t *def = &builtin_x86_defs[i];
1515 def->next = x86_defs;
1516
1517 /* Look for specific "cpudef" models that */
1518 /* have the QEMU version in .model_id */
1519 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1520 if (strcmp(model_with_versions[j], def->name) == 0) {
1521 pstrcpy(def->model_id, sizeof(def->model_id),
1522 "QEMU Virtual CPU version ");
1523 pstrcat(def->model_id, sizeof(def->model_id),
1524 qemu_get_version());
1525 break;
1526 }
1527 }
1528
1529 x86_defs = def;
1530 }
1531 }
1532
1533 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1534 uint32_t *ecx, uint32_t *edx)
1535 {
1536 *ebx = env->cpuid_vendor1;
1537 *edx = env->cpuid_vendor2;
1538 *ecx = env->cpuid_vendor3;
1539
1540 /* sysenter isn't supported on compatibility mode on AMD, syscall
1541 * isn't supported in compatibility mode on Intel.
1542 * Normally we advertise the actual cpu vendor, but you can override
1543 * this if you want to use KVM's sysenter/syscall emulation
1544 * in compatibility mode and when doing cross vendor migration
1545 */
1546 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1547 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1548 }
1549 }
1550
1551 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1552 uint32_t *eax, uint32_t *ebx,
1553 uint32_t *ecx, uint32_t *edx)
1554 {
1555 /* test if maximum index reached */
1556 if (index & 0x80000000) {
1557 if (index > env->cpuid_xlevel) {
1558 if (env->cpuid_xlevel2 > 0) {
1559 /* Handle the Centaur's CPUID instruction. */
1560 if (index > env->cpuid_xlevel2) {
1561 index = env->cpuid_xlevel2;
1562 } else if (index < 0xC0000000) {
1563 index = env->cpuid_xlevel;
1564 }
1565 } else {
1566 index = env->cpuid_xlevel;
1567 }
1568 }
1569 } else {
1570 if (index > env->cpuid_level)
1571 index = env->cpuid_level;
1572 }
1573
1574 switch(index) {
1575 case 0:
1576 *eax = env->cpuid_level;
1577 get_cpuid_vendor(env, ebx, ecx, edx);
1578 break;
1579 case 1:
1580 *eax = env->cpuid_version;
1581 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1582 *ecx = env->cpuid_ext_features;
1583 *edx = env->cpuid_features;
1584 if (env->nr_cores * env->nr_threads > 1) {
1585 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1586 *edx |= 1 << 28; /* HTT bit */
1587 }
1588 break;
1589 case 2:
1590 /* cache info: needed for Pentium Pro compatibility */
1591 *eax = 1;
1592 *ebx = 0;
1593 *ecx = 0;
1594 *edx = 0x2c307d;
1595 break;
1596 case 4:
1597 /* cache info: needed for Core compatibility */
1598 if (env->nr_cores > 1) {
1599 *eax = (env->nr_cores - 1) << 26;
1600 } else {
1601 *eax = 0;
1602 }
1603 switch (count) {
1604 case 0: /* L1 dcache info */
1605 *eax |= 0x0000121;
1606 *ebx = 0x1c0003f;
1607 *ecx = 0x000003f;
1608 *edx = 0x0000001;
1609 break;
1610 case 1: /* L1 icache info */
1611 *eax |= 0x0000122;
1612 *ebx = 0x1c0003f;
1613 *ecx = 0x000003f;
1614 *edx = 0x0000001;
1615 break;
1616 case 2: /* L2 cache info */
1617 *eax |= 0x0000143;
1618 if (env->nr_threads > 1) {
1619 *eax |= (env->nr_threads - 1) << 14;
1620 }
1621 *ebx = 0x3c0003f;
1622 *ecx = 0x0000fff;
1623 *edx = 0x0000001;
1624 break;
1625 default: /* end of info */
1626 *eax = 0;
1627 *ebx = 0;
1628 *ecx = 0;
1629 *edx = 0;
1630 break;
1631 }
1632 break;
1633 case 5:
1634 /* mwait info: needed for Core compatibility */
1635 *eax = 0; /* Smallest monitor-line size in bytes */
1636 *ebx = 0; /* Largest monitor-line size in bytes */
1637 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1638 *edx = 0;
1639 break;
1640 case 6:
1641 /* Thermal and Power Leaf */
1642 *eax = 0;
1643 *ebx = 0;
1644 *ecx = 0;
1645 *edx = 0;
1646 break;
1647 case 7:
1648 /* Structured Extended Feature Flags Enumeration Leaf */
1649 if (count == 0) {
1650 *eax = 0; /* Maximum ECX value for sub-leaves */
1651 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1652 *ecx = 0; /* Reserved */
1653 *edx = 0; /* Reserved */
1654 } else {
1655 *eax = 0;
1656 *ebx = 0;
1657 *ecx = 0;
1658 *edx = 0;
1659 }
1660 break;
1661 case 9:
1662 /* Direct Cache Access Information Leaf */
1663 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1664 *ebx = 0;
1665 *ecx = 0;
1666 *edx = 0;
1667 break;
1668 case 0xA:
1669 /* Architectural Performance Monitoring Leaf */
1670 if (kvm_enabled()) {
1671 KVMState *s = env->kvm_state;
1672
1673 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1674 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1675 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1676 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1677 } else {
1678 *eax = 0;
1679 *ebx = 0;
1680 *ecx = 0;
1681 *edx = 0;
1682 }
1683 break;
1684 case 0xD:
1685 /* Processor Extended State */
1686 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1687 *eax = 0;
1688 *ebx = 0;
1689 *ecx = 0;
1690 *edx = 0;
1691 break;
1692 }
1693 if (kvm_enabled()) {
1694 KVMState *s = env->kvm_state;
1695
1696 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1697 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1698 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1699 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1700 } else {
1701 *eax = 0;
1702 *ebx = 0;
1703 *ecx = 0;
1704 *edx = 0;
1705 }
1706 break;
1707 case 0x80000000:
1708 *eax = env->cpuid_xlevel;
1709 *ebx = env->cpuid_vendor1;
1710 *edx = env->cpuid_vendor2;
1711 *ecx = env->cpuid_vendor3;
1712 break;
1713 case 0x80000001:
1714 *eax = env->cpuid_version;
1715 *ebx = 0;
1716 *ecx = env->cpuid_ext3_features;
1717 *edx = env->cpuid_ext2_features;
1718
1719 /* The Linux kernel checks for the CMPLegacy bit and
1720 * discards multiple thread information if it is set.
1721 * So dont set it here for Intel to make Linux guests happy.
1722 */
1723 if (env->nr_cores * env->nr_threads > 1) {
1724 uint32_t tebx, tecx, tedx;
1725 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1726 if (tebx != CPUID_VENDOR_INTEL_1 ||
1727 tedx != CPUID_VENDOR_INTEL_2 ||
1728 tecx != CPUID_VENDOR_INTEL_3) {
1729 *ecx |= 1 << 1; /* CmpLegacy bit */
1730 }
1731 }
1732 break;
1733 case 0x80000002:
1734 case 0x80000003:
1735 case 0x80000004:
1736 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1737 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1738 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1739 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1740 break;
1741 case 0x80000005:
1742 /* cache info (L1 cache) */
1743 *eax = 0x01ff01ff;
1744 *ebx = 0x01ff01ff;
1745 *ecx = 0x40020140;
1746 *edx = 0x40020140;
1747 break;
1748 case 0x80000006:
1749 /* cache info (L2 cache) */
1750 *eax = 0;
1751 *ebx = 0x42004200;
1752 *ecx = 0x02008140;
1753 *edx = 0;
1754 break;
1755 case 0x80000008:
1756 /* virtual & phys address size in low 2 bytes. */
1757 /* XXX: This value must match the one used in the MMU code. */
1758 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1759 /* 64 bit processor */
1760 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1761 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1762 } else {
1763 if (env->cpuid_features & CPUID_PSE36)
1764 *eax = 0x00000024; /* 36 bits physical */
1765 else
1766 *eax = 0x00000020; /* 32 bits physical */
1767 }
1768 *ebx = 0;
1769 *ecx = 0;
1770 *edx = 0;
1771 if (env->nr_cores * env->nr_threads > 1) {
1772 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1773 }
1774 break;
1775 case 0x8000000A:
1776 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1777 *eax = 0x00000001; /* SVM Revision */
1778 *ebx = 0x00000010; /* nr of ASIDs */
1779 *ecx = 0;
1780 *edx = env->cpuid_svm_features; /* optional features */
1781 } else {
1782 *eax = 0;
1783 *ebx = 0;
1784 *ecx = 0;
1785 *edx = 0;
1786 }
1787 break;
1788 case 0xC0000000:
1789 *eax = env->cpuid_xlevel2;
1790 *ebx = 0;
1791 *ecx = 0;
1792 *edx = 0;
1793 break;
1794 case 0xC0000001:
1795 /* Support for VIA CPU's CPUID instruction */
1796 *eax = env->cpuid_version;
1797 *ebx = 0;
1798 *ecx = 0;
1799 *edx = env->cpuid_ext4_features;
1800 break;
1801 case 0xC0000002:
1802 case 0xC0000003:
1803 case 0xC0000004:
1804 /* Reserved for the future, and now filled with zero */
1805 *eax = 0;
1806 *ebx = 0;
1807 *ecx = 0;
1808 *edx = 0;
1809 break;
1810 default:
1811 /* reserved values: zero */
1812 *eax = 0;
1813 *ebx = 0;
1814 *ecx = 0;
1815 *edx = 0;
1816 break;
1817 }
1818 }
1819
1820 /* CPUClass::reset() */
1821 static void x86_cpu_reset(CPUState *s)
1822 {
1823 X86CPU *cpu = X86_CPU(s);
1824 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1825 CPUX86State *env = &cpu->env;
1826 int i;
1827
1828 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1829 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1830 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1831 }
1832
1833 xcc->parent_reset(s);
1834
1835
1836 memset(env, 0, offsetof(CPUX86State, breakpoints));
1837
1838 tlb_flush(env, 1);
1839
1840 env->old_exception = -1;
1841
1842 /* init to reset state */
1843
1844 #ifdef CONFIG_SOFTMMU
1845 env->hflags |= HF_SOFTMMU_MASK;
1846 #endif
1847 env->hflags2 |= HF2_GIF_MASK;
1848
1849 cpu_x86_update_cr0(env, 0x60000010);
1850 env->a20_mask = ~0x0;
1851 env->smbase = 0x30000;
1852
1853 env->idt.limit = 0xffff;
1854 env->gdt.limit = 0xffff;
1855 env->ldt.limit = 0xffff;
1856 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1857 env->tr.limit = 0xffff;
1858 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1859
1860 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1861 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1862 DESC_R_MASK | DESC_A_MASK);
1863 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1864 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1865 DESC_A_MASK);
1866 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1867 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1868 DESC_A_MASK);
1869 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1870 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1871 DESC_A_MASK);
1872 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1873 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1874 DESC_A_MASK);
1875 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1876 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1877 DESC_A_MASK);
1878
1879 env->eip = 0xfff0;
1880 env->regs[R_EDX] = env->cpuid_version;
1881
1882 env->eflags = 0x2;
1883
1884 /* FPU init */
1885 for (i = 0; i < 8; i++) {
1886 env->fptags[i] = 1;
1887 }
1888 env->fpuc = 0x37f;
1889
1890 env->mxcsr = 0x1f80;
1891
1892 env->pat = 0x0007040600070406ULL;
1893 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1894
1895 memset(env->dr, 0, sizeof(env->dr));
1896 env->dr[6] = DR6_FIXED_1;
1897 env->dr[7] = DR7_FIXED_1;
1898 cpu_breakpoint_remove_all(env, BP_CPU);
1899 cpu_watchpoint_remove_all(env, BP_CPU);
1900
1901 #if !defined(CONFIG_USER_ONLY)
1902 /* We hard-wire the BSP to the first CPU. */
1903 if (env->cpu_index == 0) {
1904 apic_designate_bsp(env->apic_state);
1905 }
1906
1907 env->halted = !cpu_is_bsp(cpu);
1908 #endif
1909 }
1910
1911 #ifndef CONFIG_USER_ONLY
1912 bool cpu_is_bsp(X86CPU *cpu)
1913 {
1914 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1915 }
1916
1917 /* TODO: remove me, when reset over QOM tree is implemented */
1918 static void x86_cpu_machine_reset_cb(void *opaque)
1919 {
1920 X86CPU *cpu = opaque;
1921 cpu_reset(CPU(cpu));
1922 }
1923 #endif
1924
1925 static void mce_init(X86CPU *cpu)
1926 {
1927 CPUX86State *cenv = &cpu->env;
1928 unsigned int bank;
1929
1930 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1931 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1932 (CPUID_MCE | CPUID_MCA)) {
1933 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1934 cenv->mcg_ctl = ~(uint64_t)0;
1935 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1936 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1937 }
1938 }
1939 }
1940
1941 #define MSI_ADDR_BASE 0xfee00000
1942
1943 #ifndef CONFIG_USER_ONLY
1944 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
1945 {
1946 static int apic_mapped;
1947 CPUX86State *env = &cpu->env;
1948 APICCommonState *apic;
1949 const char *apic_type = "apic";
1950
1951 if (kvm_irqchip_in_kernel()) {
1952 apic_type = "kvm-apic";
1953 } else if (xen_enabled()) {
1954 apic_type = "xen-apic";
1955 }
1956
1957 env->apic_state = qdev_try_create(NULL, apic_type);
1958 if (env->apic_state == NULL) {
1959 error_setg(errp, "APIC device '%s' could not be created", apic_type);
1960 return;
1961 }
1962
1963 object_property_add_child(OBJECT(cpu), "apic",
1964 OBJECT(env->apic_state), NULL);
1965 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
1966 /* TODO: convert to link<> */
1967 apic = APIC_COMMON(env->apic_state);
1968 apic->cpu = cpu;
1969
1970 if (qdev_init(env->apic_state)) {
1971 error_setg(errp, "APIC device '%s' could not be initialized",
1972 object_get_typename(OBJECT(env->apic_state)));
1973 return;
1974 }
1975
1976 /* XXX: mapping more APICs at the same memory location */
1977 if (apic_mapped == 0) {
1978 /* NOTE: the APIC is directly connected to the CPU - it is not
1979 on the global memory bus. */
1980 /* XXX: what if the base changes? */
1981 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
1982 apic_mapped = 1;
1983 }
1984 }
1985 #endif
1986
1987 void x86_cpu_realize(Object *obj, Error **errp)
1988 {
1989 X86CPU *cpu = X86_CPU(obj);
1990
1991 #ifndef CONFIG_USER_ONLY
1992 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1993
1994 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
1995 x86_cpu_apic_init(cpu, errp);
1996 if (error_is_set(errp)) {
1997 return;
1998 }
1999 }
2000 #endif
2001
2002 mce_init(cpu);
2003 qemu_init_vcpu(&cpu->env);
2004 cpu_reset(CPU(cpu));
2005 }
2006
2007 static void x86_cpu_initfn(Object *obj)
2008 {
2009 X86CPU *cpu = X86_CPU(obj);
2010 CPUX86State *env = &cpu->env;
2011 static int inited;
2012
2013 cpu_exec_init(env);
2014
2015 object_property_add(obj, "family", "int",
2016 x86_cpuid_version_get_family,
2017 x86_cpuid_version_set_family, NULL, NULL, NULL);
2018 object_property_add(obj, "model", "int",
2019 x86_cpuid_version_get_model,
2020 x86_cpuid_version_set_model, NULL, NULL, NULL);
2021 object_property_add(obj, "stepping", "int",
2022 x86_cpuid_version_get_stepping,
2023 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2024 object_property_add(obj, "level", "int",
2025 x86_cpuid_get_level,
2026 x86_cpuid_set_level, NULL, NULL, NULL);
2027 object_property_add(obj, "xlevel", "int",
2028 x86_cpuid_get_xlevel,
2029 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2030 object_property_add_str(obj, "vendor",
2031 x86_cpuid_get_vendor,
2032 x86_cpuid_set_vendor, NULL);
2033 object_property_add_str(obj, "model-id",
2034 x86_cpuid_get_model_id,
2035 x86_cpuid_set_model_id, NULL);
2036 object_property_add(obj, "tsc-frequency", "int",
2037 x86_cpuid_get_tsc_freq,
2038 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2039
2040 env->cpuid_apic_id = env->cpu_index;
2041
2042 /* init various static tables used in TCG mode */
2043 if (tcg_enabled() && !inited) {
2044 inited = 1;
2045 optimize_flags_init();
2046 #ifndef CONFIG_USER_ONLY
2047 cpu_set_debug_excp_handler(breakpoint_handler);
2048 #endif
2049 }
2050 }
2051
2052 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2053 {
2054 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2055 CPUClass *cc = CPU_CLASS(oc);
2056
2057 xcc->parent_reset = cc->reset;
2058 cc->reset = x86_cpu_reset;
2059 }
2060
2061 static const TypeInfo x86_cpu_type_info = {
2062 .name = TYPE_X86_CPU,
2063 .parent = TYPE_CPU,
2064 .instance_size = sizeof(X86CPU),
2065 .instance_init = x86_cpu_initfn,
2066 .abstract = false,
2067 .class_size = sizeof(X86CPUClass),
2068 .class_init = x86_cpu_common_class_init,
2069 };
2070
2071 static void x86_cpu_register_types(void)
2072 {
2073 type_register_static(&x86_cpu_type_info);
2074 }
2075
2076 type_init(x86_cpu_register_types)
Qemu copy for testing