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extract/unify the constant 0xfee00000 as APIC_DEFAULT_ADDRESS
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52 {
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60 }
61
62 /* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66 static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75 };
76 static const char *ext_feature_name[] = {
77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
78 "ds_cpl", "vmx", "smx", "est",
79 "tm2", "ssse3", "cid", NULL,
80 "fma", "cx16", "xtpr", "pdcm",
81 NULL, "pcid", "dca", "sse4.1|sse4_1",
82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
83 "tsc-deadline", "aes", "xsave", "osxsave",
84 "avx", "f16c", "rdrand", "hypervisor",
85 };
86 /* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
91 static const char *ext2_feature_name[] = {
92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
99 NULL, "lm|i64", "3dnowext", "3dnow",
100 };
101 static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
104 "3dnowprefetch", "osvw", "ibs", "xop",
105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 };
111
112 static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 };
122
123 static const char *kvm_feature_name[] = {
124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 };
133
134 static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 };
144
145 static const char *cpuid_7_0_ebx_feature_name[] = {
146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150 };
151
152 typedef struct FeatureWordInfo {
153 const char **feat_names;
154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
156 } FeatureWordInfo;
157
158 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
191 };
192
193 const char *get_register_name_32(unsigned int reg)
194 {
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210 }
211
212 /* collects per-function cpuid data
213 */
214 typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
217 FeatureWord feat_word;
218 } model_features_t;
219
220 int check_cpuid = 0;
221 int enforce_cpuid = 0;
222
223 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
228 (1 << KVM_FEATURE_PV_EOI) |
229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
230
231 void disable_kvm_pv_eoi(void)
232 {
233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
234 }
235
236 void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
238 {
239 #if defined(CONFIG_KVM)
240 uint32_t vec[4];
241
242 #ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247 #else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257 #endif
258
259 if (eax)
260 *eax = vec[0];
261 if (ebx)
262 *ebx = vec[1];
263 if (ecx)
264 *ecx = vec[2];
265 if (edx)
266 *edx = vec[3];
267 #endif
268 }
269
270 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277 static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279 {
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291 }
292
293 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298 static int altcmp(const char *s, const char *e, const char *altstr)
299 {
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312 }
313
314 /* search featureset for flag *[s..e), if found set corresponding bit in
315 * *pval and return true, otherwise return false
316 */
317 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
319 {
320 uint32_t mask;
321 const char **ppc;
322 bool found = false;
323
324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
327 found = true;
328 }
329 }
330 return found;
331 }
332
333 static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
335 {
336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
347 }
348
349 typedef struct x86_def_t {
350 const char *name;
351 uint32_t level;
352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
354 int family;
355 int model;
356 int stepping;
357 uint32_t features, ext_features, ext2_features, ext3_features;
358 uint32_t kvm_features, svm_features;
359 uint32_t xlevel;
360 char model_id[48];
361 /* Store the results of Centaur's CPUID instructions */
362 uint32_t ext4_features;
363 uint32_t xlevel2;
364 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
365 uint32_t cpuid_7_0_ebx_features;
366 } x86_def_t;
367
368 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
369 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
370 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
371 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
373 CPUID_PSE36 | CPUID_FXSR)
374 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
375 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
376 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
377 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
378 CPUID_PAE | CPUID_SEP | CPUID_APIC)
379
380 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
381 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
382 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
383 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
384 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
385 /* partly implemented:
386 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
387 CPUID_PSE36 (needed for Solaris) */
388 /* missing:
389 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
390 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
391 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | \
392 CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | \
393 CPUID_EXT_HYPERVISOR)
394 /* missing:
395 CPUID_EXT_PCLMULQDQ, CPUID_EXT_DTES64, CPUID_EXT_DSCPL,
396 CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2,
397 CPUID_EXT_CID, CPUID_EXT_FMA, CPUID_EXT_XTPR, CPUID_EXT_PDCM,
398 CPUID_EXT_PCID, CPUID_EXT_DCA, CPUID_EXT_X2APIC,
399 CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, CPUID_EXT_XSAVE,
400 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
401 CPUID_EXT_RDRAND */
402 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
403 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
404 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
405 /* missing:
406 CPUID_EXT2_PDPE1GB */
407 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
408 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
409 #define TCG_SVM_FEATURES 0
410 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
411 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
412 /* missing:
413 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
414 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
415 CPUID_7_0_EBX_RDSEED */
416
417 /* built-in CPU model definitions
418 */
419 static x86_def_t builtin_x86_defs[] = {
420 {
421 .name = "qemu64",
422 .level = 4,
423 .vendor = CPUID_VENDOR_AMD,
424 .family = 6,
425 .model = 2,
426 .stepping = 3,
427 .features = PPRO_FEATURES |
428 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
429 CPUID_PSE36,
430 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
431 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
433 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
434 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
435 .xlevel = 0x8000000A,
436 },
437 {
438 .name = "phenom",
439 .level = 5,
440 .vendor = CPUID_VENDOR_AMD,
441 .family = 16,
442 .model = 2,
443 .stepping = 3,
444 .features = PPRO_FEATURES |
445 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
446 CPUID_PSE36 | CPUID_VME | CPUID_HT,
447 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
448 CPUID_EXT_POPCNT,
449 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
450 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
451 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
452 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
453 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
454 CPUID_EXT3_CR8LEG,
455 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
456 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
457 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
458 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
459 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
460 .xlevel = 0x8000001A,
461 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
462 },
463 {
464 .name = "core2duo",
465 .level = 10,
466 .vendor = CPUID_VENDOR_INTEL,
467 .family = 6,
468 .model = 15,
469 .stepping = 11,
470 .features = PPRO_FEATURES |
471 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
472 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
473 CPUID_HT | CPUID_TM | CPUID_PBE,
474 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
475 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
476 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
477 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
478 .ext3_features = CPUID_EXT3_LAHF_LM,
479 .xlevel = 0x80000008,
480 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
481 },
482 {
483 .name = "kvm64",
484 .level = 5,
485 .vendor = CPUID_VENDOR_INTEL,
486 .family = 15,
487 .model = 6,
488 .stepping = 1,
489 /* Missing: CPUID_VME, CPUID_HT */
490 .features = PPRO_FEATURES |
491 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
492 CPUID_PSE36,
493 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
494 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
495 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
496 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
497 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
498 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
499 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
500 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
501 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
502 .ext3_features = 0,
503 .xlevel = 0x80000008,
504 .model_id = "Common KVM processor"
505 },
506 {
507 .name = "qemu32",
508 .level = 4,
509 .vendor = CPUID_VENDOR_INTEL,
510 .family = 6,
511 .model = 3,
512 .stepping = 3,
513 .features = PPRO_FEATURES,
514 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
515 .xlevel = 0x80000004,
516 },
517 {
518 .name = "kvm32",
519 .level = 5,
520 .vendor = CPUID_VENDOR_INTEL,
521 .family = 15,
522 .model = 6,
523 .stepping = 1,
524 .features = PPRO_FEATURES |
525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
526 .ext_features = CPUID_EXT_SSE3,
527 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
528 .ext3_features = 0,
529 .xlevel = 0x80000008,
530 .model_id = "Common 32-bit KVM processor"
531 },
532 {
533 .name = "coreduo",
534 .level = 10,
535 .vendor = CPUID_VENDOR_INTEL,
536 .family = 6,
537 .model = 14,
538 .stepping = 8,
539 .features = PPRO_FEATURES | CPUID_VME |
540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
541 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
542 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
543 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
544 .ext2_features = CPUID_EXT2_NX,
545 .xlevel = 0x80000008,
546 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
547 },
548 {
549 .name = "486",
550 .level = 1,
551 .vendor = CPUID_VENDOR_INTEL,
552 .family = 4,
553 .model = 0,
554 .stepping = 0,
555 .features = I486_FEATURES,
556 .xlevel = 0,
557 },
558 {
559 .name = "pentium",
560 .level = 1,
561 .vendor = CPUID_VENDOR_INTEL,
562 .family = 5,
563 .model = 4,
564 .stepping = 3,
565 .features = PENTIUM_FEATURES,
566 .xlevel = 0,
567 },
568 {
569 .name = "pentium2",
570 .level = 2,
571 .vendor = CPUID_VENDOR_INTEL,
572 .family = 6,
573 .model = 5,
574 .stepping = 2,
575 .features = PENTIUM2_FEATURES,
576 .xlevel = 0,
577 },
578 {
579 .name = "pentium3",
580 .level = 2,
581 .vendor = CPUID_VENDOR_INTEL,
582 .family = 6,
583 .model = 7,
584 .stepping = 3,
585 .features = PENTIUM3_FEATURES,
586 .xlevel = 0,
587 },
588 {
589 .name = "athlon",
590 .level = 2,
591 .vendor = CPUID_VENDOR_AMD,
592 .family = 6,
593 .model = 2,
594 .stepping = 3,
595 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
596 CPUID_MCA,
597 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
598 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
599 .xlevel = 0x80000008,
600 },
601 {
602 .name = "n270",
603 /* original is on level 10 */
604 .level = 5,
605 .vendor = CPUID_VENDOR_INTEL,
606 .family = 6,
607 .model = 28,
608 .stepping = 2,
609 .features = PPRO_FEATURES |
610 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
611 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
612 /* Some CPUs got no CPUID_SEP */
613 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
614 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
615 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
616 CPUID_EXT2_NX,
617 .ext3_features = CPUID_EXT3_LAHF_LM,
618 .xlevel = 0x8000000A,
619 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
620 },
621 {
622 .name = "Conroe",
623 .level = 2,
624 .vendor = CPUID_VENDOR_INTEL,
625 .family = 6,
626 .model = 2,
627 .stepping = 3,
628 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
629 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
630 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
631 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
632 CPUID_DE | CPUID_FP87,
633 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
634 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
635 .ext3_features = CPUID_EXT3_LAHF_LM,
636 .xlevel = 0x8000000A,
637 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
638 },
639 {
640 .name = "Penryn",
641 .level = 2,
642 .vendor = CPUID_VENDOR_INTEL,
643 .family = 6,
644 .model = 2,
645 .stepping = 3,
646 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
647 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
648 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
649 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
650 CPUID_DE | CPUID_FP87,
651 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
652 CPUID_EXT_SSE3,
653 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
654 .ext3_features = CPUID_EXT3_LAHF_LM,
655 .xlevel = 0x8000000A,
656 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
657 },
658 {
659 .name = "Nehalem",
660 .level = 2,
661 .vendor = CPUID_VENDOR_INTEL,
662 .family = 6,
663 .model = 2,
664 .stepping = 3,
665 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
666 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
667 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
668 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
669 CPUID_DE | CPUID_FP87,
670 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
671 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
672 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
673 .ext3_features = CPUID_EXT3_LAHF_LM,
674 .xlevel = 0x8000000A,
675 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
676 },
677 {
678 .name = "Westmere",
679 .level = 11,
680 .vendor = CPUID_VENDOR_INTEL,
681 .family = 6,
682 .model = 44,
683 .stepping = 1,
684 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
685 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
686 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
687 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
688 CPUID_DE | CPUID_FP87,
689 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
690 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
691 CPUID_EXT_SSE3,
692 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
693 .ext3_features = CPUID_EXT3_LAHF_LM,
694 .xlevel = 0x8000000A,
695 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
696 },
697 {
698 .name = "SandyBridge",
699 .level = 0xd,
700 .vendor = CPUID_VENDOR_INTEL,
701 .family = 6,
702 .model = 42,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
710 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
711 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
712 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
713 CPUID_EXT_SSE3,
714 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
715 CPUID_EXT2_SYSCALL,
716 .ext3_features = CPUID_EXT3_LAHF_LM,
717 .xlevel = 0x8000000A,
718 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
719 },
720 {
721 .name = "Haswell",
722 .level = 0xd,
723 .vendor = CPUID_VENDOR_INTEL,
724 .family = 6,
725 .model = 60,
726 .stepping = 1,
727 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
728 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
729 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
730 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
731 CPUID_DE | CPUID_FP87,
732 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
733 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
734 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
735 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
736 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
737 CPUID_EXT_PCID,
738 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
739 CPUID_EXT2_SYSCALL,
740 .ext3_features = CPUID_EXT3_LAHF_LM,
741 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
742 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
743 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
744 CPUID_7_0_EBX_RTM,
745 .xlevel = 0x8000000A,
746 .model_id = "Intel Core Processor (Haswell)",
747 },
748 {
749 .name = "Opteron_G1",
750 .level = 5,
751 .vendor = CPUID_VENDOR_AMD,
752 .family = 15,
753 .model = 6,
754 .stepping = 1,
755 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
756 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
757 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
758 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
759 CPUID_DE | CPUID_FP87,
760 .ext_features = CPUID_EXT_SSE3,
761 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
762 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
763 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
764 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
765 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
766 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
767 .xlevel = 0x80000008,
768 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
769 },
770 {
771 .name = "Opteron_G2",
772 .level = 5,
773 .vendor = CPUID_VENDOR_AMD,
774 .family = 15,
775 .model = 6,
776 .stepping = 1,
777 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
778 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
779 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
780 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
781 CPUID_DE | CPUID_FP87,
782 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
783 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
784 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
785 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
786 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
787 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
788 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
789 CPUID_EXT2_DE | CPUID_EXT2_FPU,
790 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
791 .xlevel = 0x80000008,
792 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
793 },
794 {
795 .name = "Opteron_G3",
796 .level = 5,
797 .vendor = CPUID_VENDOR_AMD,
798 .family = 15,
799 .model = 6,
800 .stepping = 1,
801 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
802 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
803 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
804 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
805 CPUID_DE | CPUID_FP87,
806 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
807 CPUID_EXT_SSE3,
808 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
809 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
810 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
811 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
812 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
813 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
814 CPUID_EXT2_DE | CPUID_EXT2_FPU,
815 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
816 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
817 .xlevel = 0x80000008,
818 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
819 },
820 {
821 .name = "Opteron_G4",
822 .level = 0xd,
823 .vendor = CPUID_VENDOR_AMD,
824 .family = 21,
825 .model = 1,
826 .stepping = 2,
827 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
828 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
829 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
830 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
831 CPUID_DE | CPUID_FP87,
832 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
833 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
834 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
835 CPUID_EXT_SSE3,
836 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
837 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
838 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
839 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
840 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
841 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
842 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
843 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
844 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
845 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
846 CPUID_EXT3_LAHF_LM,
847 .xlevel = 0x8000001A,
848 .model_id = "AMD Opteron 62xx class CPU",
849 },
850 {
851 .name = "Opteron_G5",
852 .level = 0xd,
853 .vendor = CPUID_VENDOR_AMD,
854 .family = 21,
855 .model = 2,
856 .stepping = 0,
857 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
861 CPUID_DE | CPUID_FP87,
862 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
863 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
864 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
865 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
866 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
867 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
868 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
869 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
870 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
871 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
872 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
873 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
874 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
875 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
876 CPUID_EXT3_LAHF_LM,
877 .xlevel = 0x8000001A,
878 .model_id = "AMD Opteron 63xx class CPU",
879 },
880 };
881
882 #ifdef CONFIG_KVM
883 static int cpu_x86_fill_model_id(char *str)
884 {
885 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
886 int i;
887
888 for (i = 0; i < 3; i++) {
889 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
890 memcpy(str + i * 16 + 0, &eax, 4);
891 memcpy(str + i * 16 + 4, &ebx, 4);
892 memcpy(str + i * 16 + 8, &ecx, 4);
893 memcpy(str + i * 16 + 12, &edx, 4);
894 }
895 return 0;
896 }
897 #endif
898
899 /* Fill a x86_def_t struct with information about the host CPU, and
900 * the CPU features supported by the host hardware + host kernel
901 *
902 * This function may be called only if KVM is enabled.
903 */
904 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
905 {
906 #ifdef CONFIG_KVM
907 KVMState *s = kvm_state;
908 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
909
910 assert(kvm_enabled());
911
912 x86_cpu_def->name = "host";
913 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
914 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
915
916 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
917 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
918 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
919 x86_cpu_def->stepping = eax & 0x0F;
920
921 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
922 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
923 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
924
925 if (x86_cpu_def->level >= 7) {
926 x86_cpu_def->cpuid_7_0_ebx_features =
927 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
928 } else {
929 x86_cpu_def->cpuid_7_0_ebx_features = 0;
930 }
931
932 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
933 x86_cpu_def->ext2_features =
934 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
935 x86_cpu_def->ext3_features =
936 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
937
938 cpu_x86_fill_model_id(x86_cpu_def->model_id);
939
940 /* Call Centaur's CPUID instruction. */
941 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
942 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
943 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
944 if (eax >= 0xC0000001) {
945 /* Support VIA max extended level */
946 x86_cpu_def->xlevel2 = eax;
947 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
948 x86_cpu_def->ext4_features =
949 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
950 }
951 }
952
953 /* Other KVM-specific feature fields: */
954 x86_cpu_def->svm_features =
955 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
956 x86_cpu_def->kvm_features =
957 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
958
959 #endif /* CONFIG_KVM */
960 }
961
962 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
963 {
964 int i;
965
966 for (i = 0; i < 32; ++i)
967 if (1 << i & mask) {
968 const char *reg = get_register_name_32(f->cpuid_reg);
969 assert(reg);
970 fprintf(stderr, "warning: host doesn't support requested feature: "
971 "CPUID.%02XH:%s%s%s [bit %d]\n",
972 f->cpuid_eax, reg,
973 f->feat_names[i] ? "." : "",
974 f->feat_names[i] ? f->feat_names[i] : "", i);
975 break;
976 }
977 return 0;
978 }
979
980 /* Check if all requested cpu flags are making their way to the guest
981 *
982 * Returns 0 if all flags are supported by the host, non-zero otherwise.
983 *
984 * This function may be called only if KVM is enabled.
985 */
986 static int kvm_check_features_against_host(X86CPU *cpu)
987 {
988 CPUX86State *env = &cpu->env;
989 x86_def_t host_def;
990 uint32_t mask;
991 int rv, i;
992 struct model_features_t ft[] = {
993 {&env->cpuid_features, &host_def.features,
994 FEAT_1_EDX },
995 {&env->cpuid_ext_features, &host_def.ext_features,
996 FEAT_1_ECX },
997 {&env->cpuid_ext2_features, &host_def.ext2_features,
998 FEAT_8000_0001_EDX },
999 {&env->cpuid_ext3_features, &host_def.ext3_features,
1000 FEAT_8000_0001_ECX },
1001 {&env->cpuid_ext4_features, &host_def.ext4_features,
1002 FEAT_C000_0001_EDX },
1003 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1004 FEAT_7_0_EBX },
1005 {&env->cpuid_svm_features, &host_def.svm_features,
1006 FEAT_SVM },
1007 {&env->cpuid_kvm_features, &host_def.kvm_features,
1008 FEAT_KVM },
1009 };
1010
1011 assert(kvm_enabled());
1012
1013 kvm_cpu_fill_host(&host_def);
1014 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1015 FeatureWord w = ft[i].feat_word;
1016 FeatureWordInfo *wi = &feature_word_info[w];
1017 for (mask = 1; mask; mask <<= 1) {
1018 if (*ft[i].guest_feat & mask &&
1019 !(*ft[i].host_feat & mask)) {
1020 unavailable_host_feature(wi, mask);
1021 rv = 1;
1022 }
1023 }
1024 }
1025 return rv;
1026 }
1027
1028 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1029 const char *name, Error **errp)
1030 {
1031 X86CPU *cpu = X86_CPU(obj);
1032 CPUX86State *env = &cpu->env;
1033 int64_t value;
1034
1035 value = (env->cpuid_version >> 8) & 0xf;
1036 if (value == 0xf) {
1037 value += (env->cpuid_version >> 20) & 0xff;
1038 }
1039 visit_type_int(v, &value, name, errp);
1040 }
1041
1042 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1043 const char *name, Error **errp)
1044 {
1045 X86CPU *cpu = X86_CPU(obj);
1046 CPUX86State *env = &cpu->env;
1047 const int64_t min = 0;
1048 const int64_t max = 0xff + 0xf;
1049 int64_t value;
1050
1051 visit_type_int(v, &value, name, errp);
1052 if (error_is_set(errp)) {
1053 return;
1054 }
1055 if (value < min || value > max) {
1056 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1057 name ? name : "null", value, min, max);
1058 return;
1059 }
1060
1061 env->cpuid_version &= ~0xff00f00;
1062 if (value > 0x0f) {
1063 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1064 } else {
1065 env->cpuid_version |= value << 8;
1066 }
1067 }
1068
1069 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1070 const char *name, Error **errp)
1071 {
1072 X86CPU *cpu = X86_CPU(obj);
1073 CPUX86State *env = &cpu->env;
1074 int64_t value;
1075
1076 value = (env->cpuid_version >> 4) & 0xf;
1077 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1078 visit_type_int(v, &value, name, errp);
1079 }
1080
1081 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1082 const char *name, Error **errp)
1083 {
1084 X86CPU *cpu = X86_CPU(obj);
1085 CPUX86State *env = &cpu->env;
1086 const int64_t min = 0;
1087 const int64_t max = 0xff;
1088 int64_t value;
1089
1090 visit_type_int(v, &value, name, errp);
1091 if (error_is_set(errp)) {
1092 return;
1093 }
1094 if (value < min || value > max) {
1095 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1096 name ? name : "null", value, min, max);
1097 return;
1098 }
1099
1100 env->cpuid_version &= ~0xf00f0;
1101 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1102 }
1103
1104 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1105 void *opaque, const char *name,
1106 Error **errp)
1107 {
1108 X86CPU *cpu = X86_CPU(obj);
1109 CPUX86State *env = &cpu->env;
1110 int64_t value;
1111
1112 value = env->cpuid_version & 0xf;
1113 visit_type_int(v, &value, name, errp);
1114 }
1115
1116 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1117 void *opaque, const char *name,
1118 Error **errp)
1119 {
1120 X86CPU *cpu = X86_CPU(obj);
1121 CPUX86State *env = &cpu->env;
1122 const int64_t min = 0;
1123 const int64_t max = 0xf;
1124 int64_t value;
1125
1126 visit_type_int(v, &value, name, errp);
1127 if (error_is_set(errp)) {
1128 return;
1129 }
1130 if (value < min || value > max) {
1131 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1132 name ? name : "null", value, min, max);
1133 return;
1134 }
1135
1136 env->cpuid_version &= ~0xf;
1137 env->cpuid_version |= value & 0xf;
1138 }
1139
1140 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1141 const char *name, Error **errp)
1142 {
1143 X86CPU *cpu = X86_CPU(obj);
1144
1145 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1146 }
1147
1148 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1149 const char *name, Error **errp)
1150 {
1151 X86CPU *cpu = X86_CPU(obj);
1152
1153 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1154 }
1155
1156 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1157 const char *name, Error **errp)
1158 {
1159 X86CPU *cpu = X86_CPU(obj);
1160
1161 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1162 }
1163
1164 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1165 const char *name, Error **errp)
1166 {
1167 X86CPU *cpu = X86_CPU(obj);
1168
1169 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1170 }
1171
1172 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1173 {
1174 X86CPU *cpu = X86_CPU(obj);
1175 CPUX86State *env = &cpu->env;
1176 char *value;
1177
1178 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1179 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1180 env->cpuid_vendor3);
1181 return value;
1182 }
1183
1184 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1185 Error **errp)
1186 {
1187 X86CPU *cpu = X86_CPU(obj);
1188 CPUX86State *env = &cpu->env;
1189 int i;
1190
1191 if (strlen(value) != CPUID_VENDOR_SZ) {
1192 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1193 "vendor", value);
1194 return;
1195 }
1196
1197 env->cpuid_vendor1 = 0;
1198 env->cpuid_vendor2 = 0;
1199 env->cpuid_vendor3 = 0;
1200 for (i = 0; i < 4; i++) {
1201 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1202 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1203 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1204 }
1205 }
1206
1207 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1208 {
1209 X86CPU *cpu = X86_CPU(obj);
1210 CPUX86State *env = &cpu->env;
1211 char *value;
1212 int i;
1213
1214 value = g_malloc(48 + 1);
1215 for (i = 0; i < 48; i++) {
1216 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1217 }
1218 value[48] = '\0';
1219 return value;
1220 }
1221
1222 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1223 Error **errp)
1224 {
1225 X86CPU *cpu = X86_CPU(obj);
1226 CPUX86State *env = &cpu->env;
1227 int c, len, i;
1228
1229 if (model_id == NULL) {
1230 model_id = "";
1231 }
1232 len = strlen(model_id);
1233 memset(env->cpuid_model, 0, 48);
1234 for (i = 0; i < 48; i++) {
1235 if (i >= len) {
1236 c = '\0';
1237 } else {
1238 c = (uint8_t)model_id[i];
1239 }
1240 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1241 }
1242 }
1243
1244 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1245 const char *name, Error **errp)
1246 {
1247 X86CPU *cpu = X86_CPU(obj);
1248 int64_t value;
1249
1250 value = cpu->env.tsc_khz * 1000;
1251 visit_type_int(v, &value, name, errp);
1252 }
1253
1254 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1255 const char *name, Error **errp)
1256 {
1257 X86CPU *cpu = X86_CPU(obj);
1258 const int64_t min = 0;
1259 const int64_t max = INT64_MAX;
1260 int64_t value;
1261
1262 visit_type_int(v, &value, name, errp);
1263 if (error_is_set(errp)) {
1264 return;
1265 }
1266 if (value < min || value > max) {
1267 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1268 name ? name : "null", value, min, max);
1269 return;
1270 }
1271
1272 cpu->env.tsc_khz = value / 1000;
1273 }
1274
1275 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1276 {
1277 x86_def_t *def;
1278 int i;
1279
1280 if (name == NULL) {
1281 return -1;
1282 }
1283 if (kvm_enabled() && strcmp(name, "host") == 0) {
1284 kvm_cpu_fill_host(x86_cpu_def);
1285 return 0;
1286 }
1287
1288 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1289 def = &builtin_x86_defs[i];
1290 if (strcmp(name, def->name) == 0) {
1291 memcpy(x86_cpu_def, def, sizeof(*def));
1292 /* sysenter isn't supported in compatibility mode on AMD,
1293 * syscall isn't supported in compatibility mode on Intel.
1294 * Normally we advertise the actual CPU vendor, but you can
1295 * override this using the 'vendor' property if you want to use
1296 * KVM's sysenter/syscall emulation in compatibility mode and
1297 * when doing cross vendor migration
1298 */
1299 if (kvm_enabled()) {
1300 uint32_t ebx = 0, ecx = 0, edx = 0;
1301 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1302 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1303 }
1304 return 0;
1305 }
1306 }
1307
1308 return -1;
1309 }
1310
1311 /* Parse "+feature,-feature,feature=foo" CPU feature string
1312 */
1313 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1314 {
1315 char *featurestr; /* Single 'key=value" string being parsed */
1316 /* Features to be added */
1317 FeatureWordArray plus_features = { 0 };
1318 /* Features to be removed */
1319 FeatureWordArray minus_features = { 0 };
1320 uint32_t numvalue;
1321 CPUX86State *env = &cpu->env;
1322
1323 featurestr = features ? strtok(features, ",") : NULL;
1324
1325 while (featurestr) {
1326 char *val;
1327 if (featurestr[0] == '+') {
1328 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1329 } else if (featurestr[0] == '-') {
1330 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1331 } else if ((val = strchr(featurestr, '='))) {
1332 *val = 0; val++;
1333 if (!strcmp(featurestr, "family")) {
1334 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1335 } else if (!strcmp(featurestr, "model")) {
1336 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1337 } else if (!strcmp(featurestr, "stepping")) {
1338 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1339 } else if (!strcmp(featurestr, "level")) {
1340 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1341 } else if (!strcmp(featurestr, "xlevel")) {
1342 char *err;
1343 char num[32];
1344
1345 numvalue = strtoul(val, &err, 0);
1346 if (!*val || *err) {
1347 error_setg(errp, "bad numerical value %s", val);
1348 goto out;
1349 }
1350 if (numvalue < 0x80000000) {
1351 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1352 ", fixup will be removed in future versions\n");
1353 numvalue += 0x80000000;
1354 }
1355 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1356 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1357 } else if (!strcmp(featurestr, "vendor")) {
1358 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1359 } else if (!strcmp(featurestr, "model_id")) {
1360 object_property_parse(OBJECT(cpu), val, "model-id", errp);
1361 } else if (!strcmp(featurestr, "tsc_freq")) {
1362 int64_t tsc_freq;
1363 char *err;
1364 char num[32];
1365
1366 tsc_freq = strtosz_suffix_unit(val, &err,
1367 STRTOSZ_DEFSUFFIX_B, 1000);
1368 if (tsc_freq < 0 || *err) {
1369 error_setg(errp, "bad numerical value %s", val);
1370 goto out;
1371 }
1372 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1373 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1374 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1375 char *err;
1376 numvalue = strtoul(val, &err, 0);
1377 if (!*val || *err) {
1378 error_setg(errp, "bad numerical value %s", val);
1379 goto out;
1380 }
1381 hyperv_set_spinlock_retries(numvalue);
1382 } else {
1383 error_setg(errp, "unrecognized feature %s", featurestr);
1384 goto out;
1385 }
1386 } else if (!strcmp(featurestr, "check")) {
1387 check_cpuid = 1;
1388 } else if (!strcmp(featurestr, "enforce")) {
1389 check_cpuid = enforce_cpuid = 1;
1390 } else if (!strcmp(featurestr, "hv_relaxed")) {
1391 hyperv_enable_relaxed_timing(true);
1392 } else if (!strcmp(featurestr, "hv_vapic")) {
1393 hyperv_enable_vapic_recommended(true);
1394 } else {
1395 error_setg(errp, "feature string `%s' not in format (+feature|"
1396 "-feature|feature=xyz)", featurestr);
1397 goto out;
1398 }
1399 if (error_is_set(errp)) {
1400 goto out;
1401 }
1402 featurestr = strtok(NULL, ",");
1403 }
1404 env->cpuid_features |= plus_features[FEAT_1_EDX];
1405 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1406 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1407 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1408 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1409 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1410 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1411 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1412 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1413 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1414 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1415 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1416 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1417 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1418 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1419 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1420
1421 out:
1422 return;
1423 }
1424
1425 /* generate a composite string into buf of all cpuid names in featureset
1426 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1427 * if flags, suppress names undefined in featureset.
1428 */
1429 static void listflags(char *buf, int bufsize, uint32_t fbits,
1430 const char **featureset, uint32_t flags)
1431 {
1432 const char **p = &featureset[31];
1433 char *q, *b, bit;
1434 int nc;
1435
1436 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1437 *buf = '\0';
1438 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1439 if (fbits & 1 << bit && (*p || !flags)) {
1440 if (*p)
1441 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1442 else
1443 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1444 if (bufsize <= nc) {
1445 if (b) {
1446 memcpy(b, "...", sizeof("..."));
1447 }
1448 return;
1449 }
1450 q += nc;
1451 bufsize -= nc;
1452 }
1453 }
1454
1455 /* generate CPU information. */
1456 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1457 {
1458 x86_def_t *def;
1459 char buf[256];
1460 int i;
1461
1462 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1463 def = &builtin_x86_defs[i];
1464 snprintf(buf, sizeof(buf), "%s", def->name);
1465 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1466 }
1467 if (kvm_enabled()) {
1468 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1469 }
1470 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1471 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1472 (*cpu_fprintf)(f, " %s\n", buf);
1473 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1474 (*cpu_fprintf)(f, " %s\n", buf);
1475 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1476 (*cpu_fprintf)(f, " %s\n", buf);
1477 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1478 (*cpu_fprintf)(f, " %s\n", buf);
1479 }
1480
1481 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1482 {
1483 CpuDefinitionInfoList *cpu_list = NULL;
1484 x86_def_t *def;
1485 int i;
1486
1487 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1488 CpuDefinitionInfoList *entry;
1489 CpuDefinitionInfo *info;
1490
1491 def = &builtin_x86_defs[i];
1492 info = g_malloc0(sizeof(*info));
1493 info->name = g_strdup(def->name);
1494
1495 entry = g_malloc0(sizeof(*entry));
1496 entry->value = info;
1497 entry->next = cpu_list;
1498 cpu_list = entry;
1499 }
1500
1501 return cpu_list;
1502 }
1503
1504 #ifdef CONFIG_KVM
1505 static void filter_features_for_kvm(X86CPU *cpu)
1506 {
1507 CPUX86State *env = &cpu->env;
1508 KVMState *s = kvm_state;
1509
1510 env->cpuid_features &=
1511 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1512 env->cpuid_ext_features &=
1513 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1514 env->cpuid_ext2_features &=
1515 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1516 env->cpuid_ext3_features &=
1517 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1518 env->cpuid_svm_features &=
1519 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1520 env->cpuid_7_0_ebx_features &=
1521 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1522 env->cpuid_kvm_features &=
1523 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1524 env->cpuid_ext4_features &=
1525 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1526
1527 }
1528 #endif
1529
1530 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1531 {
1532 CPUX86State *env = &cpu->env;
1533 x86_def_t def1, *def = &def1;
1534
1535 memset(def, 0, sizeof(*def));
1536
1537 if (cpu_x86_find_by_name(def, name) < 0) {
1538 error_setg(errp, "Unable to find CPU definition: %s", name);
1539 return;
1540 }
1541
1542 if (kvm_enabled()) {
1543 def->kvm_features |= kvm_default_features;
1544 }
1545 def->ext_features |= CPUID_EXT_HYPERVISOR;
1546
1547 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1548 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1549 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1550 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1551 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1552 env->cpuid_features = def->features;
1553 env->cpuid_ext_features = def->ext_features;
1554 env->cpuid_ext2_features = def->ext2_features;
1555 env->cpuid_ext3_features = def->ext3_features;
1556 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1557 env->cpuid_kvm_features = def->kvm_features;
1558 env->cpuid_svm_features = def->svm_features;
1559 env->cpuid_ext4_features = def->ext4_features;
1560 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1561 env->cpuid_xlevel2 = def->xlevel2;
1562
1563 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1564 }
1565
1566 X86CPU *cpu_x86_init(const char *cpu_model)
1567 {
1568 X86CPU *cpu = NULL;
1569 CPUX86State *env;
1570 gchar **model_pieces;
1571 char *name, *features;
1572 Error *error = NULL;
1573
1574 model_pieces = g_strsplit(cpu_model, ",", 2);
1575 if (!model_pieces[0]) {
1576 error_setg(&error, "Invalid/empty CPU model name");
1577 goto out;
1578 }
1579 name = model_pieces[0];
1580 features = model_pieces[1];
1581
1582 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1583 env = &cpu->env;
1584 env->cpu_model_str = cpu_model;
1585
1586 cpu_x86_register(cpu, name, &error);
1587 if (error) {
1588 goto out;
1589 }
1590
1591 cpu_x86_parse_featurestr(cpu, features, &error);
1592 if (error) {
1593 goto out;
1594 }
1595
1596 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1597 if (error) {
1598 goto out;
1599 }
1600
1601 out:
1602 g_strfreev(model_pieces);
1603 if (error) {
1604 fprintf(stderr, "%s\n", error_get_pretty(error));
1605 error_free(error);
1606 if (cpu != NULL) {
1607 object_unref(OBJECT(cpu));
1608 cpu = NULL;
1609 }
1610 }
1611 return cpu;
1612 }
1613
1614 #if !defined(CONFIG_USER_ONLY)
1615
1616 void cpu_clear_apic_feature(CPUX86State *env)
1617 {
1618 env->cpuid_features &= ~CPUID_APIC;
1619 }
1620
1621 #endif /* !CONFIG_USER_ONLY */
1622
1623 /* Initialize list of CPU models, filling some non-static fields if necessary
1624 */
1625 void x86_cpudef_setup(void)
1626 {
1627 int i, j;
1628 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1629
1630 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1631 x86_def_t *def = &builtin_x86_defs[i];
1632
1633 /* Look for specific "cpudef" models that */
1634 /* have the QEMU version in .model_id */
1635 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1636 if (strcmp(model_with_versions[j], def->name) == 0) {
1637 pstrcpy(def->model_id, sizeof(def->model_id),
1638 "QEMU Virtual CPU version ");
1639 pstrcat(def->model_id, sizeof(def->model_id),
1640 qemu_get_version());
1641 break;
1642 }
1643 }
1644 }
1645 }
1646
1647 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1648 uint32_t *ecx, uint32_t *edx)
1649 {
1650 *ebx = env->cpuid_vendor1;
1651 *edx = env->cpuid_vendor2;
1652 *ecx = env->cpuid_vendor3;
1653 }
1654
1655 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1656 uint32_t *eax, uint32_t *ebx,
1657 uint32_t *ecx, uint32_t *edx)
1658 {
1659 X86CPU *cpu = x86_env_get_cpu(env);
1660 CPUState *cs = CPU(cpu);
1661
1662 /* test if maximum index reached */
1663 if (index & 0x80000000) {
1664 if (index > env->cpuid_xlevel) {
1665 if (env->cpuid_xlevel2 > 0) {
1666 /* Handle the Centaur's CPUID instruction. */
1667 if (index > env->cpuid_xlevel2) {
1668 index = env->cpuid_xlevel2;
1669 } else if (index < 0xC0000000) {
1670 index = env->cpuid_xlevel;
1671 }
1672 } else {
1673 /* Intel documentation states that invalid EAX input will
1674 * return the same information as EAX=cpuid_level
1675 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1676 */
1677 index = env->cpuid_level;
1678 }
1679 }
1680 } else {
1681 if (index > env->cpuid_level)
1682 index = env->cpuid_level;
1683 }
1684
1685 switch(index) {
1686 case 0:
1687 *eax = env->cpuid_level;
1688 get_cpuid_vendor(env, ebx, ecx, edx);
1689 break;
1690 case 1:
1691 *eax = env->cpuid_version;
1692 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1693 *ecx = env->cpuid_ext_features;
1694 *edx = env->cpuid_features;
1695 if (cs->nr_cores * cs->nr_threads > 1) {
1696 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1697 *edx |= 1 << 28; /* HTT bit */
1698 }
1699 break;
1700 case 2:
1701 /* cache info: needed for Pentium Pro compatibility */
1702 *eax = 1;
1703 *ebx = 0;
1704 *ecx = 0;
1705 *edx = 0x2c307d;
1706 break;
1707 case 4:
1708 /* cache info: needed for Core compatibility */
1709 if (cs->nr_cores > 1) {
1710 *eax = (cs->nr_cores - 1) << 26;
1711 } else {
1712 *eax = 0;
1713 }
1714 switch (count) {
1715 case 0: /* L1 dcache info */
1716 *eax |= 0x0000121;
1717 *ebx = 0x1c0003f;
1718 *ecx = 0x000003f;
1719 *edx = 0x0000001;
1720 break;
1721 case 1: /* L1 icache info */
1722 *eax |= 0x0000122;
1723 *ebx = 0x1c0003f;
1724 *ecx = 0x000003f;
1725 *edx = 0x0000001;
1726 break;
1727 case 2: /* L2 cache info */
1728 *eax |= 0x0000143;
1729 if (cs->nr_threads > 1) {
1730 *eax |= (cs->nr_threads - 1) << 14;
1731 }
1732 *ebx = 0x3c0003f;
1733 *ecx = 0x0000fff;
1734 *edx = 0x0000001;
1735 break;
1736 default: /* end of info */
1737 *eax = 0;
1738 *ebx = 0;
1739 *ecx = 0;
1740 *edx = 0;
1741 break;
1742 }
1743 break;
1744 case 5:
1745 /* mwait info: needed for Core compatibility */
1746 *eax = 0; /* Smallest monitor-line size in bytes */
1747 *ebx = 0; /* Largest monitor-line size in bytes */
1748 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1749 *edx = 0;
1750 break;
1751 case 6:
1752 /* Thermal and Power Leaf */
1753 *eax = 0;
1754 *ebx = 0;
1755 *ecx = 0;
1756 *edx = 0;
1757 break;
1758 case 7:
1759 /* Structured Extended Feature Flags Enumeration Leaf */
1760 if (count == 0) {
1761 *eax = 0; /* Maximum ECX value for sub-leaves */
1762 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1763 *ecx = 0; /* Reserved */
1764 *edx = 0; /* Reserved */
1765 } else {
1766 *eax = 0;
1767 *ebx = 0;
1768 *ecx = 0;
1769 *edx = 0;
1770 }
1771 break;
1772 case 9:
1773 /* Direct Cache Access Information Leaf */
1774 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1775 *ebx = 0;
1776 *ecx = 0;
1777 *edx = 0;
1778 break;
1779 case 0xA:
1780 /* Architectural Performance Monitoring Leaf */
1781 if (kvm_enabled()) {
1782 KVMState *s = cs->kvm_state;
1783
1784 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1785 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1786 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1787 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1788 } else {
1789 *eax = 0;
1790 *ebx = 0;
1791 *ecx = 0;
1792 *edx = 0;
1793 }
1794 break;
1795 case 0xD:
1796 /* Processor Extended State */
1797 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1798 *eax = 0;
1799 *ebx = 0;
1800 *ecx = 0;
1801 *edx = 0;
1802 break;
1803 }
1804 if (kvm_enabled()) {
1805 KVMState *s = cs->kvm_state;
1806
1807 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1808 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1809 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1810 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1811 } else {
1812 *eax = 0;
1813 *ebx = 0;
1814 *ecx = 0;
1815 *edx = 0;
1816 }
1817 break;
1818 case 0x80000000:
1819 *eax = env->cpuid_xlevel;
1820 *ebx = env->cpuid_vendor1;
1821 *edx = env->cpuid_vendor2;
1822 *ecx = env->cpuid_vendor3;
1823 break;
1824 case 0x80000001:
1825 *eax = env->cpuid_version;
1826 *ebx = 0;
1827 *ecx = env->cpuid_ext3_features;
1828 *edx = env->cpuid_ext2_features;
1829
1830 /* The Linux kernel checks for the CMPLegacy bit and
1831 * discards multiple thread information if it is set.
1832 * So dont set it here for Intel to make Linux guests happy.
1833 */
1834 if (cs->nr_cores * cs->nr_threads > 1) {
1835 uint32_t tebx, tecx, tedx;
1836 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1837 if (tebx != CPUID_VENDOR_INTEL_1 ||
1838 tedx != CPUID_VENDOR_INTEL_2 ||
1839 tecx != CPUID_VENDOR_INTEL_3) {
1840 *ecx |= 1 << 1; /* CmpLegacy bit */
1841 }
1842 }
1843 break;
1844 case 0x80000002:
1845 case 0x80000003:
1846 case 0x80000004:
1847 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1848 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1849 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1850 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1851 break;
1852 case 0x80000005:
1853 /* cache info (L1 cache) */
1854 *eax = 0x01ff01ff;
1855 *ebx = 0x01ff01ff;
1856 *ecx = 0x40020140;
1857 *edx = 0x40020140;
1858 break;
1859 case 0x80000006:
1860 /* cache info (L2 cache) */
1861 *eax = 0;
1862 *ebx = 0x42004200;
1863 *ecx = 0x02008140;
1864 *edx = 0;
1865 break;
1866 case 0x80000008:
1867 /* virtual & phys address size in low 2 bytes. */
1868 /* XXX: This value must match the one used in the MMU code. */
1869 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1870 /* 64 bit processor */
1871 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1872 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1873 } else {
1874 if (env->cpuid_features & CPUID_PSE36)
1875 *eax = 0x00000024; /* 36 bits physical */
1876 else
1877 *eax = 0x00000020; /* 32 bits physical */
1878 }
1879 *ebx = 0;
1880 *ecx = 0;
1881 *edx = 0;
1882 if (cs->nr_cores * cs->nr_threads > 1) {
1883 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1884 }
1885 break;
1886 case 0x8000000A:
1887 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1888 *eax = 0x00000001; /* SVM Revision */
1889 *ebx = 0x00000010; /* nr of ASIDs */
1890 *ecx = 0;
1891 *edx = env->cpuid_svm_features; /* optional features */
1892 } else {
1893 *eax = 0;
1894 *ebx = 0;
1895 *ecx = 0;
1896 *edx = 0;
1897 }
1898 break;
1899 case 0xC0000000:
1900 *eax = env->cpuid_xlevel2;
1901 *ebx = 0;
1902 *ecx = 0;
1903 *edx = 0;
1904 break;
1905 case 0xC0000001:
1906 /* Support for VIA CPU's CPUID instruction */
1907 *eax = env->cpuid_version;
1908 *ebx = 0;
1909 *ecx = 0;
1910 *edx = env->cpuid_ext4_features;
1911 break;
1912 case 0xC0000002:
1913 case 0xC0000003:
1914 case 0xC0000004:
1915 /* Reserved for the future, and now filled with zero */
1916 *eax = 0;
1917 *ebx = 0;
1918 *ecx = 0;
1919 *edx = 0;
1920 break;
1921 default:
1922 /* reserved values: zero */
1923 *eax = 0;
1924 *ebx = 0;
1925 *ecx = 0;
1926 *edx = 0;
1927 break;
1928 }
1929 }
1930
1931 /* CPUClass::reset() */
1932 static void x86_cpu_reset(CPUState *s)
1933 {
1934 X86CPU *cpu = X86_CPU(s);
1935 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1936 CPUX86State *env = &cpu->env;
1937 int i;
1938
1939 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1940 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1941 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1942 }
1943
1944 xcc->parent_reset(s);
1945
1946
1947 memset(env, 0, offsetof(CPUX86State, breakpoints));
1948
1949 tlb_flush(env, 1);
1950
1951 env->old_exception = -1;
1952
1953 /* init to reset state */
1954
1955 #ifdef CONFIG_SOFTMMU
1956 env->hflags |= HF_SOFTMMU_MASK;
1957 #endif
1958 env->hflags2 |= HF2_GIF_MASK;
1959
1960 cpu_x86_update_cr0(env, 0x60000010);
1961 env->a20_mask = ~0x0;
1962 env->smbase = 0x30000;
1963
1964 env->idt.limit = 0xffff;
1965 env->gdt.limit = 0xffff;
1966 env->ldt.limit = 0xffff;
1967 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1968 env->tr.limit = 0xffff;
1969 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1970
1971 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1972 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1973 DESC_R_MASK | DESC_A_MASK);
1974 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1975 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1976 DESC_A_MASK);
1977 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1978 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1979 DESC_A_MASK);
1980 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1981 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1982 DESC_A_MASK);
1983 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1984 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1985 DESC_A_MASK);
1986 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1987 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1988 DESC_A_MASK);
1989
1990 env->eip = 0xfff0;
1991 env->regs[R_EDX] = env->cpuid_version;
1992
1993 env->eflags = 0x2;
1994
1995 /* FPU init */
1996 for (i = 0; i < 8; i++) {
1997 env->fptags[i] = 1;
1998 }
1999 env->fpuc = 0x37f;
2000
2001 env->mxcsr = 0x1f80;
2002
2003 env->pat = 0x0007040600070406ULL;
2004 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2005
2006 memset(env->dr, 0, sizeof(env->dr));
2007 env->dr[6] = DR6_FIXED_1;
2008 env->dr[7] = DR7_FIXED_1;
2009 cpu_breakpoint_remove_all(env, BP_CPU);
2010 cpu_watchpoint_remove_all(env, BP_CPU);
2011
2012 #if !defined(CONFIG_USER_ONLY)
2013 /* We hard-wire the BSP to the first CPU. */
2014 if (s->cpu_index == 0) {
2015 apic_designate_bsp(env->apic_state);
2016 }
2017
2018 s->halted = !cpu_is_bsp(cpu);
2019 #endif
2020 }
2021
2022 #ifndef CONFIG_USER_ONLY
2023 bool cpu_is_bsp(X86CPU *cpu)
2024 {
2025 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2026 }
2027
2028 /* TODO: remove me, when reset over QOM tree is implemented */
2029 static void x86_cpu_machine_reset_cb(void *opaque)
2030 {
2031 X86CPU *cpu = opaque;
2032 cpu_reset(CPU(cpu));
2033 }
2034 #endif
2035
2036 static void mce_init(X86CPU *cpu)
2037 {
2038 CPUX86State *cenv = &cpu->env;
2039 unsigned int bank;
2040
2041 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2042 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2043 (CPUID_MCE | CPUID_MCA)) {
2044 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2045 cenv->mcg_ctl = ~(uint64_t)0;
2046 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2047 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2048 }
2049 }
2050 }
2051
2052 #ifndef CONFIG_USER_ONLY
2053 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2054 {
2055 static int apic_mapped;
2056 CPUX86State *env = &cpu->env;
2057 APICCommonState *apic;
2058 const char *apic_type = "apic";
2059
2060 if (kvm_irqchip_in_kernel()) {
2061 apic_type = "kvm-apic";
2062 } else if (xen_enabled()) {
2063 apic_type = "xen-apic";
2064 }
2065
2066 env->apic_state = qdev_try_create(NULL, apic_type);
2067 if (env->apic_state == NULL) {
2068 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2069 return;
2070 }
2071
2072 object_property_add_child(OBJECT(cpu), "apic",
2073 OBJECT(env->apic_state), NULL);
2074 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2075 /* TODO: convert to link<> */
2076 apic = APIC_COMMON(env->apic_state);
2077 apic->cpu = cpu;
2078
2079 if (qdev_init(env->apic_state)) {
2080 error_setg(errp, "APIC device '%s' could not be initialized",
2081 object_get_typename(OBJECT(env->apic_state)));
2082 return;
2083 }
2084
2085 /* XXX: mapping more APICs at the same memory location */
2086 if (apic_mapped == 0) {
2087 /* NOTE: the APIC is directly connected to the CPU - it is not
2088 on the global memory bus. */
2089 /* XXX: what if the base changes? */
2090 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(env->apic_state), 0,
2091 APIC_DEFAULT_ADDRESS, 0x1000);
2092 apic_mapped = 1;
2093 }
2094 }
2095 #endif
2096
2097 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2098 {
2099 X86CPU *cpu = X86_CPU(dev);
2100 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2101 CPUX86State *env = &cpu->env;
2102 #ifndef CONFIG_USER_ONLY
2103 Error *local_err = NULL;
2104 #endif
2105
2106 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2107 env->cpuid_level = 7;
2108 }
2109
2110 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2111 * CPUID[1].EDX.
2112 */
2113 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2114 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2115 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2116 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2117 env->cpuid_ext2_features |= (env->cpuid_features
2118 & CPUID_EXT2_AMD_ALIASES);
2119 }
2120
2121 if (!kvm_enabled()) {
2122 env->cpuid_features &= TCG_FEATURES;
2123 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2124 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2125 #ifdef TARGET_X86_64
2126 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2127 #endif
2128 );
2129 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2130 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2131 } else {
2132 if (check_cpuid && kvm_check_features_against_host(cpu)
2133 && enforce_cpuid) {
2134 error_setg(errp, "Host's CPU doesn't support requested features");
2135 return;
2136 }
2137 #ifdef CONFIG_KVM
2138 filter_features_for_kvm(cpu);
2139 #endif
2140 }
2141
2142 #ifndef CONFIG_USER_ONLY
2143 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2144
2145 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2146 x86_cpu_apic_init(cpu, &local_err);
2147 if (local_err != NULL) {
2148 error_propagate(errp, local_err);
2149 return;
2150 }
2151 }
2152 #endif
2153
2154 mce_init(cpu);
2155 qemu_init_vcpu(&cpu->env);
2156 cpu_reset(CPU(cpu));
2157
2158 xcc->parent_realize(dev, errp);
2159 }
2160
2161 /* Enables contiguous-apic-ID mode, for compatibility */
2162 static bool compat_apic_id_mode;
2163
2164 void enable_compat_apic_id_mode(void)
2165 {
2166 compat_apic_id_mode = true;
2167 }
2168
2169 /* Calculates initial APIC ID for a specific CPU index
2170 *
2171 * Currently we need to be able to calculate the APIC ID from the CPU index
2172 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2173 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2174 * all CPUs up to max_cpus.
2175 */
2176 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2177 {
2178 uint32_t correct_id;
2179 static bool warned;
2180
2181 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2182 if (compat_apic_id_mode) {
2183 if (cpu_index != correct_id && !warned) {
2184 error_report("APIC IDs set in compatibility mode, "
2185 "CPU topology won't match the configuration");
2186 warned = true;
2187 }
2188 return cpu_index;
2189 } else {
2190 return correct_id;
2191 }
2192 }
2193
2194 static void x86_cpu_initfn(Object *obj)
2195 {
2196 CPUState *cs = CPU(obj);
2197 X86CPU *cpu = X86_CPU(obj);
2198 CPUX86State *env = &cpu->env;
2199 static int inited;
2200
2201 cs->env_ptr = env;
2202 cpu_exec_init(env);
2203
2204 object_property_add(obj, "family", "int",
2205 x86_cpuid_version_get_family,
2206 x86_cpuid_version_set_family, NULL, NULL, NULL);
2207 object_property_add(obj, "model", "int",
2208 x86_cpuid_version_get_model,
2209 x86_cpuid_version_set_model, NULL, NULL, NULL);
2210 object_property_add(obj, "stepping", "int",
2211 x86_cpuid_version_get_stepping,
2212 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2213 object_property_add(obj, "level", "int",
2214 x86_cpuid_get_level,
2215 x86_cpuid_set_level, NULL, NULL, NULL);
2216 object_property_add(obj, "xlevel", "int",
2217 x86_cpuid_get_xlevel,
2218 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2219 object_property_add_str(obj, "vendor",
2220 x86_cpuid_get_vendor,
2221 x86_cpuid_set_vendor, NULL);
2222 object_property_add_str(obj, "model-id",
2223 x86_cpuid_get_model_id,
2224 x86_cpuid_set_model_id, NULL);
2225 object_property_add(obj, "tsc-frequency", "int",
2226 x86_cpuid_get_tsc_freq,
2227 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2228
2229 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2230
2231 /* init various static tables used in TCG mode */
2232 if (tcg_enabled() && !inited) {
2233 inited = 1;
2234 optimize_flags_init();
2235 #ifndef CONFIG_USER_ONLY
2236 cpu_set_debug_excp_handler(breakpoint_handler);
2237 #endif
2238 }
2239 }
2240
2241 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2242 {
2243 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2244 CPUClass *cc = CPU_CLASS(oc);
2245 DeviceClass *dc = DEVICE_CLASS(oc);
2246
2247 xcc->parent_realize = dc->realize;
2248 dc->realize = x86_cpu_realizefn;
2249
2250 xcc->parent_reset = cc->reset;
2251 cc->reset = x86_cpu_reset;
2252
2253 cc->do_interrupt = x86_cpu_do_interrupt;
2254 cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2255 }
2256
2257 static const TypeInfo x86_cpu_type_info = {
2258 .name = TYPE_X86_CPU,
2259 .parent = TYPE_CPU,
2260 .instance_size = sizeof(X86CPU),
2261 .instance_init = x86_cpu_initfn,
2262 .abstract = false,
2263 .class_size = sizeof(X86CPUClass),
2264 .class_init = x86_cpu_common_class_init,
2265 };
2266
2267 static void x86_cpu_register_types(void)
2268 {
2269 type_register_static(&x86_cpu_type_info);
2270 }
2271
2272 type_init(x86_cpu_register_types)
Qemu copy for testing