target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #include "cpu-defs.h"
  38
  39 #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
  40 #define USE_CODE_COPY
  41 #endif
  42 #if defined(__linux__) && defined(CONFIG_SOFTMMU) && defined(__i386__) && !defined(TARGET_X86_64)
  43 #define USE_KQEMU
  44 #endif
  45
  46 #define R_EAX 0
  47 #define R_ECX 1
  48 #define R_EDX 2
  49 #define R_EBX 3
  50 #define R_ESP 4
  51 #define R_EBP 5
  52 #define R_ESI 6
  53 #define R_EDI 7
  54
  55 #define R_AL 0
  56 #define R_CL 1
  57 #define R_DL 2
  58 #define R_BL 3
  59 #define R_AH 4
  60 #define R_CH 5
  61 #define R_DH 6
  62 #define R_BH 7
  63
  64 #define R_ES 0
  65 #define R_CS 1
  66 #define R_SS 2
  67 #define R_DS 3
  68 #define R_FS 4
  69 #define R_GS 5
  70
  71 /* segment descriptor fields */
  72 #define DESC_G_MASK     (1 << 23)
  73 #define DESC_B_SHIFT    22
  74 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  75 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  76 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  77 #define DESC_AVL_MASK   (1 << 20)
  78 #define DESC_P_MASK     (1 << 15)
  79 #define DESC_DPL_SHIFT  13
  80 #define DESC_S_MASK     (1 << 12)
  81 #define DESC_TYPE_SHIFT 8
  82 #define DESC_A_MASK     (1 << 8)
  83
  84 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  85 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  86 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  87
  88 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  89 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  90
  91 #define DESC_TSS_BUSY_MASK (1 << 9)
  92
  93 /* eflags masks */
  94 #define CC_C    0x0001
  95 #define CC_P    0x0004
  96 #define CC_A    0x0010
  97 #define CC_Z    0x0040
  98 #define CC_S    0x0080
  99 #define CC_O    0x0800
 100
 101 #define TF_SHIFT   8
 102 #define IOPL_SHIFT 12
 103 #define VM_SHIFT   17
 104
 105 #define TF_MASK                 0x00000100
 106 #define IF_MASK                 0x00000200
 107 #define DF_MASK                 0x00000400
 108 #define IOPL_MASK               0x00003000
 109 #define NT_MASK                 0x00004000
 110 #define RF_MASK                 0x00010000
 111 #define VM_MASK                 0x00020000
 112 #define AC_MASK                 0x00040000
 113 #define VIF_MASK                0x00080000
 114 #define VIP_MASK                0x00100000
 115 #define ID_MASK                 0x00200000
 116
 117 /* hidden flags - used internally by qemu to represent additionnal cpu
 118    states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
 119    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
 120    with eflags. */
 121 /* current cpl */
 122 #define HF_CPL_SHIFT         0
 123 /* true if soft mmu is being used */
 124 #define HF_SOFTMMU_SHIFT     2
 125 /* true if hardware interrupts must be disabled for next instruction */
 126 #define HF_INHIBIT_IRQ_SHIFT 3
 127 /* 16 or 32 segments */
 128 #define HF_CS32_SHIFT        4
 129 #define HF_SS32_SHIFT        5
 130 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 131 #define HF_ADDSEG_SHIFT      6
 132 /* copy of CR0.PE (protected mode) */
 133 #define HF_PE_SHIFT          7
 134 #define HF_TF_SHIFT          8 /* must be same as eflags */
 135 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 136 #define HF_EM_SHIFT         10
 137 #define HF_TS_SHIFT         11
 138 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 139 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 140 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 141 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 142 #define HF_VM_SHIFT         17 /* must be same as eflags */
 143
 144 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 145 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 146 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 147 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 148 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 149 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 150 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 151 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 152 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 153 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 154 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 155 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 156 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 157 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 158
 159 #define CR0_PE_MASK  (1 << 0)
 160 #define CR0_MP_MASK  (1 << 1)
 161 #define CR0_EM_MASK  (1 << 2)
 162 #define CR0_TS_MASK  (1 << 3)
 163 #define CR0_ET_MASK  (1 << 4)
 164 #define CR0_NE_MASK  (1 << 5)
 165 #define CR0_WP_MASK  (1 << 16)
 166 #define CR0_AM_MASK  (1 << 18)
 167 #define CR0_PG_MASK  (1 << 31)
 168
 169 #define CR4_VME_MASK  (1 << 0)
 170 #define CR4_PVI_MASK  (1 << 1)
 171 #define CR4_TSD_MASK  (1 << 2)
 172 #define CR4_DE_MASK   (1 << 3)
 173 #define CR4_PSE_MASK  (1 << 4)
 174 #define CR4_PAE_MASK  (1 << 5)
 175 #define CR4_PGE_MASK  (1 << 7)
 176 #define CR4_PCE_MASK  (1 << 8)
 177 #define CR4_OSFXSR_MASK (1 << 9)
 178 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 179
 180 #define PG_PRESENT_BIT  0
 181 #define PG_RW_BIT       1
 182 #define PG_USER_BIT     2
 183 #define PG_PWT_BIT      3
 184 #define PG_PCD_BIT      4
 185 #define PG_ACCESSED_BIT 5
 186 #define PG_DIRTY_BIT    6
 187 #define PG_PSE_BIT      7
 188 #define PG_GLOBAL_BIT   8
 189
 190 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 191 #define PG_RW_MASK       (1 << PG_RW_BIT)
 192 #define PG_USER_MASK     (1 << PG_USER_BIT)
 193 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 194 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 195 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 196 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 197 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 198 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 199
 200 #define PG_ERROR_W_BIT     1
 201
 202 #define PG_ERROR_P_MASK    0x01
 203 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 204 #define PG_ERROR_U_MASK    0x04
 205 #define PG_ERROR_RSVD_MASK 0x08
 206
 207 #define MSR_IA32_APICBASE               0x1b
 208 #define MSR_IA32_APICBASE_BSP           (1<<8)
 209 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 210 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 211
 212 #define MSR_IA32_SYSENTER_CS            0x174
 213 #define MSR_IA32_SYSENTER_ESP           0x175
 214 #define MSR_IA32_SYSENTER_EIP           0x176
 215
 216 #define MSR_EFER                        0xc0000080
 217
 218 #define MSR_EFER_SCE   (1 << 0)
 219 #define MSR_EFER_LME   (1 << 8)
 220 #define MSR_EFER_LMA   (1 << 10)
 221 #define MSR_EFER_NXE   (1 << 11)
 222 #define MSR_EFER_FFXSR (1 << 14)
 223
 224 #define MSR_STAR                        0xc0000081
 225 #define MSR_LSTAR                       0xc0000082
 226 #define MSR_CSTAR                       0xc0000083
 227 #define MSR_FMASK                       0xc0000084
 228 #define MSR_FSBASE                      0xc0000100
 229 #define MSR_GSBASE                      0xc0000101
 230 #define MSR_KERNELGSBASE                0xc0000102
 231
 232 /* cpuid_features bits */
 233 #define CPUID_FP87 (1 << 0)
 234 #define CPUID_VME  (1 << 1)
 235 #define CPUID_DE   (1 << 2)
 236 #define CPUID_PSE  (1 << 3)
 237 #define CPUID_TSC  (1 << 4)
 238 #define CPUID_MSR  (1 << 5)
 239 #define CPUID_PAE  (1 << 6)
 240 #define CPUID_MCE  (1 << 7)
 241 #define CPUID_CX8  (1 << 8)
 242 #define CPUID_APIC (1 << 9)
 243 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 244 #define CPUID_MTRR (1 << 12)
 245 #define CPUID_PGE  (1 << 13)
 246 #define CPUID_MCA  (1 << 14)
 247 #define CPUID_CMOV (1 << 15)
 248 /* ... */
 249 #define CPUID_MMX  (1 << 23)
 250 #define CPUID_FXSR (1 << 24)
 251 #define CPUID_SSE  (1 << 25)
 252 #define CPUID_SSE2 (1 << 26)
 253
 254 #define CPUID_EXT_SS3      (1 << 0)
 255 #define CPUID_EXT_MONITOR  (1 << 3)
 256 #define CPUID_EXT_CX16     (1 << 13)
 257
 258 #define CPUID_EXT2_SYSCALL (1 << 11)
 259 #define CPUID_EXT2_NX      (1 << 20)
 260 #define CPUID_EXT2_LM      (1 << 29)
 261
 262 #define EXCP00_DIVZ     0
 263 #define EXCP01_SSTP     1
 264 #define EXCP02_NMI      2
 265 #define EXCP03_INT3     3
 266 #define EXCP04_INTO     4
 267 #define EXCP05_BOUND    5
 268 #define EXCP06_ILLOP    6
 269 #define EXCP07_PREX     7
 270 #define EXCP08_DBLE     8
 271 #define EXCP09_XERR     9
 272 #define EXCP0A_TSS      10
 273 #define EXCP0B_NOSEG    11
 274 #define EXCP0C_STACK    12
 275 #define EXCP0D_GPF      13
 276 #define EXCP0E_PAGE     14
 277 #define EXCP10_COPR     16
 278 #define EXCP11_ALGN     17
 279 #define EXCP12_MCHK     18
 280
 281 enum {
 282     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 283     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 284
 285     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 286     CC_OP_MULW,
 287     CC_OP_MULL,
 288     CC_OP_MULQ,
 289
 290     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 291     CC_OP_ADDW,
 292     CC_OP_ADDL,
 293     CC_OP_ADDQ,
 294
 295     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 296     CC_OP_ADCW,
 297     CC_OP_ADCL,
 298     CC_OP_ADCQ,
 299
 300     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 301     CC_OP_SUBW,
 302     CC_OP_SUBL,
 303     CC_OP_SUBQ,
 304
 305     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 306     CC_OP_SBBW,
 307     CC_OP_SBBL,
 308     CC_OP_SBBQ,
 309
 310     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 311     CC_OP_LOGICW,
 312     CC_OP_LOGICL,
 313     CC_OP_LOGICQ,
 314
 315     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 316     CC_OP_INCW,
 317     CC_OP_INCL,
 318     CC_OP_INCQ,
 319
 320     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 321     CC_OP_DECW,
 322     CC_OP_DECL,
 323     CC_OP_DECQ,
 324
 325     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 326     CC_OP_SHLW,
 327     CC_OP_SHLL,
 328     CC_OP_SHLQ,
 329
 330     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 331     CC_OP_SARW,
 332     CC_OP_SARL,
 333     CC_OP_SARQ,
 334
 335     CC_OP_NB,
 336 };
 337
 338 #if (defined(__i386__) || defined(__x86_64__)) && !defined(_BSD)
 339 #define USE_X86LDOUBLE
 340 #endif
 341
 342 #ifdef USE_X86LDOUBLE
 343 typedef long double CPU86_LDouble;
 344 #else
 345 typedef double CPU86_LDouble;
 346 #endif
 347
 348 typedef struct SegmentCache {
 349     uint32_t selector;
 350     target_ulong base;
 351     uint32_t limit;
 352     uint32_t flags;
 353 } SegmentCache;
 354
 355 typedef union {
 356     uint8_t _b[16];
 357     uint16_t _w[8];
 358     uint32_t _l[4];
 359     uint64_t _q[2];
 360     float _s[4];
 361     double _d[2];
 362 } XMMReg;
 363
 364 typedef union {
 365     uint8_t _b[8];
 366     uint16_t _w[2];
 367     uint32_t _l[1];
 368     uint64_t q;
 369 } MMXReg;
 370
 371 #ifdef WORDS_BIGENDIAN
 372 #define XMM_B(n) _b[15 - (n)]
 373 #define XMM_W(n) _w[7 - (n)]
 374 #define XMM_L(n) _l[3 - (n)]
 375 #define XMM_S(n) _s[3 - (n)]
 376 #define XMM_Q(n) _q[1 - (n)]
 377 #define XMM_D(n) _d[1 - (n)]
 378
 379 #define MMX_B(n) _b[7 - (n)]
 380 #define MMX_W(n) _w[3 - (n)]
 381 #define MMX_L(n) _l[1 - (n)]
 382 #else
 383 #define XMM_B(n) _b[n]
 384 #define XMM_W(n) _w[n]
 385 #define XMM_L(n) _l[n]
 386 #define XMM_S(n) _s[n]
 387 #define XMM_Q(n) _q[n]
 388 #define XMM_D(n) _d[n]
 389
 390 #define MMX_B(n) _b[n]
 391 #define MMX_W(n) _w[n]
 392 #define MMX_L(n) _l[n]
 393 #endif
 394 #define MMX_Q(n) q
 395
 396 #ifdef TARGET_X86_64
 397 #define CPU_NB_REGS 16
 398 #else
 399 #define CPU_NB_REGS 8
 400 #endif
 401
 402 typedef struct CPUX86State {
 403 #if TARGET_LONG_BITS > HOST_LONG_BITS
 404     /* temporaries if we cannot store them in host registers */
 405     target_ulong t0, t1, t2;
 406 #endif
 407
 408     /* standard registers */
 409     target_ulong regs[CPU_NB_REGS];
 410     target_ulong eip;
 411     target_ulong eflags; /* eflags register. During CPU emulation, CC
 412                         flags and DF are set to zero because they are
 413                         stored elsewhere */
 414
 415     /* emulator internal eflags handling */
 416     target_ulong cc_src;
 417     target_ulong cc_dst;
 418     uint32_t cc_op;
 419     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 420     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 421
 422     /* segments */
 423     SegmentCache segs[6]; /* selector values */
 424     SegmentCache ldt;
 425     SegmentCache tr;
 426     SegmentCache gdt; /* only base and limit are used */
 427     SegmentCache idt; /* only base and limit are used */
 428
 429     target_ulong cr[5]; /* NOTE: cr1 is unused */
 430     uint32_t a20_mask;
 431
 432     /* FPU state */
 433     unsigned int fpstt; /* top of stack index */
 434     unsigned int fpus;
 435     unsigned int fpuc;
 436     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 437     union {
 438 #ifdef USE_X86LDOUBLE
 439         CPU86_LDouble d __attribute__((aligned(16)));
 440 #else
 441         CPU86_LDouble d;
 442 #endif
 443         MMXReg mmx;
 444     } fpregs[8];
 445
 446     /* emulator internal variables */
 447     CPU86_LDouble ft0;
 448     union {
 449         float f;
 450         double d;
 451         int i32;
 452         int64_t i64;
 453     } fp_convert;
 454
 455     uint32_t mxcsr;
 456     XMMReg xmm_regs[CPU_NB_REGS];
 457     XMMReg xmm_t0;
 458     MMXReg mmx_t0;
 459
 460     /* sysenter registers */
 461     uint32_t sysenter_cs;
 462     uint32_t sysenter_esp;
 463     uint32_t sysenter_eip;
 464 #ifdef TARGET_X86_64
 465     target_ulong efer;
 466     target_ulong star;
 467     target_ulong lstar;
 468     target_ulong cstar;
 469     target_ulong fmask;
 470     target_ulong kernelgsbase;
 471 #endif
 472
 473     /* temporary data for USE_CODE_COPY mode */
 474 #ifdef USE_CODE_COPY
 475     uint32_t tmp0;
 476     uint32_t saved_esp;
 477     int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
 478 #endif
 479
 480     /* exception/interrupt handling */
 481     jmp_buf jmp_env;
 482     int exception_index;
 483     int error_code;
 484     int exception_is_int;
 485     target_ulong exception_next_eip;
 486     struct TranslationBlock *current_tb; /* currently executing TB */
 487     target_ulong dr[8]; /* debug registers */
 488     int interrupt_request;
 489     int user_mode_only; /* user mode only simulation */
 490
 491     /* soft mmu support */
 492     /* in order to avoid passing too many arguments to the memory
 493        write helpers, we store some rarely used information in the CPU
 494        context) */
 495     unsigned long mem_write_pc; /* host pc at which the memory was
 496                                    written */
 497     target_ulong mem_write_vaddr; /* target virtual addr at which the
 498                                      memory was written */
 499     /* 0 = kernel, 1 = user */
 500     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 501     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 502
 503     /* from this point: preserved by CPU reset */
 504     /* ice debug support */
 505     target_ulong breakpoints[MAX_BREAKPOINTS];
 506     int nb_breakpoints;
 507     int singlestep_enabled;
 508
 509     /* processor features (e.g. for CPUID insn) */
 510     uint32_t cpuid_vendor1;
 511     uint32_t cpuid_vendor2;
 512     uint32_t cpuid_vendor3;
 513     uint32_t cpuid_version;
 514     uint32_t cpuid_features;
 515     uint32_t cpuid_ext_features;
 516
 517 #ifdef USE_KQEMU
 518     int kqemu_enabled;
 519 #endif
 520     /* in order to simplify APIC support, we leave this pointer to the
 521        user */
 522     struct APICState *apic_state;
 523     /* user data */
 524     void *opaque;
 525 } CPUX86State;
 526
 527 CPUX86State *cpu_x86_init(void);
 528 int cpu_x86_exec(CPUX86State *s);
 529 void cpu_x86_close(CPUX86State *s);
 530 int cpu_get_pic_interrupt(CPUX86State *s);
 531 /* MSDOS compatibility mode FPU exception support */
 532 void cpu_set_ferr(CPUX86State *s);
 533
 534 /* this function must always be used to load data in the segment
 535    cache: it synchronizes the hflags with the segment cache values */
 536 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 537                                           int seg_reg, unsigned int selector,
 538                                           uint32_t base, unsigned int limit,
 539                                           unsigned int flags)
 540 {
 541     SegmentCache *sc;
 542     unsigned int new_hflags;
 543
 544     sc = &env->segs[seg_reg];
 545     sc->selector = selector;
 546     sc->base = base;
 547     sc->limit = limit;
 548     sc->flags = flags;
 549
 550     /* update the hidden flags */
 551     {
 552         if (seg_reg == R_CS) {
 553 #ifdef TARGET_X86_64
 554             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 555                 /* long mode */
 556                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 557                 env->hflags &= ~(HF_ADDSEG_MASK);
 558             } else
 559 #endif
 560             {
 561                 /* legacy / compatibility case */
 562                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 563                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 564                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 565                     new_hflags;
 566             }
 567         }
 568         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 569             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 570         if (env->hflags & HF_CS64_MASK) {
 571             /* zero base assumed for DS, ES and SS in long mode */
 572         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 573                    (env->eflags & VM_MASK) ||
 574                    !(env->hflags & HF_CS32_MASK)) {
 575             /* XXX: try to avoid this test. The problem comes from the
 576                fact that is real mode or vm86 mode we only modify the
 577                'base' and 'selector' fields of the segment cache to go
 578                faster. A solution may be to force addseg to one in
 579                translate-i386.c. */
 580             new_hflags |= HF_ADDSEG_MASK;
 581         } else {
 582             new_hflags |= ((env->segs[R_DS].base |
 583                             env->segs[R_ES].base |
 584                             env->segs[R_SS].base) != 0) <<
 585                 HF_ADDSEG_SHIFT;
 586         }
 587         env->hflags = (env->hflags &
 588                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 589     }
 590 }
 591
 592 /* wrapper, just in case memory mappings must be changed */
 593 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 594 {
 595 #if HF_CPL_MASK == 3
 596     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 597 #else
 598 #error HF_CPL_MASK is hardcoded
 599 #endif
 600 }
 601
 602 /* used for debug or cpu save/restore */
 603 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 604 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 605
 606 /* the following helpers are only usable in user mode simulation as
 607    they can trigger unexpected exceptions */
 608 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 609 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 610 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 611
 612 /* you can call this signal handler from your SIGBUS and SIGSEGV
 613    signal handlers to inform the virtual CPU of exceptions. non zero
 614    is returned if the signal was handled by the virtual CPU.  */
 615 struct siginfo;
 616 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 617                            void *puc);
 618 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 619
 620 uint64_t cpu_get_tsc(CPUX86State *env);
 621
 622 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 623 uint64_t cpu_get_apic_base(CPUX86State *env);
 624 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 625 #ifndef NO_CPU_IO_DEFS
 626 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 627 #endif
 628
 629 /* will be suppressed */
 630 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 631
 632 /* used to debug */
 633 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 634 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 635
 636 #define TARGET_PAGE_BITS 12
 637 #include "cpu-all.h"
 638
 639 #endif /* CPU_I386_H */