2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "sysemu/kvm.h"
22 #ifndef CONFIG_USER_ONLY
23 #include "sysemu/sysemu.h"
24 #include "monitor/monitor.h"
29 static void cpu_x86_version(CPUX86State
*env
, int *family
, int *model
)
31 int cpuver
= env
->cpuid_version
;
33 if (family
== NULL
|| model
== NULL
) {
37 *family
= (cpuver
>> 8) & 0x0f;
38 *model
= ((cpuver
>> 12) & 0xf0) + ((cpuver
>> 4) & 0x0f);
41 /* Broadcast MCA signal for processor version 06H_EH and above */
42 int cpu_x86_support_mca_broadcast(CPUX86State
*env
)
47 cpu_x86_version(env
, &family
, &model
);
48 if ((family
== 6 && model
>= 14) || family
> 6) {
55 /***********************************************************/
58 static const char *cc_op_str
[] = {
114 cpu_x86_dump_seg_cache(CPUX86State
*env
, FILE *f
, fprintf_function cpu_fprintf
,
115 const char *name
, struct SegmentCache
*sc
)
118 if (env
->hflags
& HF_CS64_MASK
) {
119 cpu_fprintf(f
, "%-3s=%04x %016" PRIx64
" %08x %08x", name
,
120 sc
->selector
, sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
124 cpu_fprintf(f
, "%-3s=%04x %08x %08x %08x", name
, sc
->selector
,
125 (uint32_t)sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
128 if (!(env
->hflags
& HF_PE_MASK
) || !(sc
->flags
& DESC_P_MASK
))
131 cpu_fprintf(f
, " DPL=%d ", (sc
->flags
& DESC_DPL_MASK
) >> DESC_DPL_SHIFT
);
132 if (sc
->flags
& DESC_S_MASK
) {
133 if (sc
->flags
& DESC_CS_MASK
) {
134 cpu_fprintf(f
, (sc
->flags
& DESC_L_MASK
) ? "CS64" :
135 ((sc
->flags
& DESC_B_MASK
) ? "CS32" : "CS16"));
136 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_C_MASK
) ? 'C' : '-',
137 (sc
->flags
& DESC_R_MASK
) ? 'R' : '-');
139 cpu_fprintf(f
, (sc
->flags
& DESC_B_MASK
) ? "DS " : "DS16");
140 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_E_MASK
) ? 'E' : '-',
141 (sc
->flags
& DESC_W_MASK
) ? 'W' : '-');
143 cpu_fprintf(f
, "%c]", (sc
->flags
& DESC_A_MASK
) ? 'A' : '-');
145 static const char *sys_type_name
[2][16] = {
147 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
148 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
149 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
150 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
153 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
154 "Reserved", "Reserved", "Reserved", "Reserved",
155 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
156 "Reserved", "IntGate64", "TrapGate64"
160 sys_type_name
[(env
->hflags
& HF_LMA_MASK
) ? 1 : 0]
161 [(sc
->flags
& DESC_TYPE_MASK
)
162 >> DESC_TYPE_SHIFT
]);
165 cpu_fprintf(f
, "\n");
168 #define DUMP_CODE_BYTES_TOTAL 50
169 #define DUMP_CODE_BYTES_BACKWARD 20
171 void cpu_dump_state(CPUX86State
*env
, FILE *f
, fprintf_function cpu_fprintf
,
176 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
178 cpu_synchronize_state(env
);
180 eflags
= env
->eflags
;
182 if (env
->hflags
& HF_CS64_MASK
) {
184 "RAX=%016" PRIx64
" RBX=%016" PRIx64
" RCX=%016" PRIx64
" RDX=%016" PRIx64
"\n"
185 "RSI=%016" PRIx64
" RDI=%016" PRIx64
" RBP=%016" PRIx64
" RSP=%016" PRIx64
"\n"
186 "R8 =%016" PRIx64
" R9 =%016" PRIx64
" R10=%016" PRIx64
" R11=%016" PRIx64
"\n"
187 "R12=%016" PRIx64
" R13=%016" PRIx64
" R14=%016" PRIx64
" R15=%016" PRIx64
"\n"
188 "RIP=%016" PRIx64
" RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
206 eflags
& DF_MASK
? 'D' : '-',
207 eflags
& CC_O
? 'O' : '-',
208 eflags
& CC_S
? 'S' : '-',
209 eflags
& CC_Z
? 'Z' : '-',
210 eflags
& CC_A
? 'A' : '-',
211 eflags
& CC_P
? 'P' : '-',
212 eflags
& CC_C
? 'C' : '-',
213 env
->hflags
& HF_CPL_MASK
,
214 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
215 (env
->a20_mask
>> 20) & 1,
216 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
221 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
222 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
223 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
224 (uint32_t)env
->regs
[R_EAX
],
225 (uint32_t)env
->regs
[R_EBX
],
226 (uint32_t)env
->regs
[R_ECX
],
227 (uint32_t)env
->regs
[R_EDX
],
228 (uint32_t)env
->regs
[R_ESI
],
229 (uint32_t)env
->regs
[R_EDI
],
230 (uint32_t)env
->regs
[R_EBP
],
231 (uint32_t)env
->regs
[R_ESP
],
232 (uint32_t)env
->eip
, eflags
,
233 eflags
& DF_MASK
? 'D' : '-',
234 eflags
& CC_O
? 'O' : '-',
235 eflags
& CC_S
? 'S' : '-',
236 eflags
& CC_Z
? 'Z' : '-',
237 eflags
& CC_A
? 'A' : '-',
238 eflags
& CC_P
? 'P' : '-',
239 eflags
& CC_C
? 'C' : '-',
240 env
->hflags
& HF_CPL_MASK
,
241 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
242 (env
->a20_mask
>> 20) & 1,
243 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
247 for(i
= 0; i
< 6; i
++) {
248 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, seg_name
[i
],
251 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "LDT", &env
->ldt
);
252 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "TR", &env
->tr
);
255 if (env
->hflags
& HF_LMA_MASK
) {
256 cpu_fprintf(f
, "GDT= %016" PRIx64
" %08x\n",
257 env
->gdt
.base
, env
->gdt
.limit
);
258 cpu_fprintf(f
, "IDT= %016" PRIx64
" %08x\n",
259 env
->idt
.base
, env
->idt
.limit
);
260 cpu_fprintf(f
, "CR0=%08x CR2=%016" PRIx64
" CR3=%016" PRIx64
" CR4=%08x\n",
261 (uint32_t)env
->cr
[0],
264 (uint32_t)env
->cr
[4]);
265 for(i
= 0; i
< 4; i
++)
266 cpu_fprintf(f
, "DR%d=%016" PRIx64
" ", i
, env
->dr
[i
]);
267 cpu_fprintf(f
, "\nDR6=%016" PRIx64
" DR7=%016" PRIx64
"\n",
268 env
->dr
[6], env
->dr
[7]);
272 cpu_fprintf(f
, "GDT= %08x %08x\n",
273 (uint32_t)env
->gdt
.base
, env
->gdt
.limit
);
274 cpu_fprintf(f
, "IDT= %08x %08x\n",
275 (uint32_t)env
->idt
.base
, env
->idt
.limit
);
276 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
277 (uint32_t)env
->cr
[0],
278 (uint32_t)env
->cr
[2],
279 (uint32_t)env
->cr
[3],
280 (uint32_t)env
->cr
[4]);
281 for(i
= 0; i
< 4; i
++) {
282 cpu_fprintf(f
, "DR%d=" TARGET_FMT_lx
" ", i
, env
->dr
[i
]);
284 cpu_fprintf(f
, "\nDR6=" TARGET_FMT_lx
" DR7=" TARGET_FMT_lx
"\n",
285 env
->dr
[6], env
->dr
[7]);
287 if (flags
& CPU_DUMP_CCOP
) {
288 if ((unsigned)env
->cc_op
< CC_OP_NB
)
289 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
291 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
293 if (env
->hflags
& HF_CS64_MASK
) {
294 cpu_fprintf(f
, "CCS=%016" PRIx64
" CCD=%016" PRIx64
" CCO=%-8s\n",
295 env
->cc_src
, env
->cc_dst
,
300 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
301 (uint32_t)env
->cc_src
, (uint32_t)env
->cc_dst
,
305 cpu_fprintf(f
, "EFER=%016" PRIx64
"\n", env
->efer
);
306 if (flags
& CPU_DUMP_FPU
) {
309 for(i
= 0; i
< 8; i
++) {
310 fptag
|= ((!env
->fptags
[i
]) << i
);
312 cpu_fprintf(f
, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
314 (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11,
320 u
.d
= env
->fpregs
[i
].d
;
321 cpu_fprintf(f
, "FPR%d=%016" PRIx64
" %04x",
322 i
, u
.l
.lower
, u
.l
.upper
);
324 cpu_fprintf(f
, "\n");
328 if (env
->hflags
& HF_CS64_MASK
)
333 cpu_fprintf(f
, "XMM%02d=%08x%08x%08x%08x",
335 env
->xmm_regs
[i
].XMM_L(3),
336 env
->xmm_regs
[i
].XMM_L(2),
337 env
->xmm_regs
[i
].XMM_L(1),
338 env
->xmm_regs
[i
].XMM_L(0));
340 cpu_fprintf(f
, "\n");
345 if (flags
& CPU_DUMP_CODE
) {
346 target_ulong base
= env
->segs
[R_CS
].base
+ env
->eip
;
347 target_ulong offs
= MIN(env
->eip
, DUMP_CODE_BYTES_BACKWARD
);
351 cpu_fprintf(f
, "Code=");
352 for (i
= 0; i
< DUMP_CODE_BYTES_TOTAL
; i
++) {
353 if (cpu_memory_rw_debug(env
, base
- offs
+ i
, &code
, 1, 0) == 0) {
354 snprintf(codestr
, sizeof(codestr
), "%02x", code
);
356 snprintf(codestr
, sizeof(codestr
), "??");
358 cpu_fprintf(f
, "%s%s%s%s", i
> 0 ? " " : "",
359 i
== offs
? "<" : "", codestr
, i
== offs
? ">" : "");
361 cpu_fprintf(f
, "\n");
365 /***********************************************************/
367 /* XXX: add PGE support */
369 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
)
371 CPUX86State
*env
= &cpu
->env
;
373 a20_state
= (a20_state
!= 0);
374 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
375 #if defined(DEBUG_MMU)
376 printf("A20 update: a20=%d\n", a20_state
);
378 /* if the cpu is currently executing code, we must unlink it and
379 all the potentially executing TB */
380 cpu_interrupt(env
, CPU_INTERRUPT_EXITTB
);
382 /* when a20 is changed, all the MMU mappings are invalid, so
383 we must flush everything */
385 env
->a20_mask
= ~(1 << 20) | (a20_state
<< 20);
389 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
393 #if defined(DEBUG_MMU)
394 printf("CR0 update: CR0=0x%08x\n", new_cr0
);
396 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
397 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
402 if (!(env
->cr
[0] & CR0_PG_MASK
) && (new_cr0
& CR0_PG_MASK
) &&
403 (env
->efer
& MSR_EFER_LME
)) {
404 /* enter in long mode */
405 /* XXX: generate an exception */
406 if (!(env
->cr
[4] & CR4_PAE_MASK
))
408 env
->efer
|= MSR_EFER_LMA
;
409 env
->hflags
|= HF_LMA_MASK
;
410 } else if ((env
->cr
[0] & CR0_PG_MASK
) && !(new_cr0
& CR0_PG_MASK
) &&
411 (env
->efer
& MSR_EFER_LMA
)) {
413 env
->efer
&= ~MSR_EFER_LMA
;
414 env
->hflags
&= ~(HF_LMA_MASK
| HF_CS64_MASK
);
415 env
->eip
&= 0xffffffff;
418 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
420 /* update PE flag in hidden flags */
421 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
422 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
423 /* ensure that ADDSEG is always set in real mode */
424 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
425 /* update FPU flags */
426 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
427 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
430 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
432 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
)
434 env
->cr
[3] = new_cr3
;
435 if (env
->cr
[0] & CR0_PG_MASK
) {
436 #if defined(DEBUG_MMU)
437 printf("CR3 update: CR3=" TARGET_FMT_lx
"\n", new_cr3
);
443 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
445 #if defined(DEBUG_MMU)
446 printf("CR4 update: CR4=%08x\n", (uint32_t)env
->cr
[4]);
448 if ((new_cr4
^ env
->cr
[4]) &
449 (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
|
450 CR4_SMEP_MASK
| CR4_SMAP_MASK
)) {
454 if (!(env
->cpuid_features
& CPUID_SSE
)) {
455 new_cr4
&= ~CR4_OSFXSR_MASK
;
457 env
->hflags
&= ~HF_OSFXSR_MASK
;
458 if (new_cr4
& CR4_OSFXSR_MASK
) {
459 env
->hflags
|= HF_OSFXSR_MASK
;
462 if (!(env
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
)) {
463 new_cr4
&= ~CR4_SMAP_MASK
;
465 env
->hflags
&= ~HF_SMAP_MASK
;
466 if (new_cr4
& CR4_SMAP_MASK
) {
467 env
->hflags
|= HF_SMAP_MASK
;
470 env
->cr
[4] = new_cr4
;
473 #if defined(CONFIG_USER_ONLY)
475 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
476 int is_write
, int mmu_idx
)
478 /* user mode only emulation */
481 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
);
482 env
->error_code
|= PG_ERROR_U_MASK
;
483 env
->exception_index
= EXCP0E_PAGE
;
489 /* XXX: This value should match the one returned by CPUID
491 # if defined(TARGET_X86_64)
492 # define PHYS_ADDR_MASK 0xfffffff000LL
494 # define PHYS_ADDR_MASK 0xffffff000LL
498 -1 = cannot handle fault
499 0 = nothing more to do
500 1 = generate PF fault
502 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
503 int is_write1
, int mmu_idx
)
506 target_ulong pde_addr
, pte_addr
;
507 int error_code
, is_dirty
, prot
, page_size
, is_write
, is_user
;
509 uint32_t page_offset
;
510 target_ulong vaddr
, virt_addr
;
512 is_user
= mmu_idx
== MMU_USER_IDX
;
513 #if defined(DEBUG_MMU)
514 printf("MMU fault: addr=" TARGET_FMT_lx
" w=%d u=%d eip=" TARGET_FMT_lx
"\n",
515 addr
, is_write1
, is_user
, env
->eip
);
517 is_write
= is_write1
& 1;
519 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
521 virt_addr
= addr
& TARGET_PAGE_MASK
;
522 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
527 if (env
->cr
[4] & CR4_PAE_MASK
) {
529 target_ulong pdpe_addr
;
532 if (env
->hflags
& HF_LMA_MASK
) {
533 uint64_t pml4e_addr
, pml4e
;
536 /* test virtual address sign extension */
537 sext
= (int64_t)addr
>> 47;
538 if (sext
!= 0 && sext
!= -1) {
540 env
->exception_index
= EXCP0D_GPF
;
544 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
546 pml4e
= ldq_phys(pml4e_addr
);
547 if (!(pml4e
& PG_PRESENT_MASK
)) {
551 if (!(env
->efer
& MSR_EFER_NXE
) && (pml4e
& PG_NX_MASK
)) {
552 error_code
= PG_ERROR_RSVD_MASK
;
555 if (!(pml4e
& PG_ACCESSED_MASK
)) {
556 pml4e
|= PG_ACCESSED_MASK
;
557 stl_phys_notdirty(pml4e_addr
, pml4e
);
559 ptep
= pml4e
^ PG_NX_MASK
;
560 pdpe_addr
= ((pml4e
& PHYS_ADDR_MASK
) + (((addr
>> 30) & 0x1ff) << 3)) &
562 pdpe
= ldq_phys(pdpe_addr
);
563 if (!(pdpe
& PG_PRESENT_MASK
)) {
567 if (!(env
->efer
& MSR_EFER_NXE
) && (pdpe
& PG_NX_MASK
)) {
568 error_code
= PG_ERROR_RSVD_MASK
;
571 ptep
&= pdpe
^ PG_NX_MASK
;
572 if (!(pdpe
& PG_ACCESSED_MASK
)) {
573 pdpe
|= PG_ACCESSED_MASK
;
574 stl_phys_notdirty(pdpe_addr
, pdpe
);
579 /* XXX: load them when cr3 is loaded ? */
580 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
582 pdpe
= ldq_phys(pdpe_addr
);
583 if (!(pdpe
& PG_PRESENT_MASK
)) {
587 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
590 pde_addr
= ((pdpe
& PHYS_ADDR_MASK
) + (((addr
>> 21) & 0x1ff) << 3)) &
592 pde
= ldq_phys(pde_addr
);
593 if (!(pde
& PG_PRESENT_MASK
)) {
597 if (!(env
->efer
& MSR_EFER_NXE
) && (pde
& PG_NX_MASK
)) {
598 error_code
= PG_ERROR_RSVD_MASK
;
601 ptep
&= pde
^ PG_NX_MASK
;
602 if (pde
& PG_PSE_MASK
) {
604 page_size
= 2048 * 1024;
606 if ((ptep
& PG_NX_MASK
) && is_write1
== 2) {
607 goto do_fault_protect
;
611 if (!(ptep
& PG_USER_MASK
)) {
612 goto do_fault_protect
;
614 if (is_write
&& !(ptep
& PG_RW_MASK
)) {
615 goto do_fault_protect
;
620 if (is_write1
!= 2 && (env
->cr
[4] & CR4_SMAP_MASK
) &&
621 (ptep
& PG_USER_MASK
)) {
622 goto do_fault_protect
;
626 if (is_write1
== 2 && (env
->cr
[4] & CR4_SMEP_MASK
) &&
627 (ptep
& PG_USER_MASK
)) {
628 goto do_fault_protect
;
630 if ((env
->cr
[0] & CR0_WP_MASK
) &&
631 is_write
&& !(ptep
& PG_RW_MASK
)) {
632 goto do_fault_protect
;
636 default: /* cannot happen */
639 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
640 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
641 pde
|= PG_ACCESSED_MASK
;
643 pde
|= PG_DIRTY_MASK
;
644 stl_phys_notdirty(pde_addr
, pde
);
646 /* align to page_size */
647 pte
= pde
& ((PHYS_ADDR_MASK
& ~(page_size
- 1)) | 0xfff);
648 virt_addr
= addr
& ~(page_size
- 1);
651 if (!(pde
& PG_ACCESSED_MASK
)) {
652 pde
|= PG_ACCESSED_MASK
;
653 stl_phys_notdirty(pde_addr
, pde
);
655 pte_addr
= ((pde
& PHYS_ADDR_MASK
) + (((addr
>> 12) & 0x1ff) << 3)) &
657 pte
= ldq_phys(pte_addr
);
658 if (!(pte
& PG_PRESENT_MASK
)) {
662 if (!(env
->efer
& MSR_EFER_NXE
) && (pte
& PG_NX_MASK
)) {
663 error_code
= PG_ERROR_RSVD_MASK
;
666 /* combine pde and pte nx, user and rw protections */
667 ptep
&= pte
^ PG_NX_MASK
;
669 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
670 goto do_fault_protect
;
673 if (!(ptep
& PG_USER_MASK
)) {
674 goto do_fault_protect
;
676 if (is_write
&& !(ptep
& PG_RW_MASK
)) {
677 goto do_fault_protect
;
682 if (is_write1
!= 2 && (env
->cr
[4] & CR4_SMAP_MASK
) &&
683 (ptep
& PG_USER_MASK
)) {
684 goto do_fault_protect
;
688 if (is_write1
== 2 && (env
->cr
[4] & CR4_SMEP_MASK
) &&
689 (ptep
& PG_USER_MASK
)) {
690 goto do_fault_protect
;
692 if ((env
->cr
[0] & CR0_WP_MASK
) &&
693 is_write
&& !(ptep
& PG_RW_MASK
)) {
694 goto do_fault_protect
;
698 default: /* cannot happen */
701 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
702 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
703 pte
|= PG_ACCESSED_MASK
;
705 pte
|= PG_DIRTY_MASK
;
706 stl_phys_notdirty(pte_addr
, pte
);
709 virt_addr
= addr
& ~0xfff;
710 pte
= pte
& (PHYS_ADDR_MASK
| 0xfff);
715 /* page directory entry */
716 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) &
718 pde
= ldl_phys(pde_addr
);
719 if (!(pde
& PG_PRESENT_MASK
)) {
723 /* if PSE bit is set, then we use a 4MB page */
724 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
725 page_size
= 4096 * 1024;
728 if (!(pde
& PG_USER_MASK
)) {
729 goto do_fault_protect
;
731 if (is_write
&& !(pde
& PG_RW_MASK
)) {
732 goto do_fault_protect
;
737 if (is_write1
!= 2 && (env
->cr
[4] & CR4_SMAP_MASK
) &&
738 (pde
& PG_USER_MASK
)) {
739 goto do_fault_protect
;
743 if (is_write1
== 2 && (env
->cr
[4] & CR4_SMEP_MASK
) &&
744 (pde
& PG_USER_MASK
)) {
745 goto do_fault_protect
;
747 if ((env
->cr
[0] & CR0_WP_MASK
) &&
748 is_write
&& !(pde
& PG_RW_MASK
)) {
749 goto do_fault_protect
;
753 default: /* cannot happen */
756 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
757 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
758 pde
|= PG_ACCESSED_MASK
;
760 pde
|= PG_DIRTY_MASK
;
761 stl_phys_notdirty(pde_addr
, pde
);
764 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
766 virt_addr
= addr
& ~(page_size
- 1);
768 if (!(pde
& PG_ACCESSED_MASK
)) {
769 pde
|= PG_ACCESSED_MASK
;
770 stl_phys_notdirty(pde_addr
, pde
);
773 /* page directory entry */
774 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) &
776 pte
= ldl_phys(pte_addr
);
777 if (!(pte
& PG_PRESENT_MASK
)) {
781 /* combine pde and pte user and rw protections */
785 if (!(ptep
& PG_USER_MASK
)) {
786 goto do_fault_protect
;
788 if (is_write
&& !(ptep
& PG_RW_MASK
)) {
789 goto do_fault_protect
;
794 if (is_write1
!= 2 && (env
->cr
[4] & CR4_SMAP_MASK
) &&
795 (ptep
& PG_USER_MASK
)) {
796 goto do_fault_protect
;
800 if (is_write1
== 2 && (env
->cr
[4] & CR4_SMEP_MASK
) &&
801 (ptep
& PG_USER_MASK
)) {
802 goto do_fault_protect
;
804 if ((env
->cr
[0] & CR0_WP_MASK
) &&
805 is_write
&& !(ptep
& PG_RW_MASK
)) {
806 goto do_fault_protect
;
810 default: /* cannot happen */
813 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
814 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
815 pte
|= PG_ACCESSED_MASK
;
817 pte
|= PG_DIRTY_MASK
;
818 stl_phys_notdirty(pte_addr
, pte
);
821 virt_addr
= addr
& ~0xfff;
824 /* the page can be put in the TLB */
826 if (!(ptep
& PG_NX_MASK
))
828 if (pte
& PG_DIRTY_MASK
) {
829 /* only set write access if already dirty... otherwise wait
832 if (ptep
& PG_RW_MASK
)
835 if (!(env
->cr
[0] & CR0_WP_MASK
) ||
841 pte
= pte
& env
->a20_mask
;
843 /* Even if 4MB pages, we map only one 4KB page in the cache to
844 avoid filling it too fast */
845 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
846 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
847 vaddr
= virt_addr
+ page_offset
;
849 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
852 error_code
= PG_ERROR_P_MASK
;
854 error_code
|= (is_write
<< PG_ERROR_W_BIT
);
856 error_code
|= PG_ERROR_U_MASK
;
857 if (is_write1
== 2 &&
858 (((env
->efer
& MSR_EFER_NXE
) &&
859 (env
->cr
[4] & CR4_PAE_MASK
)) ||
860 (env
->cr
[4] & CR4_SMEP_MASK
)))
861 error_code
|= PG_ERROR_I_D_MASK
;
862 if (env
->intercept_exceptions
& (1 << EXCP0E_PAGE
)) {
863 /* cr2 is not modified in case of exceptions */
864 stq_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.exit_info_2
),
869 env
->error_code
= error_code
;
870 env
->exception_index
= EXCP0E_PAGE
;
874 hwaddr
cpu_get_phys_page_debug(CPUX86State
*env
, target_ulong addr
)
876 target_ulong pde_addr
, pte_addr
;
879 uint32_t page_offset
;
882 if (env
->cr
[4] & CR4_PAE_MASK
) {
883 target_ulong pdpe_addr
;
887 if (env
->hflags
& HF_LMA_MASK
) {
888 uint64_t pml4e_addr
, pml4e
;
891 /* test virtual address sign extension */
892 sext
= (int64_t)addr
>> 47;
893 if (sext
!= 0 && sext
!= -1)
896 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
898 pml4e
= ldq_phys(pml4e_addr
);
899 if (!(pml4e
& PG_PRESENT_MASK
))
902 pdpe_addr
= ((pml4e
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
903 (((addr
>> 30) & 0x1ff) << 3)) & env
->a20_mask
;
904 pdpe
= ldq_phys(pdpe_addr
);
905 if (!(pdpe
& PG_PRESENT_MASK
))
910 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
912 pdpe
= ldq_phys(pdpe_addr
);
913 if (!(pdpe
& PG_PRESENT_MASK
))
917 pde_addr
= ((pdpe
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
918 (((addr
>> 21) & 0x1ff) << 3)) & env
->a20_mask
;
919 pde
= ldq_phys(pde_addr
);
920 if (!(pde
& PG_PRESENT_MASK
)) {
923 if (pde
& PG_PSE_MASK
) {
925 page_size
= 2048 * 1024;
926 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
929 pte_addr
= ((pde
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
930 (((addr
>> 12) & 0x1ff) << 3)) & env
->a20_mask
;
932 pte
= ldq_phys(pte_addr
);
934 pte
&= ~(PG_NX_MASK
| PG_HI_USER_MASK
);
935 if (!(pte
& PG_PRESENT_MASK
))
940 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
944 /* page directory entry */
945 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) & env
->a20_mask
;
946 pde
= ldl_phys(pde_addr
);
947 if (!(pde
& PG_PRESENT_MASK
))
949 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
950 pte
= pde
& ~0x003ff000; /* align to 4MB */
951 page_size
= 4096 * 1024;
953 /* page directory entry */
954 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
;
955 pte
= ldl_phys(pte_addr
);
956 if (!(pte
& PG_PRESENT_MASK
))
961 pte
= pte
& env
->a20_mask
;
964 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
965 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
969 void hw_breakpoint_insert(CPUX86State
*env
, int index
)
971 int type
= 0, err
= 0;
973 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
974 case DR7_TYPE_BP_INST
:
975 if (hw_breakpoint_enabled(env
->dr
[7], index
)) {
976 err
= cpu_breakpoint_insert(env
, env
->dr
[index
], BP_CPU
,
977 &env
->cpu_breakpoint
[index
]);
980 case DR7_TYPE_DATA_WR
:
981 type
= BP_CPU
| BP_MEM_WRITE
;
984 /* No support for I/O watchpoints yet */
986 case DR7_TYPE_DATA_RW
:
987 type
= BP_CPU
| BP_MEM_ACCESS
;
992 err
= cpu_watchpoint_insert(env
, env
->dr
[index
],
993 hw_breakpoint_len(env
->dr
[7], index
),
994 type
, &env
->cpu_watchpoint
[index
]);
998 env
->cpu_breakpoint
[index
] = NULL
;
1002 void hw_breakpoint_remove(CPUX86State
*env
, int index
)
1004 if (!env
->cpu_breakpoint
[index
])
1006 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
1007 case DR7_TYPE_BP_INST
:
1008 if (hw_breakpoint_enabled(env
->dr
[7], index
)) {
1009 cpu_breakpoint_remove_by_ref(env
, env
->cpu_breakpoint
[index
]);
1012 case DR7_TYPE_DATA_WR
:
1013 case DR7_TYPE_DATA_RW
:
1014 cpu_watchpoint_remove_by_ref(env
, env
->cpu_watchpoint
[index
]);
1016 case DR7_TYPE_IO_RW
:
1017 /* No support for I/O watchpoints yet */
1022 bool check_hw_breakpoints(CPUX86State
*env
, bool force_dr6_update
)
1026 bool hit_enabled
= false;
1028 dr6
= env
->dr
[6] & ~0xf;
1029 for (reg
= 0; reg
< DR7_MAX_BP
; reg
++) {
1030 bool bp_match
= false;
1031 bool wp_match
= false;
1033 switch (hw_breakpoint_type(env
->dr
[7], reg
)) {
1034 case DR7_TYPE_BP_INST
:
1035 if (env
->dr
[reg
] == env
->eip
) {
1039 case DR7_TYPE_DATA_WR
:
1040 case DR7_TYPE_DATA_RW
:
1041 if (env
->cpu_watchpoint
[reg
] &&
1042 env
->cpu_watchpoint
[reg
]->flags
& BP_WATCHPOINT_HIT
) {
1046 case DR7_TYPE_IO_RW
:
1049 if (bp_match
|| wp_match
) {
1051 if (hw_breakpoint_enabled(env
->dr
[7], reg
)) {
1057 if (hit_enabled
|| force_dr6_update
) {
1064 void breakpoint_handler(CPUX86State
*env
)
1068 if (env
->watchpoint_hit
) {
1069 if (env
->watchpoint_hit
->flags
& BP_CPU
) {
1070 env
->watchpoint_hit
= NULL
;
1071 if (check_hw_breakpoints(env
, false)) {
1072 raise_exception(env
, EXCP01_DB
);
1074 cpu_resume_from_signal(env
, NULL
);
1078 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
)
1079 if (bp
->pc
== env
->eip
) {
1080 if (bp
->flags
& BP_CPU
) {
1081 check_hw_breakpoints(env
, true);
1082 raise_exception(env
, EXCP01_DB
);
1089 typedef struct MCEInjectionParams
{
1094 uint64_t mcg_status
;
1098 } MCEInjectionParams
;
1100 static void do_inject_x86_mce(void *data
)
1102 MCEInjectionParams
*params
= data
;
1103 CPUX86State
*cenv
= ¶ms
->cpu
->env
;
1104 CPUState
*cpu
= CPU(params
->cpu
);
1105 uint64_t *banks
= cenv
->mce_banks
+ 4 * params
->bank
;
1107 cpu_synchronize_state(cenv
);
1110 * If there is an MCE exception being processed, ignore this SRAO MCE
1111 * unless unconditional injection was requested.
1113 if (!(params
->flags
& MCE_INJECT_UNCOND_AO
)
1114 && !(params
->status
& MCI_STATUS_AR
)
1115 && (cenv
->mcg_status
& MCG_STATUS_MCIP
)) {
1119 if (params
->status
& MCI_STATUS_UC
) {
1121 * if MSR_MCG_CTL is not all 1s, the uncorrected error
1122 * reporting is disabled
1124 if ((cenv
->mcg_cap
& MCG_CTL_P
) && cenv
->mcg_ctl
!= ~(uint64_t)0) {
1125 monitor_printf(params
->mon
,
1126 "CPU %d: Uncorrected error reporting disabled\n",
1132 * if MSR_MCi_CTL is not all 1s, the uncorrected error
1133 * reporting is disabled for the bank
1135 if (banks
[0] != ~(uint64_t)0) {
1136 monitor_printf(params
->mon
,
1137 "CPU %d: Uncorrected error reporting disabled for"
1139 cpu
->cpu_index
, params
->bank
);
1143 if ((cenv
->mcg_status
& MCG_STATUS_MCIP
) ||
1144 !(cenv
->cr
[4] & CR4_MCE_MASK
)) {
1145 monitor_printf(params
->mon
,
1146 "CPU %d: Previous MCE still in progress, raising"
1149 qemu_log_mask(CPU_LOG_RESET
, "Triple fault\n");
1150 qemu_system_reset_request();
1153 if (banks
[1] & MCI_STATUS_VAL
) {
1154 params
->status
|= MCI_STATUS_OVER
;
1156 banks
[2] = params
->addr
;
1157 banks
[3] = params
->misc
;
1158 cenv
->mcg_status
= params
->mcg_status
;
1159 banks
[1] = params
->status
;
1160 cpu_interrupt(cenv
, CPU_INTERRUPT_MCE
);
1161 } else if (!(banks
[1] & MCI_STATUS_VAL
)
1162 || !(banks
[1] & MCI_STATUS_UC
)) {
1163 if (banks
[1] & MCI_STATUS_VAL
) {
1164 params
->status
|= MCI_STATUS_OVER
;
1166 banks
[2] = params
->addr
;
1167 banks
[3] = params
->misc
;
1168 banks
[1] = params
->status
;
1170 banks
[1] |= MCI_STATUS_OVER
;
1174 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
1175 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
1176 uint64_t misc
, int flags
)
1178 CPUX86State
*cenv
= &cpu
->env
;
1179 MCEInjectionParams params
= {
1184 .mcg_status
= mcg_status
,
1189 unsigned bank_num
= cenv
->mcg_cap
& 0xff;
1192 if (!cenv
->mcg_cap
) {
1193 monitor_printf(mon
, "MCE injection not supported\n");
1196 if (bank
>= bank_num
) {
1197 monitor_printf(mon
, "Invalid MCE bank number\n");
1200 if (!(status
& MCI_STATUS_VAL
)) {
1201 monitor_printf(mon
, "Invalid MCE status code\n");
1204 if ((flags
& MCE_INJECT_BROADCAST
)
1205 && !cpu_x86_support_mca_broadcast(cenv
)) {
1206 monitor_printf(mon
, "Guest CPU does not support MCA broadcast\n");
1210 run_on_cpu(CPU(cpu
), do_inject_x86_mce
, ¶ms
);
1211 if (flags
& MCE_INJECT_BROADCAST
) {
1213 params
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
;
1214 params
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
;
1217 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1221 params
.cpu
= x86_env_get_cpu(env
);
1222 run_on_cpu(CPU(cpu
), do_inject_x86_mce
, ¶ms
);
1227 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
)
1229 if (kvm_enabled()) {
1230 env
->tpr_access_type
= access
;
1232 cpu_interrupt(env
, CPU_INTERRUPT_TPR
);
1234 cpu_restore_state(env
, env
->mem_io_pc
);
1236 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
, access
);
1239 #endif /* !CONFIG_USER_ONLY */
1241 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
1242 target_ulong
*base
, unsigned int *limit
,
1243 unsigned int *flags
)
1254 index
= selector
& ~7;
1255 ptr
= dt
->base
+ index
;
1256 if ((index
+ 7) > dt
->limit
1257 || cpu_memory_rw_debug(env
, ptr
, (uint8_t *)&e1
, sizeof(e1
), 0) != 0
1258 || cpu_memory_rw_debug(env
, ptr
+4, (uint8_t *)&e2
, sizeof(e2
), 0) != 0)
1261 *base
= ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
1262 *limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
1263 if (e2
& DESC_G_MASK
)
1264 *limit
= (*limit
<< 12) | 0xfff;
1270 X86CPU
*cpu_x86_init(const char *cpu_model
)
1274 Error
*error
= NULL
;
1276 cpu
= X86_CPU(object_new(TYPE_X86_CPU
));
1278 env
->cpu_model_str
= cpu_model
;
1280 if (cpu_x86_register(cpu
, cpu_model
) < 0) {
1281 object_unref(OBJECT(cpu
));
1285 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
1288 object_unref(OBJECT(cpu
));
1294 #if !defined(CONFIG_USER_ONLY)
1295 void do_cpu_init(X86CPU
*cpu
)
1297 CPUX86State
*env
= &cpu
->env
;
1298 int sipi
= env
->interrupt_request
& CPU_INTERRUPT_SIPI
;
1299 uint64_t pat
= env
->pat
;
1301 cpu_reset(CPU(cpu
));
1302 env
->interrupt_request
= sipi
;
1304 apic_init_reset(env
->apic_state
);
1307 void do_cpu_sipi(X86CPU
*cpu
)
1309 CPUX86State
*env
= &cpu
->env
;
1311 apic_sipi(env
->apic_state
);
1314 void do_cpu_init(X86CPU
*cpu
)
1317 void do_cpu_sipi(X86CPU
*cpu
)