4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 const uint8_t parity_table
[256] = {
25 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
26 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
27 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
28 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
29 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
30 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
31 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
32 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
33 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
34 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
35 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
36 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
37 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
38 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
39 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
40 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
41 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
42 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
43 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
44 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
45 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
46 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
47 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
48 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
49 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
50 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
51 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
52 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
53 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
54 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
55 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
56 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
60 const uint8_t rclw_table
[32] = {
61 0, 1, 2, 3, 4, 5, 6, 7,
62 8, 9,10,11,12,13,14,15,
63 16, 0, 1, 2, 3, 4, 5, 6,
64 7, 8, 9,10,11,12,13,14,
68 const uint8_t rclb_table
[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 0, 1, 2, 3, 4, 5, 6,
71 7, 8, 0, 1, 2, 3, 4, 5,
72 6, 7, 8, 0, 1, 2, 3, 4,
75 const CPU86_LDouble f15rk
[7] =
77 0.00000000000000000000L,
78 1.00000000000000000000L,
79 3.14159265358979323851L, /*pi*/
80 0.30102999566398119523L, /*lg2*/
81 0.69314718055994530943L, /*ln2*/
82 1.44269504088896340739L, /*l2e*/
83 3.32192809488736234781L, /*l2t*/
88 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
92 spin_lock(&global_cpu_lock
);
97 spin_unlock(&global_cpu_lock
);
100 void cpu_loop_exit(void)
102 /* NOTE: the register at this point must be saved by hand because
103 longjmp restore them */
105 env
->regs
[R_EAX
] = EAX
;
108 env
->regs
[R_ECX
] = ECX
;
111 env
->regs
[R_EDX
] = EDX
;
114 env
->regs
[R_EBX
] = EBX
;
117 env
->regs
[R_ESP
] = ESP
;
120 env
->regs
[R_EBP
] = EBP
;
123 env
->regs
[R_ESI
] = ESI
;
126 env
->regs
[R_EDI
] = EDI
;
128 longjmp(env
->jmp_env
, 1);
131 /* return non zero if error */
132 static inline int load_segment(uint32_t *e1_ptr
, uint32_t *e2_ptr
,
143 index
= selector
& ~7;
144 if ((index
+ 7) > dt
->limit
)
146 ptr
= dt
->base
+ index
;
147 *e1_ptr
= ldl_kernel(ptr
);
148 *e2_ptr
= ldl_kernel(ptr
+ 4);
152 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
155 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
156 if (e2
& DESC_G_MASK
)
157 limit
= (limit
<< 12) | 0xfff;
161 static inline uint8_t *get_seg_base(uint32_t e1
, uint32_t e2
)
163 return (uint8_t *)((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
166 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
, uint32_t e2
)
168 sc
->base
= get_seg_base(e1
, e2
);
169 sc
->limit
= get_seg_limit(e1
, e2
);
173 /* init the segment cache in vm86 mode. */
174 static inline void load_seg_vm(int seg
, int selector
)
177 cpu_x86_load_seg_cache(env
, seg
, selector
,
178 (uint8_t *)(selector
<< 4), 0xffff, 0);
181 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr
,
182 uint32_t *esp_ptr
, int dpl
)
184 int type
, index
, shift
;
189 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
190 for(i
=0;i
<env
->tr
.limit
;i
++) {
191 printf("%02x ", env
->tr
.base
[i
]);
192 if ((i
& 7) == 7) printf("\n");
198 if (!(env
->tr
.flags
& DESC_P_MASK
))
199 cpu_abort(env
, "invalid tss");
200 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
202 cpu_abort(env
, "invalid tss type");
204 index
= (dpl
* 4 + 2) << shift
;
205 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
)
206 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
208 *esp_ptr
= lduw_kernel(env
->tr
.base
+ index
);
209 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 2);
211 *esp_ptr
= ldl_kernel(env
->tr
.base
+ index
);
212 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 4);
216 /* XXX: merge with load_seg() */
217 static void tss_load_seg(int seg_reg
, int selector
)
222 if ((selector
& 0xfffc) != 0) {
223 if (load_segment(&e1
, &e2
, selector
) != 0)
224 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
225 if (!(e2
& DESC_S_MASK
))
226 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
228 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
229 cpl
= env
->hflags
& HF_CPL_MASK
;
230 if (seg_reg
== R_CS
) {
231 if (!(e2
& DESC_CS_MASK
))
232 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
234 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
235 if ((e2
& DESC_C_MASK
) && dpl
> rpl
)
236 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
238 } else if (seg_reg
== R_SS
) {
239 /* SS must be writable data */
240 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
241 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
242 if (dpl
!= cpl
|| dpl
!= rpl
)
243 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
245 /* not readable code */
246 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
))
247 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
248 /* if data or non conforming code, checks the rights */
249 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
250 if (dpl
< cpl
|| dpl
< rpl
)
251 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
254 if (!(e2
& DESC_P_MASK
))
255 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
256 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
257 get_seg_base(e1
, e2
),
258 get_seg_limit(e1
, e2
),
261 if (seg_reg
== R_SS
|| seg_reg
== R_CS
)
262 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
266 #define SWITCH_TSS_JMP 0
267 #define SWITCH_TSS_IRET 1
268 #define SWITCH_TSS_CALL 2
270 /* XXX: restore CPU state in registers (PowerPC case) */
271 static void switch_tss(int tss_selector
,
272 uint32_t e1
, uint32_t e2
, int source
)
274 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
276 uint32_t new_regs
[8], new_segs
[6];
277 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
278 uint32_t old_eflags
, eflags_mask
;
283 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
285 /* if task gate, we read the TSS segment and we load it */
287 if (!(e2
& DESC_P_MASK
))
288 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
289 tss_selector
= e1
>> 16;
290 if (tss_selector
& 4)
291 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
292 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
293 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
294 if (e2
& DESC_S_MASK
)
295 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
296 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
298 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
301 if (!(e2
& DESC_P_MASK
))
302 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
308 tss_limit
= get_seg_limit(e1
, e2
);
309 tss_base
= get_seg_base(e1
, e2
);
310 if ((tss_selector
& 4) != 0 ||
311 tss_limit
< tss_limit_max
)
312 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
313 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
315 old_tss_limit_max
= 103;
317 old_tss_limit_max
= 43;
319 /* read all the registers from the new TSS */
322 new_cr3
= ldl_kernel(tss_base
+ 0x1c);
323 new_eip
= ldl_kernel(tss_base
+ 0x20);
324 new_eflags
= ldl_kernel(tss_base
+ 0x24);
325 for(i
= 0; i
< 8; i
++)
326 new_regs
[i
] = ldl_kernel(tss_base
+ (0x28 + i
* 4));
327 for(i
= 0; i
< 6; i
++)
328 new_segs
[i
] = lduw_kernel(tss_base
+ (0x48 + i
* 4));
329 new_ldt
= lduw_kernel(tss_base
+ 0x60);
330 new_trap
= ldl_kernel(tss_base
+ 0x64);
334 new_eip
= lduw_kernel(tss_base
+ 0x0e);
335 new_eflags
= lduw_kernel(tss_base
+ 0x10);
336 for(i
= 0; i
< 8; i
++)
337 new_regs
[i
] = lduw_kernel(tss_base
+ (0x12 + i
* 2)) | 0xffff0000;
338 for(i
= 0; i
< 4; i
++)
339 new_segs
[i
] = lduw_kernel(tss_base
+ (0x22 + i
* 4));
340 new_ldt
= lduw_kernel(tss_base
+ 0x2a);
346 /* NOTE: we must avoid memory exceptions during the task switch,
347 so we make dummy accesses before */
348 /* XXX: it can still fail in some cases, so a bigger hack is
349 necessary to valid the TLB after having done the accesses */
351 v1
= ldub_kernel(env
->tr
.base
);
352 v2
= ldub(env
->tr
.base
+ old_tss_limit_max
);
353 stb_kernel(env
->tr
.base
, v1
);
354 stb_kernel(env
->tr
.base
+ old_tss_limit_max
, v2
);
356 /* clear busy bit (it is restartable) */
357 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
360 ptr
= env
->gdt
.base
+ (env
->tr
.selector
<< 3);
361 e2
= ldl_kernel(ptr
+ 4);
362 e2
&= ~DESC_TSS_BUSY_MASK
;
363 stl_kernel(ptr
+ 4, e2
);
365 old_eflags
= compute_eflags();
366 if (source
== SWITCH_TSS_IRET
)
367 old_eflags
&= ~NT_MASK
;
369 /* save the current state in the old TSS */
372 stl_kernel(env
->tr
.base
+ 0x20, env
->eip
);
373 stl_kernel(env
->tr
.base
+ 0x24, old_eflags
);
374 for(i
= 0; i
< 8; i
++)
375 stl_kernel(env
->tr
.base
+ (0x28 + i
* 4), env
->regs
[i
]);
376 for(i
= 0; i
< 6; i
++)
377 stw_kernel(env
->tr
.base
+ (0x48 + i
* 4), env
->segs
[i
].selector
);
380 stw_kernel(env
->tr
.base
+ 0x0e, new_eip
);
381 stw_kernel(env
->tr
.base
+ 0x10, old_eflags
);
382 for(i
= 0; i
< 8; i
++)
383 stw_kernel(env
->tr
.base
+ (0x12 + i
* 2), env
->regs
[i
]);
384 for(i
= 0; i
< 4; i
++)
385 stw_kernel(env
->tr
.base
+ (0x22 + i
* 4), env
->segs
[i
].selector
);
388 /* now if an exception occurs, it will occurs in the next task
391 if (source
== SWITCH_TSS_CALL
) {
392 stw_kernel(tss_base
, env
->tr
.selector
);
393 new_eflags
|= NT_MASK
;
397 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
400 ptr
= env
->gdt
.base
+ (tss_selector
<< 3);
401 e2
= ldl_kernel(ptr
+ 4);
402 e2
|= DESC_TSS_BUSY_MASK
;
403 stl_kernel(ptr
+ 4, e2
);
406 /* set the new CPU state */
407 /* from this point, any exception which occurs can give problems */
408 env
->cr
[0] |= CR0_TS_MASK
;
409 env
->tr
.selector
= tss_selector
;
410 env
->tr
.base
= tss_base
;
411 env
->tr
.limit
= tss_limit
;
412 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
414 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
415 env
->cr
[3] = new_cr3
;
416 cpu_x86_update_cr3(env
);
419 /* load all registers without an exception, then reload them with
420 possible exception */
422 eflags_mask
= FL_UPDATE_CPL0_MASK
;
424 eflags_mask
&= 0xffff;
425 load_eflags(new_eflags
, eflags_mask
);
426 for(i
= 0; i
< 8; i
++)
427 env
->regs
[i
] = new_regs
[i
];
428 if (new_eflags
& VM_MASK
) {
429 for(i
= 0; i
< 6; i
++)
430 load_seg_vm(i
, new_segs
[i
]);
431 /* in vm86, CPL is always 3 */
432 cpu_x86_set_cpl(env
, 3);
434 /* CPL is set the RPL of CS */
435 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
436 /* first just selectors as the rest may trigger exceptions */
437 for(i
= 0; i
< 6; i
++)
438 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], NULL
, 0, 0);
441 env
->ldt
.selector
= new_ldt
& ~4;
442 env
->ldt
.base
= NULL
;
448 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
451 index
= new_ldt
& ~7;
452 if ((index
+ 7) > dt
->limit
)
453 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
454 ptr
= dt
->base
+ index
;
455 e1
= ldl_kernel(ptr
);
456 e2
= ldl_kernel(ptr
+ 4);
457 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
458 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
459 if (!(e2
& DESC_P_MASK
))
460 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
461 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
463 /* load the segments */
464 if (!(new_eflags
& VM_MASK
)) {
465 tss_load_seg(R_CS
, new_segs
[R_CS
]);
466 tss_load_seg(R_SS
, new_segs
[R_SS
]);
467 tss_load_seg(R_ES
, new_segs
[R_ES
]);
468 tss_load_seg(R_DS
, new_segs
[R_DS
]);
469 tss_load_seg(R_FS
, new_segs
[R_FS
]);
470 tss_load_seg(R_GS
, new_segs
[R_GS
]);
473 /* check that EIP is in the CS segment limits */
474 if (new_eip
> env
->segs
[R_CS
].limit
) {
475 raise_exception_err(EXCP0D_GPF
, 0);
479 /* check if Port I/O is allowed in TSS */
480 static inline void check_io(int addr
, int size
)
482 int io_offset
, val
, mask
;
484 /* TSS must be a valid 32 bit one */
485 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
486 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
489 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
490 io_offset
+= (addr
>> 3);
491 /* Note: the check needs two bytes */
492 if ((io_offset
+ 1) > env
->tr
.limit
)
494 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
496 mask
= (1 << size
) - 1;
497 /* all bits must be zero to allow the I/O */
498 if ((val
& mask
) != 0) {
500 raise_exception_err(EXCP0D_GPF
, 0);
504 void check_iob_T0(void)
509 void check_iow_T0(void)
514 void check_iol_T0(void)
519 void check_iob_DX(void)
521 check_io(EDX
& 0xffff, 1);
524 void check_iow_DX(void)
526 check_io(EDX
& 0xffff, 2);
529 void check_iol_DX(void)
531 check_io(EDX
& 0xffff, 4);
534 static inline unsigned int get_sp_mask(unsigned int e2
)
536 if (e2
& DESC_B_MASK
)
542 /* XXX: add a is_user flag to have proper security support */
543 #define PUSHW(ssp, sp, sp_mask, val)\
546 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
549 #define PUSHL(ssp, sp, sp_mask, val)\
552 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
555 #define POPW(ssp, sp, sp_mask, val)\
557 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
561 #define POPL(ssp, sp, sp_mask, val)\
563 val = ldl_kernel((ssp) + (sp & (sp_mask)));\
567 /* protected mode interrupt */
568 static void do_interrupt_protected(int intno
, int is_int
, int error_code
,
569 unsigned int next_eip
, int is_hw
)
573 int type
, dpl
, selector
, ss_dpl
, cpl
, sp_mask
;
574 int has_error_code
, new_stack
, shift
;
575 uint32_t e1
, e2
, offset
, ss
, esp
, ss_e1
, ss_e2
;
581 fprintf(logfile
, "%d: interrupt: vector=%02x error_code=%04x int=%d CS:IP=%04x:%08x CPL=%d\n",
582 count
, intno
, error_code
, is_int
, env
->segs
[R_CS
].selector
, env
->eip
, env
->hflags
& 3);
588 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
589 for(i
= 0; i
< 16; i
++) {
590 printf(" %02x", ldub(ptr
+ i
));
600 if (!is_int
&& !is_hw
) {
615 if (intno
* 8 + 7 > dt
->limit
)
616 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
617 ptr
= dt
->base
+ intno
* 8;
618 e1
= ldl_kernel(ptr
);
619 e2
= ldl_kernel(ptr
+ 4);
620 /* check gate type */
621 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
623 case 5: /* task gate */
624 /* must do that check here to return the correct error code */
625 if (!(e2
& DESC_P_MASK
))
626 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
627 switch_tss(intno
* 8, e1
, e2
, SWITCH_TSS_CALL
);
628 if (has_error_code
) {
630 /* push the error code */
631 shift
= (env
->segs
[R_CS
].flags
>> DESC_B_SHIFT
) & 1;
632 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
636 esp
= (env
->regs
[R_ESP
] - (2 << shift
)) & mask
;
637 ssp
= env
->segs
[R_SS
].base
+ esp
;
639 stl_kernel(ssp
, error_code
);
641 stw_kernel(ssp
, error_code
);
642 env
->regs
[R_ESP
] = (esp
& mask
) | (env
->regs
[R_ESP
] & ~mask
);
645 case 6: /* 286 interrupt gate */
646 case 7: /* 286 trap gate */
647 case 14: /* 386 interrupt gate */
648 case 15: /* 386 trap gate */
651 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
654 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
655 cpl
= env
->hflags
& HF_CPL_MASK
;
656 /* check privledge if software int */
657 if (is_int
&& dpl
< cpl
)
658 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
659 /* check valid bit */
660 if (!(e2
& DESC_P_MASK
))
661 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
663 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
664 if ((selector
& 0xfffc) == 0)
665 raise_exception_err(EXCP0D_GPF
, 0);
667 if (load_segment(&e1
, &e2
, selector
) != 0)
668 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
669 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
670 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
671 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
673 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
674 if (!(e2
& DESC_P_MASK
))
675 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
676 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
677 /* to inner priviledge */
678 get_ss_esp_from_tss(&ss
, &esp
, dpl
);
679 if ((ss
& 0xfffc) == 0)
680 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
682 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
683 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
684 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
685 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
687 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
688 if (!(ss_e2
& DESC_S_MASK
) ||
689 (ss_e2
& DESC_CS_MASK
) ||
690 !(ss_e2
& DESC_W_MASK
))
691 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
692 if (!(ss_e2
& DESC_P_MASK
))
693 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
695 sp_mask
= get_sp_mask(ss_e2
);
696 ssp
= get_seg_base(ss_e1
, ss_e2
);
697 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
698 /* to same priviledge */
700 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
701 ssp
= env
->segs
[R_SS
].base
;
704 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
705 new_stack
= 0; /* avoid warning */
706 sp_mask
= 0; /* avoid warning */
707 ssp
= NULL
; /* avoid warning */
708 esp
= 0; /* avoid warning */
714 /* XXX: check that enough room is available */
715 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
716 if (env
->eflags
& VM_MASK
)
725 if (env
->eflags
& VM_MASK
) {
726 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
727 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
728 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
729 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
732 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
733 PUSHL(ssp
, esp
, sp_mask
, ESP
);
735 PUSHL(ssp
, esp
, sp_mask
, compute_eflags());
736 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
737 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
738 if (has_error_code
) {
739 PUSHL(ssp
, esp
, sp_mask
, error_code
);
743 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
744 PUSHW(ssp
, esp
, sp_mask
, ESP
);
746 PUSHW(ssp
, esp
, sp_mask
, compute_eflags());
747 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
748 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
749 if (has_error_code
) {
750 PUSHW(ssp
, esp
, sp_mask
, error_code
);
755 ss
= (ss
& ~3) | dpl
;
756 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
757 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
759 ESP
= (ESP
& ~sp_mask
) | (esp
& sp_mask
);
761 selector
= (selector
& ~3) | dpl
;
762 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
763 get_seg_base(e1
, e2
),
764 get_seg_limit(e1
, e2
),
766 cpu_x86_set_cpl(env
, dpl
);
769 /* interrupt gate clear IF mask */
770 if ((type
& 1) == 0) {
771 env
->eflags
&= ~IF_MASK
;
773 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
776 /* real mode interrupt */
777 static void do_interrupt_real(int intno
, int is_int
, int error_code
,
778 unsigned int next_eip
)
783 uint32_t offset
, esp
;
784 uint32_t old_cs
, old_eip
;
786 /* real mode (simpler !) */
788 if (intno
* 4 + 3 > dt
->limit
)
789 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
790 ptr
= dt
->base
+ intno
* 4;
791 offset
= lduw_kernel(ptr
);
792 selector
= lduw_kernel(ptr
+ 2);
794 ssp
= env
->segs
[R_SS
].base
;
799 old_cs
= env
->segs
[R_CS
].selector
;
800 /* XXX: use SS segment size ? */
801 PUSHW(ssp
, esp
, 0xffff, compute_eflags());
802 PUSHW(ssp
, esp
, 0xffff, old_cs
);
803 PUSHW(ssp
, esp
, 0xffff, old_eip
);
805 /* update processor state */
806 ESP
= (ESP
& ~0xffff) | (esp
& 0xffff);
808 env
->segs
[R_CS
].selector
= selector
;
809 env
->segs
[R_CS
].base
= (uint8_t *)(selector
<< 4);
810 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
813 /* fake user mode interrupt */
814 void do_interrupt_user(int intno
, int is_int
, int error_code
,
815 unsigned int next_eip
)
823 ptr
= dt
->base
+ (intno
* 8);
824 e2
= ldl_kernel(ptr
+ 4);
826 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
827 cpl
= env
->hflags
& HF_CPL_MASK
;
828 /* check privledge if software int */
829 if (is_int
&& dpl
< cpl
)
830 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
832 /* Since we emulate only user space, we cannot do more than
833 exiting the emulation with the suitable exception and error
840 * Begin excution of an interruption. is_int is TRUE if coming from
841 * the int instruction. next_eip is the EIP value AFTER the interrupt
842 * instruction. It is only relevant if is_int is TRUE.
844 void do_interrupt(int intno
, int is_int
, int error_code
,
845 unsigned int next_eip
, int is_hw
)
847 if (env
->cr
[0] & CR0_PE_MASK
) {
848 do_interrupt_protected(intno
, is_int
, error_code
, next_eip
, is_hw
);
850 do_interrupt_real(intno
, is_int
, error_code
, next_eip
);
855 * Signal an interruption. It is executed in the main CPU loop.
856 * is_int is TRUE if coming from the int instruction. next_eip is the
857 * EIP value AFTER the interrupt instruction. It is only relevant if
860 void raise_interrupt(int intno
, int is_int
, int error_code
,
861 unsigned int next_eip
)
863 env
->exception_index
= intno
;
864 env
->error_code
= error_code
;
865 env
->exception_is_int
= is_int
;
866 env
->exception_next_eip
= next_eip
;
870 /* shortcuts to generate exceptions */
871 void raise_exception_err(int exception_index
, int error_code
)
873 raise_interrupt(exception_index
, 0, error_code
, 0);
876 void raise_exception(int exception_index
)
878 raise_interrupt(exception_index
, 0, 0, 0);
881 #ifdef BUGGY_GCC_DIV64
882 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
883 call it from another function */
884 uint32_t div64(uint32_t *q_ptr
, uint64_t num
, uint32_t den
)
890 int32_t idiv64(int32_t *q_ptr
, int64_t num
, int32_t den
)
897 void helper_divl_EAX_T0(uint32_t eip
)
899 unsigned int den
, q
, r
;
902 num
= EAX
| ((uint64_t)EDX
<< 32);
906 raise_exception(EXCP00_DIVZ
);
908 #ifdef BUGGY_GCC_DIV64
909 r
= div64(&q
, num
, den
);
918 void helper_idivl_EAX_T0(uint32_t eip
)
923 num
= EAX
| ((uint64_t)EDX
<< 32);
927 raise_exception(EXCP00_DIVZ
);
929 #ifdef BUGGY_GCC_DIV64
930 r
= idiv64(&q
, num
, den
);
939 void helper_cmpxchg8b(void)
944 eflags
= cc_table
[CC_OP
].compute_all();
945 d
= ldq((uint8_t *)A0
);
946 if (d
== (((uint64_t)EDX
<< 32) | EAX
)) {
947 stq((uint8_t *)A0
, ((uint64_t)ECX
<< 32) | EBX
);
957 /* We simulate a pre-MMX pentium as in valgrind */
958 #define CPUID_FP87 (1 << 0)
959 #define CPUID_VME (1 << 1)
960 #define CPUID_DE (1 << 2)
961 #define CPUID_PSE (1 << 3)
962 #define CPUID_TSC (1 << 4)
963 #define CPUID_MSR (1 << 5)
964 #define CPUID_PAE (1 << 6)
965 #define CPUID_MCE (1 << 7)
966 #define CPUID_CX8 (1 << 8)
967 #define CPUID_APIC (1 << 9)
968 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
969 #define CPUID_MTRR (1 << 12)
970 #define CPUID_PGE (1 << 13)
971 #define CPUID_MCA (1 << 14)
972 #define CPUID_CMOV (1 << 15)
974 #define CPUID_MMX (1 << 23)
975 #define CPUID_FXSR (1 << 24)
976 #define CPUID_SSE (1 << 25)
977 #define CPUID_SSE2 (1 << 26)
979 void helper_cpuid(void)
982 EAX
= 1; /* max EAX index supported */
986 } else if (EAX
== 1) {
987 int family
, model
, stepping
;
1000 EAX
= (family
<< 8) | (model
<< 4) | stepping
;
1003 EDX
= CPUID_FP87
| CPUID_DE
| CPUID_PSE
|
1004 CPUID_TSC
| CPUID_MSR
| CPUID_MCE
|
1005 CPUID_CX8
| CPUID_PGE
| CPUID_CMOV
;
1009 void helper_lldt_T0(void)
1017 selector
= T0
& 0xffff;
1018 if ((selector
& 0xfffc) == 0) {
1019 /* XXX: NULL selector case: invalid LDT */
1020 env
->ldt
.base
= NULL
;
1024 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1026 index
= selector
& ~7;
1027 if ((index
+ 7) > dt
->limit
)
1028 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1029 ptr
= dt
->base
+ index
;
1030 e1
= ldl_kernel(ptr
);
1031 e2
= ldl_kernel(ptr
+ 4);
1032 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
1033 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1034 if (!(e2
& DESC_P_MASK
))
1035 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1036 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1038 env
->ldt
.selector
= selector
;
1041 void helper_ltr_T0(void)
1049 selector
= T0
& 0xffff;
1050 if ((selector
& 0xfffc) == 0) {
1051 /* NULL selector case: invalid LDT */
1052 env
->tr
.base
= NULL
;
1057 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1059 index
= selector
& ~7;
1060 if ((index
+ 7) > dt
->limit
)
1061 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1062 ptr
= dt
->base
+ index
;
1063 e1
= ldl_kernel(ptr
);
1064 e2
= ldl_kernel(ptr
+ 4);
1065 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1066 if ((e2
& DESC_S_MASK
) ||
1067 (type
!= 1 && type
!= 9))
1068 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1069 if (!(e2
& DESC_P_MASK
))
1070 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1071 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1072 e2
|= 0x00000200; /* set the busy bit */
1073 stl_kernel(ptr
+ 4, e2
);
1075 env
->tr
.selector
= selector
;
1078 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1079 void load_seg(int seg_reg
, int selector
, unsigned int cur_eip
)
1087 if ((selector
& 0xfffc) == 0) {
1088 /* null selector case */
1089 if (seg_reg
== R_SS
) {
1091 raise_exception_err(EXCP0D_GPF
, 0);
1093 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, NULL
, 0, 0);
1101 index
= selector
& ~7;
1102 if ((index
+ 7) > dt
->limit
) {
1104 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1106 ptr
= dt
->base
+ index
;
1107 e1
= ldl_kernel(ptr
);
1108 e2
= ldl_kernel(ptr
+ 4);
1110 if (!(e2
& DESC_S_MASK
)) {
1112 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1115 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1116 cpl
= env
->hflags
& HF_CPL_MASK
;
1117 if (seg_reg
== R_SS
) {
1118 /* must be writable segment */
1119 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
)) {
1121 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1123 if (rpl
!= cpl
|| dpl
!= cpl
) {
1125 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1128 /* must be readable segment */
1129 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
) {
1131 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1134 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1135 /* if not conforming code, test rights */
1136 if (dpl
< cpl
|| dpl
< rpl
) {
1138 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1143 if (!(e2
& DESC_P_MASK
)) {
1145 if (seg_reg
== R_SS
)
1146 raise_exception_err(EXCP0C_STACK
, selector
& 0xfffc);
1148 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1151 /* set the access bit if not already set */
1152 if (!(e2
& DESC_A_MASK
)) {
1154 stl_kernel(ptr
+ 4, e2
);
1157 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1158 get_seg_base(e1
, e2
),
1159 get_seg_limit(e1
, e2
),
1162 fprintf(logfile
, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1163 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1168 /* protected mode jump */
1169 void helper_ljmp_protected_T0_T1(void)
1171 int new_cs
, new_eip
, gate_cs
, type
;
1172 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1176 if ((new_cs
& 0xfffc) == 0)
1177 raise_exception_err(EXCP0D_GPF
, 0);
1178 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1179 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1180 cpl
= env
->hflags
& HF_CPL_MASK
;
1181 if (e2
& DESC_S_MASK
) {
1182 if (!(e2
& DESC_CS_MASK
))
1183 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1184 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1185 if (e2
& DESC_C_MASK
) {
1186 /* conforming code segment */
1188 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1190 /* non conforming code segment */
1193 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1195 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1197 if (!(e2
& DESC_P_MASK
))
1198 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1199 limit
= get_seg_limit(e1
, e2
);
1200 if (new_eip
> limit
)
1201 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1202 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1203 get_seg_base(e1
, e2
), limit
, e2
);
1206 /* jump to call or task gate */
1207 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1209 cpl
= env
->hflags
& HF_CPL_MASK
;
1210 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1212 case 1: /* 286 TSS */
1213 case 9: /* 386 TSS */
1214 case 5: /* task gate */
1215 if (dpl
< cpl
|| dpl
< rpl
)
1216 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1217 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_JMP
);
1219 case 4: /* 286 call gate */
1220 case 12: /* 386 call gate */
1221 if ((dpl
< cpl
) || (dpl
< rpl
))
1222 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1223 if (!(e2
& DESC_P_MASK
))
1224 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1226 if (load_segment(&e1
, &e2
, gate_cs
) != 0)
1227 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1228 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1229 /* must be code segment */
1230 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
1231 (DESC_S_MASK
| DESC_CS_MASK
)))
1232 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1233 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
1234 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
)))
1235 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1236 if (!(e2
& DESC_P_MASK
))
1237 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1238 new_eip
= (e1
& 0xffff);
1240 new_eip
|= (e2
& 0xffff0000);
1241 limit
= get_seg_limit(e1
, e2
);
1242 if (new_eip
> limit
)
1243 raise_exception_err(EXCP0D_GPF
, 0);
1244 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
1245 get_seg_base(e1
, e2
), limit
, e2
);
1249 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1255 /* real mode call */
1256 void helper_lcall_real_T0_T1(int shift
, int next_eip
)
1258 int new_cs
, new_eip
;
1259 uint32_t esp
, esp_mask
;
1265 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1266 ssp
= env
->segs
[R_SS
].base
;
1268 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1269 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
1271 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1272 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
1275 ESP
= (ESP
& ~esp_mask
) | (esp
& esp_mask
);
1277 env
->segs
[R_CS
].selector
= new_cs
;
1278 env
->segs
[R_CS
].base
= (uint8_t *)(new_cs
<< 4);
1281 /* protected mode call */
1282 void helper_lcall_protected_T0_T1(int shift
, int next_eip
)
1284 int new_cs
, new_eip
, new_stack
, i
;
1285 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
1286 uint32_t ss
, ss_e1
, ss_e2
, sp
, type
, ss_dpl
, sp_mask
;
1287 uint32_t val
, limit
, old_sp_mask
;
1288 uint8_t *ssp
, *old_ssp
;
1294 fprintf(logfile
, "lcall %04x:%08x\n",
1298 if ((new_cs
& 0xfffc) == 0)
1299 raise_exception_err(EXCP0D_GPF
, 0);
1300 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1301 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1302 cpl
= env
->hflags
& HF_CPL_MASK
;
1305 fprintf(logfile
, "desc=%08x:%08x\n", e1
, e2
);
1308 if (e2
& DESC_S_MASK
) {
1309 if (!(e2
& DESC_CS_MASK
))
1310 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1311 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1312 if (e2
& DESC_C_MASK
) {
1313 /* conforming code segment */
1315 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1317 /* non conforming code segment */
1320 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1322 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1324 if (!(e2
& DESC_P_MASK
))
1325 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1328 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1329 ssp
= env
->segs
[R_SS
].base
;
1331 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1332 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1334 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1335 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1338 limit
= get_seg_limit(e1
, e2
);
1339 if (new_eip
> limit
)
1340 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1341 /* from this point, not restartable */
1342 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1343 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1344 get_seg_base(e1
, e2
), limit
, e2
);
1347 /* check gate type */
1348 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
1349 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1352 case 1: /* available 286 TSS */
1353 case 9: /* available 386 TSS */
1354 case 5: /* task gate */
1355 if (dpl
< cpl
|| dpl
< rpl
)
1356 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1357 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_CALL
);
1359 case 4: /* 286 call gate */
1360 case 12: /* 386 call gate */
1363 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1368 if (dpl
< cpl
|| dpl
< rpl
)
1369 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1370 /* check valid bit */
1371 if (!(e2
& DESC_P_MASK
))
1372 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1373 selector
= e1
>> 16;
1374 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
1375 param_count
= e2
& 0x1f;
1376 if ((selector
& 0xfffc) == 0)
1377 raise_exception_err(EXCP0D_GPF
, 0);
1379 if (load_segment(&e1
, &e2
, selector
) != 0)
1380 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1381 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
1382 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1383 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1385 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1386 if (!(e2
& DESC_P_MASK
))
1387 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1389 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
1390 /* to inner priviledge */
1391 get_ss_esp_from_tss(&ss
, &sp
, dpl
);
1394 fprintf(logfile
, "ss=%04x sp=%04x param_count=%d ESP=%x\n",
1395 ss
, sp
, param_count
, ESP
);
1397 if ((ss
& 0xfffc) == 0)
1398 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1399 if ((ss
& 3) != dpl
)
1400 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1401 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
1402 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1403 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1405 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1406 if (!(ss_e2
& DESC_S_MASK
) ||
1407 (ss_e2
& DESC_CS_MASK
) ||
1408 !(ss_e2
& DESC_W_MASK
))
1409 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1410 if (!(ss_e2
& DESC_P_MASK
))
1411 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1413 // push_size = ((param_count * 2) + 8) << shift;
1415 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1416 old_ssp
= env
->segs
[R_SS
].base
;
1418 sp_mask
= get_sp_mask(ss_e2
);
1419 ssp
= get_seg_base(ss_e1
, ss_e2
);
1421 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1422 PUSHL(ssp
, sp
, sp_mask
, ESP
);
1423 for(i
= param_count
- 1; i
>= 0; i
--) {
1424 val
= ldl_kernel(old_ssp
+ ((ESP
+ i
* 4) & old_sp_mask
));
1425 PUSHL(ssp
, sp
, sp_mask
, val
);
1428 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1429 PUSHW(ssp
, sp
, sp_mask
, ESP
);
1430 for(i
= param_count
- 1; i
>= 0; i
--) {
1431 val
= lduw_kernel(old_ssp
+ ((ESP
+ i
* 2) & old_sp_mask
));
1432 PUSHW(ssp
, sp
, sp_mask
, val
);
1437 /* to same priviledge */
1439 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1440 ssp
= env
->segs
[R_SS
].base
;
1441 // push_size = (4 << shift);
1446 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1447 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1449 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1450 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1453 /* from this point, not restartable */
1456 ss
= (ss
& ~3) | dpl
;
1457 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
1459 get_seg_limit(ss_e1
, ss_e2
),
1463 selector
= (selector
& ~3) | dpl
;
1464 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
1465 get_seg_base(e1
, e2
),
1466 get_seg_limit(e1
, e2
),
1468 cpu_x86_set_cpl(env
, dpl
);
1469 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1474 /* real and vm86 mode iret */
1475 void helper_iret_real(int shift
)
1477 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
1481 sp_mask
= 0xffff; /* XXXX: use SS segment size ? */
1483 ssp
= env
->segs
[R_SS
].base
;
1486 POPL(ssp
, sp
, sp_mask
, new_eip
);
1487 POPL(ssp
, sp
, sp_mask
, new_cs
);
1489 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1492 POPW(ssp
, sp
, sp_mask
, new_eip
);
1493 POPW(ssp
, sp
, sp_mask
, new_cs
);
1494 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1496 ESP
= (ESP
& ~sp_mask
) | (sp
& 0xffff);
1497 load_seg_vm(R_CS
, new_cs
);
1499 if (env
->eflags
& VM_MASK
)
1500 eflags_mask
= FL_UPDATE_MASK32
| IF_MASK
| RF_MASK
;
1502 eflags_mask
= FL_UPDATE_CPL0_MASK
;
1504 eflags_mask
&= 0xffff;
1505 load_eflags(new_eflags
, eflags_mask
);
1508 /* protected mode iret */
1509 static inline void helper_ret_protected(int shift
, int is_iret
, int addend
)
1511 uint32_t sp
, new_cs
, new_eip
, new_eflags
, new_esp
, new_ss
, sp_mask
;
1512 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
1513 uint32_t e1
, e2
, ss_e1
, ss_e2
;
1514 int cpl
, dpl
, rpl
, eflags_mask
;
1517 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1519 ssp
= env
->segs
[R_SS
].base
;
1522 POPL(ssp
, sp
, sp_mask
, new_eip
);
1523 POPL(ssp
, sp
, sp_mask
, new_cs
);
1526 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1527 if (new_eflags
& VM_MASK
)
1528 goto return_to_vm86
;
1532 POPW(ssp
, sp
, sp_mask
, new_eip
);
1533 POPW(ssp
, sp
, sp_mask
, new_cs
);
1535 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1539 fprintf(logfile
, "lret new %04x:%08x\n",
1543 if ((new_cs
& 0xfffc) == 0)
1544 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1545 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1546 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1547 if (!(e2
& DESC_S_MASK
) ||
1548 !(e2
& DESC_CS_MASK
))
1549 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1550 cpl
= env
->hflags
& HF_CPL_MASK
;
1553 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1554 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1555 if (e2
& DESC_C_MASK
) {
1557 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1560 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1562 if (!(e2
& DESC_P_MASK
))
1563 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1567 /* return to same priledge level */
1568 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1569 get_seg_base(e1
, e2
),
1570 get_seg_limit(e1
, e2
),
1573 /* return to different priviledge level */
1576 POPL(ssp
, sp
, sp_mask
, new_esp
);
1577 POPL(ssp
, sp
, sp_mask
, new_ss
);
1581 POPW(ssp
, sp
, sp_mask
, new_esp
);
1582 POPW(ssp
, sp
, sp_mask
, new_ss
);
1585 if ((new_ss
& 3) != rpl
)
1586 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1587 if (load_segment(&ss_e1
, &ss_e2
, new_ss
) != 0)
1588 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1589 if (!(ss_e2
& DESC_S_MASK
) ||
1590 (ss_e2
& DESC_CS_MASK
) ||
1591 !(ss_e2
& DESC_W_MASK
))
1592 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1593 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1595 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1596 if (!(ss_e2
& DESC_P_MASK
))
1597 raise_exception_err(EXCP0B_NOSEG
, new_ss
& 0xfffc);
1599 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1600 get_seg_base(e1
, e2
),
1601 get_seg_limit(e1
, e2
),
1603 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
1604 get_seg_base(ss_e1
, ss_e2
),
1605 get_seg_limit(ss_e1
, ss_e2
),
1607 cpu_x86_set_cpl(env
, rpl
);
1609 /* XXX: change sp_mask according to old segment ? */
1611 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1614 /* NOTE: 'cpl' can be different from the current CPL */
1616 eflags_mask
= FL_UPDATE_CPL0_MASK
;
1618 eflags_mask
= FL_UPDATE_MASK32
;
1620 eflags_mask
&= 0xffff;
1621 load_eflags(new_eflags
, eflags_mask
);
1626 POPL(ssp
, sp
, sp_mask
, new_esp
);
1627 POPL(ssp
, sp
, sp_mask
, new_ss
);
1628 POPL(ssp
, sp
, sp_mask
, new_es
);
1629 POPL(ssp
, sp
, sp_mask
, new_ds
);
1630 POPL(ssp
, sp
, sp_mask
, new_fs
);
1631 POPL(ssp
, sp
, sp_mask
, new_gs
);
1633 /* modify processor state */
1634 load_eflags(new_eflags
, FL_UPDATE_CPL0_MASK
| VM_MASK
| VIF_MASK
| VIP_MASK
);
1635 load_seg_vm(R_CS
, new_cs
& 0xffff);
1636 cpu_x86_set_cpl(env
, 3);
1637 load_seg_vm(R_SS
, new_ss
& 0xffff);
1638 load_seg_vm(R_ES
, new_es
& 0xffff);
1639 load_seg_vm(R_DS
, new_ds
& 0xffff);
1640 load_seg_vm(R_FS
, new_fs
& 0xffff);
1641 load_seg_vm(R_GS
, new_gs
& 0xffff);
1647 void helper_iret_protected(int shift
)
1649 int tss_selector
, type
;
1652 /* specific case for TSS */
1653 if (env
->eflags
& NT_MASK
) {
1654 tss_selector
= lduw_kernel(env
->tr
.base
+ 0);
1655 if (tss_selector
& 4)
1656 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1657 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
1658 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1659 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
1660 /* NOTE: we check both segment and busy TSS */
1662 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1663 switch_tss(tss_selector
, e1
, e2
, SWITCH_TSS_IRET
);
1665 helper_ret_protected(shift
, 1, 0);
1669 void helper_lret_protected(int shift
, int addend
)
1671 helper_ret_protected(shift
, 0, addend
);
1674 void helper_movl_crN_T0(int reg
)
1679 cpu_x86_update_cr0(env
);
1682 cpu_x86_update_cr3(env
);
1688 void helper_movl_drN_T0(int reg
)
1693 void helper_invlpg(unsigned int addr
)
1695 cpu_x86_flush_tlb(env
, addr
);
1703 void helper_rdtsc(void)
1707 asm("rdtsc" : "=A" (val
));
1709 /* better than nothing: the time increases */
1716 void helper_wrmsr(void)
1719 case MSR_IA32_SYSENTER_CS
:
1720 env
->sysenter_cs
= EAX
& 0xffff;
1722 case MSR_IA32_SYSENTER_ESP
:
1723 env
->sysenter_esp
= EAX
;
1725 case MSR_IA32_SYSENTER_EIP
:
1726 env
->sysenter_eip
= EAX
;
1729 /* XXX: exception ? */
1734 void helper_rdmsr(void)
1737 case MSR_IA32_SYSENTER_CS
:
1738 EAX
= env
->sysenter_cs
;
1741 case MSR_IA32_SYSENTER_ESP
:
1742 EAX
= env
->sysenter_esp
;
1745 case MSR_IA32_SYSENTER_EIP
:
1746 EAX
= env
->sysenter_eip
;
1750 /* XXX: exception ? */
1755 void helper_lsl(void)
1757 unsigned int selector
, limit
;
1759 int rpl
, dpl
, cpl
, type
;
1761 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1762 selector
= T0
& 0xffff;
1763 if (load_segment(&e1
, &e2
, selector
) != 0)
1766 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1767 cpl
= env
->hflags
& HF_CPL_MASK
;
1768 if (e2
& DESC_S_MASK
) {
1769 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1772 if (dpl
< cpl
|| dpl
< rpl
)
1776 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1787 if (dpl
< cpl
|| dpl
< rpl
)
1790 limit
= get_seg_limit(e1
, e2
);
1795 void helper_lar(void)
1797 unsigned int selector
;
1799 int rpl
, dpl
, cpl
, type
;
1801 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1802 selector
= T0
& 0xffff;
1803 if ((selector
& 0xfffc) == 0)
1805 if (load_segment(&e1
, &e2
, selector
) != 0)
1808 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1809 cpl
= env
->hflags
& HF_CPL_MASK
;
1810 if (e2
& DESC_S_MASK
) {
1811 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1814 if (dpl
< cpl
|| dpl
< rpl
)
1818 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1832 if (dpl
< cpl
|| dpl
< rpl
)
1835 T1
= e2
& 0x00f0ff00;
1839 void helper_verr(void)
1841 unsigned int selector
;
1845 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1846 selector
= T0
& 0xffff;
1847 if ((selector
& 0xfffc) == 0)
1849 if (load_segment(&e1
, &e2
, selector
) != 0)
1851 if (!(e2
& DESC_S_MASK
))
1854 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1855 cpl
= env
->hflags
& HF_CPL_MASK
;
1856 if (e2
& DESC_CS_MASK
) {
1857 if (!(e2
& DESC_R_MASK
))
1859 if (!(e2
& DESC_C_MASK
)) {
1860 if (dpl
< cpl
|| dpl
< rpl
)
1864 if (dpl
< cpl
|| dpl
< rpl
)
1870 void helper_verw(void)
1872 unsigned int selector
;
1876 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1877 selector
= T0
& 0xffff;
1878 if ((selector
& 0xfffc) == 0)
1880 if (load_segment(&e1
, &e2
, selector
) != 0)
1882 if (!(e2
& DESC_S_MASK
))
1885 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1886 cpl
= env
->hflags
& HF_CPL_MASK
;
1887 if (e2
& DESC_CS_MASK
) {
1890 if (dpl
< cpl
|| dpl
< rpl
)
1892 if (!(e2
& DESC_W_MASK
))
1900 void helper_fldt_ST0_A0(void)
1903 new_fpstt
= (env
->fpstt
- 1) & 7;
1904 env
->fpregs
[new_fpstt
] = helper_fldt((uint8_t *)A0
);
1905 env
->fpstt
= new_fpstt
;
1906 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
1909 void helper_fstt_ST0_A0(void)
1911 helper_fstt(ST0
, (uint8_t *)A0
);
1916 #define MUL10(iv) ( iv + iv + (iv << 3) )
1918 void helper_fbld_ST0_A0(void)
1926 for(i
= 8; i
>= 0; i
--) {
1927 v
= ldub((uint8_t *)A0
+ i
);
1928 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
1931 if (ldub((uint8_t *)A0
+ 9) & 0x80)
1937 void helper_fbst_ST0_A0(void)
1941 uint8_t *mem_ref
, *mem_end
;
1946 mem_ref
= (uint8_t *)A0
;
1947 mem_end
= mem_ref
+ 9;
1954 while (mem_ref
< mem_end
) {
1959 v
= ((v
/ 10) << 4) | (v
% 10);
1962 while (mem_ref
< mem_end
) {
1967 void helper_f2xm1(void)
1969 ST0
= pow(2.0,ST0
) - 1.0;
1972 void helper_fyl2x(void)
1974 CPU86_LDouble fptemp
;
1978 fptemp
= log(fptemp
)/log(2.0); /* log2(ST) */
1982 env
->fpus
&= (~0x4700);
1987 void helper_fptan(void)
1989 CPU86_LDouble fptemp
;
1992 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
1998 env
->fpus
&= (~0x400); /* C2 <-- 0 */
1999 /* the above code is for |arg| < 2**52 only */
2003 void helper_fpatan(void)
2005 CPU86_LDouble fptemp
, fpsrcop
;
2009 ST1
= atan2(fpsrcop
,fptemp
);
2013 void helper_fxtract(void)
2015 CPU86_LDoubleU temp
;
2016 unsigned int expdif
;
2019 expdif
= EXPD(temp
) - EXPBIAS
;
2020 /*DP exponent bias*/
2027 void helper_fprem1(void)
2029 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2030 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2036 fpsrcop1
.d
= fpsrcop
;
2038 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2040 dblq
= fpsrcop
/ fptemp
;
2041 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2042 ST0
= fpsrcop
- fptemp
*dblq
;
2043 q
= (int)dblq
; /* cutting off top bits is assumed here */
2044 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2045 /* (C0,C1,C3) <-- (q2,q1,q0) */
2046 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2047 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2048 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2050 env
->fpus
|= 0x400; /* C2 <-- 1 */
2051 fptemp
= pow(2.0, expdif
-50);
2052 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2053 /* fpsrcop = integer obtained by rounding to the nearest */
2054 fpsrcop
= (fpsrcop
-floor(fpsrcop
) < ceil(fpsrcop
)-fpsrcop
)?
2055 floor(fpsrcop
): ceil(fpsrcop
);
2056 ST0
-= (ST1
* fpsrcop
* fptemp
);
2060 void helper_fprem(void)
2062 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2063 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2069 fpsrcop1
.d
= fpsrcop
;
2071 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2072 if ( expdif
< 53 ) {
2073 dblq
= fpsrcop
/ fptemp
;
2074 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2075 ST0
= fpsrcop
- fptemp
*dblq
;
2076 q
= (int)dblq
; /* cutting off top bits is assumed here */
2077 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2078 /* (C0,C1,C3) <-- (q2,q1,q0) */
2079 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2080 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2081 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2083 env
->fpus
|= 0x400; /* C2 <-- 1 */
2084 fptemp
= pow(2.0, expdif
-50);
2085 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2086 /* fpsrcop = integer obtained by chopping */
2087 fpsrcop
= (fpsrcop
< 0.0)?
2088 -(floor(fabs(fpsrcop
))): floor(fpsrcop
);
2089 ST0
-= (ST1
* fpsrcop
* fptemp
);
2093 void helper_fyl2xp1(void)
2095 CPU86_LDouble fptemp
;
2098 if ((fptemp
+1.0)>0.0) {
2099 fptemp
= log(fptemp
+1.0) / log(2.0); /* log2(ST+1.0) */
2103 env
->fpus
&= (~0x4700);
2108 void helper_fsqrt(void)
2110 CPU86_LDouble fptemp
;
2114 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2120 void helper_fsincos(void)
2122 CPU86_LDouble fptemp
;
2125 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2131 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2132 /* the above code is for |arg| < 2**63 only */
2136 void helper_frndint(void)
2142 switch(env
->fpuc
& RC_MASK
) {
2145 asm("rndd %0, %1" : "=f" (a
) : "f"(a
));
2148 asm("rnddm %0, %1" : "=f" (a
) : "f"(a
));
2151 asm("rnddp %0, %1" : "=f" (a
) : "f"(a
));
2154 asm("rnddz %0, %1" : "=f" (a
) : "f"(a
));
2163 void helper_fscale(void)
2165 CPU86_LDouble fpsrcop
, fptemp
;
2168 fptemp
= pow(fpsrcop
,ST1
);
2172 void helper_fsin(void)
2174 CPU86_LDouble fptemp
;
2177 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2181 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2182 /* the above code is for |arg| < 2**53 only */
2186 void helper_fcos(void)
2188 CPU86_LDouble fptemp
;
2191 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2195 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2196 /* the above code is for |arg5 < 2**63 only */
2200 void helper_fxam_ST0(void)
2202 CPU86_LDoubleU temp
;
2207 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2209 env
->fpus
|= 0x200; /* C1 <-- 1 */
2211 expdif
= EXPD(temp
);
2212 if (expdif
== MAXEXPD
) {
2213 if (MANTD(temp
) == 0)
2214 env
->fpus
|= 0x500 /*Infinity*/;
2216 env
->fpus
|= 0x100 /*NaN*/;
2217 } else if (expdif
== 0) {
2218 if (MANTD(temp
) == 0)
2219 env
->fpus
|= 0x4000 /*Zero*/;
2221 env
->fpus
|= 0x4400 /*Denormal*/;
2227 void helper_fstenv(uint8_t *ptr
, int data32
)
2229 int fpus
, fptag
, exp
, i
;
2233 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
2235 for (i
=7; i
>=0; i
--) {
2237 if (env
->fptags
[i
]) {
2240 tmp
.d
= env
->fpregs
[i
];
2243 if (exp
== 0 && mant
== 0) {
2246 } else if (exp
== 0 || exp
== MAXEXPD
2247 #ifdef USE_X86LDOUBLE
2248 || (mant
& (1LL << 63)) == 0
2251 /* NaNs, infinity, denormal */
2258 stl(ptr
, env
->fpuc
);
2260 stl(ptr
+ 8, fptag
);
2267 stw(ptr
, env
->fpuc
);
2269 stw(ptr
+ 4, fptag
);
2277 void helper_fldenv(uint8_t *ptr
, int data32
)
2282 env
->fpuc
= lduw(ptr
);
2283 fpus
= lduw(ptr
+ 4);
2284 fptag
= lduw(ptr
+ 8);
2287 env
->fpuc
= lduw(ptr
);
2288 fpus
= lduw(ptr
+ 2);
2289 fptag
= lduw(ptr
+ 4);
2291 env
->fpstt
= (fpus
>> 11) & 7;
2292 env
->fpus
= fpus
& ~0x3800;
2293 for(i
= 0;i
< 7; i
++) {
2294 env
->fptags
[i
] = ((fptag
& 3) == 3);
2299 void helper_fsave(uint8_t *ptr
, int data32
)
2304 helper_fstenv(ptr
, data32
);
2306 ptr
+= (14 << data32
);
2307 for(i
= 0;i
< 8; i
++) {
2309 helper_fstt(tmp
, ptr
);
2327 void helper_frstor(uint8_t *ptr
, int data32
)
2332 helper_fldenv(ptr
, data32
);
2333 ptr
+= (14 << data32
);
2335 for(i
= 0;i
< 8; i
++) {
2336 tmp
= helper_fldt(ptr
);
2342 #if !defined(CONFIG_USER_ONLY)
2344 #define MMUSUFFIX _mmu
2345 #define GETPC() (__builtin_return_address(0))
2348 #include "softmmu_template.h"
2351 #include "softmmu_template.h"
2354 #include "softmmu_template.h"
2357 #include "softmmu_template.h"
2361 /* try to fill the TLB and return an exception if error. If retaddr is
2362 NULL, it means that the function was called in C code (i.e. not
2363 from generated code or from helper.c) */
2364 /* XXX: fix it to restore all registers */
2365 void tlb_fill(unsigned long addr
, int is_write
, int is_user
, void *retaddr
)
2367 TranslationBlock
*tb
;
2370 CPUX86State
*saved_env
;
2372 /* XXX: hack to restore env in all cases, even if not called from
2375 env
= cpu_single_env
;
2376 if (is_write
&& page_unprotect(addr
)) {
2377 /* nothing more to do: the page was write protected because
2378 there was code in it. page_unprotect() flushed the code. */
2381 ret
= cpu_x86_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
2384 /* now we have a real cpu fault */
2385 pc
= (unsigned long)retaddr
;
2386 tb
= tb_find_pc(pc
);
2388 /* the PC is inside the translated code. It means that we have
2389 a virtual CPU fault */
2390 cpu_restore_state(tb
, env
, pc
);
2393 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);