4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 const uint8_t parity_table
[256] = {
25 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
26 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
27 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
28 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
29 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
30 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
31 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
32 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
33 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
34 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
35 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
36 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
37 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
38 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
39 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
40 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
41 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
42 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
43 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
44 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
45 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
46 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
47 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
48 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
49 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
50 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
51 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
52 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
53 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
54 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
55 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
56 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
60 const uint8_t rclw_table
[32] = {
61 0, 1, 2, 3, 4, 5, 6, 7,
62 8, 9,10,11,12,13,14,15,
63 16, 0, 1, 2, 3, 4, 5, 6,
64 7, 8, 9,10,11,12,13,14,
68 const uint8_t rclb_table
[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 0, 1, 2, 3, 4, 5, 6,
71 7, 8, 0, 1, 2, 3, 4, 5,
72 6, 7, 8, 0, 1, 2, 3, 4,
75 const CPU86_LDouble f15rk
[7] =
77 0.00000000000000000000L,
78 1.00000000000000000000L,
79 3.14159265358979323851L, /*pi*/
80 0.30102999566398119523L, /*lg2*/
81 0.69314718055994530943L, /*ln2*/
82 1.44269504088896340739L, /*l2e*/
83 3.32192809488736234781L, /*l2t*/
88 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
92 spin_lock(&global_cpu_lock
);
97 spin_unlock(&global_cpu_lock
);
100 void cpu_loop_exit(void)
102 /* NOTE: the register at this point must be saved by hand because
103 longjmp restore them */
105 env
->regs
[R_EAX
] = EAX
;
108 env
->regs
[R_ECX
] = ECX
;
111 env
->regs
[R_EDX
] = EDX
;
114 env
->regs
[R_EBX
] = EBX
;
117 env
->regs
[R_ESP
] = ESP
;
120 env
->regs
[R_EBP
] = EBP
;
123 env
->regs
[R_ESI
] = ESI
;
126 env
->regs
[R_EDI
] = EDI
;
128 longjmp(env
->jmp_env
, 1);
131 /* return non zero if error */
132 static inline int load_segment(uint32_t *e1_ptr
, uint32_t *e2_ptr
,
143 index
= selector
& ~7;
144 if ((index
+ 7) > dt
->limit
)
146 ptr
= dt
->base
+ index
;
147 *e1_ptr
= ldl_kernel(ptr
);
148 *e2_ptr
= ldl_kernel(ptr
+ 4);
152 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
155 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
156 if (e2
& DESC_G_MASK
)
157 limit
= (limit
<< 12) | 0xfff;
161 static inline uint8_t *get_seg_base(uint32_t e1
, uint32_t e2
)
163 return (uint8_t *)((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
166 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
, uint32_t e2
)
168 sc
->base
= get_seg_base(e1
, e2
);
169 sc
->limit
= get_seg_limit(e1
, e2
);
173 /* init the segment cache in vm86 mode. */
174 static inline void load_seg_vm(int seg
, int selector
)
177 cpu_x86_load_seg_cache(env
, seg
, selector
,
178 (uint8_t *)(selector
<< 4), 0xffff, 0);
181 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr
,
182 uint32_t *esp_ptr
, int dpl
)
184 int type
, index
, shift
;
189 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
190 for(i
=0;i
<env
->tr
.limit
;i
++) {
191 printf("%02x ", env
->tr
.base
[i
]);
192 if ((i
& 7) == 7) printf("\n");
198 if (!(env
->tr
.flags
& DESC_P_MASK
))
199 cpu_abort(env
, "invalid tss");
200 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
202 cpu_abort(env
, "invalid tss type");
204 index
= (dpl
* 4 + 2) << shift
;
205 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
)
206 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
208 *esp_ptr
= lduw_kernel(env
->tr
.base
+ index
);
209 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 2);
211 *esp_ptr
= ldl_kernel(env
->tr
.base
+ index
);
212 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 4);
216 /* XXX: merge with load_seg() */
217 static void tss_load_seg(int seg_reg
, int selector
)
222 if ((selector
& 0xfffc) != 0) {
223 if (load_segment(&e1
, &e2
, selector
) != 0)
224 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
225 if (!(e2
& DESC_S_MASK
))
226 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
228 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
229 cpl
= env
->hflags
& HF_CPL_MASK
;
230 if (seg_reg
== R_CS
) {
231 if (!(e2
& DESC_CS_MASK
))
232 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
234 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
235 if ((e2
& DESC_C_MASK
) && dpl
> rpl
)
236 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
238 } else if (seg_reg
== R_SS
) {
239 /* SS must be writable data */
240 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
241 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
242 if (dpl
!= cpl
|| dpl
!= rpl
)
243 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
245 /* not readable code */
246 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
))
247 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
248 /* if data or non conforming code, checks the rights */
249 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
250 if (dpl
< cpl
|| dpl
< rpl
)
251 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
254 if (!(e2
& DESC_P_MASK
))
255 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
256 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
257 get_seg_base(e1
, e2
),
258 get_seg_limit(e1
, e2
),
261 if (seg_reg
== R_SS
|| seg_reg
== R_CS
)
262 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
266 #define SWITCH_TSS_JMP 0
267 #define SWITCH_TSS_IRET 1
268 #define SWITCH_TSS_CALL 2
270 /* XXX: restore CPU state in registers (PowerPC case) */
271 static void switch_tss(int tss_selector
,
272 uint32_t e1
, uint32_t e2
, int source
)
274 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
276 uint32_t new_regs
[8], new_segs
[6];
277 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
278 uint32_t old_eflags
, eflags_mask
;
283 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
285 /* if task gate, we read the TSS segment and we load it */
287 if (!(e2
& DESC_P_MASK
))
288 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
289 tss_selector
= e1
>> 16;
290 if (tss_selector
& 4)
291 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
292 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
293 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
294 if (e2
& DESC_S_MASK
)
295 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
296 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
298 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
301 if (!(e2
& DESC_P_MASK
))
302 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
308 tss_limit
= get_seg_limit(e1
, e2
);
309 tss_base
= get_seg_base(e1
, e2
);
310 if ((tss_selector
& 4) != 0 ||
311 tss_limit
< tss_limit_max
)
312 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
313 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
315 old_tss_limit_max
= 103;
317 old_tss_limit_max
= 43;
319 /* read all the registers from the new TSS */
322 new_cr3
= ldl_kernel(tss_base
+ 0x1c);
323 new_eip
= ldl_kernel(tss_base
+ 0x20);
324 new_eflags
= ldl_kernel(tss_base
+ 0x24);
325 for(i
= 0; i
< 8; i
++)
326 new_regs
[i
] = ldl_kernel(tss_base
+ (0x28 + i
* 4));
327 for(i
= 0; i
< 6; i
++)
328 new_segs
[i
] = lduw_kernel(tss_base
+ (0x48 + i
* 4));
329 new_ldt
= lduw_kernel(tss_base
+ 0x60);
330 new_trap
= ldl_kernel(tss_base
+ 0x64);
334 new_eip
= lduw_kernel(tss_base
+ 0x0e);
335 new_eflags
= lduw_kernel(tss_base
+ 0x10);
336 for(i
= 0; i
< 8; i
++)
337 new_regs
[i
] = lduw_kernel(tss_base
+ (0x12 + i
* 2)) | 0xffff0000;
338 for(i
= 0; i
< 4; i
++)
339 new_segs
[i
] = lduw_kernel(tss_base
+ (0x22 + i
* 4));
340 new_ldt
= lduw_kernel(tss_base
+ 0x2a);
346 /* NOTE: we must avoid memory exceptions during the task switch,
347 so we make dummy accesses before */
348 /* XXX: it can still fail in some cases, so a bigger hack is
349 necessary to valid the TLB after having done the accesses */
351 v1
= ldub_kernel(env
->tr
.base
);
352 v2
= ldub(env
->tr
.base
+ old_tss_limit_max
);
353 stb_kernel(env
->tr
.base
, v1
);
354 stb_kernel(env
->tr
.base
+ old_tss_limit_max
, v2
);
356 /* clear busy bit (it is restartable) */
357 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
360 ptr
= env
->gdt
.base
+ (env
->tr
.selector
<< 3);
361 e2
= ldl_kernel(ptr
+ 4);
362 e2
&= ~DESC_TSS_BUSY_MASK
;
363 stl_kernel(ptr
+ 4, e2
);
365 old_eflags
= compute_eflags();
366 if (source
== SWITCH_TSS_IRET
)
367 old_eflags
&= ~NT_MASK
;
369 /* save the current state in the old TSS */
372 stl_kernel(env
->tr
.base
+ 0x20, env
->eip
);
373 stl_kernel(env
->tr
.base
+ 0x24, old_eflags
);
374 for(i
= 0; i
< 8; i
++)
375 stl_kernel(env
->tr
.base
+ (0x28 + i
* 4), env
->regs
[i
]);
376 for(i
= 0; i
< 6; i
++)
377 stw_kernel(env
->tr
.base
+ (0x48 + i
* 4), env
->segs
[i
].selector
);
380 stw_kernel(env
->tr
.base
+ 0x0e, new_eip
);
381 stw_kernel(env
->tr
.base
+ 0x10, old_eflags
);
382 for(i
= 0; i
< 8; i
++)
383 stw_kernel(env
->tr
.base
+ (0x12 + i
* 2), env
->regs
[i
]);
384 for(i
= 0; i
< 4; i
++)
385 stw_kernel(env
->tr
.base
+ (0x22 + i
* 4), env
->segs
[i
].selector
);
388 /* now if an exception occurs, it will occurs in the next task
391 if (source
== SWITCH_TSS_CALL
) {
392 stw_kernel(tss_base
, env
->tr
.selector
);
393 new_eflags
|= NT_MASK
;
397 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
400 ptr
= env
->gdt
.base
+ (tss_selector
<< 3);
401 e2
= ldl_kernel(ptr
+ 4);
402 e2
|= DESC_TSS_BUSY_MASK
;
403 stl_kernel(ptr
+ 4, e2
);
406 /* set the new CPU state */
407 /* from this point, any exception which occurs can give problems */
408 env
->cr
[0] |= CR0_TS_MASK
;
409 env
->tr
.selector
= tss_selector
;
410 env
->tr
.base
= tss_base
;
411 env
->tr
.limit
= tss_limit
;
412 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
414 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
415 env
->cr
[3] = new_cr3
;
416 cpu_x86_update_cr3(env
);
419 /* load all registers without an exception, then reload them with
420 possible exception */
422 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
|
423 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
;
425 eflags_mask
&= 0xffff;
426 load_eflags(new_eflags
, eflags_mask
);
427 for(i
= 0; i
< 8; i
++)
428 env
->regs
[i
] = new_regs
[i
];
429 if (new_eflags
& VM_MASK
) {
430 for(i
= 0; i
< 6; i
++)
431 load_seg_vm(i
, new_segs
[i
]);
432 /* in vm86, CPL is always 3 */
433 cpu_x86_set_cpl(env
, 3);
435 /* CPL is set the RPL of CS */
436 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
437 /* first just selectors as the rest may trigger exceptions */
438 for(i
= 0; i
< 6; i
++)
439 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], NULL
, 0, 0);
442 env
->ldt
.selector
= new_ldt
& ~4;
443 env
->ldt
.base
= NULL
;
449 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
452 index
= new_ldt
& ~7;
453 if ((index
+ 7) > dt
->limit
)
454 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
455 ptr
= dt
->base
+ index
;
456 e1
= ldl_kernel(ptr
);
457 e2
= ldl_kernel(ptr
+ 4);
458 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
459 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
460 if (!(e2
& DESC_P_MASK
))
461 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
462 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
464 /* load the segments */
465 if (!(new_eflags
& VM_MASK
)) {
466 tss_load_seg(R_CS
, new_segs
[R_CS
]);
467 tss_load_seg(R_SS
, new_segs
[R_SS
]);
468 tss_load_seg(R_ES
, new_segs
[R_ES
]);
469 tss_load_seg(R_DS
, new_segs
[R_DS
]);
470 tss_load_seg(R_FS
, new_segs
[R_FS
]);
471 tss_load_seg(R_GS
, new_segs
[R_GS
]);
474 /* check that EIP is in the CS segment limits */
475 if (new_eip
> env
->segs
[R_CS
].limit
) {
476 raise_exception_err(EXCP0D_GPF
, 0);
480 /* check if Port I/O is allowed in TSS */
481 static inline void check_io(int addr
, int size
)
483 int io_offset
, val
, mask
;
485 /* TSS must be a valid 32 bit one */
486 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
487 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
490 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
491 io_offset
+= (addr
>> 3);
492 /* Note: the check needs two bytes */
493 if ((io_offset
+ 1) > env
->tr
.limit
)
495 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
497 mask
= (1 << size
) - 1;
498 /* all bits must be zero to allow the I/O */
499 if ((val
& mask
) != 0) {
501 raise_exception_err(EXCP0D_GPF
, 0);
505 void check_iob_T0(void)
510 void check_iow_T0(void)
515 void check_iol_T0(void)
520 void check_iob_DX(void)
522 check_io(EDX
& 0xffff, 1);
525 void check_iow_DX(void)
527 check_io(EDX
& 0xffff, 2);
530 void check_iol_DX(void)
532 check_io(EDX
& 0xffff, 4);
535 static inline unsigned int get_sp_mask(unsigned int e2
)
537 if (e2
& DESC_B_MASK
)
543 /* XXX: add a is_user flag to have proper security support */
544 #define PUSHW(ssp, sp, sp_mask, val)\
547 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
550 #define PUSHL(ssp, sp, sp_mask, val)\
553 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
556 #define POPW(ssp, sp, sp_mask, val)\
558 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
562 #define POPL(ssp, sp, sp_mask, val)\
564 val = ldl_kernel((ssp) + (sp & (sp_mask)));\
568 /* protected mode interrupt */
569 static void do_interrupt_protected(int intno
, int is_int
, int error_code
,
570 unsigned int next_eip
, int is_hw
)
574 int type
, dpl
, selector
, ss_dpl
, cpl
, sp_mask
;
575 int has_error_code
, new_stack
, shift
;
576 uint32_t e1
, e2
, offset
, ss
, esp
, ss_e1
, ss_e2
;
580 if (!is_int
&& !is_hw
) {
595 if (intno
* 8 + 7 > dt
->limit
)
596 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
597 ptr
= dt
->base
+ intno
* 8;
598 e1
= ldl_kernel(ptr
);
599 e2
= ldl_kernel(ptr
+ 4);
600 /* check gate type */
601 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
603 case 5: /* task gate */
604 /* must do that check here to return the correct error code */
605 if (!(e2
& DESC_P_MASK
))
606 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
607 switch_tss(intno
* 8, e1
, e2
, SWITCH_TSS_CALL
);
608 if (has_error_code
) {
610 /* push the error code */
611 shift
= (env
->segs
[R_CS
].flags
>> DESC_B_SHIFT
) & 1;
612 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
616 esp
= (env
->regs
[R_ESP
] - (2 << shift
)) & mask
;
617 ssp
= env
->segs
[R_SS
].base
+ esp
;
619 stl_kernel(ssp
, error_code
);
621 stw_kernel(ssp
, error_code
);
622 env
->regs
[R_ESP
] = (esp
& mask
) | (env
->regs
[R_ESP
] & ~mask
);
625 case 6: /* 286 interrupt gate */
626 case 7: /* 286 trap gate */
627 case 14: /* 386 interrupt gate */
628 case 15: /* 386 trap gate */
631 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
634 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
635 cpl
= env
->hflags
& HF_CPL_MASK
;
636 /* check privledge if software int */
637 if (is_int
&& dpl
< cpl
)
638 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
639 /* check valid bit */
640 if (!(e2
& DESC_P_MASK
))
641 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
643 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
644 if ((selector
& 0xfffc) == 0)
645 raise_exception_err(EXCP0D_GPF
, 0);
647 if (load_segment(&e1
, &e2
, selector
) != 0)
648 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
649 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
650 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
651 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
653 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
654 if (!(e2
& DESC_P_MASK
))
655 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
656 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
657 /* to inner priviledge */
658 get_ss_esp_from_tss(&ss
, &esp
, dpl
);
659 if ((ss
& 0xfffc) == 0)
660 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
662 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
663 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
664 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
665 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
667 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
668 if (!(ss_e2
& DESC_S_MASK
) ||
669 (ss_e2
& DESC_CS_MASK
) ||
670 !(ss_e2
& DESC_W_MASK
))
671 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
672 if (!(ss_e2
& DESC_P_MASK
))
673 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
675 sp_mask
= get_sp_mask(ss_e2
);
676 ssp
= get_seg_base(ss_e1
, ss_e2
);
677 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
678 /* to same priviledge */
679 if (env
->eflags
& VM_MASK
)
680 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
682 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
683 ssp
= env
->segs
[R_SS
].base
;
686 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
687 new_stack
= 0; /* avoid warning */
688 sp_mask
= 0; /* avoid warning */
689 ssp
= NULL
; /* avoid warning */
690 esp
= 0; /* avoid warning */
696 /* XXX: check that enough room is available */
697 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
698 if (env
->eflags
& VM_MASK
)
708 if (env
->eflags
& VM_MASK
) {
709 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
710 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
711 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
712 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
714 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
715 PUSHL(ssp
, esp
, sp_mask
, ESP
);
717 PUSHL(ssp
, esp
, sp_mask
, compute_eflags());
718 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
719 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
720 if (has_error_code
) {
721 PUSHL(ssp
, esp
, sp_mask
, error_code
);
725 if (env
->eflags
& VM_MASK
) {
726 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
727 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
728 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
729 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
731 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
732 PUSHW(ssp
, esp
, sp_mask
, ESP
);
734 PUSHW(ssp
, esp
, sp_mask
, compute_eflags());
735 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
736 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
737 if (has_error_code
) {
738 PUSHW(ssp
, esp
, sp_mask
, error_code
);
743 if (env
->eflags
& VM_MASK
) {
744 /* XXX: explain me why W2K hangs if the whole segment cache is
746 env
->segs
[R_ES
].selector
= 0;
747 env
->segs
[R_ES
].flags
= 0;
748 env
->segs
[R_DS
].selector
= 0;
749 env
->segs
[R_DS
].flags
= 0;
750 env
->segs
[R_FS
].selector
= 0;
751 env
->segs
[R_FS
].flags
= 0;
752 env
->segs
[R_GS
].selector
= 0;
753 env
->segs
[R_GS
].flags
= 0;
755 ss
= (ss
& ~3) | dpl
;
756 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
757 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
759 ESP
= (ESP
& ~sp_mask
) | (esp
& sp_mask
);
761 selector
= (selector
& ~3) | dpl
;
762 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
763 get_seg_base(e1
, e2
),
764 get_seg_limit(e1
, e2
),
766 cpu_x86_set_cpl(env
, dpl
);
769 /* interrupt gate clear IF mask */
770 if ((type
& 1) == 0) {
771 env
->eflags
&= ~IF_MASK
;
773 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
776 /* real mode interrupt */
777 static void do_interrupt_real(int intno
, int is_int
, int error_code
,
778 unsigned int next_eip
)
783 uint32_t offset
, esp
;
784 uint32_t old_cs
, old_eip
;
786 /* real mode (simpler !) */
788 if (intno
* 4 + 3 > dt
->limit
)
789 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
790 ptr
= dt
->base
+ intno
* 4;
791 offset
= lduw_kernel(ptr
);
792 selector
= lduw_kernel(ptr
+ 2);
794 ssp
= env
->segs
[R_SS
].base
;
799 old_cs
= env
->segs
[R_CS
].selector
;
800 /* XXX: use SS segment size ? */
801 PUSHW(ssp
, esp
, 0xffff, compute_eflags());
802 PUSHW(ssp
, esp
, 0xffff, old_cs
);
803 PUSHW(ssp
, esp
, 0xffff, old_eip
);
805 /* update processor state */
806 ESP
= (ESP
& ~0xffff) | (esp
& 0xffff);
808 env
->segs
[R_CS
].selector
= selector
;
809 env
->segs
[R_CS
].base
= (uint8_t *)(selector
<< 4);
810 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
813 /* fake user mode interrupt */
814 void do_interrupt_user(int intno
, int is_int
, int error_code
,
815 unsigned int next_eip
)
823 ptr
= dt
->base
+ (intno
* 8);
824 e2
= ldl_kernel(ptr
+ 4);
826 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
827 cpl
= env
->hflags
& HF_CPL_MASK
;
828 /* check privledge if software int */
829 if (is_int
&& dpl
< cpl
)
830 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
832 /* Since we emulate only user space, we cannot do more than
833 exiting the emulation with the suitable exception and error
840 * Begin excution of an interruption. is_int is TRUE if coming from
841 * the int instruction. next_eip is the EIP value AFTER the interrupt
842 * instruction. It is only relevant if is_int is TRUE.
844 void do_interrupt(int intno
, int is_int
, int error_code
,
845 unsigned int next_eip
, int is_hw
)
851 if (env
->cr
[0] & CR0_PE_MASK
) {
852 fprintf(stdout
, "%d: interrupt: vector=%02x error_code=%04x int=%d\n",
853 count
, intno
, error_code
, is_int
);
857 if ((env
->cr
[0] & CR0_PE_MASK
) && intno
== 0x10) {
859 cpu_set_log(CPU_LOG_ALL
);
865 fprintf(logfile
, "%d: interrupt: vector=%02x error_code=%04x int=%d\n",
866 count
, intno
, error_code
, is_int
);
867 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
872 fprintf(logfile
, " code=");
873 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
874 for(i
= 0; i
< 16; i
++) {
875 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
877 fprintf(logfile
, "\n");
883 if (env
->cr
[0] & CR0_PE_MASK
) {
884 do_interrupt_protected(intno
, is_int
, error_code
, next_eip
, is_hw
);
886 do_interrupt_real(intno
, is_int
, error_code
, next_eip
);
891 * Signal an interruption. It is executed in the main CPU loop.
892 * is_int is TRUE if coming from the int instruction. next_eip is the
893 * EIP value AFTER the interrupt instruction. It is only relevant if
896 void raise_interrupt(int intno
, int is_int
, int error_code
,
897 unsigned int next_eip
)
899 env
->exception_index
= intno
;
900 env
->error_code
= error_code
;
901 env
->exception_is_int
= is_int
;
902 env
->exception_next_eip
= next_eip
;
906 /* shortcuts to generate exceptions */
907 void raise_exception_err(int exception_index
, int error_code
)
909 raise_interrupt(exception_index
, 0, error_code
, 0);
912 void raise_exception(int exception_index
)
914 raise_interrupt(exception_index
, 0, 0, 0);
917 #ifdef BUGGY_GCC_DIV64
918 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
919 call it from another function */
920 uint32_t div64(uint32_t *q_ptr
, uint64_t num
, uint32_t den
)
926 int32_t idiv64(int32_t *q_ptr
, int64_t num
, int32_t den
)
933 void helper_divl_EAX_T0(uint32_t eip
)
935 unsigned int den
, q
, r
;
938 num
= EAX
| ((uint64_t)EDX
<< 32);
942 raise_exception(EXCP00_DIVZ
);
944 #ifdef BUGGY_GCC_DIV64
945 r
= div64(&q
, num
, den
);
954 void helper_idivl_EAX_T0(uint32_t eip
)
959 num
= EAX
| ((uint64_t)EDX
<< 32);
963 raise_exception(EXCP00_DIVZ
);
965 #ifdef BUGGY_GCC_DIV64
966 r
= idiv64(&q
, num
, den
);
975 void helper_cmpxchg8b(void)
980 eflags
= cc_table
[CC_OP
].compute_all();
981 d
= ldq((uint8_t *)A0
);
982 if (d
== (((uint64_t)EDX
<< 32) | EAX
)) {
983 stq((uint8_t *)A0
, ((uint64_t)ECX
<< 32) | EBX
);
993 #define CPUID_FP87 (1 << 0)
994 #define CPUID_VME (1 << 1)
995 #define CPUID_DE (1 << 2)
996 #define CPUID_PSE (1 << 3)
997 #define CPUID_TSC (1 << 4)
998 #define CPUID_MSR (1 << 5)
999 #define CPUID_PAE (1 << 6)
1000 #define CPUID_MCE (1 << 7)
1001 #define CPUID_CX8 (1 << 8)
1002 #define CPUID_APIC (1 << 9)
1003 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
1004 #define CPUID_MTRR (1 << 12)
1005 #define CPUID_PGE (1 << 13)
1006 #define CPUID_MCA (1 << 14)
1007 #define CPUID_CMOV (1 << 15)
1009 #define CPUID_MMX (1 << 23)
1010 #define CPUID_FXSR (1 << 24)
1011 #define CPUID_SSE (1 << 25)
1012 #define CPUID_SSE2 (1 << 26)
1014 void helper_cpuid(void)
1018 EAX
= 2; /* max EAX index supported */
1025 int family
, model
, stepping
;
1028 /* pentium 75-200 */
1038 EAX
= (family
<< 8) | (model
<< 4) | stepping
;
1041 EDX
= CPUID_FP87
| CPUID_DE
| CPUID_PSE
|
1042 CPUID_TSC
| CPUID_MSR
| CPUID_MCE
|
1043 CPUID_CX8
| CPUID_PGE
| CPUID_CMOV
;
1047 /* cache info: needed for Pentium Pro compatibility */
1056 void helper_lldt_T0(void)
1064 selector
= T0
& 0xffff;
1065 if ((selector
& 0xfffc) == 0) {
1066 /* XXX: NULL selector case: invalid LDT */
1067 env
->ldt
.base
= NULL
;
1071 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1073 index
= selector
& ~7;
1074 if ((index
+ 7) > dt
->limit
)
1075 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1076 ptr
= dt
->base
+ index
;
1077 e1
= ldl_kernel(ptr
);
1078 e2
= ldl_kernel(ptr
+ 4);
1079 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
1080 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1081 if (!(e2
& DESC_P_MASK
))
1082 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1083 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1085 env
->ldt
.selector
= selector
;
1088 void helper_ltr_T0(void)
1096 selector
= T0
& 0xffff;
1097 if ((selector
& 0xfffc) == 0) {
1098 /* NULL selector case: invalid LDT */
1099 env
->tr
.base
= NULL
;
1104 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1106 index
= selector
& ~7;
1107 if ((index
+ 7) > dt
->limit
)
1108 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1109 ptr
= dt
->base
+ index
;
1110 e1
= ldl_kernel(ptr
);
1111 e2
= ldl_kernel(ptr
+ 4);
1112 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1113 if ((e2
& DESC_S_MASK
) ||
1114 (type
!= 1 && type
!= 9))
1115 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1116 if (!(e2
& DESC_P_MASK
))
1117 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1118 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1119 e2
|= DESC_TSS_BUSY_MASK
;
1120 stl_kernel(ptr
+ 4, e2
);
1122 env
->tr
.selector
= selector
;
1125 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1126 void load_seg(int seg_reg
, int selector
)
1135 if ((selector
& 0xfffc) == 0) {
1136 /* null selector case */
1137 if (seg_reg
== R_SS
)
1138 raise_exception_err(EXCP0D_GPF
, 0);
1139 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, NULL
, 0, 0);
1146 index
= selector
& ~7;
1147 if ((index
+ 7) > dt
->limit
)
1148 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1149 ptr
= dt
->base
+ index
;
1150 e1
= ldl_kernel(ptr
);
1151 e2
= ldl_kernel(ptr
+ 4);
1153 if (!(e2
& DESC_S_MASK
))
1154 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1156 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1157 cpl
= env
->hflags
& HF_CPL_MASK
;
1158 if (seg_reg
== R_SS
) {
1159 /* must be writable segment */
1160 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
1161 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1162 if (rpl
!= cpl
|| dpl
!= cpl
)
1163 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1165 /* must be readable segment */
1166 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
)
1167 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1169 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1170 /* if not conforming code, test rights */
1171 if (dpl
< cpl
|| dpl
< rpl
)
1172 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1176 if (!(e2
& DESC_P_MASK
)) {
1177 if (seg_reg
== R_SS
)
1178 raise_exception_err(EXCP0C_STACK
, selector
& 0xfffc);
1180 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1183 /* set the access bit if not already set */
1184 if (!(e2
& DESC_A_MASK
)) {
1186 stl_kernel(ptr
+ 4, e2
);
1189 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1190 get_seg_base(e1
, e2
),
1191 get_seg_limit(e1
, e2
),
1194 fprintf(logfile
, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1195 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1200 /* protected mode jump */
1201 void helper_ljmp_protected_T0_T1(void)
1203 int new_cs
, new_eip
, gate_cs
, type
;
1204 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1208 if ((new_cs
& 0xfffc) == 0)
1209 raise_exception_err(EXCP0D_GPF
, 0);
1210 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1211 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1212 cpl
= env
->hflags
& HF_CPL_MASK
;
1213 if (e2
& DESC_S_MASK
) {
1214 if (!(e2
& DESC_CS_MASK
))
1215 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1216 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1217 if (e2
& DESC_C_MASK
) {
1218 /* conforming code segment */
1220 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1222 /* non conforming code segment */
1225 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1227 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1229 if (!(e2
& DESC_P_MASK
))
1230 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1231 limit
= get_seg_limit(e1
, e2
);
1232 if (new_eip
> limit
)
1233 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1234 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1235 get_seg_base(e1
, e2
), limit
, e2
);
1238 /* jump to call or task gate */
1239 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1241 cpl
= env
->hflags
& HF_CPL_MASK
;
1242 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1244 case 1: /* 286 TSS */
1245 case 9: /* 386 TSS */
1246 case 5: /* task gate */
1247 if (dpl
< cpl
|| dpl
< rpl
)
1248 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1249 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_JMP
);
1251 case 4: /* 286 call gate */
1252 case 12: /* 386 call gate */
1253 if ((dpl
< cpl
) || (dpl
< rpl
))
1254 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1255 if (!(e2
& DESC_P_MASK
))
1256 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1258 if (load_segment(&e1
, &e2
, gate_cs
) != 0)
1259 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1260 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1261 /* must be code segment */
1262 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
1263 (DESC_S_MASK
| DESC_CS_MASK
)))
1264 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1265 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
1266 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
)))
1267 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1268 if (!(e2
& DESC_P_MASK
))
1269 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1270 new_eip
= (e1
& 0xffff);
1272 new_eip
|= (e2
& 0xffff0000);
1273 limit
= get_seg_limit(e1
, e2
);
1274 if (new_eip
> limit
)
1275 raise_exception_err(EXCP0D_GPF
, 0);
1276 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
1277 get_seg_base(e1
, e2
), limit
, e2
);
1281 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1287 /* real mode call */
1288 void helper_lcall_real_T0_T1(int shift
, int next_eip
)
1290 int new_cs
, new_eip
;
1291 uint32_t esp
, esp_mask
;
1297 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1298 ssp
= env
->segs
[R_SS
].base
;
1300 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1301 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
1303 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1304 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
1307 ESP
= (ESP
& ~esp_mask
) | (esp
& esp_mask
);
1309 env
->segs
[R_CS
].selector
= new_cs
;
1310 env
->segs
[R_CS
].base
= (uint8_t *)(new_cs
<< 4);
1313 /* protected mode call */
1314 void helper_lcall_protected_T0_T1(int shift
, int next_eip
)
1316 int new_cs
, new_eip
, new_stack
, i
;
1317 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
1318 uint32_t ss
, ss_e1
, ss_e2
, sp
, type
, ss_dpl
, sp_mask
;
1319 uint32_t val
, limit
, old_sp_mask
;
1320 uint8_t *ssp
, *old_ssp
;
1326 fprintf(logfile
, "lcall %04x:%08x\n",
1328 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1331 if ((new_cs
& 0xfffc) == 0)
1332 raise_exception_err(EXCP0D_GPF
, 0);
1333 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1334 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1335 cpl
= env
->hflags
& HF_CPL_MASK
;
1338 fprintf(logfile
, "desc=%08x:%08x\n", e1
, e2
);
1341 if (e2
& DESC_S_MASK
) {
1342 if (!(e2
& DESC_CS_MASK
))
1343 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1344 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1345 if (e2
& DESC_C_MASK
) {
1346 /* conforming code segment */
1348 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1350 /* non conforming code segment */
1353 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1355 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1357 if (!(e2
& DESC_P_MASK
))
1358 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1361 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1362 ssp
= env
->segs
[R_SS
].base
;
1364 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1365 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1367 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1368 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1371 limit
= get_seg_limit(e1
, e2
);
1372 if (new_eip
> limit
)
1373 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1374 /* from this point, not restartable */
1375 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1376 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1377 get_seg_base(e1
, e2
), limit
, e2
);
1380 /* check gate type */
1381 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
1382 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1385 case 1: /* available 286 TSS */
1386 case 9: /* available 386 TSS */
1387 case 5: /* task gate */
1388 if (dpl
< cpl
|| dpl
< rpl
)
1389 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1390 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_CALL
);
1392 case 4: /* 286 call gate */
1393 case 12: /* 386 call gate */
1396 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1401 if (dpl
< cpl
|| dpl
< rpl
)
1402 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1403 /* check valid bit */
1404 if (!(e2
& DESC_P_MASK
))
1405 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1406 selector
= e1
>> 16;
1407 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
1408 param_count
= e2
& 0x1f;
1409 if ((selector
& 0xfffc) == 0)
1410 raise_exception_err(EXCP0D_GPF
, 0);
1412 if (load_segment(&e1
, &e2
, selector
) != 0)
1413 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1414 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
1415 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1416 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1418 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1419 if (!(e2
& DESC_P_MASK
))
1420 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1422 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
1423 /* to inner priviledge */
1424 get_ss_esp_from_tss(&ss
, &sp
, dpl
);
1427 fprintf(logfile
, "ss=%04x sp=%04x param_count=%d ESP=%x\n",
1428 ss
, sp
, param_count
, ESP
);
1430 if ((ss
& 0xfffc) == 0)
1431 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1432 if ((ss
& 3) != dpl
)
1433 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1434 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
1435 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1436 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1438 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1439 if (!(ss_e2
& DESC_S_MASK
) ||
1440 (ss_e2
& DESC_CS_MASK
) ||
1441 !(ss_e2
& DESC_W_MASK
))
1442 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1443 if (!(ss_e2
& DESC_P_MASK
))
1444 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1446 // push_size = ((param_count * 2) + 8) << shift;
1448 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1449 old_ssp
= env
->segs
[R_SS
].base
;
1451 sp_mask
= get_sp_mask(ss_e2
);
1452 ssp
= get_seg_base(ss_e1
, ss_e2
);
1454 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1455 PUSHL(ssp
, sp
, sp_mask
, ESP
);
1456 for(i
= param_count
- 1; i
>= 0; i
--) {
1457 val
= ldl_kernel(old_ssp
+ ((ESP
+ i
* 4) & old_sp_mask
));
1458 PUSHL(ssp
, sp
, sp_mask
, val
);
1461 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1462 PUSHW(ssp
, sp
, sp_mask
, ESP
);
1463 for(i
= param_count
- 1; i
>= 0; i
--) {
1464 val
= lduw_kernel(old_ssp
+ ((ESP
+ i
* 2) & old_sp_mask
));
1465 PUSHW(ssp
, sp
, sp_mask
, val
);
1470 /* to same priviledge */
1472 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1473 ssp
= env
->segs
[R_SS
].base
;
1474 // push_size = (4 << shift);
1479 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1480 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1482 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1483 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1486 /* from this point, not restartable */
1489 ss
= (ss
& ~3) | dpl
;
1490 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
1492 get_seg_limit(ss_e1
, ss_e2
),
1496 selector
= (selector
& ~3) | dpl
;
1497 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
1498 get_seg_base(e1
, e2
),
1499 get_seg_limit(e1
, e2
),
1501 cpu_x86_set_cpl(env
, dpl
);
1502 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1507 /* real and vm86 mode iret */
1508 void helper_iret_real(int shift
)
1510 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
1514 sp_mask
= 0xffff; /* XXXX: use SS segment size ? */
1516 ssp
= env
->segs
[R_SS
].base
;
1519 POPL(ssp
, sp
, sp_mask
, new_eip
);
1520 POPL(ssp
, sp
, sp_mask
, new_cs
);
1522 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1525 POPW(ssp
, sp
, sp_mask
, new_eip
);
1526 POPW(ssp
, sp
, sp_mask
, new_cs
);
1527 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1529 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1530 load_seg_vm(R_CS
, new_cs
);
1532 if (env
->eflags
& VM_MASK
)
1533 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| RF_MASK
;
1535 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| IOPL_MASK
| RF_MASK
;
1537 eflags_mask
&= 0xffff;
1538 load_eflags(new_eflags
, eflags_mask
);
1541 static inline void validate_seg(int seg_reg
, int cpl
)
1546 e2
= env
->segs
[seg_reg
].flags
;
1547 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1548 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1549 /* data or non conforming code segment */
1551 cpu_x86_load_seg_cache(env
, seg_reg
, 0, NULL
, 0, 0);
1556 /* protected mode iret */
1557 static inline void helper_ret_protected(int shift
, int is_iret
, int addend
)
1559 uint32_t sp
, new_cs
, new_eip
, new_eflags
, new_esp
, new_ss
, sp_mask
;
1560 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
1561 uint32_t e1
, e2
, ss_e1
, ss_e2
;
1562 int cpl
, dpl
, rpl
, eflags_mask
, iopl
;
1565 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1567 ssp
= env
->segs
[R_SS
].base
;
1570 POPL(ssp
, sp
, sp_mask
, new_eip
);
1571 POPL(ssp
, sp
, sp_mask
, new_cs
);
1574 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1575 if (new_eflags
& VM_MASK
)
1576 goto return_to_vm86
;
1580 POPW(ssp
, sp
, sp_mask
, new_eip
);
1581 POPW(ssp
, sp
, sp_mask
, new_cs
);
1583 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1587 fprintf(logfile
, "lret new %04x:%08x addend=0x%x\n",
1588 new_cs
, new_eip
, addend
);
1589 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1592 if ((new_cs
& 0xfffc) == 0)
1593 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1594 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1595 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1596 if (!(e2
& DESC_S_MASK
) ||
1597 !(e2
& DESC_CS_MASK
))
1598 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1599 cpl
= env
->hflags
& HF_CPL_MASK
;
1602 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1603 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1604 if (e2
& DESC_C_MASK
) {
1606 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1609 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1611 if (!(e2
& DESC_P_MASK
))
1612 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1616 /* return to same priledge level */
1617 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1618 get_seg_base(e1
, e2
),
1619 get_seg_limit(e1
, e2
),
1622 /* return to different priviledge level */
1625 POPL(ssp
, sp
, sp_mask
, new_esp
);
1626 POPL(ssp
, sp
, sp_mask
, new_ss
);
1630 POPW(ssp
, sp
, sp_mask
, new_esp
);
1631 POPW(ssp
, sp
, sp_mask
, new_ss
);
1634 if ((new_ss
& 3) != rpl
)
1635 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1636 if (load_segment(&ss_e1
, &ss_e2
, new_ss
) != 0)
1637 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1638 if (!(ss_e2
& DESC_S_MASK
) ||
1639 (ss_e2
& DESC_CS_MASK
) ||
1640 !(ss_e2
& DESC_W_MASK
))
1641 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1642 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1644 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1645 if (!(ss_e2
& DESC_P_MASK
))
1646 raise_exception_err(EXCP0B_NOSEG
, new_ss
& 0xfffc);
1648 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1649 get_seg_base(e1
, e2
),
1650 get_seg_limit(e1
, e2
),
1652 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
1653 get_seg_base(ss_e1
, ss_e2
),
1654 get_seg_limit(ss_e1
, ss_e2
),
1656 cpu_x86_set_cpl(env
, rpl
);
1658 /* XXX: change sp_mask according to old segment ? */
1660 /* validate data segments */
1661 validate_seg(R_ES
, cpl
);
1662 validate_seg(R_DS
, cpl
);
1663 validate_seg(R_FS
, cpl
);
1664 validate_seg(R_GS
, cpl
);
1666 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1669 /* NOTE: 'cpl' is the _old_ CPL */
1670 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| RF_MASK
;
1672 eflags_mask
|= IOPL_MASK
;
1673 iopl
= (env
->eflags
>> IOPL_SHIFT
) & 3;
1675 eflags_mask
|= IF_MASK
;
1677 eflags_mask
&= 0xffff;
1678 load_eflags(new_eflags
, eflags_mask
);
1683 POPL(ssp
, sp
, sp_mask
, new_esp
);
1684 POPL(ssp
, sp
, sp_mask
, new_ss
);
1685 POPL(ssp
, sp
, sp_mask
, new_es
);
1686 POPL(ssp
, sp
, sp_mask
, new_ds
);
1687 POPL(ssp
, sp
, sp_mask
, new_fs
);
1688 POPL(ssp
, sp
, sp_mask
, new_gs
);
1690 /* modify processor state */
1691 load_eflags(new_eflags
, TF_MASK
| AC_MASK
| ID_MASK
|
1692 IF_MASK
| IOPL_MASK
| VM_MASK
| VIF_MASK
| VIP_MASK
);
1693 load_seg_vm(R_CS
, new_cs
& 0xffff);
1694 cpu_x86_set_cpl(env
, 3);
1695 load_seg_vm(R_SS
, new_ss
& 0xffff);
1696 load_seg_vm(R_ES
, new_es
& 0xffff);
1697 load_seg_vm(R_DS
, new_ds
& 0xffff);
1698 load_seg_vm(R_FS
, new_fs
& 0xffff);
1699 load_seg_vm(R_GS
, new_gs
& 0xffff);
1705 void helper_iret_protected(int shift
)
1707 int tss_selector
, type
;
1710 /* specific case for TSS */
1711 if (env
->eflags
& NT_MASK
) {
1712 tss_selector
= lduw_kernel(env
->tr
.base
+ 0);
1713 if (tss_selector
& 4)
1714 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1715 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
1716 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1717 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
1718 /* NOTE: we check both segment and busy TSS */
1720 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1721 switch_tss(tss_selector
, e1
, e2
, SWITCH_TSS_IRET
);
1723 helper_ret_protected(shift
, 1, 0);
1727 void helper_lret_protected(int shift
, int addend
)
1729 helper_ret_protected(shift
, 0, addend
);
1732 void helper_movl_crN_T0(int reg
)
1737 cpu_x86_update_cr0(env
);
1740 cpu_x86_update_cr3(env
);
1746 void helper_movl_drN_T0(int reg
)
1751 void helper_invlpg(unsigned int addr
)
1753 cpu_x86_flush_tlb(env
, addr
);
1761 void helper_rdtsc(void)
1765 asm("rdtsc" : "=A" (val
));
1767 /* better than nothing: the time increases */
1774 void helper_wrmsr(void)
1777 case MSR_IA32_SYSENTER_CS
:
1778 env
->sysenter_cs
= EAX
& 0xffff;
1780 case MSR_IA32_SYSENTER_ESP
:
1781 env
->sysenter_esp
= EAX
;
1783 case MSR_IA32_SYSENTER_EIP
:
1784 env
->sysenter_eip
= EAX
;
1787 /* XXX: exception ? */
1792 void helper_rdmsr(void)
1795 case MSR_IA32_SYSENTER_CS
:
1796 EAX
= env
->sysenter_cs
;
1799 case MSR_IA32_SYSENTER_ESP
:
1800 EAX
= env
->sysenter_esp
;
1803 case MSR_IA32_SYSENTER_EIP
:
1804 EAX
= env
->sysenter_eip
;
1808 /* XXX: exception ? */
1813 void helper_lsl(void)
1815 unsigned int selector
, limit
;
1817 int rpl
, dpl
, cpl
, type
;
1819 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1820 selector
= T0
& 0xffff;
1821 if (load_segment(&e1
, &e2
, selector
) != 0)
1824 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1825 cpl
= env
->hflags
& HF_CPL_MASK
;
1826 if (e2
& DESC_S_MASK
) {
1827 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1830 if (dpl
< cpl
|| dpl
< rpl
)
1834 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1845 if (dpl
< cpl
|| dpl
< rpl
)
1848 limit
= get_seg_limit(e1
, e2
);
1853 void helper_lar(void)
1855 unsigned int selector
;
1857 int rpl
, dpl
, cpl
, type
;
1859 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1860 selector
= T0
& 0xffff;
1861 if ((selector
& 0xfffc) == 0)
1863 if (load_segment(&e1
, &e2
, selector
) != 0)
1866 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1867 cpl
= env
->hflags
& HF_CPL_MASK
;
1868 if (e2
& DESC_S_MASK
) {
1869 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1872 if (dpl
< cpl
|| dpl
< rpl
)
1876 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1890 if (dpl
< cpl
|| dpl
< rpl
)
1893 T1
= e2
& 0x00f0ff00;
1897 void helper_verr(void)
1899 unsigned int selector
;
1903 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1904 selector
= T0
& 0xffff;
1905 if ((selector
& 0xfffc) == 0)
1907 if (load_segment(&e1
, &e2
, selector
) != 0)
1909 if (!(e2
& DESC_S_MASK
))
1912 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1913 cpl
= env
->hflags
& HF_CPL_MASK
;
1914 if (e2
& DESC_CS_MASK
) {
1915 if (!(e2
& DESC_R_MASK
))
1917 if (!(e2
& DESC_C_MASK
)) {
1918 if (dpl
< cpl
|| dpl
< rpl
)
1922 if (dpl
< cpl
|| dpl
< rpl
)
1928 void helper_verw(void)
1930 unsigned int selector
;
1934 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1935 selector
= T0
& 0xffff;
1936 if ((selector
& 0xfffc) == 0)
1938 if (load_segment(&e1
, &e2
, selector
) != 0)
1940 if (!(e2
& DESC_S_MASK
))
1943 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1944 cpl
= env
->hflags
& HF_CPL_MASK
;
1945 if (e2
& DESC_CS_MASK
) {
1948 if (dpl
< cpl
|| dpl
< rpl
)
1950 if (!(e2
& DESC_W_MASK
))
1958 void helper_fldt_ST0_A0(void)
1961 new_fpstt
= (env
->fpstt
- 1) & 7;
1962 env
->fpregs
[new_fpstt
] = helper_fldt((uint8_t *)A0
);
1963 env
->fpstt
= new_fpstt
;
1964 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
1967 void helper_fstt_ST0_A0(void)
1969 helper_fstt(ST0
, (uint8_t *)A0
);
1974 #define MUL10(iv) ( iv + iv + (iv << 3) )
1976 void helper_fbld_ST0_A0(void)
1984 for(i
= 8; i
>= 0; i
--) {
1985 v
= ldub((uint8_t *)A0
+ i
);
1986 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
1989 if (ldub((uint8_t *)A0
+ 9) & 0x80)
1995 void helper_fbst_ST0_A0(void)
1999 uint8_t *mem_ref
, *mem_end
;
2004 mem_ref
= (uint8_t *)A0
;
2005 mem_end
= mem_ref
+ 9;
2012 while (mem_ref
< mem_end
) {
2017 v
= ((v
/ 10) << 4) | (v
% 10);
2020 while (mem_ref
< mem_end
) {
2025 void helper_f2xm1(void)
2027 ST0
= pow(2.0,ST0
) - 1.0;
2030 void helper_fyl2x(void)
2032 CPU86_LDouble fptemp
;
2036 fptemp
= log(fptemp
)/log(2.0); /* log2(ST) */
2040 env
->fpus
&= (~0x4700);
2045 void helper_fptan(void)
2047 CPU86_LDouble fptemp
;
2050 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2056 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2057 /* the above code is for |arg| < 2**52 only */
2061 void helper_fpatan(void)
2063 CPU86_LDouble fptemp
, fpsrcop
;
2067 ST1
= atan2(fpsrcop
,fptemp
);
2071 void helper_fxtract(void)
2073 CPU86_LDoubleU temp
;
2074 unsigned int expdif
;
2077 expdif
= EXPD(temp
) - EXPBIAS
;
2078 /*DP exponent bias*/
2085 void helper_fprem1(void)
2087 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2088 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2094 fpsrcop1
.d
= fpsrcop
;
2096 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2098 dblq
= fpsrcop
/ fptemp
;
2099 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2100 ST0
= fpsrcop
- fptemp
*dblq
;
2101 q
= (int)dblq
; /* cutting off top bits is assumed here */
2102 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2103 /* (C0,C1,C3) <-- (q2,q1,q0) */
2104 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2105 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2106 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2108 env
->fpus
|= 0x400; /* C2 <-- 1 */
2109 fptemp
= pow(2.0, expdif
-50);
2110 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2111 /* fpsrcop = integer obtained by rounding to the nearest */
2112 fpsrcop
= (fpsrcop
-floor(fpsrcop
) < ceil(fpsrcop
)-fpsrcop
)?
2113 floor(fpsrcop
): ceil(fpsrcop
);
2114 ST0
-= (ST1
* fpsrcop
* fptemp
);
2118 void helper_fprem(void)
2120 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2121 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2127 fpsrcop1
.d
= fpsrcop
;
2129 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2130 if ( expdif
< 53 ) {
2131 dblq
= fpsrcop
/ fptemp
;
2132 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2133 ST0
= fpsrcop
- fptemp
*dblq
;
2134 q
= (int)dblq
; /* cutting off top bits is assumed here */
2135 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2136 /* (C0,C1,C3) <-- (q2,q1,q0) */
2137 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2138 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2139 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2141 env
->fpus
|= 0x400; /* C2 <-- 1 */
2142 fptemp
= pow(2.0, expdif
-50);
2143 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2144 /* fpsrcop = integer obtained by chopping */
2145 fpsrcop
= (fpsrcop
< 0.0)?
2146 -(floor(fabs(fpsrcop
))): floor(fpsrcop
);
2147 ST0
-= (ST1
* fpsrcop
* fptemp
);
2151 void helper_fyl2xp1(void)
2153 CPU86_LDouble fptemp
;
2156 if ((fptemp
+1.0)>0.0) {
2157 fptemp
= log(fptemp
+1.0) / log(2.0); /* log2(ST+1.0) */
2161 env
->fpus
&= (~0x4700);
2166 void helper_fsqrt(void)
2168 CPU86_LDouble fptemp
;
2172 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2178 void helper_fsincos(void)
2180 CPU86_LDouble fptemp
;
2183 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2189 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2190 /* the above code is for |arg| < 2**63 only */
2194 void helper_frndint(void)
2200 switch(env
->fpuc
& RC_MASK
) {
2203 asm("rndd %0, %1" : "=f" (a
) : "f"(a
));
2206 asm("rnddm %0, %1" : "=f" (a
) : "f"(a
));
2209 asm("rnddp %0, %1" : "=f" (a
) : "f"(a
));
2212 asm("rnddz %0, %1" : "=f" (a
) : "f"(a
));
2221 void helper_fscale(void)
2223 CPU86_LDouble fpsrcop
, fptemp
;
2226 fptemp
= pow(fpsrcop
,ST1
);
2230 void helper_fsin(void)
2232 CPU86_LDouble fptemp
;
2235 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2239 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2240 /* the above code is for |arg| < 2**53 only */
2244 void helper_fcos(void)
2246 CPU86_LDouble fptemp
;
2249 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2253 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2254 /* the above code is for |arg5 < 2**63 only */
2258 void helper_fxam_ST0(void)
2260 CPU86_LDoubleU temp
;
2265 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2267 env
->fpus
|= 0x200; /* C1 <-- 1 */
2269 expdif
= EXPD(temp
);
2270 if (expdif
== MAXEXPD
) {
2271 if (MANTD(temp
) == 0)
2272 env
->fpus
|= 0x500 /*Infinity*/;
2274 env
->fpus
|= 0x100 /*NaN*/;
2275 } else if (expdif
== 0) {
2276 if (MANTD(temp
) == 0)
2277 env
->fpus
|= 0x4000 /*Zero*/;
2279 env
->fpus
|= 0x4400 /*Denormal*/;
2285 void helper_fstenv(uint8_t *ptr
, int data32
)
2287 int fpus
, fptag
, exp
, i
;
2291 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
2293 for (i
=7; i
>=0; i
--) {
2295 if (env
->fptags
[i
]) {
2298 tmp
.d
= env
->fpregs
[i
];
2301 if (exp
== 0 && mant
== 0) {
2304 } else if (exp
== 0 || exp
== MAXEXPD
2305 #ifdef USE_X86LDOUBLE
2306 || (mant
& (1LL << 63)) == 0
2309 /* NaNs, infinity, denormal */
2316 stl(ptr
, env
->fpuc
);
2318 stl(ptr
+ 8, fptag
);
2325 stw(ptr
, env
->fpuc
);
2327 stw(ptr
+ 4, fptag
);
2335 void helper_fldenv(uint8_t *ptr
, int data32
)
2340 env
->fpuc
= lduw(ptr
);
2341 fpus
= lduw(ptr
+ 4);
2342 fptag
= lduw(ptr
+ 8);
2345 env
->fpuc
= lduw(ptr
);
2346 fpus
= lduw(ptr
+ 2);
2347 fptag
= lduw(ptr
+ 4);
2349 env
->fpstt
= (fpus
>> 11) & 7;
2350 env
->fpus
= fpus
& ~0x3800;
2351 for(i
= 0;i
< 7; i
++) {
2352 env
->fptags
[i
] = ((fptag
& 3) == 3);
2357 void helper_fsave(uint8_t *ptr
, int data32
)
2362 helper_fstenv(ptr
, data32
);
2364 ptr
+= (14 << data32
);
2365 for(i
= 0;i
< 8; i
++) {
2367 helper_fstt(tmp
, ptr
);
2385 void helper_frstor(uint8_t *ptr
, int data32
)
2390 helper_fldenv(ptr
, data32
);
2391 ptr
+= (14 << data32
);
2393 for(i
= 0;i
< 8; i
++) {
2394 tmp
= helper_fldt(ptr
);
2400 #if !defined(CONFIG_USER_ONLY)
2402 #define MMUSUFFIX _mmu
2403 #define GETPC() (__builtin_return_address(0))
2406 #include "softmmu_template.h"
2409 #include "softmmu_template.h"
2412 #include "softmmu_template.h"
2415 #include "softmmu_template.h"
2419 /* try to fill the TLB and return an exception if error. If retaddr is
2420 NULL, it means that the function was called in C code (i.e. not
2421 from generated code or from helper.c) */
2422 /* XXX: fix it to restore all registers */
2423 void tlb_fill(unsigned long addr
, int is_write
, int is_user
, void *retaddr
)
2425 TranslationBlock
*tb
;
2428 CPUX86State
*saved_env
;
2430 /* XXX: hack to restore env in all cases, even if not called from
2433 env
= cpu_single_env
;
2434 if (is_write
&& page_unprotect(addr
)) {
2435 /* nothing more to do: the page was write protected because
2436 there was code in it. page_unprotect() flushed the code. */
2439 ret
= cpu_x86_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
2442 /* now we have a real cpu fault */
2443 pc
= (unsigned long)retaddr
;
2444 tb
= tb_find_pc(pc
);
2446 /* the PC is inside the translated code. It means that we have
2447 a virtual CPU fault */
2448 cpu_restore_state(tb
, env
, pc
);
2451 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);