2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "qemu-common.h"
34 /* NOTE: must be called outside the CPU execute loop */
35 void cpu_reset(CPUX86State
*env
)
39 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
40 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
41 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
44 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
48 env
->old_exception
= -1;
50 /* init to reset state */
53 env
->hflags
|= HF_SOFTMMU_MASK
;
55 env
->hflags2
|= HF2_GIF_MASK
;
57 cpu_x86_update_cr0(env
, 0x60000010);
59 env
->smbase
= 0x30000;
61 env
->idt
.limit
= 0xffff;
62 env
->gdt
.limit
= 0xffff;
63 env
->ldt
.limit
= 0xffff;
64 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
65 env
->tr
.limit
= 0xffff;
66 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
68 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
69 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
70 DESC_R_MASK
| DESC_A_MASK
);
71 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
72 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
74 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
75 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
77 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
78 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
80 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
81 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
83 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
84 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
88 env
->regs
[R_EDX
] = env
->cpuid_version
;
99 memset(env
->dr
, 0, sizeof(env
->dr
));
100 env
->dr
[6] = DR6_FIXED_1
;
101 env
->dr
[7] = DR7_FIXED_1
;
102 cpu_breakpoint_remove_all(env
, BP_CPU
);
103 cpu_watchpoint_remove_all(env
, BP_CPU
);
106 void cpu_x86_close(CPUX86State
*env
)
111 static void cpu_x86_version(CPUState
*env
, int *family
, int *model
)
113 int cpuver
= env
->cpuid_version
;
115 if (family
== NULL
|| model
== NULL
) {
119 *family
= (cpuver
>> 8) & 0x0f;
120 *model
= ((cpuver
>> 12) & 0xf0) + ((cpuver
>> 4) & 0x0f);
123 /* Broadcast MCA signal for processor version 06H_EH and above */
124 int cpu_x86_support_mca_broadcast(CPUState
*env
)
129 cpu_x86_version(env
, &family
, &model
);
130 if ((family
== 6 && model
>= 14) || family
> 6) {
137 /***********************************************************/
140 static const char *cc_op_str
[] = {
196 cpu_x86_dump_seg_cache(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
197 const char *name
, struct SegmentCache
*sc
)
200 if (env
->hflags
& HF_CS64_MASK
) {
201 cpu_fprintf(f
, "%-3s=%04x %016" PRIx64
" %08x %08x", name
,
202 sc
->selector
, sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
206 cpu_fprintf(f
, "%-3s=%04x %08x %08x %08x", name
, sc
->selector
,
207 (uint32_t)sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
210 if (!(env
->hflags
& HF_PE_MASK
) || !(sc
->flags
& DESC_P_MASK
))
213 cpu_fprintf(f
, " DPL=%d ", (sc
->flags
& DESC_DPL_MASK
) >> DESC_DPL_SHIFT
);
214 if (sc
->flags
& DESC_S_MASK
) {
215 if (sc
->flags
& DESC_CS_MASK
) {
216 cpu_fprintf(f
, (sc
->flags
& DESC_L_MASK
) ? "CS64" :
217 ((sc
->flags
& DESC_B_MASK
) ? "CS32" : "CS16"));
218 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_C_MASK
) ? 'C' : '-',
219 (sc
->flags
& DESC_R_MASK
) ? 'R' : '-');
221 cpu_fprintf(f
, (sc
->flags
& DESC_B_MASK
) ? "DS " : "DS16");
222 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_E_MASK
) ? 'E' : '-',
223 (sc
->flags
& DESC_W_MASK
) ? 'W' : '-');
225 cpu_fprintf(f
, "%c]", (sc
->flags
& DESC_A_MASK
) ? 'A' : '-');
227 static const char *sys_type_name
[2][16] = {
229 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
230 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
231 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
232 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
235 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
236 "Reserved", "Reserved", "Reserved", "Reserved",
237 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
238 "Reserved", "IntGate64", "TrapGate64"
242 sys_type_name
[(env
->hflags
& HF_LMA_MASK
) ? 1 : 0]
243 [(sc
->flags
& DESC_TYPE_MASK
)
244 >> DESC_TYPE_SHIFT
]);
247 cpu_fprintf(f
, "\n");
250 #define DUMP_CODE_BYTES_TOTAL 50
251 #define DUMP_CODE_BYTES_BACKWARD 20
253 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
258 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
260 cpu_synchronize_state(env
);
262 eflags
= env
->eflags
;
264 if (env
->hflags
& HF_CS64_MASK
) {
266 "RAX=%016" PRIx64
" RBX=%016" PRIx64
" RCX=%016" PRIx64
" RDX=%016" PRIx64
"\n"
267 "RSI=%016" PRIx64
" RDI=%016" PRIx64
" RBP=%016" PRIx64
" RSP=%016" PRIx64
"\n"
268 "R8 =%016" PRIx64
" R9 =%016" PRIx64
" R10=%016" PRIx64
" R11=%016" PRIx64
"\n"
269 "R12=%016" PRIx64
" R13=%016" PRIx64
" R14=%016" PRIx64
" R15=%016" PRIx64
"\n"
270 "RIP=%016" PRIx64
" RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
288 eflags
& DF_MASK
? 'D' : '-',
289 eflags
& CC_O
? 'O' : '-',
290 eflags
& CC_S
? 'S' : '-',
291 eflags
& CC_Z
? 'Z' : '-',
292 eflags
& CC_A
? 'A' : '-',
293 eflags
& CC_P
? 'P' : '-',
294 eflags
& CC_C
? 'C' : '-',
295 env
->hflags
& HF_CPL_MASK
,
296 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
297 (env
->a20_mask
>> 20) & 1,
298 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
303 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
304 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
305 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
306 (uint32_t)env
->regs
[R_EAX
],
307 (uint32_t)env
->regs
[R_EBX
],
308 (uint32_t)env
->regs
[R_ECX
],
309 (uint32_t)env
->regs
[R_EDX
],
310 (uint32_t)env
->regs
[R_ESI
],
311 (uint32_t)env
->regs
[R_EDI
],
312 (uint32_t)env
->regs
[R_EBP
],
313 (uint32_t)env
->regs
[R_ESP
],
314 (uint32_t)env
->eip
, eflags
,
315 eflags
& DF_MASK
? 'D' : '-',
316 eflags
& CC_O
? 'O' : '-',
317 eflags
& CC_S
? 'S' : '-',
318 eflags
& CC_Z
? 'Z' : '-',
319 eflags
& CC_A
? 'A' : '-',
320 eflags
& CC_P
? 'P' : '-',
321 eflags
& CC_C
? 'C' : '-',
322 env
->hflags
& HF_CPL_MASK
,
323 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
324 (env
->a20_mask
>> 20) & 1,
325 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
329 for(i
= 0; i
< 6; i
++) {
330 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, seg_name
[i
],
333 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "LDT", &env
->ldt
);
334 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "TR", &env
->tr
);
337 if (env
->hflags
& HF_LMA_MASK
) {
338 cpu_fprintf(f
, "GDT= %016" PRIx64
" %08x\n",
339 env
->gdt
.base
, env
->gdt
.limit
);
340 cpu_fprintf(f
, "IDT= %016" PRIx64
" %08x\n",
341 env
->idt
.base
, env
->idt
.limit
);
342 cpu_fprintf(f
, "CR0=%08x CR2=%016" PRIx64
" CR3=%016" PRIx64
" CR4=%08x\n",
343 (uint32_t)env
->cr
[0],
346 (uint32_t)env
->cr
[4]);
347 for(i
= 0; i
< 4; i
++)
348 cpu_fprintf(f
, "DR%d=%016" PRIx64
" ", i
, env
->dr
[i
]);
349 cpu_fprintf(f
, "\nDR6=%016" PRIx64
" DR7=%016" PRIx64
"\n",
350 env
->dr
[6], env
->dr
[7]);
354 cpu_fprintf(f
, "GDT= %08x %08x\n",
355 (uint32_t)env
->gdt
.base
, env
->gdt
.limit
);
356 cpu_fprintf(f
, "IDT= %08x %08x\n",
357 (uint32_t)env
->idt
.base
, env
->idt
.limit
);
358 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
359 (uint32_t)env
->cr
[0],
360 (uint32_t)env
->cr
[2],
361 (uint32_t)env
->cr
[3],
362 (uint32_t)env
->cr
[4]);
363 for(i
= 0; i
< 4; i
++) {
364 cpu_fprintf(f
, "DR%d=" TARGET_FMT_lx
" ", i
, env
->dr
[i
]);
366 cpu_fprintf(f
, "\nDR6=" TARGET_FMT_lx
" DR7=" TARGET_FMT_lx
"\n",
367 env
->dr
[6], env
->dr
[7]);
369 if (flags
& X86_DUMP_CCOP
) {
370 if ((unsigned)env
->cc_op
< CC_OP_NB
)
371 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
373 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
375 if (env
->hflags
& HF_CS64_MASK
) {
376 cpu_fprintf(f
, "CCS=%016" PRIx64
" CCD=%016" PRIx64
" CCO=%-8s\n",
377 env
->cc_src
, env
->cc_dst
,
382 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
383 (uint32_t)env
->cc_src
, (uint32_t)env
->cc_dst
,
387 cpu_fprintf(f
, "EFER=%016" PRIx64
"\n", env
->efer
);
388 if (flags
& X86_DUMP_FPU
) {
391 for(i
= 0; i
< 8; i
++) {
392 fptag
|= ((!env
->fptags
[i
]) << i
);
394 cpu_fprintf(f
, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
396 (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11,
401 #if defined(USE_X86LDOUBLE)
409 tmp
.d
= env
->fpregs
[i
].d
;
410 cpu_fprintf(f
, "FPR%d=%016" PRIx64
" %04x",
411 i
, tmp
.l
.lower
, tmp
.l
.upper
);
413 cpu_fprintf(f
, "FPR%d=%016" PRIx64
,
414 i
, env
->fpregs
[i
].mmx
.q
);
417 cpu_fprintf(f
, "\n");
421 if (env
->hflags
& HF_CS64_MASK
)
426 cpu_fprintf(f
, "XMM%02d=%08x%08x%08x%08x",
428 env
->xmm_regs
[i
].XMM_L(3),
429 env
->xmm_regs
[i
].XMM_L(2),
430 env
->xmm_regs
[i
].XMM_L(1),
431 env
->xmm_regs
[i
].XMM_L(0));
433 cpu_fprintf(f
, "\n");
438 if (flags
& CPU_DUMP_CODE
) {
439 target_ulong base
= env
->segs
[R_CS
].base
+ env
->eip
;
440 target_ulong offs
= MIN(env
->eip
, DUMP_CODE_BYTES_BACKWARD
);
444 cpu_fprintf(f
, "Code=");
445 for (i
= 0; i
< DUMP_CODE_BYTES_TOTAL
; i
++) {
446 if (cpu_memory_rw_debug(env
, base
- offs
+ i
, &code
, 1, 0) == 0) {
447 snprintf(codestr
, sizeof(codestr
), "%02x", code
);
449 snprintf(codestr
, sizeof(codestr
), "??");
451 cpu_fprintf(f
, "%s%s%s%s", i
> 0 ? " " : "",
452 i
== offs
? "<" : "", codestr
, i
== offs
? ">" : "");
454 cpu_fprintf(f
, "\n");
458 /***********************************************************/
460 /* XXX: add PGE support */
462 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
)
464 a20_state
= (a20_state
!= 0);
465 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
466 #if defined(DEBUG_MMU)
467 printf("A20 update: a20=%d\n", a20_state
);
469 /* if the cpu is currently executing code, we must unlink it and
470 all the potentially executing TB */
471 cpu_interrupt(env
, CPU_INTERRUPT_EXITTB
);
473 /* when a20 is changed, all the MMU mappings are invalid, so
474 we must flush everything */
476 env
->a20_mask
= ~(1 << 20) | (a20_state
<< 20);
480 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
484 #if defined(DEBUG_MMU)
485 printf("CR0 update: CR0=0x%08x\n", new_cr0
);
487 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
488 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
493 if (!(env
->cr
[0] & CR0_PG_MASK
) && (new_cr0
& CR0_PG_MASK
) &&
494 (env
->efer
& MSR_EFER_LME
)) {
495 /* enter in long mode */
496 /* XXX: generate an exception */
497 if (!(env
->cr
[4] & CR4_PAE_MASK
))
499 env
->efer
|= MSR_EFER_LMA
;
500 env
->hflags
|= HF_LMA_MASK
;
501 } else if ((env
->cr
[0] & CR0_PG_MASK
) && !(new_cr0
& CR0_PG_MASK
) &&
502 (env
->efer
& MSR_EFER_LMA
)) {
504 env
->efer
&= ~MSR_EFER_LMA
;
505 env
->hflags
&= ~(HF_LMA_MASK
| HF_CS64_MASK
);
506 env
->eip
&= 0xffffffff;
509 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
511 /* update PE flag in hidden flags */
512 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
513 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
514 /* ensure that ADDSEG is always set in real mode */
515 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
516 /* update FPU flags */
517 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
518 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
521 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
523 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
)
525 env
->cr
[3] = new_cr3
;
526 if (env
->cr
[0] & CR0_PG_MASK
) {
527 #if defined(DEBUG_MMU)
528 printf("CR3 update: CR3=" TARGET_FMT_lx
"\n", new_cr3
);
534 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
536 #if defined(DEBUG_MMU)
537 printf("CR4 update: CR4=%08x\n", (uint32_t)env
->cr
[4]);
539 if ((new_cr4
& (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
)) !=
540 (env
->cr
[4] & (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
))) {
544 if (!(env
->cpuid_features
& CPUID_SSE
))
545 new_cr4
&= ~CR4_OSFXSR_MASK
;
546 if (new_cr4
& CR4_OSFXSR_MASK
)
547 env
->hflags
|= HF_OSFXSR_MASK
;
549 env
->hflags
&= ~HF_OSFXSR_MASK
;
551 env
->cr
[4] = new_cr4
;
554 #if defined(CONFIG_USER_ONLY)
556 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
557 int is_write
, int mmu_idx
, int is_softmmu
)
559 /* user mode only emulation */
562 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
);
563 env
->error_code
|= PG_ERROR_U_MASK
;
564 env
->exception_index
= EXCP0E_PAGE
;
570 /* XXX: This value should match the one returned by CPUID
572 # if defined(TARGET_X86_64)
573 # define PHYS_ADDR_MASK 0xfffffff000LL
575 # define PHYS_ADDR_MASK 0xffffff000LL
579 -1 = cannot handle fault
580 0 = nothing more to do
581 1 = generate PF fault
583 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
584 int is_write1
, int mmu_idx
, int is_softmmu
)
587 target_ulong pde_addr
, pte_addr
;
588 int error_code
, is_dirty
, prot
, page_size
, is_write
, is_user
;
589 target_phys_addr_t paddr
;
590 uint32_t page_offset
;
591 target_ulong vaddr
, virt_addr
;
593 is_user
= mmu_idx
== MMU_USER_IDX
;
594 #if defined(DEBUG_MMU)
595 printf("MMU fault: addr=" TARGET_FMT_lx
" w=%d u=%d eip=" TARGET_FMT_lx
"\n",
596 addr
, is_write1
, is_user
, env
->eip
);
598 is_write
= is_write1
& 1;
600 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
602 virt_addr
= addr
& TARGET_PAGE_MASK
;
603 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
608 if (env
->cr
[4] & CR4_PAE_MASK
) {
610 target_ulong pdpe_addr
;
613 if (env
->hflags
& HF_LMA_MASK
) {
614 uint64_t pml4e_addr
, pml4e
;
617 /* test virtual address sign extension */
618 sext
= (int64_t)addr
>> 47;
619 if (sext
!= 0 && sext
!= -1) {
621 env
->exception_index
= EXCP0D_GPF
;
625 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
627 pml4e
= ldq_phys(pml4e_addr
);
628 if (!(pml4e
& PG_PRESENT_MASK
)) {
632 if (!(env
->efer
& MSR_EFER_NXE
) && (pml4e
& PG_NX_MASK
)) {
633 error_code
= PG_ERROR_RSVD_MASK
;
636 if (!(pml4e
& PG_ACCESSED_MASK
)) {
637 pml4e
|= PG_ACCESSED_MASK
;
638 stl_phys_notdirty(pml4e_addr
, pml4e
);
640 ptep
= pml4e
^ PG_NX_MASK
;
641 pdpe_addr
= ((pml4e
& PHYS_ADDR_MASK
) + (((addr
>> 30) & 0x1ff) << 3)) &
643 pdpe
= ldq_phys(pdpe_addr
);
644 if (!(pdpe
& PG_PRESENT_MASK
)) {
648 if (!(env
->efer
& MSR_EFER_NXE
) && (pdpe
& PG_NX_MASK
)) {
649 error_code
= PG_ERROR_RSVD_MASK
;
652 ptep
&= pdpe
^ PG_NX_MASK
;
653 if (!(pdpe
& PG_ACCESSED_MASK
)) {
654 pdpe
|= PG_ACCESSED_MASK
;
655 stl_phys_notdirty(pdpe_addr
, pdpe
);
660 /* XXX: load them when cr3 is loaded ? */
661 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
663 pdpe
= ldq_phys(pdpe_addr
);
664 if (!(pdpe
& PG_PRESENT_MASK
)) {
668 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
671 pde_addr
= ((pdpe
& PHYS_ADDR_MASK
) + (((addr
>> 21) & 0x1ff) << 3)) &
673 pde
= ldq_phys(pde_addr
);
674 if (!(pde
& PG_PRESENT_MASK
)) {
678 if (!(env
->efer
& MSR_EFER_NXE
) && (pde
& PG_NX_MASK
)) {
679 error_code
= PG_ERROR_RSVD_MASK
;
682 ptep
&= pde
^ PG_NX_MASK
;
683 if (pde
& PG_PSE_MASK
) {
685 page_size
= 2048 * 1024;
687 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
688 goto do_fault_protect
;
690 if (!(ptep
& PG_USER_MASK
))
691 goto do_fault_protect
;
692 if (is_write
&& !(ptep
& PG_RW_MASK
))
693 goto do_fault_protect
;
695 if ((env
->cr
[0] & CR0_WP_MASK
) &&
696 is_write
&& !(ptep
& PG_RW_MASK
))
697 goto do_fault_protect
;
699 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
700 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
701 pde
|= PG_ACCESSED_MASK
;
703 pde
|= PG_DIRTY_MASK
;
704 stl_phys_notdirty(pde_addr
, pde
);
706 /* align to page_size */
707 pte
= pde
& ((PHYS_ADDR_MASK
& ~(page_size
- 1)) | 0xfff);
708 virt_addr
= addr
& ~(page_size
- 1);
711 if (!(pde
& PG_ACCESSED_MASK
)) {
712 pde
|= PG_ACCESSED_MASK
;
713 stl_phys_notdirty(pde_addr
, pde
);
715 pte_addr
= ((pde
& PHYS_ADDR_MASK
) + (((addr
>> 12) & 0x1ff) << 3)) &
717 pte
= ldq_phys(pte_addr
);
718 if (!(pte
& PG_PRESENT_MASK
)) {
722 if (!(env
->efer
& MSR_EFER_NXE
) && (pte
& PG_NX_MASK
)) {
723 error_code
= PG_ERROR_RSVD_MASK
;
726 /* combine pde and pte nx, user and rw protections */
727 ptep
&= pte
^ PG_NX_MASK
;
729 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
730 goto do_fault_protect
;
732 if (!(ptep
& PG_USER_MASK
))
733 goto do_fault_protect
;
734 if (is_write
&& !(ptep
& PG_RW_MASK
))
735 goto do_fault_protect
;
737 if ((env
->cr
[0] & CR0_WP_MASK
) &&
738 is_write
&& !(ptep
& PG_RW_MASK
))
739 goto do_fault_protect
;
741 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
742 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
743 pte
|= PG_ACCESSED_MASK
;
745 pte
|= PG_DIRTY_MASK
;
746 stl_phys_notdirty(pte_addr
, pte
);
749 virt_addr
= addr
& ~0xfff;
750 pte
= pte
& (PHYS_ADDR_MASK
| 0xfff);
755 /* page directory entry */
756 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) &
758 pde
= ldl_phys(pde_addr
);
759 if (!(pde
& PG_PRESENT_MASK
)) {
763 /* if PSE bit is set, then we use a 4MB page */
764 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
765 page_size
= 4096 * 1024;
767 if (!(pde
& PG_USER_MASK
))
768 goto do_fault_protect
;
769 if (is_write
&& !(pde
& PG_RW_MASK
))
770 goto do_fault_protect
;
772 if ((env
->cr
[0] & CR0_WP_MASK
) &&
773 is_write
&& !(pde
& PG_RW_MASK
))
774 goto do_fault_protect
;
776 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
777 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
778 pde
|= PG_ACCESSED_MASK
;
780 pde
|= PG_DIRTY_MASK
;
781 stl_phys_notdirty(pde_addr
, pde
);
784 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
786 virt_addr
= addr
& ~(page_size
- 1);
788 if (!(pde
& PG_ACCESSED_MASK
)) {
789 pde
|= PG_ACCESSED_MASK
;
790 stl_phys_notdirty(pde_addr
, pde
);
793 /* page directory entry */
794 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) &
796 pte
= ldl_phys(pte_addr
);
797 if (!(pte
& PG_PRESENT_MASK
)) {
801 /* combine pde and pte user and rw protections */
804 if (!(ptep
& PG_USER_MASK
))
805 goto do_fault_protect
;
806 if (is_write
&& !(ptep
& PG_RW_MASK
))
807 goto do_fault_protect
;
809 if ((env
->cr
[0] & CR0_WP_MASK
) &&
810 is_write
&& !(ptep
& PG_RW_MASK
))
811 goto do_fault_protect
;
813 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
814 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
815 pte
|= PG_ACCESSED_MASK
;
817 pte
|= PG_DIRTY_MASK
;
818 stl_phys_notdirty(pte_addr
, pte
);
821 virt_addr
= addr
& ~0xfff;
824 /* the page can be put in the TLB */
826 if (!(ptep
& PG_NX_MASK
))
828 if (pte
& PG_DIRTY_MASK
) {
829 /* only set write access if already dirty... otherwise wait
832 if (ptep
& PG_RW_MASK
)
835 if (!(env
->cr
[0] & CR0_WP_MASK
) ||
841 pte
= pte
& env
->a20_mask
;
843 /* Even if 4MB pages, we map only one 4KB page in the cache to
844 avoid filling it too fast */
845 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
846 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
847 vaddr
= virt_addr
+ page_offset
;
849 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
852 error_code
= PG_ERROR_P_MASK
;
854 error_code
|= (is_write
<< PG_ERROR_W_BIT
);
856 error_code
|= PG_ERROR_U_MASK
;
857 if (is_write1
== 2 &&
858 (env
->efer
& MSR_EFER_NXE
) &&
859 (env
->cr
[4] & CR4_PAE_MASK
))
860 error_code
|= PG_ERROR_I_D_MASK
;
861 if (env
->intercept_exceptions
& (1 << EXCP0E_PAGE
)) {
862 /* cr2 is not modified in case of exceptions */
863 stq_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.exit_info_2
),
868 env
->error_code
= error_code
;
869 env
->exception_index
= EXCP0E_PAGE
;
873 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
875 target_ulong pde_addr
, pte_addr
;
877 target_phys_addr_t paddr
;
878 uint32_t page_offset
;
881 if (env
->cr
[4] & CR4_PAE_MASK
) {
882 target_ulong pdpe_addr
;
886 if (env
->hflags
& HF_LMA_MASK
) {
887 uint64_t pml4e_addr
, pml4e
;
890 /* test virtual address sign extension */
891 sext
= (int64_t)addr
>> 47;
892 if (sext
!= 0 && sext
!= -1)
895 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
897 pml4e
= ldq_phys(pml4e_addr
);
898 if (!(pml4e
& PG_PRESENT_MASK
))
901 pdpe_addr
= ((pml4e
& ~0xfff) + (((addr
>> 30) & 0x1ff) << 3)) &
903 pdpe
= ldq_phys(pdpe_addr
);
904 if (!(pdpe
& PG_PRESENT_MASK
))
909 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
911 pdpe
= ldq_phys(pdpe_addr
);
912 if (!(pdpe
& PG_PRESENT_MASK
))
916 pde_addr
= ((pdpe
& ~0xfff) + (((addr
>> 21) & 0x1ff) << 3)) &
918 pde
= ldq_phys(pde_addr
);
919 if (!(pde
& PG_PRESENT_MASK
)) {
922 if (pde
& PG_PSE_MASK
) {
924 page_size
= 2048 * 1024;
925 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
928 pte_addr
= ((pde
& ~0xfff) + (((addr
>> 12) & 0x1ff) << 3)) &
931 pte
= ldq_phys(pte_addr
);
933 if (!(pte
& PG_PRESENT_MASK
))
938 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
942 /* page directory entry */
943 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) & env
->a20_mask
;
944 pde
= ldl_phys(pde_addr
);
945 if (!(pde
& PG_PRESENT_MASK
))
947 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
948 pte
= pde
& ~0x003ff000; /* align to 4MB */
949 page_size
= 4096 * 1024;
951 /* page directory entry */
952 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
;
953 pte
= ldl_phys(pte_addr
);
954 if (!(pte
& PG_PRESENT_MASK
))
959 pte
= pte
& env
->a20_mask
;
962 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
963 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
967 void hw_breakpoint_insert(CPUState
*env
, int index
)
971 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
973 if (hw_breakpoint_enabled(env
->dr
[7], index
))
974 err
= cpu_breakpoint_insert(env
, env
->dr
[index
], BP_CPU
,
975 &env
->cpu_breakpoint
[index
]);
978 type
= BP_CPU
| BP_MEM_WRITE
;
981 /* No support for I/O watchpoints yet */
984 type
= BP_CPU
| BP_MEM_ACCESS
;
986 err
= cpu_watchpoint_insert(env
, env
->dr
[index
],
987 hw_breakpoint_len(env
->dr
[7], index
),
988 type
, &env
->cpu_watchpoint
[index
]);
992 env
->cpu_breakpoint
[index
] = NULL
;
995 void hw_breakpoint_remove(CPUState
*env
, int index
)
997 if (!env
->cpu_breakpoint
[index
])
999 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
1001 if (hw_breakpoint_enabled(env
->dr
[7], index
))
1002 cpu_breakpoint_remove_by_ref(env
, env
->cpu_breakpoint
[index
]);
1006 cpu_watchpoint_remove_by_ref(env
, env
->cpu_watchpoint
[index
]);
1009 /* No support for I/O watchpoints yet */
1014 int check_hw_breakpoints(CPUState
*env
, int force_dr6_update
)
1018 int hit_enabled
= 0;
1020 dr6
= env
->dr
[6] & ~0xf;
1021 for (reg
= 0; reg
< 4; reg
++) {
1022 type
= hw_breakpoint_type(env
->dr
[7], reg
);
1023 if ((type
== 0 && env
->dr
[reg
] == env
->eip
) ||
1024 ((type
& 1) && env
->cpu_watchpoint
[reg
] &&
1025 (env
->cpu_watchpoint
[reg
]->flags
& BP_WATCHPOINT_HIT
))) {
1027 if (hw_breakpoint_enabled(env
->dr
[7], reg
))
1031 if (hit_enabled
|| force_dr6_update
)
1036 static CPUDebugExcpHandler
*prev_debug_excp_handler
;
1038 void raise_exception_env(int exception_index
, CPUState
*env
);
1040 static void breakpoint_handler(CPUState
*env
)
1044 if (env
->watchpoint_hit
) {
1045 if (env
->watchpoint_hit
->flags
& BP_CPU
) {
1046 env
->watchpoint_hit
= NULL
;
1047 if (check_hw_breakpoints(env
, 0))
1048 raise_exception_env(EXCP01_DB
, env
);
1050 cpu_resume_from_signal(env
, NULL
);
1053 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
)
1054 if (bp
->pc
== env
->eip
) {
1055 if (bp
->flags
& BP_CPU
) {
1056 check_hw_breakpoints(env
, 1);
1057 raise_exception_env(EXCP01_DB
, env
);
1062 if (prev_debug_excp_handler
)
1063 prev_debug_excp_handler(env
);
1066 /* This should come from sysemu.h - if we could include it here... */
1067 void qemu_system_reset_request(void);
1069 static void qemu_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
1070 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
)
1072 uint64_t mcg_cap
= cenv
->mcg_cap
;
1073 uint64_t *banks
= cenv
->mce_banks
;
1076 * if MSR_MCG_CTL is not all 1s, the uncorrected error
1077 * reporting is disabled
1079 if ((status
& MCI_STATUS_UC
) && (mcg_cap
& MCG_CTL_P
) &&
1080 cenv
->mcg_ctl
!= ~(uint64_t)0)
1084 * if MSR_MCi_CTL is not all 1s, the uncorrected error
1085 * reporting is disabled for the bank
1087 if ((status
& MCI_STATUS_UC
) && banks
[0] != ~(uint64_t)0)
1089 if (status
& MCI_STATUS_UC
) {
1090 if ((cenv
->mcg_status
& MCG_STATUS_MCIP
) ||
1091 !(cenv
->cr
[4] & CR4_MCE_MASK
)) {
1092 fprintf(stderr
, "injects mce exception while previous "
1093 "one is in progress!\n");
1094 qemu_log_mask(CPU_LOG_RESET
, "Triple fault\n");
1095 qemu_system_reset_request();
1098 if (banks
[1] & MCI_STATUS_VAL
)
1099 status
|= MCI_STATUS_OVER
;
1102 cenv
->mcg_status
= mcg_status
;
1104 cpu_interrupt(cenv
, CPU_INTERRUPT_MCE
);
1105 } else if (!(banks
[1] & MCI_STATUS_VAL
)
1106 || !(banks
[1] & MCI_STATUS_UC
)) {
1107 if (banks
[1] & MCI_STATUS_VAL
)
1108 status
|= MCI_STATUS_OVER
;
1113 banks
[1] |= MCI_STATUS_OVER
;
1116 void cpu_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
1117 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
,
1120 unsigned bank_num
= cenv
->mcg_cap
& 0xff;
1124 if (bank
>= bank_num
|| !(status
& MCI_STATUS_VAL
)) {
1129 if (!cpu_x86_support_mca_broadcast(cenv
)) {
1130 fprintf(stderr
, "Current CPU does not support broadcast\n");
1135 if (kvm_enabled()) {
1137 flag
|= MCE_BROADCAST
;
1140 kvm_inject_x86_mce(cenv
, bank
, status
, mcg_status
, addr
, misc
, flag
);
1142 qemu_inject_x86_mce(cenv
, bank
, status
, mcg_status
, addr
, misc
);
1144 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1148 qemu_inject_x86_mce(env
, 1, MCI_STATUS_VAL
| MCI_STATUS_UC
,
1149 MCG_STATUS_MCIP
| MCG_STATUS_RIPV
, 0, 0);
1154 #endif /* !CONFIG_USER_ONLY */
1156 static void mce_init(CPUX86State
*cenv
)
1158 unsigned int bank
, bank_num
;
1160 if (((cenv
->cpuid_version
>> 8)&0xf) >= 6
1161 && (cenv
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)) {
1162 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1163 cenv
->mcg_ctl
= ~(uint64_t)0;
1164 bank_num
= MCE_BANKS_DEF
;
1165 for (bank
= 0; bank
< bank_num
; bank
++)
1166 cenv
->mce_banks
[bank
*4] = ~(uint64_t)0;
1170 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
1171 target_ulong
*base
, unsigned int *limit
,
1172 unsigned int *flags
)
1183 index
= selector
& ~7;
1184 ptr
= dt
->base
+ index
;
1185 if ((index
+ 7) > dt
->limit
1186 || cpu_memory_rw_debug(env
, ptr
, (uint8_t *)&e1
, sizeof(e1
), 0) != 0
1187 || cpu_memory_rw_debug(env
, ptr
+4, (uint8_t *)&e2
, sizeof(e2
), 0) != 0)
1190 *base
= ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
1191 *limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
1192 if (e2
& DESC_G_MASK
)
1193 *limit
= (*limit
<< 12) | 0xfff;
1199 CPUX86State
*cpu_x86_init(const char *cpu_model
)
1204 env
= qemu_mallocz(sizeof(CPUX86State
));
1206 env
->cpu_model_str
= cpu_model
;
1208 /* init various static tables */
1211 optimize_flags_init();
1212 #ifndef CONFIG_USER_ONLY
1213 prev_debug_excp_handler
=
1214 cpu_set_debug_excp_handler(breakpoint_handler
);
1217 if (cpu_x86_register(env
, cpu_model
) < 0) {
1223 qemu_init_vcpu(env
);
1228 #if !defined(CONFIG_USER_ONLY)
1229 void do_cpu_init(CPUState
*env
)
1231 int sipi
= env
->interrupt_request
& CPU_INTERRUPT_SIPI
;
1233 env
->interrupt_request
= sipi
;
1234 apic_init_reset(env
->apic_state
);
1235 env
->halted
= !cpu_is_bsp(env
);
1238 void do_cpu_sipi(CPUState
*env
)
1240 apic_sipi(env
->apic_state
);
1243 void do_cpu_init(CPUState
*env
)
1246 void do_cpu_sipi(CPUState
*env
)