2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #ifndef CONFIG_USER_ONLY
29 /* NOTE: must be called outside the CPU execute loop */
30 void cpu_state_reset(CPUX86State
*env
)
34 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
35 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
36 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
39 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
43 env
->old_exception
= -1;
45 /* init to reset state */
48 env
->hflags
|= HF_SOFTMMU_MASK
;
50 env
->hflags2
|= HF2_GIF_MASK
;
52 cpu_x86_update_cr0(env
, 0x60000010);
54 env
->smbase
= 0x30000;
56 env
->idt
.limit
= 0xffff;
57 env
->gdt
.limit
= 0xffff;
58 env
->ldt
.limit
= 0xffff;
59 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
60 env
->tr
.limit
= 0xffff;
61 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
63 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
64 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
65 DESC_R_MASK
| DESC_A_MASK
);
66 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
67 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
69 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
70 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
72 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
73 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
75 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
76 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
78 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
79 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
83 env
->regs
[R_EDX
] = env
->cpuid_version
;
94 env
->pat
= 0x0007040600070406ULL
;
95 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
97 memset(env
->dr
, 0, sizeof(env
->dr
));
98 env
->dr
[6] = DR6_FIXED_1
;
99 env
->dr
[7] = DR7_FIXED_1
;
100 cpu_breakpoint_remove_all(env
, BP_CPU
);
101 cpu_watchpoint_remove_all(env
, BP_CPU
);
104 static void cpu_x86_version(CPUX86State
*env
, int *family
, int *model
)
106 int cpuver
= env
->cpuid_version
;
108 if (family
== NULL
|| model
== NULL
) {
112 *family
= (cpuver
>> 8) & 0x0f;
113 *model
= ((cpuver
>> 12) & 0xf0) + ((cpuver
>> 4) & 0x0f);
116 /* Broadcast MCA signal for processor version 06H_EH and above */
117 int cpu_x86_support_mca_broadcast(CPUX86State
*env
)
122 cpu_x86_version(env
, &family
, &model
);
123 if ((family
== 6 && model
>= 14) || family
> 6) {
130 /***********************************************************/
133 static const char *cc_op_str
[] = {
189 cpu_x86_dump_seg_cache(CPUX86State
*env
, FILE *f
, fprintf_function cpu_fprintf
,
190 const char *name
, struct SegmentCache
*sc
)
193 if (env
->hflags
& HF_CS64_MASK
) {
194 cpu_fprintf(f
, "%-3s=%04x %016" PRIx64
" %08x %08x", name
,
195 sc
->selector
, sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
199 cpu_fprintf(f
, "%-3s=%04x %08x %08x %08x", name
, sc
->selector
,
200 (uint32_t)sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
203 if (!(env
->hflags
& HF_PE_MASK
) || !(sc
->flags
& DESC_P_MASK
))
206 cpu_fprintf(f
, " DPL=%d ", (sc
->flags
& DESC_DPL_MASK
) >> DESC_DPL_SHIFT
);
207 if (sc
->flags
& DESC_S_MASK
) {
208 if (sc
->flags
& DESC_CS_MASK
) {
209 cpu_fprintf(f
, (sc
->flags
& DESC_L_MASK
) ? "CS64" :
210 ((sc
->flags
& DESC_B_MASK
) ? "CS32" : "CS16"));
211 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_C_MASK
) ? 'C' : '-',
212 (sc
->flags
& DESC_R_MASK
) ? 'R' : '-');
214 cpu_fprintf(f
, (sc
->flags
& DESC_B_MASK
) ? "DS " : "DS16");
215 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_E_MASK
) ? 'E' : '-',
216 (sc
->flags
& DESC_W_MASK
) ? 'W' : '-');
218 cpu_fprintf(f
, "%c]", (sc
->flags
& DESC_A_MASK
) ? 'A' : '-');
220 static const char *sys_type_name
[2][16] = {
222 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
223 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
224 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
225 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
228 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
229 "Reserved", "Reserved", "Reserved", "Reserved",
230 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
231 "Reserved", "IntGate64", "TrapGate64"
235 sys_type_name
[(env
->hflags
& HF_LMA_MASK
) ? 1 : 0]
236 [(sc
->flags
& DESC_TYPE_MASK
)
237 >> DESC_TYPE_SHIFT
]);
240 cpu_fprintf(f
, "\n");
243 #define DUMP_CODE_BYTES_TOTAL 50
244 #define DUMP_CODE_BYTES_BACKWARD 20
246 void cpu_dump_state(CPUX86State
*env
, FILE *f
, fprintf_function cpu_fprintf
,
251 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
253 cpu_synchronize_state(env
);
255 eflags
= env
->eflags
;
257 if (env
->hflags
& HF_CS64_MASK
) {
259 "RAX=%016" PRIx64
" RBX=%016" PRIx64
" RCX=%016" PRIx64
" RDX=%016" PRIx64
"\n"
260 "RSI=%016" PRIx64
" RDI=%016" PRIx64
" RBP=%016" PRIx64
" RSP=%016" PRIx64
"\n"
261 "R8 =%016" PRIx64
" R9 =%016" PRIx64
" R10=%016" PRIx64
" R11=%016" PRIx64
"\n"
262 "R12=%016" PRIx64
" R13=%016" PRIx64
" R14=%016" PRIx64
" R15=%016" PRIx64
"\n"
263 "RIP=%016" PRIx64
" RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
281 eflags
& DF_MASK
? 'D' : '-',
282 eflags
& CC_O
? 'O' : '-',
283 eflags
& CC_S
? 'S' : '-',
284 eflags
& CC_Z
? 'Z' : '-',
285 eflags
& CC_A
? 'A' : '-',
286 eflags
& CC_P
? 'P' : '-',
287 eflags
& CC_C
? 'C' : '-',
288 env
->hflags
& HF_CPL_MASK
,
289 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
290 (env
->a20_mask
>> 20) & 1,
291 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
296 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
297 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
298 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
299 (uint32_t)env
->regs
[R_EAX
],
300 (uint32_t)env
->regs
[R_EBX
],
301 (uint32_t)env
->regs
[R_ECX
],
302 (uint32_t)env
->regs
[R_EDX
],
303 (uint32_t)env
->regs
[R_ESI
],
304 (uint32_t)env
->regs
[R_EDI
],
305 (uint32_t)env
->regs
[R_EBP
],
306 (uint32_t)env
->regs
[R_ESP
],
307 (uint32_t)env
->eip
, eflags
,
308 eflags
& DF_MASK
? 'D' : '-',
309 eflags
& CC_O
? 'O' : '-',
310 eflags
& CC_S
? 'S' : '-',
311 eflags
& CC_Z
? 'Z' : '-',
312 eflags
& CC_A
? 'A' : '-',
313 eflags
& CC_P
? 'P' : '-',
314 eflags
& CC_C
? 'C' : '-',
315 env
->hflags
& HF_CPL_MASK
,
316 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
317 (env
->a20_mask
>> 20) & 1,
318 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
322 for(i
= 0; i
< 6; i
++) {
323 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, seg_name
[i
],
326 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "LDT", &env
->ldt
);
327 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "TR", &env
->tr
);
330 if (env
->hflags
& HF_LMA_MASK
) {
331 cpu_fprintf(f
, "GDT= %016" PRIx64
" %08x\n",
332 env
->gdt
.base
, env
->gdt
.limit
);
333 cpu_fprintf(f
, "IDT= %016" PRIx64
" %08x\n",
334 env
->idt
.base
, env
->idt
.limit
);
335 cpu_fprintf(f
, "CR0=%08x CR2=%016" PRIx64
" CR3=%016" PRIx64
" CR4=%08x\n",
336 (uint32_t)env
->cr
[0],
339 (uint32_t)env
->cr
[4]);
340 for(i
= 0; i
< 4; i
++)
341 cpu_fprintf(f
, "DR%d=%016" PRIx64
" ", i
, env
->dr
[i
]);
342 cpu_fprintf(f
, "\nDR6=%016" PRIx64
" DR7=%016" PRIx64
"\n",
343 env
->dr
[6], env
->dr
[7]);
347 cpu_fprintf(f
, "GDT= %08x %08x\n",
348 (uint32_t)env
->gdt
.base
, env
->gdt
.limit
);
349 cpu_fprintf(f
, "IDT= %08x %08x\n",
350 (uint32_t)env
->idt
.base
, env
->idt
.limit
);
351 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
352 (uint32_t)env
->cr
[0],
353 (uint32_t)env
->cr
[2],
354 (uint32_t)env
->cr
[3],
355 (uint32_t)env
->cr
[4]);
356 for(i
= 0; i
< 4; i
++) {
357 cpu_fprintf(f
, "DR%d=" TARGET_FMT_lx
" ", i
, env
->dr
[i
]);
359 cpu_fprintf(f
, "\nDR6=" TARGET_FMT_lx
" DR7=" TARGET_FMT_lx
"\n",
360 env
->dr
[6], env
->dr
[7]);
362 if (flags
& X86_DUMP_CCOP
) {
363 if ((unsigned)env
->cc_op
< CC_OP_NB
)
364 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
366 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
368 if (env
->hflags
& HF_CS64_MASK
) {
369 cpu_fprintf(f
, "CCS=%016" PRIx64
" CCD=%016" PRIx64
" CCO=%-8s\n",
370 env
->cc_src
, env
->cc_dst
,
375 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
376 (uint32_t)env
->cc_src
, (uint32_t)env
->cc_dst
,
380 cpu_fprintf(f
, "EFER=%016" PRIx64
"\n", env
->efer
);
381 if (flags
& X86_DUMP_FPU
) {
384 for(i
= 0; i
< 8; i
++) {
385 fptag
|= ((!env
->fptags
[i
]) << i
);
387 cpu_fprintf(f
, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
389 (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11,
395 u
.d
= env
->fpregs
[i
].d
;
396 cpu_fprintf(f
, "FPR%d=%016" PRIx64
" %04x",
397 i
, u
.l
.lower
, u
.l
.upper
);
399 cpu_fprintf(f
, "\n");
403 if (env
->hflags
& HF_CS64_MASK
)
408 cpu_fprintf(f
, "XMM%02d=%08x%08x%08x%08x",
410 env
->xmm_regs
[i
].XMM_L(3),
411 env
->xmm_regs
[i
].XMM_L(2),
412 env
->xmm_regs
[i
].XMM_L(1),
413 env
->xmm_regs
[i
].XMM_L(0));
415 cpu_fprintf(f
, "\n");
420 if (flags
& CPU_DUMP_CODE
) {
421 target_ulong base
= env
->segs
[R_CS
].base
+ env
->eip
;
422 target_ulong offs
= MIN(env
->eip
, DUMP_CODE_BYTES_BACKWARD
);
426 cpu_fprintf(f
, "Code=");
427 for (i
= 0; i
< DUMP_CODE_BYTES_TOTAL
; i
++) {
428 if (cpu_memory_rw_debug(env
, base
- offs
+ i
, &code
, 1, 0) == 0) {
429 snprintf(codestr
, sizeof(codestr
), "%02x", code
);
431 snprintf(codestr
, sizeof(codestr
), "??");
433 cpu_fprintf(f
, "%s%s%s%s", i
> 0 ? " " : "",
434 i
== offs
? "<" : "", codestr
, i
== offs
? ">" : "");
436 cpu_fprintf(f
, "\n");
440 /***********************************************************/
442 /* XXX: add PGE support */
444 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
)
446 a20_state
= (a20_state
!= 0);
447 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
448 #if defined(DEBUG_MMU)
449 printf("A20 update: a20=%d\n", a20_state
);
451 /* if the cpu is currently executing code, we must unlink it and
452 all the potentially executing TB */
453 cpu_interrupt(env
, CPU_INTERRUPT_EXITTB
);
455 /* when a20 is changed, all the MMU mappings are invalid, so
456 we must flush everything */
458 env
->a20_mask
= ~(1 << 20) | (a20_state
<< 20);
462 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
466 #if defined(DEBUG_MMU)
467 printf("CR0 update: CR0=0x%08x\n", new_cr0
);
469 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
470 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
475 if (!(env
->cr
[0] & CR0_PG_MASK
) && (new_cr0
& CR0_PG_MASK
) &&
476 (env
->efer
& MSR_EFER_LME
)) {
477 /* enter in long mode */
478 /* XXX: generate an exception */
479 if (!(env
->cr
[4] & CR4_PAE_MASK
))
481 env
->efer
|= MSR_EFER_LMA
;
482 env
->hflags
|= HF_LMA_MASK
;
483 } else if ((env
->cr
[0] & CR0_PG_MASK
) && !(new_cr0
& CR0_PG_MASK
) &&
484 (env
->efer
& MSR_EFER_LMA
)) {
486 env
->efer
&= ~MSR_EFER_LMA
;
487 env
->hflags
&= ~(HF_LMA_MASK
| HF_CS64_MASK
);
488 env
->eip
&= 0xffffffff;
491 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
493 /* update PE flag in hidden flags */
494 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
495 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
496 /* ensure that ADDSEG is always set in real mode */
497 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
498 /* update FPU flags */
499 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
500 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
503 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
505 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
)
507 env
->cr
[3] = new_cr3
;
508 if (env
->cr
[0] & CR0_PG_MASK
) {
509 #if defined(DEBUG_MMU)
510 printf("CR3 update: CR3=" TARGET_FMT_lx
"\n", new_cr3
);
516 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
518 #if defined(DEBUG_MMU)
519 printf("CR4 update: CR4=%08x\n", (uint32_t)env
->cr
[4]);
521 if ((new_cr4
& (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
)) !=
522 (env
->cr
[4] & (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
))) {
526 if (!(env
->cpuid_features
& CPUID_SSE
))
527 new_cr4
&= ~CR4_OSFXSR_MASK
;
528 if (new_cr4
& CR4_OSFXSR_MASK
)
529 env
->hflags
|= HF_OSFXSR_MASK
;
531 env
->hflags
&= ~HF_OSFXSR_MASK
;
533 env
->cr
[4] = new_cr4
;
536 #if defined(CONFIG_USER_ONLY)
538 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
539 int is_write
, int mmu_idx
)
541 /* user mode only emulation */
544 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
);
545 env
->error_code
|= PG_ERROR_U_MASK
;
546 env
->exception_index
= EXCP0E_PAGE
;
552 /* XXX: This value should match the one returned by CPUID
554 # if defined(TARGET_X86_64)
555 # define PHYS_ADDR_MASK 0xfffffff000LL
557 # define PHYS_ADDR_MASK 0xffffff000LL
561 -1 = cannot handle fault
562 0 = nothing more to do
563 1 = generate PF fault
565 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
566 int is_write1
, int mmu_idx
)
569 target_ulong pde_addr
, pte_addr
;
570 int error_code
, is_dirty
, prot
, page_size
, is_write
, is_user
;
571 target_phys_addr_t paddr
;
572 uint32_t page_offset
;
573 target_ulong vaddr
, virt_addr
;
575 is_user
= mmu_idx
== MMU_USER_IDX
;
576 #if defined(DEBUG_MMU)
577 printf("MMU fault: addr=" TARGET_FMT_lx
" w=%d u=%d eip=" TARGET_FMT_lx
"\n",
578 addr
, is_write1
, is_user
, env
->eip
);
580 is_write
= is_write1
& 1;
582 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
584 virt_addr
= addr
& TARGET_PAGE_MASK
;
585 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
590 if (env
->cr
[4] & CR4_PAE_MASK
) {
592 target_ulong pdpe_addr
;
595 if (env
->hflags
& HF_LMA_MASK
) {
596 uint64_t pml4e_addr
, pml4e
;
599 /* test virtual address sign extension */
600 sext
= (int64_t)addr
>> 47;
601 if (sext
!= 0 && sext
!= -1) {
603 env
->exception_index
= EXCP0D_GPF
;
607 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
609 pml4e
= ldq_phys(pml4e_addr
);
610 if (!(pml4e
& PG_PRESENT_MASK
)) {
614 if (!(env
->efer
& MSR_EFER_NXE
) && (pml4e
& PG_NX_MASK
)) {
615 error_code
= PG_ERROR_RSVD_MASK
;
618 if (!(pml4e
& PG_ACCESSED_MASK
)) {
619 pml4e
|= PG_ACCESSED_MASK
;
620 stl_phys_notdirty(pml4e_addr
, pml4e
);
622 ptep
= pml4e
^ PG_NX_MASK
;
623 pdpe_addr
= ((pml4e
& PHYS_ADDR_MASK
) + (((addr
>> 30) & 0x1ff) << 3)) &
625 pdpe
= ldq_phys(pdpe_addr
);
626 if (!(pdpe
& PG_PRESENT_MASK
)) {
630 if (!(env
->efer
& MSR_EFER_NXE
) && (pdpe
& PG_NX_MASK
)) {
631 error_code
= PG_ERROR_RSVD_MASK
;
634 ptep
&= pdpe
^ PG_NX_MASK
;
635 if (!(pdpe
& PG_ACCESSED_MASK
)) {
636 pdpe
|= PG_ACCESSED_MASK
;
637 stl_phys_notdirty(pdpe_addr
, pdpe
);
642 /* XXX: load them when cr3 is loaded ? */
643 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
645 pdpe
= ldq_phys(pdpe_addr
);
646 if (!(pdpe
& PG_PRESENT_MASK
)) {
650 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
653 pde_addr
= ((pdpe
& PHYS_ADDR_MASK
) + (((addr
>> 21) & 0x1ff) << 3)) &
655 pde
= ldq_phys(pde_addr
);
656 if (!(pde
& PG_PRESENT_MASK
)) {
660 if (!(env
->efer
& MSR_EFER_NXE
) && (pde
& PG_NX_MASK
)) {
661 error_code
= PG_ERROR_RSVD_MASK
;
664 ptep
&= pde
^ PG_NX_MASK
;
665 if (pde
& PG_PSE_MASK
) {
667 page_size
= 2048 * 1024;
669 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
670 goto do_fault_protect
;
672 if (!(ptep
& PG_USER_MASK
))
673 goto do_fault_protect
;
674 if (is_write
&& !(ptep
& PG_RW_MASK
))
675 goto do_fault_protect
;
677 if ((env
->cr
[0] & CR0_WP_MASK
) &&
678 is_write
&& !(ptep
& PG_RW_MASK
))
679 goto do_fault_protect
;
681 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
682 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
683 pde
|= PG_ACCESSED_MASK
;
685 pde
|= PG_DIRTY_MASK
;
686 stl_phys_notdirty(pde_addr
, pde
);
688 /* align to page_size */
689 pte
= pde
& ((PHYS_ADDR_MASK
& ~(page_size
- 1)) | 0xfff);
690 virt_addr
= addr
& ~(page_size
- 1);
693 if (!(pde
& PG_ACCESSED_MASK
)) {
694 pde
|= PG_ACCESSED_MASK
;
695 stl_phys_notdirty(pde_addr
, pde
);
697 pte_addr
= ((pde
& PHYS_ADDR_MASK
) + (((addr
>> 12) & 0x1ff) << 3)) &
699 pte
= ldq_phys(pte_addr
);
700 if (!(pte
& PG_PRESENT_MASK
)) {
704 if (!(env
->efer
& MSR_EFER_NXE
) && (pte
& PG_NX_MASK
)) {
705 error_code
= PG_ERROR_RSVD_MASK
;
708 /* combine pde and pte nx, user and rw protections */
709 ptep
&= pte
^ PG_NX_MASK
;
711 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
712 goto do_fault_protect
;
714 if (!(ptep
& PG_USER_MASK
))
715 goto do_fault_protect
;
716 if (is_write
&& !(ptep
& PG_RW_MASK
))
717 goto do_fault_protect
;
719 if ((env
->cr
[0] & CR0_WP_MASK
) &&
720 is_write
&& !(ptep
& PG_RW_MASK
))
721 goto do_fault_protect
;
723 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
724 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
725 pte
|= PG_ACCESSED_MASK
;
727 pte
|= PG_DIRTY_MASK
;
728 stl_phys_notdirty(pte_addr
, pte
);
731 virt_addr
= addr
& ~0xfff;
732 pte
= pte
& (PHYS_ADDR_MASK
| 0xfff);
737 /* page directory entry */
738 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) &
740 pde
= ldl_phys(pde_addr
);
741 if (!(pde
& PG_PRESENT_MASK
)) {
745 /* if PSE bit is set, then we use a 4MB page */
746 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
747 page_size
= 4096 * 1024;
749 if (!(pde
& PG_USER_MASK
))
750 goto do_fault_protect
;
751 if (is_write
&& !(pde
& PG_RW_MASK
))
752 goto do_fault_protect
;
754 if ((env
->cr
[0] & CR0_WP_MASK
) &&
755 is_write
&& !(pde
& PG_RW_MASK
))
756 goto do_fault_protect
;
758 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
759 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
760 pde
|= PG_ACCESSED_MASK
;
762 pde
|= PG_DIRTY_MASK
;
763 stl_phys_notdirty(pde_addr
, pde
);
766 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
768 virt_addr
= addr
& ~(page_size
- 1);
770 if (!(pde
& PG_ACCESSED_MASK
)) {
771 pde
|= PG_ACCESSED_MASK
;
772 stl_phys_notdirty(pde_addr
, pde
);
775 /* page directory entry */
776 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) &
778 pte
= ldl_phys(pte_addr
);
779 if (!(pte
& PG_PRESENT_MASK
)) {
783 /* combine pde and pte user and rw protections */
786 if (!(ptep
& PG_USER_MASK
))
787 goto do_fault_protect
;
788 if (is_write
&& !(ptep
& PG_RW_MASK
))
789 goto do_fault_protect
;
791 if ((env
->cr
[0] & CR0_WP_MASK
) &&
792 is_write
&& !(ptep
& PG_RW_MASK
))
793 goto do_fault_protect
;
795 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
796 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
797 pte
|= PG_ACCESSED_MASK
;
799 pte
|= PG_DIRTY_MASK
;
800 stl_phys_notdirty(pte_addr
, pte
);
803 virt_addr
= addr
& ~0xfff;
806 /* the page can be put in the TLB */
808 if (!(ptep
& PG_NX_MASK
))
810 if (pte
& PG_DIRTY_MASK
) {
811 /* only set write access if already dirty... otherwise wait
814 if (ptep
& PG_RW_MASK
)
817 if (!(env
->cr
[0] & CR0_WP_MASK
) ||
823 pte
= pte
& env
->a20_mask
;
825 /* Even if 4MB pages, we map only one 4KB page in the cache to
826 avoid filling it too fast */
827 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
828 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
829 vaddr
= virt_addr
+ page_offset
;
831 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
834 error_code
= PG_ERROR_P_MASK
;
836 error_code
|= (is_write
<< PG_ERROR_W_BIT
);
838 error_code
|= PG_ERROR_U_MASK
;
839 if (is_write1
== 2 &&
840 (env
->efer
& MSR_EFER_NXE
) &&
841 (env
->cr
[4] & CR4_PAE_MASK
))
842 error_code
|= PG_ERROR_I_D_MASK
;
843 if (env
->intercept_exceptions
& (1 << EXCP0E_PAGE
)) {
844 /* cr2 is not modified in case of exceptions */
845 stq_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.exit_info_2
),
850 env
->error_code
= error_code
;
851 env
->exception_index
= EXCP0E_PAGE
;
855 target_phys_addr_t
cpu_get_phys_page_debug(CPUX86State
*env
, target_ulong addr
)
857 target_ulong pde_addr
, pte_addr
;
859 target_phys_addr_t paddr
;
860 uint32_t page_offset
;
863 if (env
->cr
[4] & CR4_PAE_MASK
) {
864 target_ulong pdpe_addr
;
868 if (env
->hflags
& HF_LMA_MASK
) {
869 uint64_t pml4e_addr
, pml4e
;
872 /* test virtual address sign extension */
873 sext
= (int64_t)addr
>> 47;
874 if (sext
!= 0 && sext
!= -1)
877 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
879 pml4e
= ldq_phys(pml4e_addr
);
880 if (!(pml4e
& PG_PRESENT_MASK
))
883 pdpe_addr
= ((pml4e
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
884 (((addr
>> 30) & 0x1ff) << 3)) & env
->a20_mask
;
885 pdpe
= ldq_phys(pdpe_addr
);
886 if (!(pdpe
& PG_PRESENT_MASK
))
891 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
893 pdpe
= ldq_phys(pdpe_addr
);
894 if (!(pdpe
& PG_PRESENT_MASK
))
898 pde_addr
= ((pdpe
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
899 (((addr
>> 21) & 0x1ff) << 3)) & env
->a20_mask
;
900 pde
= ldq_phys(pde_addr
);
901 if (!(pde
& PG_PRESENT_MASK
)) {
904 if (pde
& PG_PSE_MASK
) {
906 page_size
= 2048 * 1024;
907 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
910 pte_addr
= ((pde
& ~0xfff & ~(PG_NX_MASK
| PG_HI_USER_MASK
)) +
911 (((addr
>> 12) & 0x1ff) << 3)) & env
->a20_mask
;
913 pte
= ldq_phys(pte_addr
);
915 pte
&= ~(PG_NX_MASK
| PG_HI_USER_MASK
);
916 if (!(pte
& PG_PRESENT_MASK
))
921 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
925 /* page directory entry */
926 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) & env
->a20_mask
;
927 pde
= ldl_phys(pde_addr
);
928 if (!(pde
& PG_PRESENT_MASK
))
930 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
931 pte
= pde
& ~0x003ff000; /* align to 4MB */
932 page_size
= 4096 * 1024;
934 /* page directory entry */
935 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
;
936 pte
= ldl_phys(pte_addr
);
937 if (!(pte
& PG_PRESENT_MASK
))
942 pte
= pte
& env
->a20_mask
;
945 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
946 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
950 void hw_breakpoint_insert(CPUX86State
*env
, int index
)
954 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
956 if (hw_breakpoint_enabled(env
->dr
[7], index
))
957 err
= cpu_breakpoint_insert(env
, env
->dr
[index
], BP_CPU
,
958 &env
->cpu_breakpoint
[index
]);
961 type
= BP_CPU
| BP_MEM_WRITE
;
964 /* No support for I/O watchpoints yet */
967 type
= BP_CPU
| BP_MEM_ACCESS
;
969 err
= cpu_watchpoint_insert(env
, env
->dr
[index
],
970 hw_breakpoint_len(env
->dr
[7], index
),
971 type
, &env
->cpu_watchpoint
[index
]);
975 env
->cpu_breakpoint
[index
] = NULL
;
978 void hw_breakpoint_remove(CPUX86State
*env
, int index
)
980 if (!env
->cpu_breakpoint
[index
])
982 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
984 if (hw_breakpoint_enabled(env
->dr
[7], index
))
985 cpu_breakpoint_remove_by_ref(env
, env
->cpu_breakpoint
[index
]);
989 cpu_watchpoint_remove_by_ref(env
, env
->cpu_watchpoint
[index
]);
992 /* No support for I/O watchpoints yet */
997 int check_hw_breakpoints(CPUX86State
*env
, int force_dr6_update
)
1001 int hit_enabled
= 0;
1003 dr6
= env
->dr
[6] & ~0xf;
1004 for (reg
= 0; reg
< 4; reg
++) {
1005 type
= hw_breakpoint_type(env
->dr
[7], reg
);
1006 if ((type
== 0 && env
->dr
[reg
] == env
->eip
) ||
1007 ((type
& 1) && env
->cpu_watchpoint
[reg
] &&
1008 (env
->cpu_watchpoint
[reg
]->flags
& BP_WATCHPOINT_HIT
))) {
1010 if (hw_breakpoint_enabled(env
->dr
[7], reg
))
1014 if (hit_enabled
|| force_dr6_update
)
1019 static CPUDebugExcpHandler
*prev_debug_excp_handler
;
1021 static void breakpoint_handler(CPUX86State
*env
)
1025 if (env
->watchpoint_hit
) {
1026 if (env
->watchpoint_hit
->flags
& BP_CPU
) {
1027 env
->watchpoint_hit
= NULL
;
1028 if (check_hw_breakpoints(env
, 0))
1029 raise_exception_env(EXCP01_DB
, env
);
1031 cpu_resume_from_signal(env
, NULL
);
1034 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
)
1035 if (bp
->pc
== env
->eip
) {
1036 if (bp
->flags
& BP_CPU
) {
1037 check_hw_breakpoints(env
, 1);
1038 raise_exception_env(EXCP01_DB
, env
);
1043 if (prev_debug_excp_handler
)
1044 prev_debug_excp_handler(env
);
1047 typedef struct MCEInjectionParams
{
1052 uint64_t mcg_status
;
1056 } MCEInjectionParams
;
1058 static void do_inject_x86_mce(void *data
)
1060 MCEInjectionParams
*params
= data
;
1061 CPUX86State
*cenv
= params
->env
;
1062 uint64_t *banks
= cenv
->mce_banks
+ 4 * params
->bank
;
1064 cpu_synchronize_state(cenv
);
1067 * If there is an MCE exception being processed, ignore this SRAO MCE
1068 * unless unconditional injection was requested.
1070 if (!(params
->flags
& MCE_INJECT_UNCOND_AO
)
1071 && !(params
->status
& MCI_STATUS_AR
)
1072 && (cenv
->mcg_status
& MCG_STATUS_MCIP
)) {
1076 if (params
->status
& MCI_STATUS_UC
) {
1078 * if MSR_MCG_CTL is not all 1s, the uncorrected error
1079 * reporting is disabled
1081 if ((cenv
->mcg_cap
& MCG_CTL_P
) && cenv
->mcg_ctl
!= ~(uint64_t)0) {
1082 monitor_printf(params
->mon
,
1083 "CPU %d: Uncorrected error reporting disabled\n",
1089 * if MSR_MCi_CTL is not all 1s, the uncorrected error
1090 * reporting is disabled for the bank
1092 if (banks
[0] != ~(uint64_t)0) {
1093 monitor_printf(params
->mon
,
1094 "CPU %d: Uncorrected error reporting disabled for"
1096 cenv
->cpu_index
, params
->bank
);
1100 if ((cenv
->mcg_status
& MCG_STATUS_MCIP
) ||
1101 !(cenv
->cr
[4] & CR4_MCE_MASK
)) {
1102 monitor_printf(params
->mon
,
1103 "CPU %d: Previous MCE still in progress, raising"
1106 qemu_log_mask(CPU_LOG_RESET
, "Triple fault\n");
1107 qemu_system_reset_request();
1110 if (banks
[1] & MCI_STATUS_VAL
) {
1111 params
->status
|= MCI_STATUS_OVER
;
1113 banks
[2] = params
->addr
;
1114 banks
[3] = params
->misc
;
1115 cenv
->mcg_status
= params
->mcg_status
;
1116 banks
[1] = params
->status
;
1117 cpu_interrupt(cenv
, CPU_INTERRUPT_MCE
);
1118 } else if (!(banks
[1] & MCI_STATUS_VAL
)
1119 || !(banks
[1] & MCI_STATUS_UC
)) {
1120 if (banks
[1] & MCI_STATUS_VAL
) {
1121 params
->status
|= MCI_STATUS_OVER
;
1123 banks
[2] = params
->addr
;
1124 banks
[3] = params
->misc
;
1125 banks
[1] = params
->status
;
1127 banks
[1] |= MCI_STATUS_OVER
;
1131 void cpu_x86_inject_mce(Monitor
*mon
, CPUX86State
*cenv
, int bank
,
1132 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
1133 uint64_t misc
, int flags
)
1135 MCEInjectionParams params
= {
1140 .mcg_status
= mcg_status
,
1145 unsigned bank_num
= cenv
->mcg_cap
& 0xff;
1148 if (!cenv
->mcg_cap
) {
1149 monitor_printf(mon
, "MCE injection not supported\n");
1152 if (bank
>= bank_num
) {
1153 monitor_printf(mon
, "Invalid MCE bank number\n");
1156 if (!(status
& MCI_STATUS_VAL
)) {
1157 monitor_printf(mon
, "Invalid MCE status code\n");
1160 if ((flags
& MCE_INJECT_BROADCAST
)
1161 && !cpu_x86_support_mca_broadcast(cenv
)) {
1162 monitor_printf(mon
, "Guest CPU does not support MCA broadcast\n");
1166 run_on_cpu(cenv
, do_inject_x86_mce
, ¶ms
);
1167 if (flags
& MCE_INJECT_BROADCAST
) {
1169 params
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
;
1170 params
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
;
1173 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1178 run_on_cpu(cenv
, do_inject_x86_mce
, ¶ms
);
1183 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
)
1185 TranslationBlock
*tb
;
1187 if (kvm_enabled()) {
1188 env
->tpr_access_type
= access
;
1190 cpu_interrupt(env
, CPU_INTERRUPT_TPR
);
1192 tb
= tb_find_pc(env
->mem_io_pc
);
1193 cpu_restore_state(tb
, env
, env
->mem_io_pc
);
1195 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
, access
);
1198 #endif /* !CONFIG_USER_ONLY */
1200 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
1201 target_ulong
*base
, unsigned int *limit
,
1202 unsigned int *flags
)
1213 index
= selector
& ~7;
1214 ptr
= dt
->base
+ index
;
1215 if ((index
+ 7) > dt
->limit
1216 || cpu_memory_rw_debug(env
, ptr
, (uint8_t *)&e1
, sizeof(e1
), 0) != 0
1217 || cpu_memory_rw_debug(env
, ptr
+4, (uint8_t *)&e2
, sizeof(e2
), 0) != 0)
1220 *base
= ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
1221 *limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
1222 if (e2
& DESC_G_MASK
)
1223 *limit
= (*limit
<< 12) | 0xfff;
1229 CPUX86State
*cpu_x86_init(const char *cpu_model
)
1235 cpu
= X86_CPU(object_new(TYPE_X86_CPU
));
1237 env
->cpu_model_str
= cpu_model
;
1239 /* init various static tables used in TCG mode */
1240 if (tcg_enabled() && !inited
) {
1242 optimize_flags_init();
1243 #ifndef CONFIG_USER_ONLY
1244 prev_debug_excp_handler
=
1245 cpu_set_debug_excp_handler(breakpoint_handler
);
1248 if (cpu_x86_register(env
, cpu_model
) < 0) {
1249 object_delete(OBJECT(cpu
));
1253 qemu_init_vcpu(env
);
1258 #if !defined(CONFIG_USER_ONLY)
1259 void do_cpu_init(CPUX86State
*env
)
1261 int sipi
= env
->interrupt_request
& CPU_INTERRUPT_SIPI
;
1262 uint64_t pat
= env
->pat
;
1264 cpu_state_reset(env
);
1265 env
->interrupt_request
= sipi
;
1267 apic_init_reset(env
->apic_state
);
1268 env
->halted
= !cpu_is_bsp(env
);
1271 void do_cpu_sipi(CPUX86State
*env
)
1273 apic_sipi(env
->apic_state
);
1276 void do_cpu_init(CPUX86State
*env
)
1279 void do_cpu_sipi(CPUX86State
*env
)