4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define raise_exception_err(a, b)\
27 printf("raise_exception line=%d\n", __LINE__);\
28 (raise_exception_err)(a, b);\
32 const uint8_t parity_table
[256] = {
33 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
34 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
35 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
36 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
37 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
38 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
39 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
40 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
41 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
42 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
43 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
44 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
45 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
46 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
47 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
48 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
49 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
50 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
51 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
52 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
53 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
54 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
55 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
56 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
57 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
58 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
59 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
60 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
61 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
62 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
63 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
64 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
68 const uint8_t rclw_table
[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 9,10,11,12,13,14,15,
71 16, 0, 1, 2, 3, 4, 5, 6,
72 7, 8, 9,10,11,12,13,14,
76 const uint8_t rclb_table
[32] = {
77 0, 1, 2, 3, 4, 5, 6, 7,
78 8, 0, 1, 2, 3, 4, 5, 6,
79 7, 8, 0, 1, 2, 3, 4, 5,
80 6, 7, 8, 0, 1, 2, 3, 4,
83 const CPU86_LDouble f15rk
[7] =
85 0.00000000000000000000L,
86 1.00000000000000000000L,
87 3.14159265358979323851L, /*pi*/
88 0.30102999566398119523L, /*lg2*/
89 0.69314718055994530943L, /*ln2*/
90 1.44269504088896340739L, /*l2e*/
91 3.32192809488736234781L, /*l2t*/
96 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
100 spin_lock(&global_cpu_lock
);
103 void cpu_unlock(void)
105 spin_unlock(&global_cpu_lock
);
108 void cpu_loop_exit(void)
110 /* NOTE: the register at this point must be saved by hand because
111 longjmp restore them */
113 env
->regs
[R_EAX
] = EAX
;
116 env
->regs
[R_ECX
] = ECX
;
119 env
->regs
[R_EDX
] = EDX
;
122 env
->regs
[R_EBX
] = EBX
;
125 env
->regs
[R_ESP
] = ESP
;
128 env
->regs
[R_EBP
] = EBP
;
131 env
->regs
[R_ESI
] = ESI
;
134 env
->regs
[R_EDI
] = EDI
;
136 longjmp(env
->jmp_env
, 1);
139 /* return non zero if error */
140 static inline int load_segment(uint32_t *e1_ptr
, uint32_t *e2_ptr
,
151 index
= selector
& ~7;
152 if ((index
+ 7) > dt
->limit
)
154 ptr
= dt
->base
+ index
;
155 *e1_ptr
= ldl_kernel(ptr
);
156 *e2_ptr
= ldl_kernel(ptr
+ 4);
160 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
163 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
164 if (e2
& DESC_G_MASK
)
165 limit
= (limit
<< 12) | 0xfff;
169 static inline uint8_t *get_seg_base(uint32_t e1
, uint32_t e2
)
171 return (uint8_t *)((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
174 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
, uint32_t e2
)
176 sc
->base
= get_seg_base(e1
, e2
);
177 sc
->limit
= get_seg_limit(e1
, e2
);
181 /* init the segment cache in vm86 mode. */
182 static inline void load_seg_vm(int seg
, int selector
)
185 cpu_x86_load_seg_cache(env
, seg
, selector
,
186 (uint8_t *)(selector
<< 4), 0xffff, 0);
189 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr
,
190 uint32_t *esp_ptr
, int dpl
)
192 int type
, index
, shift
;
197 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
198 for(i
=0;i
<env
->tr
.limit
;i
++) {
199 printf("%02x ", env
->tr
.base
[i
]);
200 if ((i
& 7) == 7) printf("\n");
206 if (!(env
->tr
.flags
& DESC_P_MASK
))
207 cpu_abort(env
, "invalid tss");
208 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
210 cpu_abort(env
, "invalid tss type");
212 index
= (dpl
* 4 + 2) << shift
;
213 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
)
214 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
216 *esp_ptr
= lduw_kernel(env
->tr
.base
+ index
);
217 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 2);
219 *esp_ptr
= ldl_kernel(env
->tr
.base
+ index
);
220 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 4);
224 /* XXX: merge with load_seg() */
225 static void tss_load_seg(int seg_reg
, int selector
)
230 if ((selector
& 0xfffc) != 0) {
231 if (load_segment(&e1
, &e2
, selector
) != 0)
232 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
233 if (!(e2
& DESC_S_MASK
))
234 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
236 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
237 cpl
= env
->hflags
& HF_CPL_MASK
;
238 if (seg_reg
== R_CS
) {
239 if (!(e2
& DESC_CS_MASK
))
240 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
242 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
243 if ((e2
& DESC_C_MASK
) && dpl
> rpl
)
244 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
246 } else if (seg_reg
== R_SS
) {
247 /* SS must be writable data */
248 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
249 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
250 if (dpl
!= cpl
|| dpl
!= rpl
)
251 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
253 /* not readable code */
254 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
))
255 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
256 /* if data or non conforming code, checks the rights */
257 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
258 if (dpl
< cpl
|| dpl
< rpl
)
259 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
262 if (!(e2
& DESC_P_MASK
))
263 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
264 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
265 get_seg_base(e1
, e2
),
266 get_seg_limit(e1
, e2
),
269 if (seg_reg
== R_SS
|| seg_reg
== R_CS
)
270 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
274 #define SWITCH_TSS_JMP 0
275 #define SWITCH_TSS_IRET 1
276 #define SWITCH_TSS_CALL 2
278 /* XXX: restore CPU state in registers (PowerPC case) */
279 static void switch_tss(int tss_selector
,
280 uint32_t e1
, uint32_t e2
, int source
,
283 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
285 uint32_t new_regs
[8], new_segs
[6];
286 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
287 uint32_t old_eflags
, eflags_mask
;
292 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
294 if (loglevel
& CPU_LOG_PCALL
)
295 fprintf(logfile
, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector
, type
, source
);
298 /* if task gate, we read the TSS segment and we load it */
300 if (!(e2
& DESC_P_MASK
))
301 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
302 tss_selector
= e1
>> 16;
303 if (tss_selector
& 4)
304 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
305 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
306 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
307 if (e2
& DESC_S_MASK
)
308 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
309 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
311 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
314 if (!(e2
& DESC_P_MASK
))
315 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
321 tss_limit
= get_seg_limit(e1
, e2
);
322 tss_base
= get_seg_base(e1
, e2
);
323 if ((tss_selector
& 4) != 0 ||
324 tss_limit
< tss_limit_max
)
325 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
326 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
328 old_tss_limit_max
= 103;
330 old_tss_limit_max
= 43;
332 /* read all the registers from the new TSS */
335 new_cr3
= ldl_kernel(tss_base
+ 0x1c);
336 new_eip
= ldl_kernel(tss_base
+ 0x20);
337 new_eflags
= ldl_kernel(tss_base
+ 0x24);
338 for(i
= 0; i
< 8; i
++)
339 new_regs
[i
] = ldl_kernel(tss_base
+ (0x28 + i
* 4));
340 for(i
= 0; i
< 6; i
++)
341 new_segs
[i
] = lduw_kernel(tss_base
+ (0x48 + i
* 4));
342 new_ldt
= lduw_kernel(tss_base
+ 0x60);
343 new_trap
= ldl_kernel(tss_base
+ 0x64);
347 new_eip
= lduw_kernel(tss_base
+ 0x0e);
348 new_eflags
= lduw_kernel(tss_base
+ 0x10);
349 for(i
= 0; i
< 8; i
++)
350 new_regs
[i
] = lduw_kernel(tss_base
+ (0x12 + i
* 2)) | 0xffff0000;
351 for(i
= 0; i
< 4; i
++)
352 new_segs
[i
] = lduw_kernel(tss_base
+ (0x22 + i
* 4));
353 new_ldt
= lduw_kernel(tss_base
+ 0x2a);
359 /* NOTE: we must avoid memory exceptions during the task switch,
360 so we make dummy accesses before */
361 /* XXX: it can still fail in some cases, so a bigger hack is
362 necessary to valid the TLB after having done the accesses */
364 v1
= ldub_kernel(env
->tr
.base
);
365 v2
= ldub(env
->tr
.base
+ old_tss_limit_max
);
366 stb_kernel(env
->tr
.base
, v1
);
367 stb_kernel(env
->tr
.base
+ old_tss_limit_max
, v2
);
369 /* clear busy bit (it is restartable) */
370 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
373 ptr
= env
->gdt
.base
+ (env
->tr
.selector
& ~7);
374 e2
= ldl_kernel(ptr
+ 4);
375 e2
&= ~DESC_TSS_BUSY_MASK
;
376 stl_kernel(ptr
+ 4, e2
);
378 old_eflags
= compute_eflags();
379 if (source
== SWITCH_TSS_IRET
)
380 old_eflags
&= ~NT_MASK
;
382 /* save the current state in the old TSS */
385 stl_kernel(env
->tr
.base
+ 0x20, next_eip
);
386 stl_kernel(env
->tr
.base
+ 0x24, old_eflags
);
387 for(i
= 0; i
< 8; i
++)
388 stl_kernel(env
->tr
.base
+ (0x28 + i
* 4), env
->regs
[i
]);
389 for(i
= 0; i
< 6; i
++)
390 stw_kernel(env
->tr
.base
+ (0x48 + i
* 4), env
->segs
[i
].selector
);
393 stw_kernel(env
->tr
.base
+ 0x0e, next_eip
);
394 stw_kernel(env
->tr
.base
+ 0x10, old_eflags
);
395 for(i
= 0; i
< 8; i
++)
396 stw_kernel(env
->tr
.base
+ (0x12 + i
* 2), env
->regs
[i
]);
397 for(i
= 0; i
< 4; i
++)
398 stw_kernel(env
->tr
.base
+ (0x22 + i
* 4), env
->segs
[i
].selector
);
401 /* now if an exception occurs, it will occurs in the next task
404 if (source
== SWITCH_TSS_CALL
) {
405 stw_kernel(tss_base
, env
->tr
.selector
);
406 new_eflags
|= NT_MASK
;
410 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
413 ptr
= env
->gdt
.base
+ (tss_selector
& ~7);
414 e2
= ldl_kernel(ptr
+ 4);
415 e2
|= DESC_TSS_BUSY_MASK
;
416 stl_kernel(ptr
+ 4, e2
);
419 /* set the new CPU state */
420 /* from this point, any exception which occurs can give problems */
421 env
->cr
[0] |= CR0_TS_MASK
;
422 env
->hflags
|= HF_TS_MASK
;
423 env
->tr
.selector
= tss_selector
;
424 env
->tr
.base
= tss_base
;
425 env
->tr
.limit
= tss_limit
;
426 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
428 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
429 cpu_x86_update_cr3(env
, new_cr3
);
432 /* load all registers without an exception, then reload them with
433 possible exception */
435 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
|
436 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
| NT_MASK
;
438 eflags_mask
&= 0xffff;
439 load_eflags(new_eflags
, eflags_mask
);
440 for(i
= 0; i
< 8; i
++)
441 env
->regs
[i
] = new_regs
[i
];
442 if (new_eflags
& VM_MASK
) {
443 for(i
= 0; i
< 6; i
++)
444 load_seg_vm(i
, new_segs
[i
]);
445 /* in vm86, CPL is always 3 */
446 cpu_x86_set_cpl(env
, 3);
448 /* CPL is set the RPL of CS */
449 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
450 /* first just selectors as the rest may trigger exceptions */
451 for(i
= 0; i
< 6; i
++)
452 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], NULL
, 0, 0);
455 env
->ldt
.selector
= new_ldt
& ~4;
456 env
->ldt
.base
= NULL
;
462 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
464 if ((new_ldt
& 0xfffc) != 0) {
466 index
= new_ldt
& ~7;
467 if ((index
+ 7) > dt
->limit
)
468 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
469 ptr
= dt
->base
+ index
;
470 e1
= ldl_kernel(ptr
);
471 e2
= ldl_kernel(ptr
+ 4);
472 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
473 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
474 if (!(e2
& DESC_P_MASK
))
475 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
476 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
479 /* load the segments */
480 if (!(new_eflags
& VM_MASK
)) {
481 tss_load_seg(R_CS
, new_segs
[R_CS
]);
482 tss_load_seg(R_SS
, new_segs
[R_SS
]);
483 tss_load_seg(R_ES
, new_segs
[R_ES
]);
484 tss_load_seg(R_DS
, new_segs
[R_DS
]);
485 tss_load_seg(R_FS
, new_segs
[R_FS
]);
486 tss_load_seg(R_GS
, new_segs
[R_GS
]);
489 /* check that EIP is in the CS segment limits */
490 if (new_eip
> env
->segs
[R_CS
].limit
) {
491 /* XXX: different exception if CALL ? */
492 raise_exception_err(EXCP0D_GPF
, 0);
496 /* check if Port I/O is allowed in TSS */
497 static inline void check_io(int addr
, int size
)
499 int io_offset
, val
, mask
;
501 /* TSS must be a valid 32 bit one */
502 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
503 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
506 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
507 io_offset
+= (addr
>> 3);
508 /* Note: the check needs two bytes */
509 if ((io_offset
+ 1) > env
->tr
.limit
)
511 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
513 mask
= (1 << size
) - 1;
514 /* all bits must be zero to allow the I/O */
515 if ((val
& mask
) != 0) {
517 raise_exception_err(EXCP0D_GPF
, 0);
521 void check_iob_T0(void)
526 void check_iow_T0(void)
531 void check_iol_T0(void)
536 void check_iob_DX(void)
538 check_io(EDX
& 0xffff, 1);
541 void check_iow_DX(void)
543 check_io(EDX
& 0xffff, 2);
546 void check_iol_DX(void)
548 check_io(EDX
& 0xffff, 4);
551 static inline unsigned int get_sp_mask(unsigned int e2
)
553 if (e2
& DESC_B_MASK
)
559 /* XXX: add a is_user flag to have proper security support */
560 #define PUSHW(ssp, sp, sp_mask, val)\
563 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
566 #define PUSHL(ssp, sp, sp_mask, val)\
569 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
572 #define POPW(ssp, sp, sp_mask, val)\
574 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
578 #define POPL(ssp, sp, sp_mask, val)\
580 val = ldl_kernel((ssp) + (sp & (sp_mask)));\
584 /* protected mode interrupt */
585 static void do_interrupt_protected(int intno
, int is_int
, int error_code
,
586 unsigned int next_eip
, int is_hw
)
590 int type
, dpl
, selector
, ss_dpl
, cpl
, sp_mask
;
591 int has_error_code
, new_stack
, shift
;
592 uint32_t e1
, e2
, offset
, ss
, esp
, ss_e1
, ss_e2
;
596 if (!is_int
&& !is_hw
) {
615 if (intno
* 8 + 7 > dt
->limit
)
616 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
617 ptr
= dt
->base
+ intno
* 8;
618 e1
= ldl_kernel(ptr
);
619 e2
= ldl_kernel(ptr
+ 4);
620 /* check gate type */
621 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
623 case 5: /* task gate */
624 /* must do that check here to return the correct error code */
625 if (!(e2
& DESC_P_MASK
))
626 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
627 switch_tss(intno
* 8, e1
, e2
, SWITCH_TSS_CALL
, old_eip
);
628 if (has_error_code
) {
630 /* push the error code */
631 shift
= (env
->segs
[R_CS
].flags
>> DESC_B_SHIFT
) & 1;
632 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
636 esp
= (env
->regs
[R_ESP
] - (2 << shift
)) & mask
;
637 ssp
= env
->segs
[R_SS
].base
+ esp
;
639 stl_kernel(ssp
, error_code
);
641 stw_kernel(ssp
, error_code
);
642 env
->regs
[R_ESP
] = (esp
& mask
) | (env
->regs
[R_ESP
] & ~mask
);
645 case 6: /* 286 interrupt gate */
646 case 7: /* 286 trap gate */
647 case 14: /* 386 interrupt gate */
648 case 15: /* 386 trap gate */
651 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
654 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
655 cpl
= env
->hflags
& HF_CPL_MASK
;
656 /* check privledge if software int */
657 if (is_int
&& dpl
< cpl
)
658 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
659 /* check valid bit */
660 if (!(e2
& DESC_P_MASK
))
661 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
663 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
664 if ((selector
& 0xfffc) == 0)
665 raise_exception_err(EXCP0D_GPF
, 0);
667 if (load_segment(&e1
, &e2
, selector
) != 0)
668 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
669 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
670 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
671 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
673 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
674 if (!(e2
& DESC_P_MASK
))
675 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
676 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
677 /* to inner priviledge */
678 get_ss_esp_from_tss(&ss
, &esp
, dpl
);
679 if ((ss
& 0xfffc) == 0)
680 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
682 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
683 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
684 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
685 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
687 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
688 if (!(ss_e2
& DESC_S_MASK
) ||
689 (ss_e2
& DESC_CS_MASK
) ||
690 !(ss_e2
& DESC_W_MASK
))
691 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
692 if (!(ss_e2
& DESC_P_MASK
))
693 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
695 sp_mask
= get_sp_mask(ss_e2
);
696 ssp
= get_seg_base(ss_e1
, ss_e2
);
697 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
698 /* to same priviledge */
699 if (env
->eflags
& VM_MASK
)
700 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
702 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
703 ssp
= env
->segs
[R_SS
].base
;
707 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
708 new_stack
= 0; /* avoid warning */
709 sp_mask
= 0; /* avoid warning */
710 ssp
= NULL
; /* avoid warning */
711 esp
= 0; /* avoid warning */
717 /* XXX: check that enough room is available */
718 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
719 if (env
->eflags
& VM_MASK
)
725 if (env
->eflags
& VM_MASK
) {
726 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
727 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
728 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
729 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
731 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
732 PUSHL(ssp
, esp
, sp_mask
, ESP
);
734 PUSHL(ssp
, esp
, sp_mask
, compute_eflags());
735 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
736 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
737 if (has_error_code
) {
738 PUSHL(ssp
, esp
, sp_mask
, error_code
);
742 if (env
->eflags
& VM_MASK
) {
743 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
744 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
745 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
746 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
748 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
749 PUSHW(ssp
, esp
, sp_mask
, ESP
);
751 PUSHW(ssp
, esp
, sp_mask
, compute_eflags());
752 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
753 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
754 if (has_error_code
) {
755 PUSHW(ssp
, esp
, sp_mask
, error_code
);
760 if (env
->eflags
& VM_MASK
) {
761 /* XXX: explain me why W2K hangs if the whole segment cache is
764 env
->segs
[R_ES
].selector
= 0;
765 env
->segs
[R_ES
].flags
= 0;
766 env
->segs
[R_DS
].selector
= 0;
767 env
->segs
[R_DS
].flags
= 0;
768 env
->segs
[R_FS
].selector
= 0;
769 env
->segs
[R_FS
].flags
= 0;
770 env
->segs
[R_GS
].selector
= 0;
771 env
->segs
[R_GS
].flags
= 0;
773 cpu_x86_load_seg_cache(env
, R_ES
, 0, NULL
, 0, 0);
774 cpu_x86_load_seg_cache(env
, R_DS
, 0, NULL
, 0, 0);
775 cpu_x86_load_seg_cache(env
, R_FS
, 0, NULL
, 0, 0);
776 cpu_x86_load_seg_cache(env
, R_GS
, 0, NULL
, 0, 0);
779 ss
= (ss
& ~3) | dpl
;
780 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
781 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
783 ESP
= (ESP
& ~sp_mask
) | (esp
& sp_mask
);
785 selector
= (selector
& ~3) | dpl
;
786 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
787 get_seg_base(e1
, e2
),
788 get_seg_limit(e1
, e2
),
790 cpu_x86_set_cpl(env
, dpl
);
793 /* interrupt gate clear IF mask */
794 if ((type
& 1) == 0) {
795 env
->eflags
&= ~IF_MASK
;
797 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
800 /* real mode interrupt */
801 static void do_interrupt_real(int intno
, int is_int
, int error_code
,
802 unsigned int next_eip
)
807 uint32_t offset
, esp
;
808 uint32_t old_cs
, old_eip
;
810 /* real mode (simpler !) */
812 if (intno
* 4 + 3 > dt
->limit
)
813 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
814 ptr
= dt
->base
+ intno
* 4;
815 offset
= lduw_kernel(ptr
);
816 selector
= lduw_kernel(ptr
+ 2);
818 ssp
= env
->segs
[R_SS
].base
;
823 old_cs
= env
->segs
[R_CS
].selector
;
824 /* XXX: use SS segment size ? */
825 PUSHW(ssp
, esp
, 0xffff, compute_eflags());
826 PUSHW(ssp
, esp
, 0xffff, old_cs
);
827 PUSHW(ssp
, esp
, 0xffff, old_eip
);
829 /* update processor state */
830 ESP
= (ESP
& ~0xffff) | (esp
& 0xffff);
832 env
->segs
[R_CS
].selector
= selector
;
833 env
->segs
[R_CS
].base
= (uint8_t *)(selector
<< 4);
834 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
837 /* fake user mode interrupt */
838 void do_interrupt_user(int intno
, int is_int
, int error_code
,
839 unsigned int next_eip
)
847 ptr
= dt
->base
+ (intno
* 8);
848 e2
= ldl_kernel(ptr
+ 4);
850 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
851 cpl
= env
->hflags
& HF_CPL_MASK
;
852 /* check privledge if software int */
853 if (is_int
&& dpl
< cpl
)
854 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
856 /* Since we emulate only user space, we cannot do more than
857 exiting the emulation with the suitable exception and error
864 * Begin execution of an interruption. is_int is TRUE if coming from
865 * the int instruction. next_eip is the EIP value AFTER the interrupt
866 * instruction. It is only relevant if is_int is TRUE.
868 void do_interrupt(int intno
, int is_int
, int error_code
,
869 unsigned int next_eip
, int is_hw
)
872 if (loglevel
& (CPU_LOG_PCALL
| CPU_LOG_INT
)) {
873 if ((env
->cr
[0] & CR0_PE_MASK
)) {
875 fprintf(logfile
, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:%08x SP=%04x:%08x",
876 count
, intno
, error_code
, is_int
,
877 env
->hflags
& HF_CPL_MASK
,
878 env
->segs
[R_CS
].selector
, EIP
,
879 env
->segs
[R_SS
].selector
, ESP
);
881 fprintf(logfile
, " CR2=%08x", env
->cr
[2]);
883 fprintf(logfile
, " EAX=%08x", env
->regs
[R_EAX
]);
885 fprintf(logfile
, "\n");
887 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
891 fprintf(logfile
, " code=");
892 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
893 for(i
= 0; i
< 16; i
++) {
894 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
896 fprintf(logfile
, "\n");
903 if (env
->cr
[0] & CR0_PE_MASK
) {
904 do_interrupt_protected(intno
, is_int
, error_code
, next_eip
, is_hw
);
906 do_interrupt_real(intno
, is_int
, error_code
, next_eip
);
911 * Signal an interruption. It is executed in the main CPU loop.
912 * is_int is TRUE if coming from the int instruction. next_eip is the
913 * EIP value AFTER the interrupt instruction. It is only relevant if
916 void raise_interrupt(int intno
, int is_int
, int error_code
,
917 unsigned int next_eip
)
919 env
->exception_index
= intno
;
920 env
->error_code
= error_code
;
921 env
->exception_is_int
= is_int
;
922 env
->exception_next_eip
= next_eip
;
926 /* shortcuts to generate exceptions */
928 void (raise_exception_err
)(int exception_index
, int error_code
)
930 raise_interrupt(exception_index
, 0, error_code
, 0);
933 void raise_exception(int exception_index
)
935 raise_interrupt(exception_index
, 0, 0, 0);
938 #ifdef BUGGY_GCC_DIV64
939 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
940 call it from another function */
941 uint32_t div64(uint32_t *q_ptr
, uint64_t num
, uint32_t den
)
947 int32_t idiv64(int32_t *q_ptr
, int64_t num
, int32_t den
)
954 void helper_divl_EAX_T0(uint32_t eip
)
956 unsigned int den
, q
, r
;
959 num
= EAX
| ((uint64_t)EDX
<< 32);
963 raise_exception(EXCP00_DIVZ
);
965 #ifdef BUGGY_GCC_DIV64
966 r
= div64(&q
, num
, den
);
975 void helper_idivl_EAX_T0(uint32_t eip
)
980 num
= EAX
| ((uint64_t)EDX
<< 32);
984 raise_exception(EXCP00_DIVZ
);
986 #ifdef BUGGY_GCC_DIV64
987 r
= idiv64(&q
, num
, den
);
996 void helper_cmpxchg8b(void)
1001 eflags
= cc_table
[CC_OP
].compute_all();
1002 d
= ldq((uint8_t *)A0
);
1003 if (d
== (((uint64_t)EDX
<< 32) | EAX
)) {
1004 stq((uint8_t *)A0
, ((uint64_t)ECX
<< 32) | EBX
);
1014 #define CPUID_FP87 (1 << 0)
1015 #define CPUID_VME (1 << 1)
1016 #define CPUID_DE (1 << 2)
1017 #define CPUID_PSE (1 << 3)
1018 #define CPUID_TSC (1 << 4)
1019 #define CPUID_MSR (1 << 5)
1020 #define CPUID_PAE (1 << 6)
1021 #define CPUID_MCE (1 << 7)
1022 #define CPUID_CX8 (1 << 8)
1023 #define CPUID_APIC (1 << 9)
1024 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
1025 #define CPUID_MTRR (1 << 12)
1026 #define CPUID_PGE (1 << 13)
1027 #define CPUID_MCA (1 << 14)
1028 #define CPUID_CMOV (1 << 15)
1030 #define CPUID_MMX (1 << 23)
1031 #define CPUID_FXSR (1 << 24)
1032 #define CPUID_SSE (1 << 25)
1033 #define CPUID_SSE2 (1 << 26)
1035 void helper_cpuid(void)
1039 EAX
= 2; /* max EAX index supported */
1046 int family
, model
, stepping
;
1049 /* pentium 75-200 */
1059 EAX
= (family
<< 8) | (model
<< 4) | stepping
;
1062 EDX
= CPUID_FP87
| CPUID_DE
| CPUID_PSE
|
1063 CPUID_TSC
| CPUID_MSR
| CPUID_MCE
|
1064 CPUID_CX8
| CPUID_PGE
| CPUID_CMOV
;
1068 /* cache info: needed for Pentium Pro compatibility */
1077 void helper_lldt_T0(void)
1085 selector
= T0
& 0xffff;
1086 if ((selector
& 0xfffc) == 0) {
1087 /* XXX: NULL selector case: invalid LDT */
1088 env
->ldt
.base
= NULL
;
1092 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1094 index
= selector
& ~7;
1095 if ((index
+ 7) > dt
->limit
)
1096 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1097 ptr
= dt
->base
+ index
;
1098 e1
= ldl_kernel(ptr
);
1099 e2
= ldl_kernel(ptr
+ 4);
1100 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
1101 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1102 if (!(e2
& DESC_P_MASK
))
1103 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1104 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1106 env
->ldt
.selector
= selector
;
1109 void helper_ltr_T0(void)
1117 selector
= T0
& 0xffff;
1118 if ((selector
& 0xfffc) == 0) {
1119 /* NULL selector case: invalid LDT */
1120 env
->tr
.base
= NULL
;
1125 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1127 index
= selector
& ~7;
1128 if ((index
+ 7) > dt
->limit
)
1129 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1130 ptr
= dt
->base
+ index
;
1131 e1
= ldl_kernel(ptr
);
1132 e2
= ldl_kernel(ptr
+ 4);
1133 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1134 if ((e2
& DESC_S_MASK
) ||
1135 (type
!= 1 && type
!= 9))
1136 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1137 if (!(e2
& DESC_P_MASK
))
1138 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1139 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1140 e2
|= DESC_TSS_BUSY_MASK
;
1141 stl_kernel(ptr
+ 4, e2
);
1143 env
->tr
.selector
= selector
;
1146 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1147 void load_seg(int seg_reg
, int selector
)
1156 if ((selector
& 0xfffc) == 0) {
1157 /* null selector case */
1158 if (seg_reg
== R_SS
)
1159 raise_exception_err(EXCP0D_GPF
, 0);
1160 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, NULL
, 0, 0);
1167 index
= selector
& ~7;
1168 if ((index
+ 7) > dt
->limit
)
1169 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1170 ptr
= dt
->base
+ index
;
1171 e1
= ldl_kernel(ptr
);
1172 e2
= ldl_kernel(ptr
+ 4);
1174 if (!(e2
& DESC_S_MASK
))
1175 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1177 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1178 cpl
= env
->hflags
& HF_CPL_MASK
;
1179 if (seg_reg
== R_SS
) {
1180 /* must be writable segment */
1181 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
1182 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1183 if (rpl
!= cpl
|| dpl
!= cpl
)
1184 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1186 /* must be readable segment */
1187 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
)
1188 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1190 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1191 /* if not conforming code, test rights */
1192 if (dpl
< cpl
|| dpl
< rpl
)
1193 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1197 if (!(e2
& DESC_P_MASK
)) {
1198 if (seg_reg
== R_SS
)
1199 raise_exception_err(EXCP0C_STACK
, selector
& 0xfffc);
1201 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1204 /* set the access bit if not already set */
1205 if (!(e2
& DESC_A_MASK
)) {
1207 stl_kernel(ptr
+ 4, e2
);
1210 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1211 get_seg_base(e1
, e2
),
1212 get_seg_limit(e1
, e2
),
1215 fprintf(logfile
, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1216 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1221 /* protected mode jump */
1222 void helper_ljmp_protected_T0_T1(int next_eip
)
1224 int new_cs
, new_eip
, gate_cs
, type
;
1225 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1229 if ((new_cs
& 0xfffc) == 0)
1230 raise_exception_err(EXCP0D_GPF
, 0);
1231 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1232 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1233 cpl
= env
->hflags
& HF_CPL_MASK
;
1234 if (e2
& DESC_S_MASK
) {
1235 if (!(e2
& DESC_CS_MASK
))
1236 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1237 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1238 if (e2
& DESC_C_MASK
) {
1239 /* conforming code segment */
1241 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1243 /* non conforming code segment */
1246 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1248 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1250 if (!(e2
& DESC_P_MASK
))
1251 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1252 limit
= get_seg_limit(e1
, e2
);
1253 if (new_eip
> limit
)
1254 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1255 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1256 get_seg_base(e1
, e2
), limit
, e2
);
1259 /* jump to call or task gate */
1260 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1262 cpl
= env
->hflags
& HF_CPL_MASK
;
1263 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1265 case 1: /* 286 TSS */
1266 case 9: /* 386 TSS */
1267 case 5: /* task gate */
1268 if (dpl
< cpl
|| dpl
< rpl
)
1269 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1270 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_JMP
, next_eip
);
1272 case 4: /* 286 call gate */
1273 case 12: /* 386 call gate */
1274 if ((dpl
< cpl
) || (dpl
< rpl
))
1275 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1276 if (!(e2
& DESC_P_MASK
))
1277 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1279 if (load_segment(&e1
, &e2
, gate_cs
) != 0)
1280 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1281 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1282 /* must be code segment */
1283 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
1284 (DESC_S_MASK
| DESC_CS_MASK
)))
1285 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1286 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
1287 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
)))
1288 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1289 if (!(e2
& DESC_P_MASK
))
1290 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
1291 new_eip
= (e1
& 0xffff);
1293 new_eip
|= (e2
& 0xffff0000);
1294 limit
= get_seg_limit(e1
, e2
);
1295 if (new_eip
> limit
)
1296 raise_exception_err(EXCP0D_GPF
, 0);
1297 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
1298 get_seg_base(e1
, e2
), limit
, e2
);
1302 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1308 /* real mode call */
1309 void helper_lcall_real_T0_T1(int shift
, int next_eip
)
1311 int new_cs
, new_eip
;
1312 uint32_t esp
, esp_mask
;
1318 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1319 ssp
= env
->segs
[R_SS
].base
;
1321 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1322 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
1324 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
1325 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
1328 ESP
= (ESP
& ~esp_mask
) | (esp
& esp_mask
);
1330 env
->segs
[R_CS
].selector
= new_cs
;
1331 env
->segs
[R_CS
].base
= (uint8_t *)(new_cs
<< 4);
1334 /* protected mode call */
1335 void helper_lcall_protected_T0_T1(int shift
, int next_eip
)
1337 int new_cs
, new_eip
, new_stack
, i
;
1338 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
1339 uint32_t ss
, ss_e1
, ss_e2
, sp
, type
, ss_dpl
, sp_mask
;
1340 uint32_t val
, limit
, old_sp_mask
;
1341 uint8_t *ssp
, *old_ssp
;
1346 if (loglevel
& CPU_LOG_PCALL
) {
1347 fprintf(logfile
, "lcall %04x:%08x s=%d\n",
1348 new_cs
, new_eip
, shift
);
1349 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1352 if ((new_cs
& 0xfffc) == 0)
1353 raise_exception_err(EXCP0D_GPF
, 0);
1354 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1355 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1356 cpl
= env
->hflags
& HF_CPL_MASK
;
1358 if (loglevel
& CPU_LOG_PCALL
) {
1359 fprintf(logfile
, "desc=%08x:%08x\n", e1
, e2
);
1362 if (e2
& DESC_S_MASK
) {
1363 if (!(e2
& DESC_CS_MASK
))
1364 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1365 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1366 if (e2
& DESC_C_MASK
) {
1367 /* conforming code segment */
1369 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1371 /* non conforming code segment */
1374 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1376 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1378 if (!(e2
& DESC_P_MASK
))
1379 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1382 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1383 ssp
= env
->segs
[R_SS
].base
;
1385 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1386 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1388 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1389 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1392 limit
= get_seg_limit(e1
, e2
);
1393 if (new_eip
> limit
)
1394 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1395 /* from this point, not restartable */
1396 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1397 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1398 get_seg_base(e1
, e2
), limit
, e2
);
1401 /* check gate type */
1402 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
1403 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1406 case 1: /* available 286 TSS */
1407 case 9: /* available 386 TSS */
1408 case 5: /* task gate */
1409 if (dpl
< cpl
|| dpl
< rpl
)
1410 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1411 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_CALL
, next_eip
);
1413 case 4: /* 286 call gate */
1414 case 12: /* 386 call gate */
1417 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1422 if (dpl
< cpl
|| dpl
< rpl
)
1423 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1424 /* check valid bit */
1425 if (!(e2
& DESC_P_MASK
))
1426 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1427 selector
= e1
>> 16;
1428 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
1429 param_count
= e2
& 0x1f;
1430 if ((selector
& 0xfffc) == 0)
1431 raise_exception_err(EXCP0D_GPF
, 0);
1433 if (load_segment(&e1
, &e2
, selector
) != 0)
1434 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1435 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
1436 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1437 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1439 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1440 if (!(e2
& DESC_P_MASK
))
1441 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1443 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
1444 /* to inner priviledge */
1445 get_ss_esp_from_tss(&ss
, &sp
, dpl
);
1447 if (loglevel
& CPU_LOG_PCALL
)
1448 fprintf(logfile
, "new ss:esp=%04x:%08x param_count=%d ESP=%x\n",
1449 ss
, sp
, param_count
, ESP
);
1451 if ((ss
& 0xfffc) == 0)
1452 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1453 if ((ss
& 3) != dpl
)
1454 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1455 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
1456 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1457 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1459 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1460 if (!(ss_e2
& DESC_S_MASK
) ||
1461 (ss_e2
& DESC_CS_MASK
) ||
1462 !(ss_e2
& DESC_W_MASK
))
1463 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1464 if (!(ss_e2
& DESC_P_MASK
))
1465 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
1467 // push_size = ((param_count * 2) + 8) << shift;
1469 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1470 old_ssp
= env
->segs
[R_SS
].base
;
1472 sp_mask
= get_sp_mask(ss_e2
);
1473 ssp
= get_seg_base(ss_e1
, ss_e2
);
1475 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1476 PUSHL(ssp
, sp
, sp_mask
, ESP
);
1477 for(i
= param_count
- 1; i
>= 0; i
--) {
1478 val
= ldl_kernel(old_ssp
+ ((ESP
+ i
* 4) & old_sp_mask
));
1479 PUSHL(ssp
, sp
, sp_mask
, val
);
1482 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
1483 PUSHW(ssp
, sp
, sp_mask
, ESP
);
1484 for(i
= param_count
- 1; i
>= 0; i
--) {
1485 val
= lduw_kernel(old_ssp
+ ((ESP
+ i
* 2) & old_sp_mask
));
1486 PUSHW(ssp
, sp
, sp_mask
, val
);
1491 /* to same priviledge */
1493 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1494 ssp
= env
->segs
[R_SS
].base
;
1495 // push_size = (4 << shift);
1500 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1501 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
1503 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
1504 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
1507 /* from this point, not restartable */
1510 ss
= (ss
& ~3) | dpl
;
1511 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
1513 get_seg_limit(ss_e1
, ss_e2
),
1517 selector
= (selector
& ~3) | dpl
;
1518 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
1519 get_seg_base(e1
, e2
),
1520 get_seg_limit(e1
, e2
),
1522 cpu_x86_set_cpl(env
, dpl
);
1523 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1528 /* real and vm86 mode iret */
1529 void helper_iret_real(int shift
)
1531 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
1535 sp_mask
= 0xffff; /* XXXX: use SS segment size ? */
1537 ssp
= env
->segs
[R_SS
].base
;
1540 POPL(ssp
, sp
, sp_mask
, new_eip
);
1541 POPL(ssp
, sp
, sp_mask
, new_cs
);
1543 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1546 POPW(ssp
, sp
, sp_mask
, new_eip
);
1547 POPW(ssp
, sp
, sp_mask
, new_cs
);
1548 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1550 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1551 load_seg_vm(R_CS
, new_cs
);
1553 if (env
->eflags
& VM_MASK
)
1554 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| RF_MASK
| NT_MASK
;
1556 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| IOPL_MASK
| RF_MASK
| NT_MASK
;
1558 eflags_mask
&= 0xffff;
1559 load_eflags(new_eflags
, eflags_mask
);
1562 static inline void validate_seg(int seg_reg
, int cpl
)
1567 e2
= env
->segs
[seg_reg
].flags
;
1568 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1569 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1570 /* data or non conforming code segment */
1572 cpu_x86_load_seg_cache(env
, seg_reg
, 0, NULL
, 0, 0);
1577 /* protected mode iret */
1578 static inline void helper_ret_protected(int shift
, int is_iret
, int addend
)
1580 uint32_t sp
, new_cs
, new_eip
, new_eflags
, new_esp
, new_ss
, sp_mask
;
1581 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
1582 uint32_t e1
, e2
, ss_e1
, ss_e2
;
1583 int cpl
, dpl
, rpl
, eflags_mask
, iopl
;
1586 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1588 ssp
= env
->segs
[R_SS
].base
;
1591 POPL(ssp
, sp
, sp_mask
, new_eip
);
1592 POPL(ssp
, sp
, sp_mask
, new_cs
);
1595 POPL(ssp
, sp
, sp_mask
, new_eflags
);
1596 if (new_eflags
& VM_MASK
)
1597 goto return_to_vm86
;
1601 POPW(ssp
, sp
, sp_mask
, new_eip
);
1602 POPW(ssp
, sp
, sp_mask
, new_cs
);
1604 POPW(ssp
, sp
, sp_mask
, new_eflags
);
1607 if (loglevel
& CPU_LOG_PCALL
) {
1608 fprintf(logfile
, "lret new %04x:%08x s=%d addend=0x%x\n",
1609 new_cs
, new_eip
, shift
, addend
);
1610 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
1613 if ((new_cs
& 0xfffc) == 0)
1614 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1615 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1616 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1617 if (!(e2
& DESC_S_MASK
) ||
1618 !(e2
& DESC_CS_MASK
))
1619 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1620 cpl
= env
->hflags
& HF_CPL_MASK
;
1623 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1624 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1625 if (e2
& DESC_C_MASK
) {
1627 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1630 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1632 if (!(e2
& DESC_P_MASK
))
1633 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1637 /* return to same priledge level */
1638 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1639 get_seg_base(e1
, e2
),
1640 get_seg_limit(e1
, e2
),
1643 /* return to different priviledge level */
1646 POPL(ssp
, sp
, sp_mask
, new_esp
);
1647 POPL(ssp
, sp
, sp_mask
, new_ss
);
1651 POPW(ssp
, sp
, sp_mask
, new_esp
);
1652 POPW(ssp
, sp
, sp_mask
, new_ss
);
1655 if (loglevel
& CPU_LOG_PCALL
) {
1656 fprintf(logfile
, "new ss:esp=%04x:%08x\n",
1661 if ((new_ss
& 3) != rpl
)
1662 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1663 if (load_segment(&ss_e1
, &ss_e2
, new_ss
) != 0)
1664 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1665 if (!(ss_e2
& DESC_S_MASK
) ||
1666 (ss_e2
& DESC_CS_MASK
) ||
1667 !(ss_e2
& DESC_W_MASK
))
1668 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1669 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
1671 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
1672 if (!(ss_e2
& DESC_P_MASK
))
1673 raise_exception_err(EXCP0B_NOSEG
, new_ss
& 0xfffc);
1675 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
1676 get_seg_base(e1
, e2
),
1677 get_seg_limit(e1
, e2
),
1679 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
1680 get_seg_base(ss_e1
, ss_e2
),
1681 get_seg_limit(ss_e1
, ss_e2
),
1683 cpu_x86_set_cpl(env
, rpl
);
1685 sp_mask
= get_sp_mask(ss_e2
);
1687 /* validate data segments */
1688 validate_seg(R_ES
, cpl
);
1689 validate_seg(R_DS
, cpl
);
1690 validate_seg(R_FS
, cpl
);
1691 validate_seg(R_GS
, cpl
);
1695 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
1698 /* NOTE: 'cpl' is the _old_ CPL */
1699 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| RF_MASK
| NT_MASK
;
1701 eflags_mask
|= IOPL_MASK
;
1702 iopl
= (env
->eflags
>> IOPL_SHIFT
) & 3;
1704 eflags_mask
|= IF_MASK
;
1706 eflags_mask
&= 0xffff;
1707 load_eflags(new_eflags
, eflags_mask
);
1712 POPL(ssp
, sp
, sp_mask
, new_esp
);
1713 POPL(ssp
, sp
, sp_mask
, new_ss
);
1714 POPL(ssp
, sp
, sp_mask
, new_es
);
1715 POPL(ssp
, sp
, sp_mask
, new_ds
);
1716 POPL(ssp
, sp
, sp_mask
, new_fs
);
1717 POPL(ssp
, sp
, sp_mask
, new_gs
);
1719 /* modify processor state */
1720 load_eflags(new_eflags
, TF_MASK
| AC_MASK
| ID_MASK
|
1721 IF_MASK
| IOPL_MASK
| VM_MASK
| NT_MASK
| VIF_MASK
| VIP_MASK
);
1722 load_seg_vm(R_CS
, new_cs
& 0xffff);
1723 cpu_x86_set_cpl(env
, 3);
1724 load_seg_vm(R_SS
, new_ss
& 0xffff);
1725 load_seg_vm(R_ES
, new_es
& 0xffff);
1726 load_seg_vm(R_DS
, new_ds
& 0xffff);
1727 load_seg_vm(R_FS
, new_fs
& 0xffff);
1728 load_seg_vm(R_GS
, new_gs
& 0xffff);
1730 env
->eip
= new_eip
& 0xffff;
1734 void helper_iret_protected(int shift
, int next_eip
)
1736 int tss_selector
, type
;
1739 /* specific case for TSS */
1740 if (env
->eflags
& NT_MASK
) {
1741 tss_selector
= lduw_kernel(env
->tr
.base
+ 0);
1742 if (tss_selector
& 4)
1743 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1744 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
1745 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1746 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
1747 /* NOTE: we check both segment and busy TSS */
1749 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
1750 switch_tss(tss_selector
, e1
, e2
, SWITCH_TSS_IRET
, next_eip
);
1752 helper_ret_protected(shift
, 1, 0);
1756 void helper_lret_protected(int shift
, int addend
)
1758 helper_ret_protected(shift
, 0, addend
);
1761 void helper_movl_crN_T0(int reg
)
1765 cpu_x86_update_cr0(env
, T0
);
1768 cpu_x86_update_cr3(env
, T0
);
1771 cpu_x86_update_cr4(env
, T0
);
1780 void helper_movl_drN_T0(int reg
)
1785 void helper_invlpg(unsigned int addr
)
1787 cpu_x86_flush_tlb(env
, addr
);
1791 #if !defined(__i386__) && !defined(__x86_64__)
1795 void helper_rdtsc(void)
1798 #if defined(__i386__) || defined(__x86_64__)
1799 asm volatile ("rdtsc" : "=A" (val
));
1801 /* better than nothing: the time increases */
1808 void helper_wrmsr(void)
1811 case MSR_IA32_SYSENTER_CS
:
1812 env
->sysenter_cs
= EAX
& 0xffff;
1814 case MSR_IA32_SYSENTER_ESP
:
1815 env
->sysenter_esp
= EAX
;
1817 case MSR_IA32_SYSENTER_EIP
:
1818 env
->sysenter_eip
= EAX
;
1821 /* XXX: exception ? */
1826 void helper_rdmsr(void)
1829 case MSR_IA32_SYSENTER_CS
:
1830 EAX
= env
->sysenter_cs
;
1833 case MSR_IA32_SYSENTER_ESP
:
1834 EAX
= env
->sysenter_esp
;
1837 case MSR_IA32_SYSENTER_EIP
:
1838 EAX
= env
->sysenter_eip
;
1842 /* XXX: exception ? */
1847 void helper_lsl(void)
1849 unsigned int selector
, limit
;
1851 int rpl
, dpl
, cpl
, type
;
1853 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1854 selector
= T0
& 0xffff;
1855 if (load_segment(&e1
, &e2
, selector
) != 0)
1858 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1859 cpl
= env
->hflags
& HF_CPL_MASK
;
1860 if (e2
& DESC_S_MASK
) {
1861 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1864 if (dpl
< cpl
|| dpl
< rpl
)
1868 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1879 if (dpl
< cpl
|| dpl
< rpl
)
1882 limit
= get_seg_limit(e1
, e2
);
1887 void helper_lar(void)
1889 unsigned int selector
;
1891 int rpl
, dpl
, cpl
, type
;
1893 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1894 selector
= T0
& 0xffff;
1895 if ((selector
& 0xfffc) == 0)
1897 if (load_segment(&e1
, &e2
, selector
) != 0)
1900 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1901 cpl
= env
->hflags
& HF_CPL_MASK
;
1902 if (e2
& DESC_S_MASK
) {
1903 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
1906 if (dpl
< cpl
|| dpl
< rpl
)
1910 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1924 if (dpl
< cpl
|| dpl
< rpl
)
1927 T1
= e2
& 0x00f0ff00;
1931 void helper_verr(void)
1933 unsigned int selector
;
1937 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1938 selector
= T0
& 0xffff;
1939 if ((selector
& 0xfffc) == 0)
1941 if (load_segment(&e1
, &e2
, selector
) != 0)
1943 if (!(e2
& DESC_S_MASK
))
1946 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1947 cpl
= env
->hflags
& HF_CPL_MASK
;
1948 if (e2
& DESC_CS_MASK
) {
1949 if (!(e2
& DESC_R_MASK
))
1951 if (!(e2
& DESC_C_MASK
)) {
1952 if (dpl
< cpl
|| dpl
< rpl
)
1956 if (dpl
< cpl
|| dpl
< rpl
)
1962 void helper_verw(void)
1964 unsigned int selector
;
1968 CC_SRC
= cc_table
[CC_OP
].compute_all() & ~CC_Z
;
1969 selector
= T0
& 0xffff;
1970 if ((selector
& 0xfffc) == 0)
1972 if (load_segment(&e1
, &e2
, selector
) != 0)
1974 if (!(e2
& DESC_S_MASK
))
1977 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1978 cpl
= env
->hflags
& HF_CPL_MASK
;
1979 if (e2
& DESC_CS_MASK
) {
1982 if (dpl
< cpl
|| dpl
< rpl
)
1984 if (!(e2
& DESC_W_MASK
))
1992 void helper_fldt_ST0_A0(void)
1995 new_fpstt
= (env
->fpstt
- 1) & 7;
1996 env
->fpregs
[new_fpstt
] = helper_fldt((uint8_t *)A0
);
1997 env
->fpstt
= new_fpstt
;
1998 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
2001 void helper_fstt_ST0_A0(void)
2003 helper_fstt(ST0
, (uint8_t *)A0
);
2008 void helper_fbld_ST0_A0(void)
2016 for(i
= 8; i
>= 0; i
--) {
2017 v
= ldub((uint8_t *)A0
+ i
);
2018 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
2021 if (ldub((uint8_t *)A0
+ 9) & 0x80)
2027 void helper_fbst_ST0_A0(void)
2031 uint8_t *mem_ref
, *mem_end
;
2036 mem_ref
= (uint8_t *)A0
;
2037 mem_end
= mem_ref
+ 9;
2044 while (mem_ref
< mem_end
) {
2049 v
= ((v
/ 10) << 4) | (v
% 10);
2052 while (mem_ref
< mem_end
) {
2057 void helper_f2xm1(void)
2059 ST0
= pow(2.0,ST0
) - 1.0;
2062 void helper_fyl2x(void)
2064 CPU86_LDouble fptemp
;
2068 fptemp
= log(fptemp
)/log(2.0); /* log2(ST) */
2072 env
->fpus
&= (~0x4700);
2077 void helper_fptan(void)
2079 CPU86_LDouble fptemp
;
2082 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2088 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2089 /* the above code is for |arg| < 2**52 only */
2093 void helper_fpatan(void)
2095 CPU86_LDouble fptemp
, fpsrcop
;
2099 ST1
= atan2(fpsrcop
,fptemp
);
2103 void helper_fxtract(void)
2105 CPU86_LDoubleU temp
;
2106 unsigned int expdif
;
2109 expdif
= EXPD(temp
) - EXPBIAS
;
2110 /*DP exponent bias*/
2117 void helper_fprem1(void)
2119 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2120 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2126 fpsrcop1
.d
= fpsrcop
;
2128 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2130 dblq
= fpsrcop
/ fptemp
;
2131 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2132 ST0
= fpsrcop
- fptemp
*dblq
;
2133 q
= (int)dblq
; /* cutting off top bits is assumed here */
2134 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2135 /* (C0,C1,C3) <-- (q2,q1,q0) */
2136 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2137 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2138 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2140 env
->fpus
|= 0x400; /* C2 <-- 1 */
2141 fptemp
= pow(2.0, expdif
-50);
2142 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2143 /* fpsrcop = integer obtained by rounding to the nearest */
2144 fpsrcop
= (fpsrcop
-floor(fpsrcop
) < ceil(fpsrcop
)-fpsrcop
)?
2145 floor(fpsrcop
): ceil(fpsrcop
);
2146 ST0
-= (ST1
* fpsrcop
* fptemp
);
2150 void helper_fprem(void)
2152 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
2153 CPU86_LDoubleU fpsrcop1
, fptemp1
;
2159 fpsrcop1
.d
= fpsrcop
;
2161 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
2162 if ( expdif
< 53 ) {
2163 dblq
= fpsrcop
/ fptemp
;
2164 dblq
= (dblq
< 0.0)? ceil(dblq
): floor(dblq
);
2165 ST0
= fpsrcop
- fptemp
*dblq
;
2166 q
= (int)dblq
; /* cutting off top bits is assumed here */
2167 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2168 /* (C0,C1,C3) <-- (q2,q1,q0) */
2169 env
->fpus
|= (q
&0x4) << 6; /* (C0) <-- q2 */
2170 env
->fpus
|= (q
&0x2) << 8; /* (C1) <-- q1 */
2171 env
->fpus
|= (q
&0x1) << 14; /* (C3) <-- q0 */
2173 env
->fpus
|= 0x400; /* C2 <-- 1 */
2174 fptemp
= pow(2.0, expdif
-50);
2175 fpsrcop
= (ST0
/ ST1
) / fptemp
;
2176 /* fpsrcop = integer obtained by chopping */
2177 fpsrcop
= (fpsrcop
< 0.0)?
2178 -(floor(fabs(fpsrcop
))): floor(fpsrcop
);
2179 ST0
-= (ST1
* fpsrcop
* fptemp
);
2183 void helper_fyl2xp1(void)
2185 CPU86_LDouble fptemp
;
2188 if ((fptemp
+1.0)>0.0) {
2189 fptemp
= log(fptemp
+1.0) / log(2.0); /* log2(ST+1.0) */
2193 env
->fpus
&= (~0x4700);
2198 void helper_fsqrt(void)
2200 CPU86_LDouble fptemp
;
2204 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2210 void helper_fsincos(void)
2212 CPU86_LDouble fptemp
;
2215 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2221 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2222 /* the above code is for |arg| < 2**63 only */
2226 void helper_frndint(void)
2232 switch(env
->fpuc
& RC_MASK
) {
2235 asm("rndd %0, %1" : "=f" (a
) : "f"(a
));
2238 asm("rnddm %0, %1" : "=f" (a
) : "f"(a
));
2241 asm("rnddp %0, %1" : "=f" (a
) : "f"(a
));
2244 asm("rnddz %0, %1" : "=f" (a
) : "f"(a
));
2253 void helper_fscale(void)
2255 CPU86_LDouble fpsrcop
, fptemp
;
2258 fptemp
= pow(fpsrcop
,ST1
);
2262 void helper_fsin(void)
2264 CPU86_LDouble fptemp
;
2267 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2271 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2272 /* the above code is for |arg| < 2**53 only */
2276 void helper_fcos(void)
2278 CPU86_LDouble fptemp
;
2281 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
2285 env
->fpus
&= (~0x400); /* C2 <-- 0 */
2286 /* the above code is for |arg5 < 2**63 only */
2290 void helper_fxam_ST0(void)
2292 CPU86_LDoubleU temp
;
2297 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2299 env
->fpus
|= 0x200; /* C1 <-- 1 */
2301 expdif
= EXPD(temp
);
2302 if (expdif
== MAXEXPD
) {
2303 if (MANTD(temp
) == 0)
2304 env
->fpus
|= 0x500 /*Infinity*/;
2306 env
->fpus
|= 0x100 /*NaN*/;
2307 } else if (expdif
== 0) {
2308 if (MANTD(temp
) == 0)
2309 env
->fpus
|= 0x4000 /*Zero*/;
2311 env
->fpus
|= 0x4400 /*Denormal*/;
2317 void helper_fstenv(uint8_t *ptr
, int data32
)
2319 int fpus
, fptag
, exp
, i
;
2323 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
2325 for (i
=7; i
>=0; i
--) {
2327 if (env
->fptags
[i
]) {
2330 tmp
.d
= env
->fpregs
[i
];
2333 if (exp
== 0 && mant
== 0) {
2336 } else if (exp
== 0 || exp
== MAXEXPD
2337 #ifdef USE_X86LDOUBLE
2338 || (mant
& (1LL << 63)) == 0
2341 /* NaNs, infinity, denormal */
2348 stl(ptr
, env
->fpuc
);
2350 stl(ptr
+ 8, fptag
);
2351 stl(ptr
+ 12, 0); /* fpip */
2352 stl(ptr
+ 16, 0); /* fpcs */
2353 stl(ptr
+ 20, 0); /* fpoo */
2354 stl(ptr
+ 24, 0); /* fpos */
2357 stw(ptr
, env
->fpuc
);
2359 stw(ptr
+ 4, fptag
);
2367 void helper_fldenv(uint8_t *ptr
, int data32
)
2372 env
->fpuc
= lduw(ptr
);
2373 fpus
= lduw(ptr
+ 4);
2374 fptag
= lduw(ptr
+ 8);
2377 env
->fpuc
= lduw(ptr
);
2378 fpus
= lduw(ptr
+ 2);
2379 fptag
= lduw(ptr
+ 4);
2381 env
->fpstt
= (fpus
>> 11) & 7;
2382 env
->fpus
= fpus
& ~0x3800;
2383 for(i
= 0;i
< 8; i
++) {
2384 env
->fptags
[i
] = ((fptag
& 3) == 3);
2389 void helper_fsave(uint8_t *ptr
, int data32
)
2394 helper_fstenv(ptr
, data32
);
2396 ptr
+= (14 << data32
);
2397 for(i
= 0;i
< 8; i
++) {
2399 helper_fstt(tmp
, ptr
);
2417 void helper_frstor(uint8_t *ptr
, int data32
)
2422 helper_fldenv(ptr
, data32
);
2423 ptr
+= (14 << data32
);
2425 for(i
= 0;i
< 8; i
++) {
2426 tmp
= helper_fldt(ptr
);
2432 /* XXX: merge with helper_fstt ? */
2434 #ifndef USE_X86LDOUBLE
2436 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, CPU86_LDouble f
)
2438 CPU86_LDoubleU temp
;
2443 *pmant
= (MANTD(temp
) << 11) | (1LL << 63);
2444 /* exponent + sign */
2445 e
= EXPD(temp
) - EXPBIAS
+ 16383;
2446 e
|= SIGND(temp
) >> 16;
2450 CPU86_LDouble
cpu_set_fp80(uint64_t mant
, uint16_t upper
)
2452 CPU86_LDoubleU temp
;
2456 /* XXX: handle overflow ? */
2457 e
= (upper
& 0x7fff) - 16383 + EXPBIAS
; /* exponent */
2458 e
|= (upper
>> 4) & 0x800; /* sign */
2459 ll
= (mant
>> 11) & ((1LL << 52) - 1);
2461 temp
.l
.upper
= (e
<< 20) | (ll
>> 32);
2464 temp
.ll
= ll
| ((uint64_t)e
<< 52);
2471 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, CPU86_LDouble f
)
2473 CPU86_LDoubleU temp
;
2476 *pmant
= temp
.l
.lower
;
2477 *pexp
= temp
.l
.upper
;
2480 CPU86_LDouble
cpu_set_fp80(uint64_t mant
, uint16_t upper
)
2482 CPU86_LDoubleU temp
;
2484 temp
.l
.upper
= upper
;
2485 temp
.l
.lower
= mant
;
2490 #if !defined(CONFIG_USER_ONLY)
2492 #define MMUSUFFIX _mmu
2493 #define GETPC() (__builtin_return_address(0))
2496 #include "softmmu_template.h"
2499 #include "softmmu_template.h"
2502 #include "softmmu_template.h"
2505 #include "softmmu_template.h"
2509 /* try to fill the TLB and return an exception if error. If retaddr is
2510 NULL, it means that the function was called in C code (i.e. not
2511 from generated code or from helper.c) */
2512 /* XXX: fix it to restore all registers */
2513 void tlb_fill(unsigned long addr
, int is_write
, int is_user
, void *retaddr
)
2515 TranslationBlock
*tb
;
2518 CPUX86State
*saved_env
;
2520 /* XXX: hack to restore env in all cases, even if not called from
2523 env
= cpu_single_env
;
2525 ret
= cpu_x86_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
2528 /* now we have a real cpu fault */
2529 pc
= (unsigned long)retaddr
;
2530 tb
= tb_find_pc(pc
);
2532 /* the PC is inside the translated code. It means that we have
2533 a virtual CPU fault */
2534 cpu_restore_state(tb
, env
, pc
, NULL
);
2537 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);