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git.proxmox.com Git - qemu.git/blob - target-i386/helper2.c
2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35 #include <linux/unistd.h>
36 #include <linux/version.h>
38 _syscall3(int, modify_ldt
, int, func
, void *, ptr
, unsigned long, bytecount
)
40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
41 #define modify_ldt_ldt_s user_desc
43 #endif /* USE_CODE_COPY */
45 CPUX86State
*cpu_x86_init(void)
52 env
= malloc(sizeof(CPUX86State
));
55 memset(env
, 0, sizeof(CPUX86State
));
56 /* init various static tables */
59 optimize_flags_init();
62 /* testing code for code copy case */
64 struct modify_ldt_ldt_s ldt
;
67 ldt
.base_addr
= (unsigned long)env
;
68 ldt
.limit
= (sizeof(CPUState
) + 0xfff) >> 12;
70 ldt
.contents
= MODIFY_LDT_CONTENTS_DATA
;
71 ldt
.read_exec_only
= 0;
72 ldt
.limit_in_pages
= 1;
73 ldt
.seg_not_present
= 0;
75 modify_ldt(1, &ldt
, sizeof(ldt
)); /* write ldt entry */
77 asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
85 /* NOTE: must be called outside the CPU execute loop */
86 void cpu_reset(CPUX86State
*env
)
90 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
94 /* init to reset state */
97 env
->hflags
|= HF_SOFTMMU_MASK
;
100 cpu_x86_update_cr0(env
, 0x60000010);
101 env
->a20_mask
= 0xffffffff;
103 env
->idt
.limit
= 0xffff;
104 env
->gdt
.limit
= 0xffff;
105 env
->ldt
.limit
= 0xffff;
106 env
->ldt
.flags
= DESC_P_MASK
;
107 env
->tr
.limit
= 0xffff;
108 env
->tr
.flags
= DESC_P_MASK
;
110 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, (uint8_t *)0xffff0000, 0xffff, 0);
111 cpu_x86_load_seg_cache(env
, R_DS
, 0, NULL
, 0xffff, 0);
112 cpu_x86_load_seg_cache(env
, R_ES
, 0, NULL
, 0xffff, 0);
113 cpu_x86_load_seg_cache(env
, R_SS
, 0, NULL
, 0xffff, 0);
114 cpu_x86_load_seg_cache(env
, R_FS
, 0, NULL
, 0xffff, 0);
115 cpu_x86_load_seg_cache(env
, R_GS
, 0, NULL
, 0xffff, 0);
118 env
->regs
[R_EDX
] = 0x600; /* indicate P6 processor */
123 for(i
= 0;i
< 8; i
++)
128 void cpu_x86_close(CPUX86State
*env
)
133 /***********************************************************/
136 static const char *cc_op_str
[] = {
171 void cpu_dump_state(CPUState
*env
, FILE *f
,
172 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
177 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
179 eflags
= env
->eflags
;
180 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
181 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
182 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d\n",
183 env
->regs
[R_EAX
], env
->regs
[R_EBX
], env
->regs
[R_ECX
], env
->regs
[R_EDX
],
184 env
->regs
[R_ESI
], env
->regs
[R_EDI
], env
->regs
[R_EBP
], env
->regs
[R_ESP
],
186 eflags
& DF_MASK
? 'D' : '-',
187 eflags
& CC_O
? 'O' : '-',
188 eflags
& CC_S
? 'S' : '-',
189 eflags
& CC_Z
? 'Z' : '-',
190 eflags
& CC_A
? 'A' : '-',
191 eflags
& CC_P
? 'P' : '-',
192 eflags
& CC_C
? 'C' : '-',
193 env
->hflags
& HF_CPL_MASK
,
194 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
195 (env
->a20_mask
>> 20) & 1);
196 for(i
= 0; i
< 6; i
++) {
197 SegmentCache
*sc
= &env
->segs
[i
];
198 cpu_fprintf(f
, "%s =%04x %08x %08x %08x\n",
205 cpu_fprintf(f
, "LDT=%04x %08x %08x %08x\n",
210 cpu_fprintf(f
, "TR =%04x %08x %08x %08x\n",
215 cpu_fprintf(f
, "GDT= %08x %08x\n",
216 (int)env
->gdt
.base
, env
->gdt
.limit
);
217 cpu_fprintf(f
, "IDT= %08x %08x\n",
218 (int)env
->idt
.base
, env
->idt
.limit
);
219 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
220 env
->cr
[0], env
->cr
[2], env
->cr
[3], env
->cr
[4]);
222 if (flags
& X86_DUMP_CCOP
) {
223 if ((unsigned)env
->cc_op
< CC_OP_NB
)
224 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
226 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
227 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
228 env
->cc_src
, env
->cc_dst
, cc_op_name
);
230 if (flags
& X86_DUMP_FPU
) {
231 cpu_fprintf(f
, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
232 (double)env
->fpregs
[0],
233 (double)env
->fpregs
[1],
234 (double)env
->fpregs
[2],
235 (double)env
->fpregs
[3]);
236 cpu_fprintf(f
, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
237 (double)env
->fpregs
[4],
238 (double)env
->fpregs
[5],
239 (double)env
->fpregs
[7],
240 (double)env
->fpregs
[8]);
244 /***********************************************************/
246 /* XXX: add PGE support */
248 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
)
250 a20_state
= (a20_state
!= 0);
251 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
252 #if defined(DEBUG_MMU)
253 printf("A20 update: a20=%d\n", a20_state
);
255 /* if the cpu is currently executing code, we must unlink it and
256 all the potentially executing TB */
257 cpu_interrupt(env
, CPU_INTERRUPT_EXITTB
);
259 /* when a20 is changed, all the MMU mappings are invalid, so
260 we must flush everything */
262 env
->a20_mask
= 0xffefffff | (a20_state
<< 20);
266 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
270 #if defined(DEBUG_MMU)
271 printf("CR0 update: CR0=0x%08x\n", new_cr0
);
273 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
274 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
277 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
279 /* update PE flag in hidden flags */
280 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
281 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
282 /* ensure that ADDSEG is always set in real mode */
283 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
284 /* update FPU flags */
285 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
286 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
289 void cpu_x86_update_cr3(CPUX86State
*env
, uint32_t new_cr3
)
291 env
->cr
[3] = new_cr3
;
292 if (env
->cr
[0] & CR0_PG_MASK
) {
293 #if defined(DEBUG_MMU)
294 printf("CR3 update: CR3=%08x\n", new_cr3
);
300 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
302 #if defined(DEBUG_MMU)
303 printf("CR4 update: CR4=%08x\n", env
->cr
[4]);
305 if ((new_cr4
& (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
)) !=
306 (env
->cr
[4] & (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
))) {
309 env
->cr
[4] = new_cr4
;
312 /* XXX: also flush 4MB pages */
313 void cpu_x86_flush_tlb(CPUX86State
*env
, uint32_t addr
)
315 tlb_flush_page(env
, addr
);
319 -1 = cannot handle fault
320 0 = nothing more to do
321 1 = generate PF fault
322 2 = soft MMU activation required for this block
324 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, uint32_t addr
,
325 int is_write
, int is_user
, int is_softmmu
)
327 uint8_t *pde_ptr
, *pte_ptr
;
328 uint32_t pde
, pte
, virt_addr
, ptep
;
329 int error_code
, is_dirty
, prot
, page_size
, ret
;
330 unsigned long paddr
, vaddr
, page_offset
;
332 #if defined(DEBUG_MMU)
333 printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
334 addr
, is_write
, is_user
, env
->eip
);
338 if (env
->user_mode_only
) {
339 /* user mode only emulation */
344 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
346 virt_addr
= addr
& TARGET_PAGE_MASK
;
347 prot
= PAGE_READ
| PAGE_WRITE
;
352 /* page directory entry */
353 pde_ptr
= phys_ram_base
+
354 (((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & ~3)) & env
->a20_mask
);
355 pde
= ldl_raw(pde_ptr
);
356 if (!(pde
& PG_PRESENT_MASK
)) {
360 /* if PSE bit is set, then we use a 4MB page */
361 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
363 if (!(pde
& PG_USER_MASK
))
364 goto do_fault_protect
;
365 if (is_write
&& !(pde
& PG_RW_MASK
))
366 goto do_fault_protect
;
368 if ((env
->cr
[0] & CR0_WP_MASK
) &&
369 is_write
&& !(pde
& PG_RW_MASK
))
370 goto do_fault_protect
;
372 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
373 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
374 pde
|= PG_ACCESSED_MASK
;
376 pde
|= PG_DIRTY_MASK
;
377 stl_raw(pde_ptr
, pde
);
380 pte
= pde
& ~0x003ff000; /* align to 4MB */
382 page_size
= 4096 * 1024;
383 virt_addr
= addr
& ~0x003fffff;
385 if (!(pde
& PG_ACCESSED_MASK
)) {
386 pde
|= PG_ACCESSED_MASK
;
387 stl_raw(pde_ptr
, pde
);
390 /* page directory entry */
391 pte_ptr
= phys_ram_base
+
392 (((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
);
393 pte
= ldl_raw(pte_ptr
);
394 if (!(pte
& PG_PRESENT_MASK
)) {
398 /* combine pde and pte user and rw protections */
401 if (!(ptep
& PG_USER_MASK
))
402 goto do_fault_protect
;
403 if (is_write
&& !(ptep
& PG_RW_MASK
))
404 goto do_fault_protect
;
406 if ((env
->cr
[0] & CR0_WP_MASK
) &&
407 is_write
&& !(ptep
& PG_RW_MASK
))
408 goto do_fault_protect
;
410 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
411 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
412 pte
|= PG_ACCESSED_MASK
;
414 pte
|= PG_DIRTY_MASK
;
415 stl_raw(pte_ptr
, pte
);
418 virt_addr
= addr
& ~0xfff;
421 /* the page can be put in the TLB */
423 if (pte
& PG_DIRTY_MASK
) {
424 /* only set write access if already dirty... otherwise wait
427 if (ptep
& PG_RW_MASK
)
430 if (!(env
->cr
[0] & CR0_WP_MASK
) ||
437 pte
= pte
& env
->a20_mask
;
439 /* Even if 4MB pages, we map only one 4KB page in the cache to
440 avoid filling it too fast */
441 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
442 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
443 vaddr
= virt_addr
+ page_offset
;
445 ret
= tlb_set_page(env
, vaddr
, paddr
, prot
, is_user
, is_softmmu
);
448 error_code
= PG_ERROR_P_MASK
;
451 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
) | error_code
;
453 env
->error_code
|= PG_ERROR_U_MASK
;
457 #if defined(CONFIG_USER_ONLY)
458 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
463 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
465 uint8_t *pde_ptr
, *pte_ptr
;
466 uint32_t pde
, pte
, paddr
, page_offset
, page_size
;
468 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
472 /* page directory entry */
473 pde_ptr
= phys_ram_base
+
474 (((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & ~3)) & env
->a20_mask
);
475 pde
= ldl_raw(pde_ptr
);
476 if (!(pde
& PG_PRESENT_MASK
))
478 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
479 pte
= pde
& ~0x003ff000; /* align to 4MB */
480 page_size
= 4096 * 1024;
482 /* page directory entry */
483 pte_ptr
= phys_ram_base
+
484 (((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
);
485 pte
= ldl_raw(pte_ptr
);
486 if (!(pte
& PG_PRESENT_MASK
))
491 pte
= pte
& env
->a20_mask
;
492 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
493 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
498 #if defined(USE_CODE_COPY)
511 uint8_t fpregs1
[8 * 10];
514 void restore_native_fp_state(CPUState
*env
)
517 struct fpstate fp1
, *fp
= &fp1
;
519 fp
->fpuc
= env
->fpuc
;
520 fp
->fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
522 for (i
=7; i
>=0; i
--) {
524 if (env
->fptags
[i
]) {
527 /* the FPU automatically computes it */
532 for(i
= 0;i
< 8; i
++) {
533 memcpy(&fp
->fpregs1
[i
* 10], &env
->fpregs
[j
], 10);
536 asm volatile ("frstor %0" : "=m" (*fp
));
537 env
->native_fp_regs
= 1;
540 void save_native_fp_state(CPUState
*env
)
544 struct fpstate fp1
, *fp
= &fp1
;
546 asm volatile ("fsave %0" : : "m" (*fp
));
547 env
->fpuc
= fp
->fpuc
;
548 env
->fpstt
= (fp
->fpus
>> 11) & 7;
549 env
->fpus
= fp
->fpus
& ~0x3800;
551 for(i
= 0;i
< 8; i
++) {
552 env
->fptags
[i
] = ((fptag
& 3) == 3);
556 for(i
= 0;i
< 8; i
++) {
557 memcpy(&env
->fpregs
[j
], &fp
->fpregs1
[i
* 10], 10);
560 /* we must restore the default rounding state */
561 /* XXX: we do not restore the exception state */
562 fpuc
= 0x037f | (env
->fpuc
& (3 << 10));
563 asm volatile("fldcw %0" : : "m" (fpuc
));
564 env
->native_fp_regs
= 0;