target-i386/helper2.c

   1 /*
   2  *  i386 helpers (without register variable usage)
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27 #include <sys/mman.h>
  28
  29 #include "cpu.h"
  30 #include "exec-all.h"
  31
  32 //#define DEBUG_MMU
  33
  34 CPUX86State *cpu_x86_init(void)
  35 {
  36     CPUX86State *env;
  37     int i;
  38     static int inited;
  39
  40     cpu_exec_init();
  41
  42     env = malloc(sizeof(CPUX86State));
  43     if (!env)
  44         return NULL;
  45     memset(env, 0, sizeof(CPUX86State));
  46     /* basic FPU init */
  47     for(i = 0;i < 8; i++)
  48         env->fptags[i] = 1;
  49     env->fpuc = 0x37f;
  50     /* flags setup : we activate the IRQs by default as in user mode */
  51     env->eflags = 0x2 | IF_MASK;
  52
  53     tlb_flush(env);
  54 #ifdef CONFIG_SOFTMMU
  55     env->hflags |= HF_SOFTMMU_MASK;
  56 #endif
  57     /* init various static tables */
  58     if (!inited) {
  59         inited = 1;
  60         optimize_flags_init();
  61     }
  62     return env;
  63 }
  64
  65 void cpu_x86_close(CPUX86State *env)
  66 {
  67     free(env);
  68 }
  69
  70 /***********************************************************/
  71 /* x86 debug */
  72
  73 static const char *cc_op_str[] = {
  74     "DYNAMIC",
  75     "EFLAGS",
  76     "MUL",
  77     "ADDB",
  78     "ADDW",
  79     "ADDL",
  80     "ADCB",
  81     "ADCW",
  82     "ADCL",
  83     "SUBB",
  84     "SUBW",
  85     "SUBL",
  86     "SBBB",
  87     "SBBW",
  88     "SBBL",
  89     "LOGICB",
  90     "LOGICW",
  91     "LOGICL",
  92     "INCB",
  93     "INCW",
  94     "INCL",
  95     "DECB",
  96     "DECW",
  97     "DECL",
  98     "SHLB",
  99     "SHLW",
 100     "SHLL",
 101     "SARB",
 102     "SARW",
 103     "SARL",
 104 };
 105
 106 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
 107 {
 108     int eflags, i;
 109     char cc_op_name[32];
 110     static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
 111
 112     eflags = env->eflags;
 113     fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
 114             "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
 115             "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]    CPL=%d\n",
 116             env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
 117             env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
 118             env->eip, eflags,
 119             eflags & DF_MASK ? 'D' : '-',
 120             eflags & CC_O ? 'O' : '-',
 121             eflags & CC_S ? 'S' : '-',
 122             eflags & CC_Z ? 'Z' : '-',
 123             eflags & CC_A ? 'A' : '-',
 124             eflags & CC_P ? 'P' : '-',
 125             eflags & CC_C ? 'C' : '-',
 126             env->hflags & HF_CPL_MASK);
 127     for(i = 0; i < 6; i++) {
 128         SegmentCache *sc = &env->segs[i];
 129         fprintf(f, "%s =%04x %08x %08x %08x\n",
 130                 seg_name[i],
 131                 sc->selector,
 132                 (int)sc->base,
 133                 sc->limit,
 134                 sc->flags);
 135     }
 136     fprintf(f, "LDT=%04x %08x %08x %08x\n",
 137             env->ldt.selector,
 138             (int)env->ldt.base,
 139             env->ldt.limit,
 140             env->ldt.flags);
 141     fprintf(f, "TR =%04x %08x %08x %08x\n",
 142             env->tr.selector,
 143             (int)env->tr.base,
 144             env->tr.limit,
 145             env->tr.flags);
 146     fprintf(f, "GDT=     %08x %08x\n",
 147             (int)env->gdt.base, env->gdt.limit);
 148     fprintf(f, "IDT=     %08x %08x\n",
 149             (int)env->idt.base, env->idt.limit);
 150     fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
 151             env->cr[0], env->cr[2], env->cr[3], env->cr[4]);
 152
 153     if (flags & X86_DUMP_CCOP) {
 154         if ((unsigned)env->cc_op < CC_OP_NB)
 155             strcpy(cc_op_name, cc_op_str[env->cc_op]);
 156         else
 157             snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
 158         fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
 159                 env->cc_src, env->cc_dst, cc_op_name);
 160     }
 161     if (flags & X86_DUMP_FPU) {
 162         fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
 163                 (double)env->fpregs[0],
 164                 (double)env->fpregs[1],
 165                 (double)env->fpregs[2],
 166                 (double)env->fpregs[3]);
 167         fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
 168                 (double)env->fpregs[4],
 169                 (double)env->fpregs[5],
 170                 (double)env->fpregs[7],
 171                 (double)env->fpregs[8]);
 172     }
 173 }
 174
 175 /***********************************************************/
 176 /* x86 mmu */
 177 /* XXX: add PGE support */
 178
 179 /* called when cr3 or PG bit are modified */
 180 static int last_pg_state = -1;
 181 static int last_pe_state = 0;
 182 static uint32_t a20_mask;
 183 int a20_enabled;
 184
 185 int phys_ram_size;
 186 int phys_ram_fd;
 187 uint8_t *phys_ram_base;
 188
 189 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
 190 {
 191     a20_state = (a20_state != 0);
 192     if (a20_state != a20_enabled) {
 193         /* when a20 is changed, all the MMU mappings are invalid, so
 194            we must flush everything */
 195         page_unmap();
 196         tlb_flush(env);
 197         a20_enabled = a20_state;
 198         if (a20_enabled)
 199             a20_mask = 0xffffffff;
 200         else
 201             a20_mask = 0xffefffff;
 202     }
 203 }
 204
 205 void cpu_x86_update_cr0(CPUX86State *env)
 206 {
 207     int pg_state, pe_state;
 208
 209 #ifdef DEBUG_MMU
 210     printf("CR0 update: CR0=0x%08x\n", env->cr[0]);
 211 #endif
 212     pg_state = env->cr[0] & CR0_PG_MASK;
 213     if (pg_state != last_pg_state) {
 214         page_unmap();
 215         tlb_flush(env);
 216         last_pg_state = pg_state;
 217     }
 218     pe_state = env->cr[0] & CR0_PE_MASK;
 219     if (last_pe_state != pe_state) {
 220         tb_flush();
 221         last_pe_state = pe_state;
 222     }
 223 }
 224
 225 void cpu_x86_update_cr3(CPUX86State *env)
 226 {
 227     if (env->cr[0] & CR0_PG_MASK) {
 228 #if defined(DEBUG_MMU)
 229         printf("CR3 update: CR3=%08x\n", env->cr[3]);
 230 #endif
 231         page_unmap();
 232         tlb_flush(env);
 233     }
 234 }
 235
 236 void cpu_x86_init_mmu(CPUX86State *env)
 237 {
 238     a20_enabled = 1;
 239     a20_mask = 0xffffffff;
 240
 241     last_pg_state = -1;
 242     cpu_x86_update_cr0(env);
 243 }
 244
 245 /* XXX: also flush 4MB pages */
 246 void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
 247 {
 248     int flags;
 249     unsigned long virt_addr;
 250
 251     tlb_flush_page(env, addr);
 252
 253     flags = page_get_flags(addr);
 254     if (flags & PAGE_VALID) {
 255         virt_addr = addr & ~0xfff;
 256 #if !defined(CONFIG_SOFTMMU)
 257         munmap((void *)virt_addr, 4096);
 258 #endif
 259         page_set_flags(virt_addr, virt_addr + 4096, 0);
 260     }
 261 }
 262
 263 /* return value:
 264    -1 = cannot handle fault
 265    0  = nothing more to do
 266    1  = generate PF fault
 267    2  = soft MMU activation required for this block
 268 */
 269 int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
 270                              int is_write, int is_user, int is_softmmu)
 271 {
 272     uint8_t *pde_ptr, *pte_ptr;
 273     uint32_t pde, pte, virt_addr;
 274     int error_code, is_dirty, prot, page_size, ret;
 275     unsigned long pd;
 276
 277 #ifdef DEBUG_MMU
 278     printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
 279            addr, is_write, is_user, env->eip);
 280 #endif
 281
 282     if (env->user_mode_only) {
 283         /* user mode only emulation */
 284         error_code = 0;
 285         goto do_fault;
 286     }
 287
 288     if (!(env->cr[0] & CR0_PG_MASK)) {
 289         pte = addr;
 290         virt_addr = addr & TARGET_PAGE_MASK;
 291         prot = PROT_READ | PROT_WRITE;
 292         page_size = 4096;
 293         goto do_mapping;
 294     }
 295
 296     /* page directory entry */
 297     pde_ptr = phys_ram_base +
 298         (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & a20_mask);
 299     pde = ldl_raw(pde_ptr);
 300     if (!(pde & PG_PRESENT_MASK)) {
 301         error_code = 0;
 302         goto do_fault;
 303     }
 304     if (is_user) {
 305         if (!(pde & PG_USER_MASK))
 306             goto do_fault_protect;
 307         if (is_write && !(pde & PG_RW_MASK))
 308             goto do_fault_protect;
 309     } else {
 310         if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) &&
 311             is_write && !(pde & PG_RW_MASK))
 312             goto do_fault_protect;
 313     }
 314     /* if PSE bit is set, then we use a 4MB page */
 315     if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
 316         is_dirty = is_write && !(pde & PG_DIRTY_MASK);
 317         if (!(pde & PG_ACCESSED_MASK)) {
 318             pde |= PG_ACCESSED_MASK;
 319             if (is_dirty)
 320                 pde |= PG_DIRTY_MASK;
 321             stl_raw(pde_ptr, pde);
 322         }
 323
 324         pte = pde & ~0x003ff000; /* align to 4MB */
 325         page_size = 4096 * 1024;
 326         virt_addr = addr & ~0x003fffff;
 327     } else {
 328         if (!(pde & PG_ACCESSED_MASK)) {
 329             pde |= PG_ACCESSED_MASK;
 330             stl_raw(pde_ptr, pde);
 331         }
 332
 333         /* page directory entry */
 334         pte_ptr = phys_ram_base +
 335             (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask);
 336         pte = ldl_raw(pte_ptr);
 337         if (!(pte & PG_PRESENT_MASK)) {
 338             error_code = 0;
 339             goto do_fault;
 340         }
 341         if (is_user) {
 342             if (!(pte & PG_USER_MASK))
 343                 goto do_fault_protect;
 344             if (is_write && !(pte & PG_RW_MASK))
 345                 goto do_fault_protect;
 346         } else {
 347             if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) &&
 348                 is_write && !(pte & PG_RW_MASK))
 349                 goto do_fault_protect;
 350         }
 351         is_dirty = is_write && !(pte & PG_DIRTY_MASK);
 352         if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
 353             pte |= PG_ACCESSED_MASK;
 354             if (is_dirty)
 355                 pte |= PG_DIRTY_MASK;
 356             stl_raw(pte_ptr, pte);
 357         }
 358         page_size = 4096;
 359         virt_addr = addr & ~0xfff;
 360     }
 361     /* the page can be put in the TLB */
 362     prot = PROT_READ;
 363     if (is_user) {
 364         if (pte & PG_RW_MASK)
 365             prot |= PROT_WRITE;
 366     } else {
 367         if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) ||
 368             (pte & PG_RW_MASK))
 369             prot |= PROT_WRITE;
 370     }
 371
 372  do_mapping:
 373     pte = pte & a20_mask;
 374 #if !defined(CONFIG_SOFTMMU)
 375     if (is_softmmu)
 376 #endif
 377     {
 378         unsigned long paddr, vaddr, address, addend, page_offset;
 379         int index;
 380
 381         /* software MMU case. Even if 4MB pages, we map only one 4KB
 382            page in the cache to avoid filling it too fast */
 383         page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
 384         paddr = (pte & TARGET_PAGE_MASK) + page_offset;
 385         vaddr = virt_addr + page_offset;
 386         index = (addr >> 12) & (CPU_TLB_SIZE - 1);
 387         pd = physpage_find(paddr);
 388         if (pd & 0xfff) {
 389             /* IO memory case */
 390             address = vaddr | pd;
 391             addend = paddr;
 392         } else {
 393             /* standard memory */
 394             address = vaddr;
 395             addend = (unsigned long)phys_ram_base + pd;
 396         }
 397         addend -= vaddr;
 398         env->tlb_read[is_user][index].address = address;
 399         env->tlb_read[is_user][index].addend = addend;
 400         if (prot & PROT_WRITE) {
 401             env->tlb_write[is_user][index].address = address;
 402             env->tlb_write[is_user][index].addend = addend;
 403         } else {
 404             env->tlb_write[is_user][index].address = -1;
 405             env->tlb_write[is_user][index].addend = -1;
 406         }
 407         page_set_flags(vaddr, vaddr + TARGET_PAGE_SIZE,
 408                        PAGE_VALID | PAGE_EXEC | prot);
 409         ret = 0;
 410     }
 411 #if !defined(CONFIG_SOFTMMU)
 412     else {
 413         ret = 0;
 414         /* XXX: incorrect for 4MB pages */
 415         pd = physpage_find(pte & ~0xfff);
 416         if ((pd & 0xfff) != 0) {
 417             /* IO access: no mapping is done as it will be handled by the
 418                soft MMU */
 419             if (!(env->hflags & HF_SOFTMMU_MASK))
 420                 ret = 2;
 421         } else {
 422             void *map_addr;
 423             map_addr = mmap((void *)virt_addr, page_size, prot,
 424                             MAP_SHARED | MAP_FIXED, phys_ram_fd, pd);
 425             if (map_addr == MAP_FAILED) {
 426                 fprintf(stderr,
 427                         "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
 428                         pte & ~0xfff, virt_addr);
 429                 exit(1);
 430             }
 431 #ifdef DEBUG_MMU
 432             printf("mmaping 0x%08x to virt 0x%08x pse=%d\n",
 433                    pte & ~0xfff, virt_addr, (page_size != 4096));
 434 #endif
 435             page_set_flags(virt_addr, virt_addr + page_size,
 436                            PAGE_VALID | PAGE_EXEC | prot);
 437         }
 438     }
 439 #endif
 440     return ret;
 441  do_fault_protect:
 442     error_code = PG_ERROR_P_MASK;
 443  do_fault:
 444     env->cr[2] = addr;
 445     env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
 446     if (is_user)
 447         env->error_code |= PG_ERROR_U_MASK;
 448     return 1;
 449 }