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Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
[qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include <asm/hyperv.h>
35 #include "hw/pci/pci.h"
36
37 //#define DEBUG_KVM
38
39 #ifdef DEBUG_KVM
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF(fmt, ...) \
44 do { } while (0)
45 #endif
46
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
49
50 #ifndef BUS_MCEERR_AR
51 #define BUS_MCEERR_AR 4
52 #endif
53 #ifndef BUS_MCEERR_AO
54 #define BUS_MCEERR_AO 5
55 #endif
56
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR),
59 KVM_CAP_INFO(EXT_CPUID),
60 KVM_CAP_INFO(MP_STATE),
61 KVM_CAP_LAST_INFO
62 };
63
64 static bool has_msr_star;
65 static bool has_msr_hsave_pa;
66 static bool has_msr_tsc_adjust;
67 static bool has_msr_tsc_deadline;
68 static bool has_msr_feature_control;
69 static bool has_msr_async_pf_en;
70 static bool has_msr_pv_eoi_en;
71 static bool has_msr_misc_enable;
72 static bool has_msr_kvm_steal_time;
73 static int lm_capable_kernel;
74
75 static bool has_msr_architectural_pmu;
76 static uint32_t num_architectural_pmu_counters;
77
78 bool kvm_allows_irq0_override(void)
79 {
80 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
81 }
82
83 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
84 {
85 struct kvm_cpuid2 *cpuid;
86 int r, size;
87
88 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
89 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
90 cpuid->nent = max;
91 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
92 if (r == 0 && cpuid->nent >= max) {
93 r = -E2BIG;
94 }
95 if (r < 0) {
96 if (r == -E2BIG) {
97 g_free(cpuid);
98 return NULL;
99 } else {
100 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
101 strerror(-r));
102 exit(1);
103 }
104 }
105 return cpuid;
106 }
107
108 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
109 * for all entries.
110 */
111 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
112 {
113 struct kvm_cpuid2 *cpuid;
114 int max = 1;
115 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
116 max *= 2;
117 }
118 return cpuid;
119 }
120
121 struct kvm_para_features {
122 int cap;
123 int feature;
124 } para_features[] = {
125 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
126 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
127 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
128 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
129 { -1, -1 }
130 };
131
132 static int get_para_features(KVMState *s)
133 {
134 int i, features = 0;
135
136 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
137 if (kvm_check_extension(s, para_features[i].cap)) {
138 features |= (1 << para_features[i].feature);
139 }
140 }
141
142 return features;
143 }
144
145
146 /* Returns the value for a specific register on the cpuid entry
147 */
148 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
149 {
150 uint32_t ret = 0;
151 switch (reg) {
152 case R_EAX:
153 ret = entry->eax;
154 break;
155 case R_EBX:
156 ret = entry->ebx;
157 break;
158 case R_ECX:
159 ret = entry->ecx;
160 break;
161 case R_EDX:
162 ret = entry->edx;
163 break;
164 }
165 return ret;
166 }
167
168 /* Find matching entry for function/index on kvm_cpuid2 struct
169 */
170 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
171 uint32_t function,
172 uint32_t index)
173 {
174 int i;
175 for (i = 0; i < cpuid->nent; ++i) {
176 if (cpuid->entries[i].function == function &&
177 cpuid->entries[i].index == index) {
178 return &cpuid->entries[i];
179 }
180 }
181 /* not found: */
182 return NULL;
183 }
184
185 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
186 uint32_t index, int reg)
187 {
188 struct kvm_cpuid2 *cpuid;
189 uint32_t ret = 0;
190 uint32_t cpuid_1_edx;
191 bool found = false;
192
193 cpuid = get_supported_cpuid(s);
194
195 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
196 if (entry) {
197 found = true;
198 ret = cpuid_entry_get_reg(entry, reg);
199 }
200
201 /* Fixups for the data returned by KVM, below */
202
203 if (function == 1 && reg == R_EDX) {
204 /* KVM before 2.6.30 misreports the following features */
205 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
206 } else if (function == 1 && reg == R_ECX) {
207 /* We can set the hypervisor flag, even if KVM does not return it on
208 * GET_SUPPORTED_CPUID
209 */
210 ret |= CPUID_EXT_HYPERVISOR;
211 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
212 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
213 * and the irqchip is in the kernel.
214 */
215 if (kvm_irqchip_in_kernel() &&
216 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
217 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
218 }
219
220 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
221 * without the in-kernel irqchip
222 */
223 if (!kvm_irqchip_in_kernel()) {
224 ret &= ~CPUID_EXT_X2APIC;
225 }
226 } else if (function == 0x80000001 && reg == R_EDX) {
227 /* On Intel, kvm returns cpuid according to the Intel spec,
228 * so add missing bits according to the AMD spec:
229 */
230 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
231 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
232 }
233
234 g_free(cpuid);
235
236 /* fallback for older kernels */
237 if ((function == KVM_CPUID_FEATURES) && !found) {
238 ret = get_para_features(s);
239 }
240
241 return ret;
242 }
243
244 typedef struct HWPoisonPage {
245 ram_addr_t ram_addr;
246 QLIST_ENTRY(HWPoisonPage) list;
247 } HWPoisonPage;
248
249 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
250 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
251
252 static void kvm_unpoison_all(void *param)
253 {
254 HWPoisonPage *page, *next_page;
255
256 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
257 QLIST_REMOVE(page, list);
258 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
259 g_free(page);
260 }
261 }
262
263 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
264 {
265 HWPoisonPage *page;
266
267 QLIST_FOREACH(page, &hwpoison_page_list, list) {
268 if (page->ram_addr == ram_addr) {
269 return;
270 }
271 }
272 page = g_malloc(sizeof(HWPoisonPage));
273 page->ram_addr = ram_addr;
274 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
275 }
276
277 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
278 int *max_banks)
279 {
280 int r;
281
282 r = kvm_check_extension(s, KVM_CAP_MCE);
283 if (r > 0) {
284 *max_banks = r;
285 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
286 }
287 return -ENOSYS;
288 }
289
290 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
291 {
292 CPUX86State *env = &cpu->env;
293 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
294 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
295 uint64_t mcg_status = MCG_STATUS_MCIP;
296
297 if (code == BUS_MCEERR_AR) {
298 status |= MCI_STATUS_AR | 0x134;
299 mcg_status |= MCG_STATUS_EIPV;
300 } else {
301 status |= 0xc0;
302 mcg_status |= MCG_STATUS_RIPV;
303 }
304 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
305 (MCM_ADDR_PHYS << 6) | 0xc,
306 cpu_x86_support_mca_broadcast(env) ?
307 MCE_INJECT_BROADCAST : 0);
308 }
309
310 static void hardware_memory_error(void)
311 {
312 fprintf(stderr, "Hardware memory error!\n");
313 exit(1);
314 }
315
316 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
317 {
318 X86CPU *cpu = X86_CPU(c);
319 CPUX86State *env = &cpu->env;
320 ram_addr_t ram_addr;
321 hwaddr paddr;
322
323 if ((env->mcg_cap & MCG_SER_P) && addr
324 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
325 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
326 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
327 fprintf(stderr, "Hardware memory error for memory used by "
328 "QEMU itself instead of guest system!\n");
329 /* Hope we are lucky for AO MCE */
330 if (code == BUS_MCEERR_AO) {
331 return 0;
332 } else {
333 hardware_memory_error();
334 }
335 }
336 kvm_hwpoison_page_add(ram_addr);
337 kvm_mce_inject(cpu, paddr, code);
338 } else {
339 if (code == BUS_MCEERR_AO) {
340 return 0;
341 } else if (code == BUS_MCEERR_AR) {
342 hardware_memory_error();
343 } else {
344 return 1;
345 }
346 }
347 return 0;
348 }
349
350 int kvm_arch_on_sigbus(int code, void *addr)
351 {
352 X86CPU *cpu = X86_CPU(first_cpu);
353
354 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
355 ram_addr_t ram_addr;
356 hwaddr paddr;
357
358 /* Hope we are lucky for AO MCE */
359 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
360 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
361 addr, &paddr)) {
362 fprintf(stderr, "Hardware memory error for memory used by "
363 "QEMU itself instead of guest system!: %p\n", addr);
364 return 0;
365 }
366 kvm_hwpoison_page_add(ram_addr);
367 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
368 } else {
369 if (code == BUS_MCEERR_AO) {
370 return 0;
371 } else if (code == BUS_MCEERR_AR) {
372 hardware_memory_error();
373 } else {
374 return 1;
375 }
376 }
377 return 0;
378 }
379
380 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
381 {
382 CPUX86State *env = &cpu->env;
383
384 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
385 unsigned int bank, bank_num = env->mcg_cap & 0xff;
386 struct kvm_x86_mce mce;
387
388 env->exception_injected = -1;
389
390 /*
391 * There must be at least one bank in use if an MCE is pending.
392 * Find it and use its values for the event injection.
393 */
394 for (bank = 0; bank < bank_num; bank++) {
395 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
396 break;
397 }
398 }
399 assert(bank < bank_num);
400
401 mce.bank = bank;
402 mce.status = env->mce_banks[bank * 4 + 1];
403 mce.mcg_status = env->mcg_status;
404 mce.addr = env->mce_banks[bank * 4 + 2];
405 mce.misc = env->mce_banks[bank * 4 + 3];
406
407 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
408 }
409 return 0;
410 }
411
412 static void cpu_update_state(void *opaque, int running, RunState state)
413 {
414 CPUX86State *env = opaque;
415
416 if (running) {
417 env->tsc_valid = false;
418 }
419 }
420
421 unsigned long kvm_arch_vcpu_id(CPUState *cs)
422 {
423 X86CPU *cpu = X86_CPU(cs);
424 return cpu->env.cpuid_apic_id;
425 }
426
427 #ifndef KVM_CPUID_SIGNATURE_NEXT
428 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
429 #endif
430
431 static bool hyperv_hypercall_available(X86CPU *cpu)
432 {
433 return cpu->hyperv_vapic ||
434 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
435 }
436
437 static bool hyperv_enabled(X86CPU *cpu)
438 {
439 return hyperv_hypercall_available(cpu) ||
440 cpu->hyperv_relaxed_timing;
441 }
442
443 #define KVM_MAX_CPUID_ENTRIES 100
444
445 int kvm_arch_init_vcpu(CPUState *cs)
446 {
447 struct {
448 struct kvm_cpuid2 cpuid;
449 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
450 } QEMU_PACKED cpuid_data;
451 X86CPU *cpu = X86_CPU(cs);
452 CPUX86State *env = &cpu->env;
453 uint32_t limit, i, j, cpuid_i;
454 uint32_t unused;
455 struct kvm_cpuid_entry2 *c;
456 uint32_t signature[3];
457 int r;
458
459 memset(&cpuid_data, 0, sizeof(cpuid_data));
460
461 cpuid_i = 0;
462
463 /* Paravirtualization CPUIDs */
464 c = &cpuid_data.entries[cpuid_i++];
465 c->function = KVM_CPUID_SIGNATURE;
466 if (!hyperv_enabled(cpu)) {
467 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
468 c->eax = 0;
469 } else {
470 memcpy(signature, "Microsoft Hv", 12);
471 c->eax = HYPERV_CPUID_MIN;
472 }
473 c->ebx = signature[0];
474 c->ecx = signature[1];
475 c->edx = signature[2];
476
477 c = &cpuid_data.entries[cpuid_i++];
478 c->function = KVM_CPUID_FEATURES;
479 c->eax = env->features[FEAT_KVM];
480
481 if (hyperv_enabled(cpu)) {
482 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
483 c->eax = signature[0];
484
485 c = &cpuid_data.entries[cpuid_i++];
486 c->function = HYPERV_CPUID_VERSION;
487 c->eax = 0x00001bbc;
488 c->ebx = 0x00060001;
489
490 c = &cpuid_data.entries[cpuid_i++];
491 c->function = HYPERV_CPUID_FEATURES;
492 if (cpu->hyperv_relaxed_timing) {
493 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
494 }
495 if (cpu->hyperv_vapic) {
496 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
497 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
498 }
499
500 c = &cpuid_data.entries[cpuid_i++];
501 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
502 if (cpu->hyperv_relaxed_timing) {
503 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
504 }
505 if (cpu->hyperv_vapic) {
506 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
507 }
508 c->ebx = cpu->hyperv_spinlock_attempts;
509
510 c = &cpuid_data.entries[cpuid_i++];
511 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
512 c->eax = 0x40;
513 c->ebx = 0x40;
514
515 c = &cpuid_data.entries[cpuid_i++];
516 c->function = KVM_CPUID_SIGNATURE_NEXT;
517 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
518 c->eax = 0;
519 c->ebx = signature[0];
520 c->ecx = signature[1];
521 c->edx = signature[2];
522 }
523
524 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
525
526 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
527
528 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
529
530 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
531
532 for (i = 0; i <= limit; i++) {
533 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
534 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
535 abort();
536 }
537 c = &cpuid_data.entries[cpuid_i++];
538
539 switch (i) {
540 case 2: {
541 /* Keep reading function 2 till all the input is received */
542 int times;
543
544 c->function = i;
545 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
546 KVM_CPUID_FLAG_STATE_READ_NEXT;
547 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
548 times = c->eax & 0xff;
549
550 for (j = 1; j < times; ++j) {
551 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
552 fprintf(stderr, "cpuid_data is full, no space for "
553 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
554 abort();
555 }
556 c = &cpuid_data.entries[cpuid_i++];
557 c->function = i;
558 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
559 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
560 }
561 break;
562 }
563 case 4:
564 case 0xb:
565 case 0xd:
566 for (j = 0; ; j++) {
567 if (i == 0xd && j == 64) {
568 break;
569 }
570 c->function = i;
571 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
572 c->index = j;
573 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
574
575 if (i == 4 && c->eax == 0) {
576 break;
577 }
578 if (i == 0xb && !(c->ecx & 0xff00)) {
579 break;
580 }
581 if (i == 0xd && c->eax == 0) {
582 continue;
583 }
584 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
585 fprintf(stderr, "cpuid_data is full, no space for "
586 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
587 abort();
588 }
589 c = &cpuid_data.entries[cpuid_i++];
590 }
591 break;
592 default:
593 c->function = i;
594 c->flags = 0;
595 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
596 break;
597 }
598 }
599
600 if (limit >= 0x0a) {
601 uint32_t ver;
602
603 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
604 if ((ver & 0xff) > 0) {
605 has_msr_architectural_pmu = true;
606 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
607
608 /* Shouldn't be more than 32, since that's the number of bits
609 * available in EBX to tell us _which_ counters are available.
610 * Play it safe.
611 */
612 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
613 num_architectural_pmu_counters = MAX_GP_COUNTERS;
614 }
615 }
616 }
617
618 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
619
620 for (i = 0x80000000; i <= limit; i++) {
621 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
622 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
623 abort();
624 }
625 c = &cpuid_data.entries[cpuid_i++];
626
627 c->function = i;
628 c->flags = 0;
629 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
630 }
631
632 /* Call Centaur's CPUID instructions they are supported. */
633 if (env->cpuid_xlevel2 > 0) {
634 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
635
636 for (i = 0xC0000000; i <= limit; i++) {
637 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
638 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
639 abort();
640 }
641 c = &cpuid_data.entries[cpuid_i++];
642
643 c->function = i;
644 c->flags = 0;
645 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
646 }
647 }
648
649 cpuid_data.cpuid.nent = cpuid_i;
650
651 if (((env->cpuid_version >> 8)&0xF) >= 6
652 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
653 (CPUID_MCE | CPUID_MCA)
654 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
655 uint64_t mcg_cap;
656 int banks;
657 int ret;
658
659 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
660 if (ret < 0) {
661 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
662 return ret;
663 }
664
665 if (banks > MCE_BANKS_DEF) {
666 banks = MCE_BANKS_DEF;
667 }
668 mcg_cap &= MCE_CAP_DEF;
669 mcg_cap |= banks;
670 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
671 if (ret < 0) {
672 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
673 return ret;
674 }
675
676 env->mcg_cap = mcg_cap;
677 }
678
679 qemu_add_vm_change_state_handler(cpu_update_state, env);
680
681 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
682 if (c) {
683 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
684 !!(c->ecx & CPUID_EXT_SMX);
685 }
686
687 cpuid_data.cpuid.padding = 0;
688 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
689 if (r) {
690 return r;
691 }
692
693 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
694 if (r && env->tsc_khz) {
695 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
696 if (r < 0) {
697 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
698 return r;
699 }
700 }
701
702 if (kvm_has_xsave()) {
703 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
704 }
705
706 return 0;
707 }
708
709 void kvm_arch_reset_vcpu(CPUState *cs)
710 {
711 X86CPU *cpu = X86_CPU(cs);
712 CPUX86State *env = &cpu->env;
713
714 env->exception_injected = -1;
715 env->interrupt_injected = -1;
716 env->xcr0 = 1;
717 if (kvm_irqchip_in_kernel()) {
718 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
719 KVM_MP_STATE_UNINITIALIZED;
720 } else {
721 env->mp_state = KVM_MP_STATE_RUNNABLE;
722 }
723 }
724
725 static int kvm_get_supported_msrs(KVMState *s)
726 {
727 static int kvm_supported_msrs;
728 int ret = 0;
729
730 /* first time */
731 if (kvm_supported_msrs == 0) {
732 struct kvm_msr_list msr_list, *kvm_msr_list;
733
734 kvm_supported_msrs = -1;
735
736 /* Obtain MSR list from KVM. These are the MSRs that we must
737 * save/restore */
738 msr_list.nmsrs = 0;
739 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
740 if (ret < 0 && ret != -E2BIG) {
741 return ret;
742 }
743 /* Old kernel modules had a bug and could write beyond the provided
744 memory. Allocate at least a safe amount of 1K. */
745 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
746 msr_list.nmsrs *
747 sizeof(msr_list.indices[0])));
748
749 kvm_msr_list->nmsrs = msr_list.nmsrs;
750 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
751 if (ret >= 0) {
752 int i;
753
754 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
755 if (kvm_msr_list->indices[i] == MSR_STAR) {
756 has_msr_star = true;
757 continue;
758 }
759 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
760 has_msr_hsave_pa = true;
761 continue;
762 }
763 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
764 has_msr_tsc_adjust = true;
765 continue;
766 }
767 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
768 has_msr_tsc_deadline = true;
769 continue;
770 }
771 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
772 has_msr_misc_enable = true;
773 continue;
774 }
775 }
776 }
777
778 g_free(kvm_msr_list);
779 }
780
781 return ret;
782 }
783
784 int kvm_arch_init(KVMState *s)
785 {
786 uint64_t identity_base = 0xfffbc000;
787 uint64_t shadow_mem;
788 int ret;
789 struct utsname utsname;
790
791 ret = kvm_get_supported_msrs(s);
792 if (ret < 0) {
793 return ret;
794 }
795
796 uname(&utsname);
797 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
798
799 /*
800 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
801 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
802 * Since these must be part of guest physical memory, we need to allocate
803 * them, both by setting their start addresses in the kernel and by
804 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
805 *
806 * Older KVM versions may not support setting the identity map base. In
807 * that case we need to stick with the default, i.e. a 256K maximum BIOS
808 * size.
809 */
810 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
811 /* Allows up to 16M BIOSes. */
812 identity_base = 0xfeffc000;
813
814 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
815 if (ret < 0) {
816 return ret;
817 }
818 }
819
820 /* Set TSS base one page after EPT identity map. */
821 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
822 if (ret < 0) {
823 return ret;
824 }
825
826 /* Tell fw_cfg to notify the BIOS to reserve the range. */
827 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
828 if (ret < 0) {
829 fprintf(stderr, "e820_add_entry() table is full\n");
830 return ret;
831 }
832 qemu_register_reset(kvm_unpoison_all, NULL);
833
834 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
835 "kvm_shadow_mem", -1);
836 if (shadow_mem != -1) {
837 shadow_mem /= 4096;
838 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
839 if (ret < 0) {
840 return ret;
841 }
842 }
843 return 0;
844 }
845
846 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
847 {
848 lhs->selector = rhs->selector;
849 lhs->base = rhs->base;
850 lhs->limit = rhs->limit;
851 lhs->type = 3;
852 lhs->present = 1;
853 lhs->dpl = 3;
854 lhs->db = 0;
855 lhs->s = 1;
856 lhs->l = 0;
857 lhs->g = 0;
858 lhs->avl = 0;
859 lhs->unusable = 0;
860 }
861
862 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
863 {
864 unsigned flags = rhs->flags;
865 lhs->selector = rhs->selector;
866 lhs->base = rhs->base;
867 lhs->limit = rhs->limit;
868 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
869 lhs->present = (flags & DESC_P_MASK) != 0;
870 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
871 lhs->db = (flags >> DESC_B_SHIFT) & 1;
872 lhs->s = (flags & DESC_S_MASK) != 0;
873 lhs->l = (flags >> DESC_L_SHIFT) & 1;
874 lhs->g = (flags & DESC_G_MASK) != 0;
875 lhs->avl = (flags & DESC_AVL_MASK) != 0;
876 lhs->unusable = 0;
877 lhs->padding = 0;
878 }
879
880 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
881 {
882 lhs->selector = rhs->selector;
883 lhs->base = rhs->base;
884 lhs->limit = rhs->limit;
885 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
886 (rhs->present * DESC_P_MASK) |
887 (rhs->dpl << DESC_DPL_SHIFT) |
888 (rhs->db << DESC_B_SHIFT) |
889 (rhs->s * DESC_S_MASK) |
890 (rhs->l << DESC_L_SHIFT) |
891 (rhs->g * DESC_G_MASK) |
892 (rhs->avl * DESC_AVL_MASK);
893 }
894
895 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
896 {
897 if (set) {
898 *kvm_reg = *qemu_reg;
899 } else {
900 *qemu_reg = *kvm_reg;
901 }
902 }
903
904 static int kvm_getput_regs(X86CPU *cpu, int set)
905 {
906 CPUX86State *env = &cpu->env;
907 struct kvm_regs regs;
908 int ret = 0;
909
910 if (!set) {
911 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
912 if (ret < 0) {
913 return ret;
914 }
915 }
916
917 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
918 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
919 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
920 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
921 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
922 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
923 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
924 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
925 #ifdef TARGET_X86_64
926 kvm_getput_reg(&regs.r8, &env->regs[8], set);
927 kvm_getput_reg(&regs.r9, &env->regs[9], set);
928 kvm_getput_reg(&regs.r10, &env->regs[10], set);
929 kvm_getput_reg(&regs.r11, &env->regs[11], set);
930 kvm_getput_reg(&regs.r12, &env->regs[12], set);
931 kvm_getput_reg(&regs.r13, &env->regs[13], set);
932 kvm_getput_reg(&regs.r14, &env->regs[14], set);
933 kvm_getput_reg(&regs.r15, &env->regs[15], set);
934 #endif
935
936 kvm_getput_reg(&regs.rflags, &env->eflags, set);
937 kvm_getput_reg(&regs.rip, &env->eip, set);
938
939 if (set) {
940 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
941 }
942
943 return ret;
944 }
945
946 static int kvm_put_fpu(X86CPU *cpu)
947 {
948 CPUX86State *env = &cpu->env;
949 struct kvm_fpu fpu;
950 int i;
951
952 memset(&fpu, 0, sizeof fpu);
953 fpu.fsw = env->fpus & ~(7 << 11);
954 fpu.fsw |= (env->fpstt & 7) << 11;
955 fpu.fcw = env->fpuc;
956 fpu.last_opcode = env->fpop;
957 fpu.last_ip = env->fpip;
958 fpu.last_dp = env->fpdp;
959 for (i = 0; i < 8; ++i) {
960 fpu.ftwx |= (!env->fptags[i]) << i;
961 }
962 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
963 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
964 fpu.mxcsr = env->mxcsr;
965
966 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
967 }
968
969 #define XSAVE_FCW_FSW 0
970 #define XSAVE_FTW_FOP 1
971 #define XSAVE_CWD_RIP 2
972 #define XSAVE_CWD_RDP 4
973 #define XSAVE_MXCSR 6
974 #define XSAVE_ST_SPACE 8
975 #define XSAVE_XMM_SPACE 40
976 #define XSAVE_XSTATE_BV 128
977 #define XSAVE_YMMH_SPACE 144
978
979 static int kvm_put_xsave(X86CPU *cpu)
980 {
981 CPUX86State *env = &cpu->env;
982 struct kvm_xsave* xsave = env->kvm_xsave_buf;
983 uint16_t cwd, swd, twd;
984 int i, r;
985
986 if (!kvm_has_xsave()) {
987 return kvm_put_fpu(cpu);
988 }
989
990 memset(xsave, 0, sizeof(struct kvm_xsave));
991 twd = 0;
992 swd = env->fpus & ~(7 << 11);
993 swd |= (env->fpstt & 7) << 11;
994 cwd = env->fpuc;
995 for (i = 0; i < 8; ++i) {
996 twd |= (!env->fptags[i]) << i;
997 }
998 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
999 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1000 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1001 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1002 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1003 sizeof env->fpregs);
1004 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1005 sizeof env->xmm_regs);
1006 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1007 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1008 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1009 sizeof env->ymmh_regs);
1010 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1011 return r;
1012 }
1013
1014 static int kvm_put_xcrs(X86CPU *cpu)
1015 {
1016 CPUX86State *env = &cpu->env;
1017 struct kvm_xcrs xcrs;
1018
1019 if (!kvm_has_xcrs()) {
1020 return 0;
1021 }
1022
1023 xcrs.nr_xcrs = 1;
1024 xcrs.flags = 0;
1025 xcrs.xcrs[0].xcr = 0;
1026 xcrs.xcrs[0].value = env->xcr0;
1027 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1028 }
1029
1030 static int kvm_put_sregs(X86CPU *cpu)
1031 {
1032 CPUX86State *env = &cpu->env;
1033 struct kvm_sregs sregs;
1034
1035 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1036 if (env->interrupt_injected >= 0) {
1037 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1038 (uint64_t)1 << (env->interrupt_injected % 64);
1039 }
1040
1041 if ((env->eflags & VM_MASK)) {
1042 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1043 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1044 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1045 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1046 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1047 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1048 } else {
1049 set_seg(&sregs.cs, &env->segs[R_CS]);
1050 set_seg(&sregs.ds, &env->segs[R_DS]);
1051 set_seg(&sregs.es, &env->segs[R_ES]);
1052 set_seg(&sregs.fs, &env->segs[R_FS]);
1053 set_seg(&sregs.gs, &env->segs[R_GS]);
1054 set_seg(&sregs.ss, &env->segs[R_SS]);
1055 }
1056
1057 set_seg(&sregs.tr, &env->tr);
1058 set_seg(&sregs.ldt, &env->ldt);
1059
1060 sregs.idt.limit = env->idt.limit;
1061 sregs.idt.base = env->idt.base;
1062 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1063 sregs.gdt.limit = env->gdt.limit;
1064 sregs.gdt.base = env->gdt.base;
1065 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1066
1067 sregs.cr0 = env->cr[0];
1068 sregs.cr2 = env->cr[2];
1069 sregs.cr3 = env->cr[3];
1070 sregs.cr4 = env->cr[4];
1071
1072 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1073 sregs.apic_base = cpu_get_apic_base(env->apic_state);
1074
1075 sregs.efer = env->efer;
1076
1077 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1078 }
1079
1080 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1081 uint32_t index, uint64_t value)
1082 {
1083 entry->index = index;
1084 entry->data = value;
1085 }
1086
1087 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1088 {
1089 CPUX86State *env = &cpu->env;
1090 struct {
1091 struct kvm_msrs info;
1092 struct kvm_msr_entry entries[1];
1093 } msr_data;
1094 struct kvm_msr_entry *msrs = msr_data.entries;
1095
1096 if (!has_msr_tsc_deadline) {
1097 return 0;
1098 }
1099
1100 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1101
1102 msr_data.info.nmsrs = 1;
1103
1104 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1105 }
1106
1107 static int kvm_put_msrs(X86CPU *cpu, int level)
1108 {
1109 CPUX86State *env = &cpu->env;
1110 struct {
1111 struct kvm_msrs info;
1112 struct kvm_msr_entry entries[100];
1113 } msr_data;
1114 struct kvm_msr_entry *msrs = msr_data.entries;
1115 int n = 0, i;
1116
1117 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1118 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1119 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1120 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1121 if (has_msr_star) {
1122 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1123 }
1124 if (has_msr_hsave_pa) {
1125 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1126 }
1127 if (has_msr_tsc_adjust) {
1128 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1129 }
1130 if (has_msr_misc_enable) {
1131 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1132 env->msr_ia32_misc_enable);
1133 }
1134 #ifdef TARGET_X86_64
1135 if (lm_capable_kernel) {
1136 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1137 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1138 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1139 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1140 }
1141 #endif
1142 if (level == KVM_PUT_FULL_STATE) {
1143 /*
1144 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1145 * writeback. Until this is fixed, we only write the offset to SMP
1146 * guests after migration, desynchronizing the VCPUs, but avoiding
1147 * huge jump-backs that would occur without any writeback at all.
1148 */
1149 if (smp_cpus == 1 || env->tsc != 0) {
1150 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1151 }
1152 }
1153 /*
1154 * The following MSRs have side effects on the guest or are too heavy
1155 * for normal writeback. Limit them to reset or full state updates.
1156 */
1157 if (level >= KVM_PUT_RESET_STATE) {
1158 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1159 env->system_time_msr);
1160 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1161 if (has_msr_async_pf_en) {
1162 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1163 env->async_pf_en_msr);
1164 }
1165 if (has_msr_pv_eoi_en) {
1166 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1167 env->pv_eoi_en_msr);
1168 }
1169 if (has_msr_kvm_steal_time) {
1170 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1171 env->steal_time_msr);
1172 }
1173 if (has_msr_architectural_pmu) {
1174 /* Stop the counter. */
1175 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1176 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1177
1178 /* Set the counter values. */
1179 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1180 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1181 env->msr_fixed_counters[i]);
1182 }
1183 for (i = 0; i < num_architectural_pmu_counters; i++) {
1184 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1185 env->msr_gp_counters[i]);
1186 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1187 env->msr_gp_evtsel[i]);
1188 }
1189 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1190 env->msr_global_status);
1191 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1192 env->msr_global_ovf_ctrl);
1193
1194 /* Now start the PMU. */
1195 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1196 env->msr_fixed_ctr_ctrl);
1197 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1198 env->msr_global_ctrl);
1199 }
1200 if (hyperv_hypercall_available(cpu)) {
1201 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1202 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1203 }
1204 if (cpu->hyperv_vapic) {
1205 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1206 }
1207 if (has_msr_feature_control) {
1208 kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL,
1209 env->msr_ia32_feature_control);
1210 }
1211 }
1212 if (env->mcg_cap) {
1213 int i;
1214
1215 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1216 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1217 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1218 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1219 }
1220 }
1221
1222 msr_data.info.nmsrs = n;
1223
1224 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1225
1226 }
1227
1228
1229 static int kvm_get_fpu(X86CPU *cpu)
1230 {
1231 CPUX86State *env = &cpu->env;
1232 struct kvm_fpu fpu;
1233 int i, ret;
1234
1235 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1236 if (ret < 0) {
1237 return ret;
1238 }
1239
1240 env->fpstt = (fpu.fsw >> 11) & 7;
1241 env->fpus = fpu.fsw;
1242 env->fpuc = fpu.fcw;
1243 env->fpop = fpu.last_opcode;
1244 env->fpip = fpu.last_ip;
1245 env->fpdp = fpu.last_dp;
1246 for (i = 0; i < 8; ++i) {
1247 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1248 }
1249 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1250 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1251 env->mxcsr = fpu.mxcsr;
1252
1253 return 0;
1254 }
1255
1256 static int kvm_get_xsave(X86CPU *cpu)
1257 {
1258 CPUX86State *env = &cpu->env;
1259 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1260 int ret, i;
1261 uint16_t cwd, swd, twd;
1262
1263 if (!kvm_has_xsave()) {
1264 return kvm_get_fpu(cpu);
1265 }
1266
1267 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1268 if (ret < 0) {
1269 return ret;
1270 }
1271
1272 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1273 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1274 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1275 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1276 env->fpstt = (swd >> 11) & 7;
1277 env->fpus = swd;
1278 env->fpuc = cwd;
1279 for (i = 0; i < 8; ++i) {
1280 env->fptags[i] = !((twd >> i) & 1);
1281 }
1282 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1283 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1284 env->mxcsr = xsave->region[XSAVE_MXCSR];
1285 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1286 sizeof env->fpregs);
1287 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1288 sizeof env->xmm_regs);
1289 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1290 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1291 sizeof env->ymmh_regs);
1292 return 0;
1293 }
1294
1295 static int kvm_get_xcrs(X86CPU *cpu)
1296 {
1297 CPUX86State *env = &cpu->env;
1298 int i, ret;
1299 struct kvm_xcrs xcrs;
1300
1301 if (!kvm_has_xcrs()) {
1302 return 0;
1303 }
1304
1305 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1306 if (ret < 0) {
1307 return ret;
1308 }
1309
1310 for (i = 0; i < xcrs.nr_xcrs; i++) {
1311 /* Only support xcr0 now */
1312 if (xcrs.xcrs[i].xcr == 0) {
1313 env->xcr0 = xcrs.xcrs[i].value;
1314 break;
1315 }
1316 }
1317 return 0;
1318 }
1319
1320 static int kvm_get_sregs(X86CPU *cpu)
1321 {
1322 CPUX86State *env = &cpu->env;
1323 struct kvm_sregs sregs;
1324 uint32_t hflags;
1325 int bit, i, ret;
1326
1327 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1328 if (ret < 0) {
1329 return ret;
1330 }
1331
1332 /* There can only be one pending IRQ set in the bitmap at a time, so try
1333 to find it and save its number instead (-1 for none). */
1334 env->interrupt_injected = -1;
1335 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1336 if (sregs.interrupt_bitmap[i]) {
1337 bit = ctz64(sregs.interrupt_bitmap[i]);
1338 env->interrupt_injected = i * 64 + bit;
1339 break;
1340 }
1341 }
1342
1343 get_seg(&env->segs[R_CS], &sregs.cs);
1344 get_seg(&env->segs[R_DS], &sregs.ds);
1345 get_seg(&env->segs[R_ES], &sregs.es);
1346 get_seg(&env->segs[R_FS], &sregs.fs);
1347 get_seg(&env->segs[R_GS], &sregs.gs);
1348 get_seg(&env->segs[R_SS], &sregs.ss);
1349
1350 get_seg(&env->tr, &sregs.tr);
1351 get_seg(&env->ldt, &sregs.ldt);
1352
1353 env->idt.limit = sregs.idt.limit;
1354 env->idt.base = sregs.idt.base;
1355 env->gdt.limit = sregs.gdt.limit;
1356 env->gdt.base = sregs.gdt.base;
1357
1358 env->cr[0] = sregs.cr0;
1359 env->cr[2] = sregs.cr2;
1360 env->cr[3] = sregs.cr3;
1361 env->cr[4] = sregs.cr4;
1362
1363 env->efer = sregs.efer;
1364
1365 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1366
1367 #define HFLAG_COPY_MASK \
1368 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1369 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1370 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1371 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1372
1373 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1374 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1375 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1376 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1377 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1378 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1379 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1380
1381 if (env->efer & MSR_EFER_LMA) {
1382 hflags |= HF_LMA_MASK;
1383 }
1384
1385 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1386 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1387 } else {
1388 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1389 (DESC_B_SHIFT - HF_CS32_SHIFT);
1390 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1391 (DESC_B_SHIFT - HF_SS32_SHIFT);
1392 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1393 !(hflags & HF_CS32_MASK)) {
1394 hflags |= HF_ADDSEG_MASK;
1395 } else {
1396 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1397 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1398 }
1399 }
1400 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1401
1402 return 0;
1403 }
1404
1405 static int kvm_get_msrs(X86CPU *cpu)
1406 {
1407 CPUX86State *env = &cpu->env;
1408 struct {
1409 struct kvm_msrs info;
1410 struct kvm_msr_entry entries[100];
1411 } msr_data;
1412 struct kvm_msr_entry *msrs = msr_data.entries;
1413 int ret, i, n;
1414
1415 n = 0;
1416 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1417 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1418 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1419 msrs[n++].index = MSR_PAT;
1420 if (has_msr_star) {
1421 msrs[n++].index = MSR_STAR;
1422 }
1423 if (has_msr_hsave_pa) {
1424 msrs[n++].index = MSR_VM_HSAVE_PA;
1425 }
1426 if (has_msr_tsc_adjust) {
1427 msrs[n++].index = MSR_TSC_ADJUST;
1428 }
1429 if (has_msr_tsc_deadline) {
1430 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1431 }
1432 if (has_msr_misc_enable) {
1433 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1434 }
1435 if (has_msr_feature_control) {
1436 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1437 }
1438
1439 if (!env->tsc_valid) {
1440 msrs[n++].index = MSR_IA32_TSC;
1441 env->tsc_valid = !runstate_is_running();
1442 }
1443
1444 #ifdef TARGET_X86_64
1445 if (lm_capable_kernel) {
1446 msrs[n++].index = MSR_CSTAR;
1447 msrs[n++].index = MSR_KERNELGSBASE;
1448 msrs[n++].index = MSR_FMASK;
1449 msrs[n++].index = MSR_LSTAR;
1450 }
1451 #endif
1452 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1453 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1454 if (has_msr_async_pf_en) {
1455 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1456 }
1457 if (has_msr_pv_eoi_en) {
1458 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1459 }
1460 if (has_msr_kvm_steal_time) {
1461 msrs[n++].index = MSR_KVM_STEAL_TIME;
1462 }
1463 if (has_msr_architectural_pmu) {
1464 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1465 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1466 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1467 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1468 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1469 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1470 }
1471 for (i = 0; i < num_architectural_pmu_counters; i++) {
1472 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1473 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1474 }
1475 }
1476
1477 if (env->mcg_cap) {
1478 msrs[n++].index = MSR_MCG_STATUS;
1479 msrs[n++].index = MSR_MCG_CTL;
1480 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1481 msrs[n++].index = MSR_MC0_CTL + i;
1482 }
1483 }
1484
1485 msr_data.info.nmsrs = n;
1486 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1487 if (ret < 0) {
1488 return ret;
1489 }
1490
1491 for (i = 0; i < ret; i++) {
1492 uint32_t index = msrs[i].index;
1493 switch (index) {
1494 case MSR_IA32_SYSENTER_CS:
1495 env->sysenter_cs = msrs[i].data;
1496 break;
1497 case MSR_IA32_SYSENTER_ESP:
1498 env->sysenter_esp = msrs[i].data;
1499 break;
1500 case MSR_IA32_SYSENTER_EIP:
1501 env->sysenter_eip = msrs[i].data;
1502 break;
1503 case MSR_PAT:
1504 env->pat = msrs[i].data;
1505 break;
1506 case MSR_STAR:
1507 env->star = msrs[i].data;
1508 break;
1509 #ifdef TARGET_X86_64
1510 case MSR_CSTAR:
1511 env->cstar = msrs[i].data;
1512 break;
1513 case MSR_KERNELGSBASE:
1514 env->kernelgsbase = msrs[i].data;
1515 break;
1516 case MSR_FMASK:
1517 env->fmask = msrs[i].data;
1518 break;
1519 case MSR_LSTAR:
1520 env->lstar = msrs[i].data;
1521 break;
1522 #endif
1523 case MSR_IA32_TSC:
1524 env->tsc = msrs[i].data;
1525 break;
1526 case MSR_TSC_ADJUST:
1527 env->tsc_adjust = msrs[i].data;
1528 break;
1529 case MSR_IA32_TSCDEADLINE:
1530 env->tsc_deadline = msrs[i].data;
1531 break;
1532 case MSR_VM_HSAVE_PA:
1533 env->vm_hsave = msrs[i].data;
1534 break;
1535 case MSR_KVM_SYSTEM_TIME:
1536 env->system_time_msr = msrs[i].data;
1537 break;
1538 case MSR_KVM_WALL_CLOCK:
1539 env->wall_clock_msr = msrs[i].data;
1540 break;
1541 case MSR_MCG_STATUS:
1542 env->mcg_status = msrs[i].data;
1543 break;
1544 case MSR_MCG_CTL:
1545 env->mcg_ctl = msrs[i].data;
1546 break;
1547 case MSR_IA32_MISC_ENABLE:
1548 env->msr_ia32_misc_enable = msrs[i].data;
1549 break;
1550 case MSR_IA32_FEATURE_CONTROL:
1551 env->msr_ia32_feature_control = msrs[i].data;
1552 break;
1553 default:
1554 if (msrs[i].index >= MSR_MC0_CTL &&
1555 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1556 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1557 }
1558 break;
1559 case MSR_KVM_ASYNC_PF_EN:
1560 env->async_pf_en_msr = msrs[i].data;
1561 break;
1562 case MSR_KVM_PV_EOI_EN:
1563 env->pv_eoi_en_msr = msrs[i].data;
1564 break;
1565 case MSR_KVM_STEAL_TIME:
1566 env->steal_time_msr = msrs[i].data;
1567 break;
1568 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1569 env->msr_fixed_ctr_ctrl = msrs[i].data;
1570 break;
1571 case MSR_CORE_PERF_GLOBAL_CTRL:
1572 env->msr_global_ctrl = msrs[i].data;
1573 break;
1574 case MSR_CORE_PERF_GLOBAL_STATUS:
1575 env->msr_global_status = msrs[i].data;
1576 break;
1577 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1578 env->msr_global_ovf_ctrl = msrs[i].data;
1579 break;
1580 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1581 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1582 break;
1583 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1584 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1585 break;
1586 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1587 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1588 break;
1589 }
1590 }
1591
1592 return 0;
1593 }
1594
1595 static int kvm_put_mp_state(X86CPU *cpu)
1596 {
1597 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1598
1599 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1600 }
1601
1602 static int kvm_get_mp_state(X86CPU *cpu)
1603 {
1604 CPUState *cs = CPU(cpu);
1605 CPUX86State *env = &cpu->env;
1606 struct kvm_mp_state mp_state;
1607 int ret;
1608
1609 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1610 if (ret < 0) {
1611 return ret;
1612 }
1613 env->mp_state = mp_state.mp_state;
1614 if (kvm_irqchip_in_kernel()) {
1615 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1616 }
1617 return 0;
1618 }
1619
1620 static int kvm_get_apic(X86CPU *cpu)
1621 {
1622 CPUX86State *env = &cpu->env;
1623 DeviceState *apic = env->apic_state;
1624 struct kvm_lapic_state kapic;
1625 int ret;
1626
1627 if (apic && kvm_irqchip_in_kernel()) {
1628 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1629 if (ret < 0) {
1630 return ret;
1631 }
1632
1633 kvm_get_apic_state(apic, &kapic);
1634 }
1635 return 0;
1636 }
1637
1638 static int kvm_put_apic(X86CPU *cpu)
1639 {
1640 CPUX86State *env = &cpu->env;
1641 DeviceState *apic = env->apic_state;
1642 struct kvm_lapic_state kapic;
1643
1644 if (apic && kvm_irqchip_in_kernel()) {
1645 kvm_put_apic_state(apic, &kapic);
1646
1647 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1648 }
1649 return 0;
1650 }
1651
1652 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1653 {
1654 CPUX86State *env = &cpu->env;
1655 struct kvm_vcpu_events events;
1656
1657 if (!kvm_has_vcpu_events()) {
1658 return 0;
1659 }
1660
1661 events.exception.injected = (env->exception_injected >= 0);
1662 events.exception.nr = env->exception_injected;
1663 events.exception.has_error_code = env->has_error_code;
1664 events.exception.error_code = env->error_code;
1665 events.exception.pad = 0;
1666
1667 events.interrupt.injected = (env->interrupt_injected >= 0);
1668 events.interrupt.nr = env->interrupt_injected;
1669 events.interrupt.soft = env->soft_interrupt;
1670
1671 events.nmi.injected = env->nmi_injected;
1672 events.nmi.pending = env->nmi_pending;
1673 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1674 events.nmi.pad = 0;
1675
1676 events.sipi_vector = env->sipi_vector;
1677
1678 events.flags = 0;
1679 if (level >= KVM_PUT_RESET_STATE) {
1680 events.flags |=
1681 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1682 }
1683
1684 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1685 }
1686
1687 static int kvm_get_vcpu_events(X86CPU *cpu)
1688 {
1689 CPUX86State *env = &cpu->env;
1690 struct kvm_vcpu_events events;
1691 int ret;
1692
1693 if (!kvm_has_vcpu_events()) {
1694 return 0;
1695 }
1696
1697 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1698 if (ret < 0) {
1699 return ret;
1700 }
1701 env->exception_injected =
1702 events.exception.injected ? events.exception.nr : -1;
1703 env->has_error_code = events.exception.has_error_code;
1704 env->error_code = events.exception.error_code;
1705
1706 env->interrupt_injected =
1707 events.interrupt.injected ? events.interrupt.nr : -1;
1708 env->soft_interrupt = events.interrupt.soft;
1709
1710 env->nmi_injected = events.nmi.injected;
1711 env->nmi_pending = events.nmi.pending;
1712 if (events.nmi.masked) {
1713 env->hflags2 |= HF2_NMI_MASK;
1714 } else {
1715 env->hflags2 &= ~HF2_NMI_MASK;
1716 }
1717
1718 env->sipi_vector = events.sipi_vector;
1719
1720 return 0;
1721 }
1722
1723 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1724 {
1725 CPUState *cs = CPU(cpu);
1726 CPUX86State *env = &cpu->env;
1727 int ret = 0;
1728 unsigned long reinject_trap = 0;
1729
1730 if (!kvm_has_vcpu_events()) {
1731 if (env->exception_injected == 1) {
1732 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1733 } else if (env->exception_injected == 3) {
1734 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1735 }
1736 env->exception_injected = -1;
1737 }
1738
1739 /*
1740 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1741 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1742 * by updating the debug state once again if single-stepping is on.
1743 * Another reason to call kvm_update_guest_debug here is a pending debug
1744 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1745 * reinject them via SET_GUEST_DEBUG.
1746 */
1747 if (reinject_trap ||
1748 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1749 ret = kvm_update_guest_debug(cs, reinject_trap);
1750 }
1751 return ret;
1752 }
1753
1754 static int kvm_put_debugregs(X86CPU *cpu)
1755 {
1756 CPUX86State *env = &cpu->env;
1757 struct kvm_debugregs dbgregs;
1758 int i;
1759
1760 if (!kvm_has_debugregs()) {
1761 return 0;
1762 }
1763
1764 for (i = 0; i < 4; i++) {
1765 dbgregs.db[i] = env->dr[i];
1766 }
1767 dbgregs.dr6 = env->dr[6];
1768 dbgregs.dr7 = env->dr[7];
1769 dbgregs.flags = 0;
1770
1771 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1772 }
1773
1774 static int kvm_get_debugregs(X86CPU *cpu)
1775 {
1776 CPUX86State *env = &cpu->env;
1777 struct kvm_debugregs dbgregs;
1778 int i, ret;
1779
1780 if (!kvm_has_debugregs()) {
1781 return 0;
1782 }
1783
1784 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1785 if (ret < 0) {
1786 return ret;
1787 }
1788 for (i = 0; i < 4; i++) {
1789 env->dr[i] = dbgregs.db[i];
1790 }
1791 env->dr[4] = env->dr[6] = dbgregs.dr6;
1792 env->dr[5] = env->dr[7] = dbgregs.dr7;
1793
1794 return 0;
1795 }
1796
1797 int kvm_arch_put_registers(CPUState *cpu, int level)
1798 {
1799 X86CPU *x86_cpu = X86_CPU(cpu);
1800 int ret;
1801
1802 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1803
1804 ret = kvm_getput_regs(x86_cpu, 1);
1805 if (ret < 0) {
1806 return ret;
1807 }
1808 ret = kvm_put_xsave(x86_cpu);
1809 if (ret < 0) {
1810 return ret;
1811 }
1812 ret = kvm_put_xcrs(x86_cpu);
1813 if (ret < 0) {
1814 return ret;
1815 }
1816 ret = kvm_put_sregs(x86_cpu);
1817 if (ret < 0) {
1818 return ret;
1819 }
1820 /* must be before kvm_put_msrs */
1821 ret = kvm_inject_mce_oldstyle(x86_cpu);
1822 if (ret < 0) {
1823 return ret;
1824 }
1825 ret = kvm_put_msrs(x86_cpu, level);
1826 if (ret < 0) {
1827 return ret;
1828 }
1829 if (level >= KVM_PUT_RESET_STATE) {
1830 ret = kvm_put_mp_state(x86_cpu);
1831 if (ret < 0) {
1832 return ret;
1833 }
1834 ret = kvm_put_apic(x86_cpu);
1835 if (ret < 0) {
1836 return ret;
1837 }
1838 }
1839
1840 ret = kvm_put_tscdeadline_msr(x86_cpu);
1841 if (ret < 0) {
1842 return ret;
1843 }
1844
1845 ret = kvm_put_vcpu_events(x86_cpu, level);
1846 if (ret < 0) {
1847 return ret;
1848 }
1849 ret = kvm_put_debugregs(x86_cpu);
1850 if (ret < 0) {
1851 return ret;
1852 }
1853 /* must be last */
1854 ret = kvm_guest_debug_workarounds(x86_cpu);
1855 if (ret < 0) {
1856 return ret;
1857 }
1858 return 0;
1859 }
1860
1861 int kvm_arch_get_registers(CPUState *cs)
1862 {
1863 X86CPU *cpu = X86_CPU(cs);
1864 int ret;
1865
1866 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1867
1868 ret = kvm_getput_regs(cpu, 0);
1869 if (ret < 0) {
1870 return ret;
1871 }
1872 ret = kvm_get_xsave(cpu);
1873 if (ret < 0) {
1874 return ret;
1875 }
1876 ret = kvm_get_xcrs(cpu);
1877 if (ret < 0) {
1878 return ret;
1879 }
1880 ret = kvm_get_sregs(cpu);
1881 if (ret < 0) {
1882 return ret;
1883 }
1884 ret = kvm_get_msrs(cpu);
1885 if (ret < 0) {
1886 return ret;
1887 }
1888 ret = kvm_get_mp_state(cpu);
1889 if (ret < 0) {
1890 return ret;
1891 }
1892 ret = kvm_get_apic(cpu);
1893 if (ret < 0) {
1894 return ret;
1895 }
1896 ret = kvm_get_vcpu_events(cpu);
1897 if (ret < 0) {
1898 return ret;
1899 }
1900 ret = kvm_get_debugregs(cpu);
1901 if (ret < 0) {
1902 return ret;
1903 }
1904 return 0;
1905 }
1906
1907 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1908 {
1909 X86CPU *x86_cpu = X86_CPU(cpu);
1910 CPUX86State *env = &x86_cpu->env;
1911 int ret;
1912
1913 /* Inject NMI */
1914 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1915 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1916 DPRINTF("injected NMI\n");
1917 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1918 if (ret < 0) {
1919 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1920 strerror(-ret));
1921 }
1922 }
1923
1924 if (!kvm_irqchip_in_kernel()) {
1925 /* Force the VCPU out of its inner loop to process any INIT requests
1926 * or pending TPR access reports. */
1927 if (cpu->interrupt_request &
1928 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1929 cpu->exit_request = 1;
1930 }
1931
1932 /* Try to inject an interrupt if the guest can accept it */
1933 if (run->ready_for_interrupt_injection &&
1934 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1935 (env->eflags & IF_MASK)) {
1936 int irq;
1937
1938 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
1939 irq = cpu_get_pic_interrupt(env);
1940 if (irq >= 0) {
1941 struct kvm_interrupt intr;
1942
1943 intr.irq = irq;
1944 DPRINTF("injected interrupt %d\n", irq);
1945 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1946 if (ret < 0) {
1947 fprintf(stderr,
1948 "KVM: injection failed, interrupt lost (%s)\n",
1949 strerror(-ret));
1950 }
1951 }
1952 }
1953
1954 /* If we have an interrupt but the guest is not ready to receive an
1955 * interrupt, request an interrupt window exit. This will
1956 * cause a return to userspace as soon as the guest is ready to
1957 * receive interrupts. */
1958 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
1959 run->request_interrupt_window = 1;
1960 } else {
1961 run->request_interrupt_window = 0;
1962 }
1963
1964 DPRINTF("setting tpr\n");
1965 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1966 }
1967 }
1968
1969 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1970 {
1971 X86CPU *x86_cpu = X86_CPU(cpu);
1972 CPUX86State *env = &x86_cpu->env;
1973
1974 if (run->if_flag) {
1975 env->eflags |= IF_MASK;
1976 } else {
1977 env->eflags &= ~IF_MASK;
1978 }
1979 cpu_set_apic_tpr(env->apic_state, run->cr8);
1980 cpu_set_apic_base(env->apic_state, run->apic_base);
1981 }
1982
1983 int kvm_arch_process_async_events(CPUState *cs)
1984 {
1985 X86CPU *cpu = X86_CPU(cs);
1986 CPUX86State *env = &cpu->env;
1987
1988 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
1989 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1990 assert(env->mcg_cap);
1991
1992 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1993
1994 kvm_cpu_synchronize_state(cs);
1995
1996 if (env->exception_injected == EXCP08_DBLE) {
1997 /* this means triple fault */
1998 qemu_system_reset_request();
1999 cs->exit_request = 1;
2000 return 0;
2001 }
2002 env->exception_injected = EXCP12_MCHK;
2003 env->has_error_code = 0;
2004
2005 cs->halted = 0;
2006 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2007 env->mp_state = KVM_MP_STATE_RUNNABLE;
2008 }
2009 }
2010
2011 if (kvm_irqchip_in_kernel()) {
2012 return 0;
2013 }
2014
2015 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2016 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2017 apic_poll_irq(env->apic_state);
2018 }
2019 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2020 (env->eflags & IF_MASK)) ||
2021 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2022 cs->halted = 0;
2023 }
2024 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2025 kvm_cpu_synchronize_state(cs);
2026 do_cpu_init(cpu);
2027 }
2028 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2029 kvm_cpu_synchronize_state(cs);
2030 do_cpu_sipi(cpu);
2031 }
2032 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2033 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2034 kvm_cpu_synchronize_state(cs);
2035 apic_handle_tpr_access_report(env->apic_state, env->eip,
2036 env->tpr_access_type);
2037 }
2038
2039 return cs->halted;
2040 }
2041
2042 static int kvm_handle_halt(X86CPU *cpu)
2043 {
2044 CPUState *cs = CPU(cpu);
2045 CPUX86State *env = &cpu->env;
2046
2047 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2048 (env->eflags & IF_MASK)) &&
2049 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2050 cs->halted = 1;
2051 return EXCP_HLT;
2052 }
2053
2054 return 0;
2055 }
2056
2057 static int kvm_handle_tpr_access(X86CPU *cpu)
2058 {
2059 CPUX86State *env = &cpu->env;
2060 CPUState *cs = CPU(cpu);
2061 struct kvm_run *run = cs->kvm_run;
2062
2063 apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
2064 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2065 : TPR_ACCESS_READ);
2066 return 1;
2067 }
2068
2069 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2070 {
2071 static const uint8_t int3 = 0xcc;
2072
2073 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2074 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2075 return -EINVAL;
2076 }
2077 return 0;
2078 }
2079
2080 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2081 {
2082 uint8_t int3;
2083
2084 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2085 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2086 return -EINVAL;
2087 }
2088 return 0;
2089 }
2090
2091 static struct {
2092 target_ulong addr;
2093 int len;
2094 int type;
2095 } hw_breakpoint[4];
2096
2097 static int nb_hw_breakpoint;
2098
2099 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2100 {
2101 int n;
2102
2103 for (n = 0; n < nb_hw_breakpoint; n++) {
2104 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2105 (hw_breakpoint[n].len == len || len == -1)) {
2106 return n;
2107 }
2108 }
2109 return -1;
2110 }
2111
2112 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2113 target_ulong len, int type)
2114 {
2115 switch (type) {
2116 case GDB_BREAKPOINT_HW:
2117 len = 1;
2118 break;
2119 case GDB_WATCHPOINT_WRITE:
2120 case GDB_WATCHPOINT_ACCESS:
2121 switch (len) {
2122 case 1:
2123 break;
2124 case 2:
2125 case 4:
2126 case 8:
2127 if (addr & (len - 1)) {
2128 return -EINVAL;
2129 }
2130 break;
2131 default:
2132 return -EINVAL;
2133 }
2134 break;
2135 default:
2136 return -ENOSYS;
2137 }
2138
2139 if (nb_hw_breakpoint == 4) {
2140 return -ENOBUFS;
2141 }
2142 if (find_hw_breakpoint(addr, len, type) >= 0) {
2143 return -EEXIST;
2144 }
2145 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2146 hw_breakpoint[nb_hw_breakpoint].len = len;
2147 hw_breakpoint[nb_hw_breakpoint].type = type;
2148 nb_hw_breakpoint++;
2149
2150 return 0;
2151 }
2152
2153 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2154 target_ulong len, int type)
2155 {
2156 int n;
2157
2158 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2159 if (n < 0) {
2160 return -ENOENT;
2161 }
2162 nb_hw_breakpoint--;
2163 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2164
2165 return 0;
2166 }
2167
2168 void kvm_arch_remove_all_hw_breakpoints(void)
2169 {
2170 nb_hw_breakpoint = 0;
2171 }
2172
2173 static CPUWatchpoint hw_watchpoint;
2174
2175 static int kvm_handle_debug(X86CPU *cpu,
2176 struct kvm_debug_exit_arch *arch_info)
2177 {
2178 CPUState *cs = CPU(cpu);
2179 CPUX86State *env = &cpu->env;
2180 int ret = 0;
2181 int n;
2182
2183 if (arch_info->exception == 1) {
2184 if (arch_info->dr6 & (1 << 14)) {
2185 if (cs->singlestep_enabled) {
2186 ret = EXCP_DEBUG;
2187 }
2188 } else {
2189 for (n = 0; n < 4; n++) {
2190 if (arch_info->dr6 & (1 << n)) {
2191 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2192 case 0x0:
2193 ret = EXCP_DEBUG;
2194 break;
2195 case 0x1:
2196 ret = EXCP_DEBUG;
2197 env->watchpoint_hit = &hw_watchpoint;
2198 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2199 hw_watchpoint.flags = BP_MEM_WRITE;
2200 break;
2201 case 0x3:
2202 ret = EXCP_DEBUG;
2203 env->watchpoint_hit = &hw_watchpoint;
2204 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2205 hw_watchpoint.flags = BP_MEM_ACCESS;
2206 break;
2207 }
2208 }
2209 }
2210 }
2211 } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2212 ret = EXCP_DEBUG;
2213 }
2214 if (ret == 0) {
2215 cpu_synchronize_state(CPU(cpu));
2216 assert(env->exception_injected == -1);
2217
2218 /* pass to guest */
2219 env->exception_injected = arch_info->exception;
2220 env->has_error_code = 0;
2221 }
2222
2223 return ret;
2224 }
2225
2226 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2227 {
2228 const uint8_t type_code[] = {
2229 [GDB_BREAKPOINT_HW] = 0x0,
2230 [GDB_WATCHPOINT_WRITE] = 0x1,
2231 [GDB_WATCHPOINT_ACCESS] = 0x3
2232 };
2233 const uint8_t len_code[] = {
2234 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2235 };
2236 int n;
2237
2238 if (kvm_sw_breakpoints_active(cpu)) {
2239 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2240 }
2241 if (nb_hw_breakpoint > 0) {
2242 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2243 dbg->arch.debugreg[7] = 0x0600;
2244 for (n = 0; n < nb_hw_breakpoint; n++) {
2245 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2246 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2247 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2248 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2249 }
2250 }
2251 }
2252
2253 static bool host_supports_vmx(void)
2254 {
2255 uint32_t ecx, unused;
2256
2257 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2258 return ecx & CPUID_EXT_VMX;
2259 }
2260
2261 #define VMX_INVALID_GUEST_STATE 0x80000021
2262
2263 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2264 {
2265 X86CPU *cpu = X86_CPU(cs);
2266 uint64_t code;
2267 int ret;
2268
2269 switch (run->exit_reason) {
2270 case KVM_EXIT_HLT:
2271 DPRINTF("handle_hlt\n");
2272 ret = kvm_handle_halt(cpu);
2273 break;
2274 case KVM_EXIT_SET_TPR:
2275 ret = 0;
2276 break;
2277 case KVM_EXIT_TPR_ACCESS:
2278 ret = kvm_handle_tpr_access(cpu);
2279 break;
2280 case KVM_EXIT_FAIL_ENTRY:
2281 code = run->fail_entry.hardware_entry_failure_reason;
2282 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2283 code);
2284 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2285 fprintf(stderr,
2286 "\nIf you're running a guest on an Intel machine without "
2287 "unrestricted mode\n"
2288 "support, the failure can be most likely due to the guest "
2289 "entering an invalid\n"
2290 "state for Intel VT. For example, the guest maybe running "
2291 "in big real mode\n"
2292 "which is not supported on less recent Intel processors."
2293 "\n\n");
2294 }
2295 ret = -1;
2296 break;
2297 case KVM_EXIT_EXCEPTION:
2298 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2299 run->ex.exception, run->ex.error_code);
2300 ret = -1;
2301 break;
2302 case KVM_EXIT_DEBUG:
2303 DPRINTF("kvm_exit_debug\n");
2304 ret = kvm_handle_debug(cpu, &run->debug.arch);
2305 break;
2306 default:
2307 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2308 ret = -1;
2309 break;
2310 }
2311
2312 return ret;
2313 }
2314
2315 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2316 {
2317 X86CPU *cpu = X86_CPU(cs);
2318 CPUX86State *env = &cpu->env;
2319
2320 kvm_cpu_synchronize_state(cs);
2321 return !(env->cr[0] & CR0_PE_MASK) ||
2322 ((env->segs[R_CS].selector & 3) != 3);
2323 }
2324
2325 void kvm_arch_init_irq_routing(KVMState *s)
2326 {
2327 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2328 /* If kernel can't do irq routing, interrupt source
2329 * override 0->2 cannot be set up as required by HPET.
2330 * So we have to disable it.
2331 */
2332 no_hpet = 1;
2333 }
2334 /* We know at this point that we're using the in-kernel
2335 * irqchip, so we can use irqfds, and on x86 we know
2336 * we can use msi via irqfd and GSI routing.
2337 */
2338 kvm_irqfds_allowed = true;
2339 kvm_msi_via_irqfd_allowed = true;
2340 kvm_gsi_routing_allowed = true;
2341 }
2342
2343 /* Classic KVM device assignment interface. Will remain x86 only. */
2344 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2345 uint32_t flags, uint32_t *dev_id)
2346 {
2347 struct kvm_assigned_pci_dev dev_data = {
2348 .segnr = dev_addr->domain,
2349 .busnr = dev_addr->bus,
2350 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2351 .flags = flags,
2352 };
2353 int ret;
2354
2355 dev_data.assigned_dev_id =
2356 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2357
2358 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2359 if (ret < 0) {
2360 return ret;
2361 }
2362
2363 *dev_id = dev_data.assigned_dev_id;
2364
2365 return 0;
2366 }
2367
2368 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2369 {
2370 struct kvm_assigned_pci_dev dev_data = {
2371 .assigned_dev_id = dev_id,
2372 };
2373
2374 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2375 }
2376
2377 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2378 uint32_t irq_type, uint32_t guest_irq)
2379 {
2380 struct kvm_assigned_irq assigned_irq = {
2381 .assigned_dev_id = dev_id,
2382 .guest_irq = guest_irq,
2383 .flags = irq_type,
2384 };
2385
2386 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2387 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2388 } else {
2389 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2390 }
2391 }
2392
2393 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2394 uint32_t guest_irq)
2395 {
2396 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2397 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2398
2399 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2400 }
2401
2402 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2403 {
2404 struct kvm_assigned_pci_dev dev_data = {
2405 .assigned_dev_id = dev_id,
2406 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2407 };
2408
2409 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2410 }
2411
2412 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2413 uint32_t type)
2414 {
2415 struct kvm_assigned_irq assigned_irq = {
2416 .assigned_dev_id = dev_id,
2417 .flags = type,
2418 };
2419
2420 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2421 }
2422
2423 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2424 {
2425 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2426 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2427 }
2428
2429 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2430 {
2431 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2432 KVM_DEV_IRQ_GUEST_MSI, virq);
2433 }
2434
2435 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2436 {
2437 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2438 KVM_DEV_IRQ_HOST_MSI);
2439 }
2440
2441 bool kvm_device_msix_supported(KVMState *s)
2442 {
2443 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2444 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2445 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2446 }
2447
2448 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2449 uint32_t nr_vectors)
2450 {
2451 struct kvm_assigned_msix_nr msix_nr = {
2452 .assigned_dev_id = dev_id,
2453 .entry_nr = nr_vectors,
2454 };
2455
2456 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2457 }
2458
2459 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2460 int virq)
2461 {
2462 struct kvm_assigned_msix_entry msix_entry = {
2463 .assigned_dev_id = dev_id,
2464 .gsi = virq,
2465 .entry = vector,
2466 };
2467
2468 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2469 }
2470
2471 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2472 {
2473 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2474 KVM_DEV_IRQ_GUEST_MSIX, 0);
2475 }
2476
2477 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2478 {
2479 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2480 KVM_DEV_IRQ_HOST_MSIX);
2481 }
Qemu copy for testing